diff options
| author | Zhou Zhu <zzhu3@marvell.com> | 2013-04-29 18:05:50 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-04-29 18:54:27 -0400 |
| commit | ee8ad7261cd7b18fcf750469402a34b851372814 (patch) | |
| tree | 6d72f847ffe8b1316c2c090bce50285734dbedfe | |
| parent | bb5254d2f3b60fdd49966426ee2a86a904fdf2f8 (diff) | |
drivers/video/mmp: remove legacy hw definitions
Removed legacy hw definitions in hw/mmp_ctrl.h. These definitions are
for earlier soc versions and are not supported in this driver.
Signed-off-by: Zhou Zhu <zzhu3@marvell.com>
Cc: Paul Bolle <pebolle@tiscali.nl>
Cc: Lisa Du <cldu@marvell.com>
Cc: Guoqing Li <ligq@marvell.com>
Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| -rw-r--r-- | drivers/video/mmp/hw/mmp_ctrl.h | 479 |
1 files changed, 1 insertions, 478 deletions
diff --git a/drivers/video/mmp/hw/mmp_ctrl.h b/drivers/video/mmp/hw/mmp_ctrl.h index 6408d8ef3abb..edd2002b0e99 100644 --- a/drivers/video/mmp/hw/mmp_ctrl.h +++ b/drivers/video/mmp/hw/mmp_ctrl.h | |||
| @@ -961,56 +961,7 @@ struct lcd_regs { | |||
| 961 | LCD_TVG_CUTVLN : PN2_LCD_GRA_CUTVLN) : LCD_GRA_CUTVLN) | 961 | LCD_TVG_CUTVLN : PN2_LCD_GRA_CUTVLN) : LCD_GRA_CUTVLN) |
| 962 | 962 | ||
| 963 | /* | 963 | /* |
| 964 | * defined Video Memory Color format for DMA control 0 register | 964 | * defined for Configure Dumb Mode |
| 965 | * DMA0 bit[23:20] | ||
| 966 | */ | ||
| 967 | #define VMODE_RGB565 0x0 | ||
| 968 | #define VMODE_RGB1555 0x1 | ||
| 969 | #define VMODE_RGB888PACKED 0x2 | ||
| 970 | #define VMODE_RGB888UNPACKED 0x3 | ||
| 971 | #define VMODE_RGBA888 0x4 | ||
| 972 | #define VMODE_YUV422PACKED 0x5 | ||
| 973 | #define VMODE_YUV422PLANAR 0x6 | ||
| 974 | #define VMODE_YUV420PLANAR 0x7 | ||
| 975 | #define VMODE_SMPNCMD 0x8 | ||
| 976 | #define VMODE_PALETTE4BIT 0x9 | ||
| 977 | #define VMODE_PALETTE8BIT 0xa | ||
| 978 | #define VMODE_RESERVED 0xb | ||
| 979 | |||
| 980 | /* | ||
| 981 | * defined Graphic Memory Color format for DMA control 0 register | ||
| 982 | * DMA0 bit[19:16] | ||
| 983 | */ | ||
| 984 | #define GMODE_RGB565 0x0 | ||
| 985 | #define GMODE_RGB1555 0x1 | ||
| 986 | #define GMODE_RGB888PACKED 0x2 | ||
| 987 | #define GMODE_RGB888UNPACKED 0x3 | ||
| 988 | #define GMODE_RGBA888 0x4 | ||
| 989 | #define GMODE_YUV422PACKED 0x5 | ||
| 990 | #define GMODE_YUV422PLANAR 0x6 | ||
| 991 | #define GMODE_YUV420PLANAR 0x7 | ||
| 992 | #define GMODE_SMPNCMD 0x8 | ||
| 993 | #define GMODE_PALETTE4BIT 0x9 | ||
| 994 | #define GMODE_PALETTE8BIT 0xa | ||
| 995 | #define GMODE_RESERVED 0xb | ||
| 996 | |||
| 997 | /* | ||
| 998 | * define for DMA control 1 register | ||
| 999 | */ | ||
| 1000 | #define DMA1_FRAME_TRIG 31 /* bit location */ | ||
| 1001 | #define DMA1_VSYNC_MODE 28 | ||
| 1002 | #define DMA1_VSYNC_INV 27 | ||
| 1003 | #define DMA1_CKEY 24 | ||
| 1004 | #define DMA1_CARRY 23 | ||
| 1005 | #define DMA1_LNBUF_ENA 22 | ||
| 1006 | #define DMA1_GATED_ENA 21 | ||
| 1007 | #define DMA1_PWRDN_ENA 20 | ||
| 1008 | #define DMA1_DSCALE 18 | ||
| 1009 | #define DMA1_ALPHA_MODE 16 | ||
| 1010 | #define DMA1_ALPHA 08 | ||
| 1011 | #define DMA1_PXLCMD 00 | ||
| 1012 | |||
| 1013 | /* | ||
| 1014 | * defined for Configure Dumb Mode | 965 | * defined for Configure Dumb Mode |
| 1015 | * DUMB LCD Panel bit[31:28] | 966 | * DUMB LCD Panel bit[31:28] |
| 1016 | */ | 967 | */ |
| @@ -1050,18 +1001,6 @@ struct lcd_regs { | |||
| 1050 | #define CFG_CYC_BURST_LEN16 (1<<4) | 1001 | #define CFG_CYC_BURST_LEN16 (1<<4) |
| 1051 | #define CFG_CYC_BURST_LEN8 (0<<4) | 1002 | #define CFG_CYC_BURST_LEN8 (0<<4) |
| 1052 | 1003 | ||
| 1053 | /* | ||
| 1054 | * defined Dumb Panel Clock Divider register | ||
| 1055 | * SCLK_Source bit[31] | ||
| 1056 | */ | ||
| 1057 | /* 0: PLL clock select*/ | ||
| 1058 | #define AXI_BUS_SEL 0x80000000 | ||
| 1059 | #define CCD_CLK_SEL 0x40000000 | ||
| 1060 | #define DCON_CLK_SEL 0x20000000 | ||
| 1061 | #define ENA_CLK_INT_DIV CONFIG_FB_DOVE_CLCD_SCLK_DIV | ||
| 1062 | #define IDLE_CLK_INT_DIV 0x1 /* idle Integer Divider */ | ||
| 1063 | #define DIS_CLK_INT_DIV 0x0 /* Disable Integer Divider */ | ||
| 1064 | |||
| 1065 | /* SRAM ID */ | 1004 | /* SRAM ID */ |
| 1066 | #define SRAMID_GAMMA_YR 0x0 | 1005 | #define SRAMID_GAMMA_YR 0x0 |
| 1067 | #define SRAMID_GAMMA_UG 0x1 | 1006 | #define SRAMID_GAMMA_UG 0x1 |
| @@ -1471,422 +1410,6 @@ struct dsi_regs { | |||
| 1471 | #define LVDS_FREQ_OFFSET_MODE_CK_DIV4_OUT (0x1 << 1) | 1410 | #define LVDS_FREQ_OFFSET_MODE_CK_DIV4_OUT (0x1 << 1) |
| 1472 | #define LVDS_FREQ_OFFSET_MODE_EN (0x1 << 0) | 1411 | #define LVDS_FREQ_OFFSET_MODE_EN (0x1 << 0) |
| 1473 | 1412 | ||
| 1474 | /* VDMA */ | ||
| 1475 | struct vdma_ch_regs { | ||
| 1476 | #define VDMA_DC_SADDR_1 0x320 | ||
| 1477 | #define VDMA_DC_SADDR_2 0x3A0 | ||
| 1478 | #define VDMA_DC_SZ_1 0x324 | ||
| 1479 | #define VDMA_DC_SZ_2 0x3A4 | ||
| 1480 | #define VDMA_CTRL_1 0x328 | ||
| 1481 | #define VDMA_CTRL_2 0x3A8 | ||
| 1482 | #define VDMA_SRC_SZ_1 0x32C | ||
| 1483 | #define VDMA_SRC_SZ_2 0x3AC | ||
| 1484 | #define VDMA_SA_1 0x330 | ||
| 1485 | #define VDMA_SA_2 0x3B0 | ||
| 1486 | #define VDMA_DA_1 0x334 | ||
| 1487 | #define VDMA_DA_2 0x3B4 | ||
| 1488 | #define VDMA_SZ_1 0x338 | ||
| 1489 | #define VDMA_SZ_2 0x3B8 | ||
| 1490 | u32 dc_saddr; | ||
| 1491 | u32 dc_size; | ||
| 1492 | u32 ctrl; | ||
| 1493 | u32 src_size; | ||
| 1494 | u32 src_addr; | ||
| 1495 | u32 dst_addr; | ||
| 1496 | u32 dst_size; | ||
| 1497 | #define VDMA_PITCH_1 0x33C | ||
| 1498 | #define VDMA_PITCH_2 0x3BC | ||
| 1499 | #define VDMA_ROT_CTRL_1 0x340 | ||
| 1500 | #define VDMA_ROT_CTRL_2 0x3C0 | ||
| 1501 | #define VDMA_RAM_CTRL0_1 0x344 | ||
| 1502 | #define VDMA_RAM_CTRL0_2 0x3C4 | ||
| 1503 | #define VDMA_RAM_CTRL1_1 0x348 | ||
| 1504 | #define VDMA_RAM_CTRL1_2 0x3C8 | ||
| 1505 | u32 pitch; | ||
| 1506 | u32 rot_ctrl; | ||
| 1507 | u32 ram_ctrl0; | ||
| 1508 | u32 ram_ctrl1; | ||
| 1509 | |||
| 1510 | }; | ||
| 1511 | struct vdma_regs { | ||
| 1512 | #define VDMA_ARBR_CTRL 0x300 | ||
| 1513 | #define VDMA_IRQR 0x304 | ||
| 1514 | #define VDMA_IRQM 0x308 | ||
| 1515 | #define VDMA_IRQS 0x30C | ||
| 1516 | #define VDMA_MDMA_ARBR_CTRL 0x310 | ||
| 1517 | u32 arbr_ctr; | ||
| 1518 | u32 irq_raw; | ||
| 1519 | u32 irq_mask; | ||
| 1520 | u32 irq_status; | ||
| 1521 | u32 mdma_arbr_ctrl; | ||
| 1522 | u32 reserved[3]; | ||
| 1523 | |||
| 1524 | struct vdma_ch_regs ch1; | ||
| 1525 | u32 reserved2[21]; | ||
| 1526 | struct vdma_ch_regs ch2; | ||
| 1527 | }; | ||
| 1528 | |||
| 1529 | /* CMU */ | ||
| 1530 | #define CMU_PIP_DE_H_CFG 0x0008 | ||
| 1531 | #define CMU_PRI1_H_CFG 0x000C | ||
| 1532 | #define CMU_PRI2_H_CFG 0x0010 | ||
| 1533 | #define CMU_ACE_MAIN_DE1_H_CFG 0x0014 | ||
| 1534 | #define CMU_ACE_MAIN_DE2_H_CFG 0x0018 | ||
| 1535 | #define CMU_ACE_PIP_DE1_H_CFG 0x001C | ||
| 1536 | #define CMU_ACE_PIP_DE2_H_CFG 0x0020 | ||
| 1537 | #define CMU_PIP_DE_V_CFG 0x0024 | ||
| 1538 | #define CMU_PRI_V_CFG 0x0028 | ||
| 1539 | #define CMU_ACE_MAIN_DE_V_CFG 0x002C | ||
| 1540 | #define CMU_ACE_PIP_DE_V_CFG 0x0030 | ||
| 1541 | #define CMU_BAR_0_CFG 0x0034 | ||
| 1542 | #define CMU_BAR_1_CFG 0x0038 | ||
| 1543 | #define CMU_BAR_2_CFG 0x003C | ||
| 1544 | #define CMU_BAR_3_CFG 0x0040 | ||
| 1545 | #define CMU_BAR_4_CFG 0x0044 | ||
| 1546 | #define CMU_BAR_5_CFG 0x0048 | ||
| 1547 | #define CMU_BAR_6_CFG 0x004C | ||
| 1548 | #define CMU_BAR_7_CFG 0x0050 | ||
| 1549 | #define CMU_BAR_8_CFG 0x0054 | ||
| 1550 | #define CMU_BAR_9_CFG 0x0058 | ||
| 1551 | #define CMU_BAR_10_CFG 0x005C | ||
| 1552 | #define CMU_BAR_11_CFG 0x0060 | ||
| 1553 | #define CMU_BAR_12_CFG 0x0064 | ||
| 1554 | #define CMU_BAR_13_CFG 0x0068 | ||
| 1555 | #define CMU_BAR_14_CFG 0x006C | ||
| 1556 | #define CMU_BAR_15_CFG 0x0070 | ||
| 1557 | #define CMU_BAR_CTRL 0x0074 | ||
| 1558 | #define PATTERN_TOTAL 0x0078 | ||
| 1559 | #define PATTERN_ACTIVE 0x007C | ||
| 1560 | #define PATTERN_FRONT_PORCH 0x0080 | ||
| 1561 | #define PATTERN_BACK_PORCH 0x0084 | ||
| 1562 | #define CMU_CLK_CTRL 0x0088 | ||
| 1563 | |||
| 1564 | #define CMU_ICSC_M_C0_L 0x0900 | ||
| 1565 | #define CMU_ICSC_M_C0_H 0x0901 | ||
| 1566 | #define CMU_ICSC_M_C1_L 0x0902 | ||
| 1567 | #define CMU_ICSC_M_C1_H 0x0903 | ||
| 1568 | #define CMU_ICSC_M_C2_L 0x0904 | ||
| 1569 | #define CMU_ICSC_M_C2_H 0x0905 | ||
| 1570 | #define CMU_ICSC_M_C3_L 0x0906 | ||
| 1571 | #define CMU_ICSC_M_C3_H 0x0907 | ||
| 1572 | #define CMU_ICSC_M_C4_L 0x0908 | ||
| 1573 | #define CMU_ICSC_M_C4_H 0x0909 | ||
| 1574 | #define CMU_ICSC_M_C5_L 0x090A | ||
| 1575 | #define CMU_ICSC_M_C5_H 0x090B | ||
| 1576 | #define CMU_ICSC_M_C6_L 0x090C | ||
| 1577 | #define CMU_ICSC_M_C6_H 0x090D | ||
| 1578 | #define CMU_ICSC_M_C7_L 0x090E | ||
| 1579 | #define CMU_ICSC_M_C7_H 0x090F | ||
| 1580 | #define CMU_ICSC_M_C8_L 0x0910 | ||
| 1581 | #define CMU_ICSC_M_C8_H 0x0911 | ||
| 1582 | #define CMU_ICSC_M_O1_0 0x0914 | ||
| 1583 | #define CMU_ICSC_M_O1_1 0x0915 | ||
| 1584 | #define CMU_ICSC_M_O1_2 0x0916 | ||
| 1585 | #define CMU_ICSC_M_O2_0 0x0918 | ||
| 1586 | #define CMU_ICSC_M_O2_1 0x0919 | ||
| 1587 | #define CMU_ICSC_M_O2_2 0x091A | ||
| 1588 | #define CMU_ICSC_M_O3_0 0x091C | ||
| 1589 | #define CMU_ICSC_M_O3_1 0x091D | ||
| 1590 | #define CMU_ICSC_M_O3_2 0x091E | ||
| 1591 | #define CMU_ICSC_P_C0_L 0x0920 | ||
| 1592 | #define CMU_ICSC_P_C0_H 0x0921 | ||
| 1593 | #define CMU_ICSC_P_C1_L 0x0922 | ||
| 1594 | #define CMU_ICSC_P_C1_H 0x0923 | ||
| 1595 | #define CMU_ICSC_P_C2_L 0x0924 | ||
| 1596 | #define CMU_ICSC_P_C2_H 0x0925 | ||
| 1597 | #define CMU_ICSC_P_C3_L 0x0926 | ||
| 1598 | #define CMU_ICSC_P_C3_H 0x0927 | ||
| 1599 | #define CMU_ICSC_P_C4_L 0x0928 | ||
| 1600 | #define CMU_ICSC_P_C4_H 0x0929 | ||
| 1601 | #define CMU_ICSC_P_C5_L 0x092A | ||
| 1602 | #define CMU_ICSC_P_C5_H 0x092B | ||
| 1603 | #define CMU_ICSC_P_C6_L 0x092C | ||
| 1604 | #define CMU_ICSC_P_C6_H 0x092D | ||
| 1605 | #define CMU_ICSC_P_C7_L 0x092E | ||
| 1606 | #define CMU_ICSC_P_C7_H 0x092F | ||
| 1607 | #define CMU_ICSC_P_C8_L 0x0930 | ||
| 1608 | #define CMU_ICSC_P_C8_H 0x0931 | ||
| 1609 | #define CMU_ICSC_P_O1_0 0x0934 | ||
| 1610 | #define CMU_ICSC_P_O1_1 0x0935 | ||
| 1611 | #define CMU_ICSC_P_O1_2 0x0936 | ||
| 1612 | #define CMU_ICSC_P_O2_0 0x0938 | ||
| 1613 | #define CMU_ICSC_P_O2_1 0x0939 | ||
| 1614 | #define CMU_ICSC_P_O2_2 0x093A | ||
| 1615 | #define CMU_ICSC_P_O3_0 0x093C | ||
| 1616 | #define CMU_ICSC_P_O3_1 0x093D | ||
| 1617 | #define CMU_ICSC_P_O3_2 0x093E | ||
| 1618 | #define CMU_BR_M_EN 0x0940 | ||
| 1619 | #define CMU_BR_M_TH1_L 0x0942 | ||
| 1620 | #define CMU_BR_M_TH1_H 0x0943 | ||
| 1621 | #define CMU_BR_M_TH2_L 0x0944 | ||
| 1622 | #define CMU_BR_M_TH2_H 0x0945 | ||
| 1623 | #define CMU_ACE_M_EN 0x0950 | ||
| 1624 | #define CMU_ACE_M_WFG1 0x0951 | ||
| 1625 | #define CMU_ACE_M_WFG2 0x0952 | ||
| 1626 | #define CMU_ACE_M_WFG3 0x0953 | ||
| 1627 | #define CMU_ACE_M_TH0 0x0954 | ||
| 1628 | #define CMU_ACE_M_TH1 0x0955 | ||
| 1629 | #define CMU_ACE_M_TH2 0x0956 | ||
| 1630 | #define CMU_ACE_M_TH3 0x0957 | ||
| 1631 | #define CMU_ACE_M_TH4 0x0958 | ||
| 1632 | #define CMU_ACE_M_TH5 0x0959 | ||
| 1633 | #define CMU_ACE_M_OP0_L 0x095A | ||
| 1634 | #define CMU_ACE_M_OP0_H 0x095B | ||
| 1635 | #define CMU_ACE_M_OP5_L 0x095C | ||
| 1636 | #define CMU_ACE_M_OP5_H 0x095D | ||
| 1637 | #define CMU_ACE_M_GB2 0x095E | ||
| 1638 | #define CMU_ACE_M_GB3 0x095F | ||
| 1639 | #define CMU_ACE_M_MS1 0x0960 | ||
| 1640 | #define CMU_ACE_M_MS2 0x0961 | ||
| 1641 | #define CMU_ACE_M_MS3 0x0962 | ||
| 1642 | #define CMU_BR_P_EN 0x0970 | ||
| 1643 | #define CMU_BR_P_TH1_L 0x0972 | ||
| 1644 | #define CMU_BR_P_TH1_H 0x0973 | ||
| 1645 | #define CMU_BR_P_TH2_L 0x0974 | ||
| 1646 | #define CMU_BR_P_TH2_H 0x0975 | ||
| 1647 | #define CMU_ACE_P_EN 0x0980 | ||
| 1648 | #define CMU_ACE_P_WFG1 0x0981 | ||
| 1649 | #define CMU_ACE_P_WFG2 0x0982 | ||
| 1650 | #define CMU_ACE_P_WFG3 0x0983 | ||
| 1651 | #define CMU_ACE_P_TH0 0x0984 | ||
| 1652 | #define CMU_ACE_P_TH1 0x0985 | ||
| 1653 | #define CMU_ACE_P_TH2 0x0986 | ||
| 1654 | #define CMU_ACE_P_TH3 0x0987 | ||
| 1655 | #define CMU_ACE_P_TH4 0x0988 | ||
| 1656 | #define CMU_ACE_P_TH5 0x0989 | ||
| 1657 | #define CMU_ACE_P_OP0_L 0x098A | ||
| 1658 | #define CMU_ACE_P_OP0_H 0x098B | ||
| 1659 | #define CMU_ACE_P_OP5_L 0x098C | ||
| 1660 | #define CMU_ACE_P_OP5_H 0x098D | ||
| 1661 | #define CMU_ACE_P_GB2 0x098E | ||
| 1662 | #define CMU_ACE_P_GB3 0x098F | ||
| 1663 | #define CMU_ACE_P_MS1 0x0990 | ||
| 1664 | #define CMU_ACE_P_MS2 0x0991 | ||
| 1665 | #define CMU_ACE_P_MS3 0x0992 | ||
| 1666 | #define CMU_FTDC_M_EN 0x09A0 | ||
| 1667 | #define CMU_FTDC_P_EN 0x09A1 | ||
| 1668 | #define CMU_FTDC_INLOW_L 0x09A2 | ||
| 1669 | #define CMU_FTDC_INLOW_H 0x09A3 | ||
| 1670 | #define CMU_FTDC_INHIGH_L 0x09A4 | ||
| 1671 | #define CMU_FTDC_INHIGH_H 0x09A5 | ||
| 1672 | #define CMU_FTDC_OUTLOW_L 0x09A6 | ||
| 1673 | #define CMU_FTDC_OUTLOW_H 0x09A7 | ||
| 1674 | #define CMU_FTDC_OUTHIGH_L 0x09A8 | ||
| 1675 | #define CMU_FTDC_OUTHIGH_H 0x09A9 | ||
| 1676 | #define CMU_FTDC_YLOW 0x09AA | ||
| 1677 | #define CMU_FTDC_YHIGH 0x09AB | ||
| 1678 | #define CMU_FTDC_CH1 0x09AC | ||
| 1679 | #define CMU_FTDC_CH2_L 0x09AE | ||
| 1680 | #define CMU_FTDC_CH2_H 0x09AF | ||
| 1681 | #define CMU_FTDC_CH3_L 0x09B0 | ||
| 1682 | #define CMU_FTDC_CH3_H 0x09B1 | ||
| 1683 | #define CMU_FTDC_1_C00_6 0x09B2 | ||
| 1684 | #define CMU_FTDC_1_C01_6 0x09B8 | ||
| 1685 | #define CMU_FTDC_1_C11_6 0x09BE | ||
| 1686 | #define CMU_FTDC_1_C10_6 0x09C4 | ||
| 1687 | #define CMU_FTDC_1_OFF00_6 0x09CA | ||
| 1688 | #define CMU_FTDC_1_OFF10_6 0x09D0 | ||
| 1689 | #define CMU_HS_M_EN 0x0A00 | ||
| 1690 | #define CMU_HS_M_AX1_L 0x0A02 | ||
| 1691 | #define CMU_HS_M_AX1_H 0x0A03 | ||
| 1692 | #define CMU_HS_M_AX2_L 0x0A04 | ||
| 1693 | #define CMU_HS_M_AX2_H 0x0A05 | ||
| 1694 | #define CMU_HS_M_AX3_L 0x0A06 | ||
| 1695 | #define CMU_HS_M_AX3_H 0x0A07 | ||
| 1696 | #define CMU_HS_M_AX4_L 0x0A08 | ||
| 1697 | #define CMU_HS_M_AX4_H 0x0A09 | ||
| 1698 | #define CMU_HS_M_AX5_L 0x0A0A | ||
| 1699 | #define CMU_HS_M_AX5_H 0x0A0B | ||
| 1700 | #define CMU_HS_M_AX6_L 0x0A0C | ||
| 1701 | #define CMU_HS_M_AX6_H 0x0A0D | ||
| 1702 | #define CMU_HS_M_AX7_L 0x0A0E | ||
| 1703 | #define CMU_HS_M_AX7_H 0x0A0F | ||
| 1704 | #define CMU_HS_M_AX8_L 0x0A10 | ||
| 1705 | #define CMU_HS_M_AX8_H 0x0A11 | ||
| 1706 | #define CMU_HS_M_AX9_L 0x0A12 | ||
| 1707 | #define CMU_HS_M_AX9_H 0x0A13 | ||
| 1708 | #define CMU_HS_M_AX10_L 0x0A14 | ||
| 1709 | #define CMU_HS_M_AX10_H 0x0A15 | ||
| 1710 | #define CMU_HS_M_AX11_L 0x0A16 | ||
| 1711 | #define CMU_HS_M_AX11_H 0x0A17 | ||
| 1712 | #define CMU_HS_M_AX12_L 0x0A18 | ||
| 1713 | #define CMU_HS_M_AX12_H 0x0A19 | ||
| 1714 | #define CMU_HS_M_AX13_L 0x0A1A | ||
| 1715 | #define CMU_HS_M_AX13_H 0x0A1B | ||
| 1716 | #define CMU_HS_M_AX14_L 0x0A1C | ||
| 1717 | #define CMU_HS_M_AX14_H 0x0A1D | ||
| 1718 | #define CMU_HS_M_H1_H14 0x0A1E | ||
| 1719 | #define CMU_HS_M_S1_S14 0x0A2C | ||
| 1720 | #define CMU_HS_M_GL 0x0A3A | ||
| 1721 | #define CMU_HS_M_MAXSAT_RGB_Y_L 0x0A3C | ||
| 1722 | #define CMU_HS_M_MAXSAT_RGB_Y_H 0x0A3D | ||
| 1723 | #define CMU_HS_M_MAXSAT_RCR_L 0x0A3E | ||
| 1724 | #define CMU_HS_M_MAXSAT_RCR_H 0x0A3F | ||
| 1725 | #define CMU_HS_M_MAXSAT_RCB_L 0x0A40 | ||
| 1726 | #define CMU_HS_M_MAXSAT_RCB_H 0x0A41 | ||
| 1727 | #define CMU_HS_M_MAXSAT_GCR_L 0x0A42 | ||
| 1728 | #define CMU_HS_M_MAXSAT_GCR_H 0x0A43 | ||
| 1729 | #define CMU_HS_M_MAXSAT_GCB_L 0x0A44 | ||
| 1730 | #define CMU_HS_M_MAXSAT_GCB_H 0x0A45 | ||
| 1731 | #define CMU_HS_M_MAXSAT_BCR_L 0x0A46 | ||
| 1732 | #define CMU_HS_M_MAXSAT_BCR_H 0x0A47 | ||
| 1733 | #define CMU_HS_M_MAXSAT_BCB_L 0x0A48 | ||
| 1734 | #define CMU_HS_M_MAXSAT_BCB_H 0x0A49 | ||
| 1735 | #define CMU_HS_M_ROFF_L 0x0A4A | ||
| 1736 | #define CMU_HS_M_ROFF_H 0x0A4B | ||
| 1737 | #define CMU_HS_M_GOFF_L 0x0A4C | ||
| 1738 | #define CMU_HS_M_GOFF_H 0x0A4D | ||
| 1739 | #define CMU_HS_M_BOFF_L 0x0A4E | ||
| 1740 | #define CMU_HS_M_BOFF_H 0x0A4F | ||
| 1741 | #define CMU_HS_P_EN 0x0A50 | ||
| 1742 | #define CMU_HS_P_AX1_L 0x0A52 | ||
| 1743 | #define CMU_HS_P_AX1_H 0x0A53 | ||
| 1744 | #define CMU_HS_P_AX2_L 0x0A54 | ||
| 1745 | #define CMU_HS_P_AX2_H 0x0A55 | ||
| 1746 | #define CMU_HS_P_AX3_L 0x0A56 | ||
| 1747 | #define CMU_HS_P_AX3_H 0x0A57 | ||
| 1748 | #define CMU_HS_P_AX4_L 0x0A58 | ||
| 1749 | #define CMU_HS_P_AX4_H 0x0A59 | ||
| 1750 | #define CMU_HS_P_AX5_L 0x0A5A | ||
| 1751 | #define CMU_HS_P_AX5_H 0x0A5B | ||
| 1752 | #define CMU_HS_P_AX6_L 0x0A5C | ||
| 1753 | #define CMU_HS_P_AX6_H 0x0A5D | ||
| 1754 | #define CMU_HS_P_AX7_L 0x0A5E | ||
| 1755 | #define CMU_HS_P_AX7_H 0x0A5F | ||
| 1756 | #define CMU_HS_P_AX8_L 0x0A60 | ||
| 1757 | #define CMU_HS_P_AX8_H 0x0A61 | ||
| 1758 | #define CMU_HS_P_AX9_L 0x0A62 | ||
| 1759 | #define CMU_HS_P_AX9_H 0x0A63 | ||
| 1760 | #define CMU_HS_P_AX10_L 0x0A64 | ||
| 1761 | #define CMU_HS_P_AX10_H 0x0A65 | ||
| 1762 | #define CMU_HS_P_AX11_L 0x0A66 | ||
| 1763 | #define CMU_HS_P_AX11_H 0x0A67 | ||
| 1764 | #define CMU_HS_P_AX12_L 0x0A68 | ||
| 1765 | #define CMU_HS_P_AX12_H 0x0A69 | ||
| 1766 | #define CMU_HS_P_AX13_L 0x0A6A | ||
| 1767 | #define CMU_HS_P_AX13_H 0x0A6B | ||
| 1768 | #define CMU_HS_P_AX14_L 0x0A6C | ||
| 1769 | #define CMU_HS_P_AX14_H 0x0A6D | ||
| 1770 | #define CMU_HS_P_H1_H14 0x0A6E | ||
| 1771 | #define CMU_HS_P_S1_S14 0x0A7C | ||
| 1772 | #define CMU_HS_P_GL 0x0A8A | ||
| 1773 | #define CMU_HS_P_MAXSAT_RGB_Y_L 0x0A8C | ||
| 1774 | #define CMU_HS_P_MAXSAT_RGB_Y_H 0x0A8D | ||
| 1775 | #define CMU_HS_P_MAXSAT_RCR_L 0x0A8E | ||
| 1776 | #define CMU_HS_P_MAXSAT_RCR_H 0x0A8F | ||
| 1777 | #define CMU_HS_P_MAXSAT_RCB_L 0x0A90 | ||
| 1778 | #define CMU_HS_P_MAXSAT_RCB_H 0x0A91 | ||
| 1779 | #define CMU_HS_P_MAXSAT_GCR_L 0x0A92 | ||
| 1780 | #define CMU_HS_P_MAXSAT_GCR_H 0x0A93 | ||
| 1781 | #define CMU_HS_P_MAXSAT_GCB_L 0x0A94 | ||
| 1782 | #define CMU_HS_P_MAXSAT_GCB_H 0x0A95 | ||
| 1783 | #define CMU_HS_P_MAXSAT_BCR_L 0x0A96 | ||
| 1784 | #define CMU_HS_P_MAXSAT_BCR_H 0x0A97 | ||
| 1785 | #define CMU_HS_P_MAXSAT_BCB_L 0x0A98 | ||
| 1786 | #define CMU_HS_P_MAXSAT_BCB_H 0x0A99 | ||
| 1787 | #define CMU_HS_P_ROFF_L 0x0A9A | ||
| 1788 | #define CMU_HS_P_ROFF_H 0x0A9B | ||
| 1789 | #define CMU_HS_P_GOFF_L 0x0A9C | ||
| 1790 | #define CMU_HS_P_GOFF_H 0x0A9D | ||
| 1791 | #define CMU_HS_P_BOFF_L 0x0A9E | ||
| 1792 | #define CMU_HS_P_BOFF_H 0x0A9F | ||
| 1793 | #define CMU_GLCSC_M_C0_L 0x0AA0 | ||
| 1794 | #define CMU_GLCSC_M_C0_H 0x0AA1 | ||
| 1795 | #define CMU_GLCSC_M_C1_L 0x0AA2 | ||
| 1796 | #define CMU_GLCSC_M_C1_H 0x0AA3 | ||
| 1797 | #define CMU_GLCSC_M_C2_L 0x0AA4 | ||
| 1798 | #define CMU_GLCSC_M_C2_H 0x0AA5 | ||
| 1799 | #define CMU_GLCSC_M_C3_L 0x0AA6 | ||
| 1800 | #define CMU_GLCSC_M_C3_H 0x0AA7 | ||
| 1801 | #define CMU_GLCSC_M_C4_L 0x0AA8 | ||
| 1802 | #define CMU_GLCSC_M_C4_H 0x0AA9 | ||
| 1803 | #define CMU_GLCSC_M_C5_L 0x0AAA | ||
| 1804 | #define CMU_GLCSC_M_C5_H 0x0AAB | ||
| 1805 | #define CMU_GLCSC_M_C6_L 0x0AAC | ||
| 1806 | #define CMU_GLCSC_M_C6_H 0x0AAD | ||
| 1807 | #define CMU_GLCSC_M_C7_L 0x0AAE | ||
| 1808 | #define CMU_GLCSC_M_C7_H 0x0AAF | ||
| 1809 | #define CMU_GLCSC_M_C8_L 0x0AB0 | ||
| 1810 | #define CMU_GLCSC_M_C8_H 0x0AB1 | ||
| 1811 | #define CMU_GLCSC_M_O1_1 0x0AB4 | ||
| 1812 | #define CMU_GLCSC_M_O1_2 0x0AB5 | ||
| 1813 | #define CMU_GLCSC_M_O1_3 0x0AB6 | ||
| 1814 | #define CMU_GLCSC_M_O2_1 0x0AB8 | ||
| 1815 | #define CMU_GLCSC_M_O2_2 0x0AB9 | ||
| 1816 | #define CMU_GLCSC_M_O2_3 0x0ABA | ||
| 1817 | #define CMU_GLCSC_M_O3_1 0x0ABC | ||
| 1818 | #define CMU_GLCSC_M_O3_2 0x0ABD | ||
| 1819 | #define CMU_GLCSC_M_O3_3 0x0ABE | ||
| 1820 | #define CMU_GLCSC_P_C0_L 0x0AC0 | ||
| 1821 | #define CMU_GLCSC_P_C0_H 0x0AC1 | ||
| 1822 | #define CMU_GLCSC_P_C1_L 0x0AC2 | ||
| 1823 | #define CMU_GLCSC_P_C1_H 0x0AC3 | ||
| 1824 | #define CMU_GLCSC_P_C2_L 0x0AC4 | ||
| 1825 | #define CMU_GLCSC_P_C2_H 0x0AC5 | ||
| 1826 | #define CMU_GLCSC_P_C3_L 0x0AC6 | ||
| 1827 | #define CMU_GLCSC_P_C3_H 0x0AC7 | ||
| 1828 | #define CMU_GLCSC_P_C4_L 0x0AC8 | ||
| 1829 | #define CMU_GLCSC_P_C4_H 0x0AC9 | ||
| 1830 | #define CMU_GLCSC_P_C5_L 0x0ACA | ||
| 1831 | #define CMU_GLCSC_P_C5_H 0x0ACB | ||
| 1832 | #define CMU_GLCSC_P_C6_L 0x0ACC | ||
| 1833 | #define CMU_GLCSC_P_C6_H 0x0ACD | ||
| 1834 | #define CMU_GLCSC_P_C7_L 0x0ACE | ||
| 1835 | #define CMU_GLCSC_P_C7_H 0x0ACF | ||
| 1836 | #define CMU_GLCSC_P_C8_L 0x0AD0 | ||
| 1837 | #define CMU_GLCSC_P_C8_H 0x0AD1 | ||
| 1838 | #define CMU_GLCSC_P_O1_1 0x0AD4 | ||
| 1839 | #define CMU_GLCSC_P_O1_2 0x0AD5 | ||
| 1840 | #define CMU_GLCSC_P_O1_3 0x0AD6 | ||
| 1841 | #define CMU_GLCSC_P_O2_1 0x0AD8 | ||
| 1842 | #define CMU_GLCSC_P_O2_2 0x0AD9 | ||
| 1843 | #define CMU_GLCSC_P_O2_3 0x0ADA | ||
| 1844 | #define CMU_GLCSC_P_O3_1 0x0ADC | ||
| 1845 | #define CMU_GLCSC_P_O3_2 0x0ADD | ||
| 1846 | #define CMU_GLCSC_P_O3_3 0x0ADE | ||
| 1847 | #define CMU_PIXVAL_M_EN 0x0AE0 | ||
| 1848 | #define CMU_PIXVAL_P_EN 0x0AE1 | ||
| 1849 | |||
| 1850 | #define CMU_CLK_CTRL_TCLK 0x0 | ||
| 1851 | #define CMU_CLK_CTRL_SCLK 0x2 | ||
| 1852 | #define CMU_CLK_CTRL_MSK 0x2 | ||
| 1853 | #define CMU_CLK_CTRL_ENABLE 0x1 | ||
| 1854 | |||
| 1855 | #define LCD_TOP_CTRL_TV 0x2 | ||
| 1856 | #define LCD_TOP_CTRL_PN 0x0 | ||
| 1857 | #define LCD_TOP_CTRL_SEL_MSK 0x2 | ||
| 1858 | #define LCD_IO_CMU_IN_SEL_MSK (0x3 << 20) | ||
| 1859 | #define LCD_IO_CMU_IN_SEL_TV 0 | ||
| 1860 | #define LCD_IO_CMU_IN_SEL_PN 1 | ||
| 1861 | #define LCD_IO_CMU_IN_SEL_PN2 2 | ||
| 1862 | #define LCD_IO_TV_OUT_SEL_MSK (0x3 << 26) | ||
| 1863 | #define LCD_IO_PN_OUT_SEL_MSK (0x3 << 24) | ||
| 1864 | #define LCD_IO_PN2_OUT_SEL_MSK (0x3 << 28) | ||
| 1865 | #define LCD_IO_TV_OUT_SEL_NON 3 | ||
| 1866 | #define LCD_IO_PN_OUT_SEL_NON 3 | ||
| 1867 | #define LCD_IO_PN2_OUT_SEL_NON 3 | ||
| 1868 | #define LCD_TOP_CTRL_CMU_ENABLE 0x1 | ||
| 1869 | #define LCD_IO_OVERL_MSK 0xC00000 | ||
| 1870 | #define LCD_IO_OVERL_TV 0x0 | ||
| 1871 | #define LCD_IO_OVERL_LCD1 0x400000 | ||
| 1872 | #define LCD_IO_OVERL_LCD2 0xC00000 | ||
| 1873 | #define HINVERT_MSK 0x4 | ||
| 1874 | #define VINVERT_MSK 0x8 | ||
| 1875 | #define HINVERT_LEN 0x2 | ||
| 1876 | #define VINVERT_LEN 0x3 | ||
| 1877 | |||
| 1878 | #define CMU_CTRL 0x88 | ||
| 1879 | #define CMU_CTRL_A0_MSK 0x6 | ||
| 1880 | #define CMU_CTRL_A0_TV 0x0 | ||
| 1881 | #define CMU_CTRL_A0_LCD1 0x1 | ||
| 1882 | #define CMU_CTRL_A0_LCD2 0x2 | ||
| 1883 | #define CMU_CTRL_A0_HDMI 0x3 | ||
| 1884 | |||
| 1885 | #define ICR_DRV_ROUTE_OFF 0x0 | ||
| 1886 | #define ICR_DRV_ROUTE_TV 0x1 | ||
| 1887 | #define ICR_DRV_ROUTE_LCD1 0x2 | ||
| 1888 | #define ICR_DRV_ROUTE_LCD2 0x3 | ||
| 1889 | |||
| 1890 | enum { | 1413 | enum { |
| 1891 | PATH_PN = 0, | 1414 | PATH_PN = 0, |
| 1892 | PATH_TV, | 1415 | PATH_TV, |