Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next

restore debugfs vbios, fix multiple actions with supervisor intrs

* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6:
  drm/nouveau: restore debugfs/vbios.rom support
  drm/nv50-/kms: remove UPDATE methods after each encoder disconnect
  drm/nvd0/disp: handle multiple actions from one set of supervisor intrs
  drm/nv50/disp: handle multiple actions from one set of supervisor intrs

7 files changed, 329 insertions, 220 deletions

diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 51d09729fc56..90f9140eeefd 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -242,5 +242,6 @@ ifdef CONFIG_X86
 nouveau-$(CONFIG_ACPI) += nouveau_acpi.o
 endif
 nouveau-$(CONFIG_DRM_NOUVEAU_BACKLIGHT) += nouveau_backlight.o
+nouveau-$(CONFIG_DEBUG_FS) += nouveau_debugfs.o
 
 obj-$(CONFIG_DRM_NOUVEAU)+= nouveau.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 314dda6d7cb8..5fa13267bd9f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -972,21 +972,29 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk,
 }
 
 static void
-nv50_disp_intr_unk10(struct nv50_disp_priv *priv, u32 super)
+nv50_disp_intr_unk10_0(struct nv50_disp_priv *priv, int head)
 {
-        int head = ffs((super & 0x00000060) >> 5) - 1;
-        if (head >= 0) {
-                head = ffs((super & 0x00000180) >> 7) - 1;
-                if (head >= 0)
-                        exec_script(priv, head, 1);
-        }
+        exec_script(priv, head, 1);
+}
 
-        nv_wr32(priv, 0x610030, 0x80000000);
+static void
+nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head)
+{
+        exec_script(priv, head, 2);
 }
 
 static void
-nv50_disp_intr_unk20_dp(struct nv50_disp_priv *priv,
-                        struct dcb_output *outp, u32 pclk)
+nv50_disp_intr_unk20_1(struct nv50_disp_priv *priv, int head)
+{
+        struct nouveau_clock *clk = nouveau_clock(priv);
+        u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
+        if (pclk)
+                clk->pll_set(clk, PLL_VPLL0 + head, pclk);
+}
+
+static void
+nv50_disp_intr_unk20_2_dp(struct nv50_disp_priv *priv,
+                          struct dcb_output *outp, u32 pclk)
 {
         const int link = !(outp->sorconf.link & 1);
         const int   or = ffs(outp->or) - 1;
@@ -1092,77 +1100,54 @@ nv50_disp_intr_unk20_dp(struct nv50_disp_priv *priv,
 }
 
 static void
-nv50_disp_intr_unk20(struct nv50_disp_priv *priv, u32 super)
+nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
 {
         struct dcb_output outp;
-        int head;
-
-        /* finish detaching encoder? */
-        head = ffs((super & 0x00000180) >> 7) - 1;
-        if (head >= 0)
-                exec_script(priv, head, 2);
-
-        /* check whether a vpll change is required */
-        head = ffs((super & 0x00000600) >> 9) - 1;
-        if (head >= 0) {
-                u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
-                if (pclk) {
-                        struct nouveau_clock *clk = nouveau_clock(priv);
-                        clk->pll_set(clk, PLL_VPLL0 + head, pclk);
-                }
-        }
-
-        /* (re)attach the relevant OR to the head */
-        head = ffs((super & 0x00000180) >> 7) - 1;
-        if (head >= 0) {
-                u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
-                u32 hval, hreg = 0x614200 + (head * 0x800);
-                u32 oval, oreg;
-                u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp);
-                if (conf != ~0) {
-                        if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) {
-                                u32 soff = (ffs(outp.or) - 1) * 0x08;
-                                u32 ctrl = nv_rd32(priv, 0x610798 + soff);
-                                u32 datarate;
-
-                                switch ((ctrl & 0x000f0000) >> 16) {
-                                case 6: datarate = pclk * 30 / 8; break;
-                                case 5: datarate = pclk * 24 / 8; break;
-                                case 2:
-                                default:
-                                        datarate = pclk * 18 / 8;
-                                        break;
-                                }
-
-                                nouveau_dp_train(&priv->base, priv->sor.dp,
-                                                 &outp, head, datarate);
+        u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
+        u32 hval, hreg = 0x614200 + (head * 0x800);
+        u32 oval, oreg;
+        u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp);
+        if (conf != ~0) {
+                if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) {
+                        u32 soff = (ffs(outp.or) - 1) * 0x08;
+                        u32 ctrl = nv_rd32(priv, 0x610798 + soff);
+                        u32 datarate;
+
+                        switch ((ctrl & 0x000f0000) >> 16) {
+                        case 6: datarate = pclk * 30 / 8; break;
+                        case 5: datarate = pclk * 24 / 8; break;
+                        case 2:
+                        default:
+                                datarate = pclk * 18 / 8;
+                                break;
                         }
 
-                        exec_clkcmp(priv, head, 0, pclk, &outp);
-
-                        if (!outp.location && outp.type == DCB_OUTPUT_ANALOG) {
-                                oreg = 0x614280 + (ffs(outp.or) - 1) * 0x800;
-                                oval = 0x00000000;
-                                hval = 0x00000000;
-                        } else
-                        if (!outp.location) {
-                                if (outp.type == DCB_OUTPUT_DP)
-                                        nv50_disp_intr_unk20_dp(priv, &outp, pclk);
-                                oreg = 0x614300 + (ffs(outp.or) - 1) * 0x800;
-                                oval = (conf & 0x0100) ? 0x0101 : 0x0000;
-                                hval = 0x00000000;
-                        } else {
-                                oreg = 0x614380 + (ffs(outp.or) - 1) * 0x800;
-                                oval = 0x00000001;
-                                hval = 0x00000001;
-                        }
+                        nouveau_dp_train(&priv->base, priv->sor.dp,
+                                         &outp, head, datarate);
+                }
 
-                        nv_mask(priv, hreg, 0x0000000f, hval);
-                        nv_mask(priv, oreg, 0x00000707, oval);
+                exec_clkcmp(priv, head, 0, pclk, &outp);
+
+                if (!outp.location && outp.type == DCB_OUTPUT_ANALOG) {
+                        oreg = 0x614280 + (ffs(outp.or) - 1) * 0x800;
+                        oval = 0x00000000;
+                        hval = 0x00000000;
+                } else
+                if (!outp.location) {
+                        if (outp.type == DCB_OUTPUT_DP)
+                                nv50_disp_intr_unk20_2_dp(priv, &outp, pclk);
+                        oreg = 0x614300 + (ffs(outp.or) - 1) * 0x800;
+                        oval = (conf & 0x0100) ? 0x00000101 : 0x00000000;
+                        hval = 0x00000000;
+                } else {
+                        oreg = 0x614380 + (ffs(outp.or) - 1) * 0x800;
+                        oval = 0x00000001;
+                        hval = 0x00000001;
                 }
-        }
 
-        nv_wr32(priv, 0x610030, 0x80000000);
+                nv_mask(priv, hreg, 0x0000000f, hval);
+                nv_mask(priv, oreg, 0x00000707, oval);
+        }
 }
 
 /* If programming a TMDS output on a SOR that can also be configured for
@@ -1174,7 +1159,7 @@ nv50_disp_intr_unk20(struct nv50_disp_priv *priv, u32 super)
  * programmed for DisplayPort.
  */
 static void
-nv50_disp_intr_unk40_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp)
+nv50_disp_intr_unk40_0_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp)
 {
         struct nouveau_bios *bios = nouveau_bios(priv);
         const int link = !(outp->sorconf.link & 1);
@@ -1188,37 +1173,32 @@ nv50_disp_intr_unk40_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp)
 }
 
 static void
-nv50_disp_intr_unk40(struct nv50_disp_priv *priv, u32 super)
+nv50_disp_intr_unk40_0(struct nv50_disp_priv *priv, int head)
 {
-        int head = ffs((super & 0x00000180) >> 7) - 1;
-        if (head >= 0) {
-                struct dcb_output outp;
-                u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
-                if (exec_clkcmp(priv, head, 1, pclk, &outp) != ~0) {
-                        if (outp.location == 0 && outp.type == DCB_OUTPUT_TMDS)
-                                nv50_disp_intr_unk40_tmds(priv, &outp);
-                        else
-                        if (outp.location == 1 && outp.type == DCB_OUTPUT_DP) {
-                                u32 soff = (ffs(outp.or) - 1) * 0x08;
-                                u32 ctrl = nv_rd32(priv, 0x610b84 + soff);
-                                u32 datarate;
-
-                                switch ((ctrl & 0x000f0000) >> 16) {
-                                case 6: datarate = pclk * 30 / 8; break;
-                                case 5: datarate = pclk * 24 / 8; break;
-                                case 2:
-                                default:
-                                        datarate = pclk * 18 / 8;
-                                        break;
-                                }
-
-                                nouveau_dp_train(&priv->base, priv->pior.dp,
-                                                 &outp, head, datarate);
+        struct dcb_output outp;
+        u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
+        if (exec_clkcmp(priv, head, 1, pclk, &outp) != ~0) {
+                if (outp.location == 0 && outp.type == DCB_OUTPUT_TMDS)
+                        nv50_disp_intr_unk40_0_tmds(priv, &outp);
+                else
+                if (outp.location == 1 && outp.type == DCB_OUTPUT_DP) {
+                        u32 soff = (ffs(outp.or) - 1) * 0x08;
+                        u32 ctrl = nv_rd32(priv, 0x610b84 + soff);
+                        u32 datarate;
+
+                        switch ((ctrl & 0x000f0000) >> 16) {
+                        case 6: datarate = pclk * 30 / 8; break;
+                        case 5: datarate = pclk * 24 / 8; break;
+                        case 2:
+                        default:
+                                datarate = pclk * 18 / 8;
+                                break;
                         }
+
+                        nouveau_dp_train(&priv->base, priv->pior.dp,
+                                         &outp, head, datarate);
                 }
         }
-
-        nv_wr32(priv, 0x610030, 0x80000000);
 }
 
 void
@@ -1227,15 +1207,45 @@ nv50_disp_intr_supervisor(struct work_struct *work)
         struct nv50_disp_priv *priv =
                 container_of(work, struct nv50_disp_priv, supervisor);
         u32 super = nv_rd32(priv, 0x610030);
+        int head;
 
         nv_debug(priv, "supervisor 0x%08x 0x%08x\n", priv->super, super);
 
-        if (priv->super & 0x00000010)
-                nv50_disp_intr_unk10(priv, super);
-        if (priv->super & 0x00000020)
-                nv50_disp_intr_unk20(priv, super);
-        if (priv->super & 0x00000040)
-                nv50_disp_intr_unk40(priv, super);
+        if (priv->super & 0x00000010) {
+                for (head = 0; head < priv->head.nr; head++) {
+                        if (!(super & (0x00000020 << head)))
+                                continue;
+                        if (!(super & (0x00000080 << head)))
+                                continue;
+                        nv50_disp_intr_unk10_0(priv, head);
+                }
+        } else
+        if (priv->super & 0x00000020) {
+                for (head = 0; head < priv->head.nr; head++) {
+                        if (!(super & (0x00000080 << head)))
+                                continue;
+                        nv50_disp_intr_unk20_0(priv, head);
+                }
+                for (head = 0; head < priv->head.nr; head++) {
+                        if (!(super & (0x00000200 << head)))
+                                continue;
+                        nv50_disp_intr_unk20_1(priv, head);
+                }
+                for (head = 0; head < priv->head.nr; head++) {
+                        if (!(super & (0x00000080 << head)))
+                                continue;
+                        nv50_disp_intr_unk20_2(priv, head);
+                }
+        } else
+        if (priv->super & 0x00000040) {
+                for (head = 0; head < priv->head.nr; head++) {
+                        if (!(super & (0x00000080 << head)))
+                                continue;
+                        nv50_disp_intr_unk40_0(priv, head);
+                }
+        }
+
+        nv_wr32(priv, 0x610030, 0x80000000);
 }
 
 void
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
index 7106a72e611e..788dd34ccb54 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
@@ -623,13 +623,24 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int outp, u32 ctrl,
 }
 
 static bool
-exec_script(struct nv50_disp_priv *priv, int head, int outp, u32 ctrl, int id)
+exec_script(struct nv50_disp_priv *priv, int head, int id)
 {
         struct nouveau_bios *bios = nouveau_bios(priv);
         struct nvbios_outp info;
         struct dcb_output dcb;
         u8  ver, hdr, cnt, len;
+        u32 ctrl = 0x00000000;
         u16 data;
+        int outp;
+
+        for (outp = 0; !(ctrl & (1 << head)) && outp < 8; outp++) {
+                ctrl = nv_rd32(priv, 0x640180 + (outp * 0x20));
+                if (ctrl & (1 << head))
+                        break;
+        }
+
+        if (outp == 8)
+                return false;
 
         data = exec_lookup(priv, head, outp, ctrl, &dcb, &ver, &hdr, &cnt, &len, &info);
         if (data) {
@@ -649,14 +660,25 @@ exec_script(struct nv50_disp_priv *priv, int head, int outp, u32 ctrl, int id)
 }
 
 static u32
-exec_clkcmp(struct nv50_disp_priv *priv, int head, int outp,
-            u32 ctrl, int id, u32 pclk, struct dcb_output *dcb)
+exec_clkcmp(struct nv50_disp_priv *priv, int head, int id,
+            u32 pclk, struct dcb_output *dcb)
 {
         struct nouveau_bios *bios = nouveau_bios(priv);
         struct nvbios_outp info1;
         struct nvbios_ocfg info2;
         u8  ver, hdr, cnt, len;
+        u32 ctrl = 0x00000000;
         u32 data, conf = ~0;
+        int outp;
+
+        for (outp = 0; !(ctrl & (1 << head)) && outp < 8; outp++) {
+                ctrl = nv_rd32(priv, 0x660180 + (outp * 0x20));
+                if (ctrl & (1 << head))
+                        break;
+        }
+
+        if (outp == 8)
+                return false;
 
         data = exec_lookup(priv, head, outp, ctrl, dcb, &ver, &hdr, &cnt, &len, &info1);
         if (data == 0x0000)
@@ -701,24 +723,32 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int outp,
 }
 
 static void
-nvd0_display_unk1_handler(struct nv50_disp_priv *priv, u32 head, u32 mask)
+nvd0_disp_intr_unk1_0(struct nv50_disp_priv *priv, int head)
 {
-        int i;
+        exec_script(priv, head, 1);
+}
 
-        for (i = 0; mask && i < 8; i++) {
-                u32 mcc = nv_rd32(priv, 0x640180 + (i * 0x20));
-                if (mcc & (1 << head))
-                        exec_script(priv, head, i, mcc, 1);
-        }
+static void
+nvd0_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head)
+{
+        exec_script(priv, head, 2);
+}
 
-        nv_wr32(priv, 0x6101d4, 0x00000000);
-        nv_wr32(priv, 0x6109d4, 0x00000000);
-        nv_wr32(priv, 0x6101d0, 0x80000000);
+static void
+nvd0_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head)
+{
+        struct nouveau_clock *clk = nouveau_clock(priv);
+        u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
+        if (pclk)
+                clk->pll_set(clk, PLL_VPLL0 + head, pclk);
+        nv_wr32(priv, 0x612200 + (head * 0x800), 0x00000000);
 }
 
 static void
-nvd0_display_unk2_calc_tu(struct nv50_disp_priv *priv, int head, int or)
+nvd0_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head,
+                         struct dcb_output *outp)
 {
+        const int or = ffs(outp->or) - 1;
         const u32 ctrl = nv_rd32(priv, 0x660200 + (or   * 0x020));
         const u32 conf = nv_rd32(priv, 0x660404 + (head * 0x300));
         const u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
@@ -761,97 +791,51 @@ nvd0_display_unk2_calc_tu(struct nv50_disp_priv *priv, int head, int or)
 }
 
 static void
-nvd0_display_unk2_handler(struct nv50_disp_priv *priv, u32 head, u32 mask)
+nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head)
 {
         struct dcb_output outp;
-        u32 pclk;
-        int i;
-
-        for (i = 0; mask && i < 8; i++) {
-                u32 mcc = nv_rd32(priv, 0x640180 + (i * 0x20));
-                if (mcc & (1 << head))
-                        exec_script(priv, head, i, mcc, 2);
-        }
+        u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
+        u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp);
+        if (conf != ~0) {
+                u32 addr, data;
+
+                if (outp.type == DCB_OUTPUT_DP) {
+                        u32 sync = nv_rd32(priv, 0x660404 + (head * 0x300));
+                        switch ((sync & 0x000003c0) >> 6) {
+                        case 6: pclk = pclk * 30 / 8; break;
+                        case 5: pclk = pclk * 24 / 8; break;
+                        case 2:
+                        default:
+                                pclk = pclk * 18 / 8;
+                                break;
+                        }
 
-        pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
-        nv_debug(priv, "head %d pclk %d mask 0x%08x\n", head, pclk, mask);
-        if (pclk && (mask & 0x00010000)) {
-                struct nouveau_clock *clk = nouveau_clock(priv);
-                clk->pll_set(clk, PLL_VPLL0 + head, pclk);
-        }
+                        nouveau_dp_train(&priv->base, priv->sor.dp,
+                                         &outp, head, pclk);
+                }
 
-        nv_wr32(priv, 0x612200 + (head * 0x800), 0x00000000);
+                exec_clkcmp(priv, head, 0, pclk, &outp);
 
-        for (i = 0; mask && i < 8; i++) {
-                u32 mcp = nv_rd32(priv, 0x660180 + (i * 0x20));
-                if (mcp & (1 << head)) {
-                        u32 cfg = exec_clkcmp(priv, head, i, mcp, 0xff, pclk, &outp);
-                        if (cfg != ~0) {
-                                u32 addr, mask, data = 0x00000000;
-
-                                if (outp.type == DCB_OUTPUT_DP) {
-                                        switch ((mcp & 0x000f0000) >> 16) {
-                                        case 6: pclk = pclk * 30 / 8; break;
-                                        case 5: pclk = pclk * 24 / 8; break;
-                                        case 2:
-                                        default:
-                                                pclk = pclk * 18 / 8;
-                                                break;
-                                        }
-
-                                        nouveau_dp_train(&priv->base,
-                                                          priv->sor.dp,
-                                                         &outp, head, pclk);
-                                }
-
-                                exec_clkcmp(priv, head, i, mcp, 0, pclk, &outp);
-
-                                if (i < 4) {
-                                        addr = 0x612280 + ((i - 0) * 0x800);
-                                        mask = 0xffffffff;
-                                } else {
-                                        switch (mcp & 0x00000f00) {
-                                        case 0x00000800:
-                                        case 0x00000900:
-                                                nvd0_display_unk2_calc_tu(priv, head, i - 4);
-                                                break;
-                                        default:
-                                                break;
-                                        }
-
-                                        addr = 0x612300 + ((i - 4) * 0x800);
-                                        mask = 0x00000707;
-                                        if (cfg & 0x00000100)
-                                                data = 0x00000101;
-                                }
-                                nv_mask(priv, addr, mask, data);
-                        }
-                        break;
+                if (outp.type == DCB_OUTPUT_ANALOG) {
+                        addr = 0x612280 + (ffs(outp.or) - 1) * 0x800;
+                        data = 0x00000000;
+                } else {
+                        if (outp.type == DCB_OUTPUT_DP)
+                                nvd0_disp_intr_unk2_2_tu(priv, head, &outp);
+                        addr = 0x612300 + (ffs(outp.or) - 1) * 0x800;
+                        data = (conf & 0x0100) ? 0x00000101 : 0x00000000;
                 }
-        }
 
-        nv_wr32(priv, 0x6101d4, 0x00000000);
-        nv_wr32(priv, 0x6109d4, 0x00000000);
-        nv_wr32(priv, 0x6101d0, 0x80000000);
+                nv_mask(priv, addr, 0x00000707, data);
+        }
 }
 
 static void
-nvd0_display_unk4_handler(struct nv50_disp_priv *priv, u32 head, u32 mask)
+nvd0_disp_intr_unk4_0(struct nv50_disp_priv *priv, int head)
 {
         struct dcb_output outp;
-        int pclk, i;
-
-        pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
-
-        for (i = 0; mask && i < 8; i++) {
-                u32 mcp = nv_rd32(priv, 0x660180 + (i * 0x20));
-                if (mcp & (1 << head))
-                        exec_clkcmp(priv, head, i, mcp, 1, pclk, &outp);
-        }
-
-        nv_wr32(priv, 0x6101d4, 0x00000000);
-        nv_wr32(priv, 0x6109d4, 0x00000000);
-        nv_wr32(priv, 0x6101d0, 0x80000000);
+        u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
+        exec_clkcmp(priv, head, 1, pclk, &outp);
 }
 
 void
@@ -859,19 +843,50 @@ nvd0_disp_intr_supervisor(struct work_struct *work)
 {
         struct nv50_disp_priv *priv =
                 container_of(work, struct nv50_disp_priv, supervisor);
-        u32 mask = 0, head = ~0;
+        u32 mask[4];
+        int head;
 
-        while (!mask && ++head < priv->head.nr)
-                mask = nv_rd32(priv, 0x6101d4 + (head * 0x800));
+        nv_debug(priv, "supervisor %08x\n", priv->super);
+        for (head = 0; head < priv->head.nr; head++) {
+                mask[head] = nv_rd32(priv, 0x6101d4 + (head * 0x800));
+                nv_debug(priv, "head %d: 0x%08x\n", head, mask[head]);
+        }
 
-        nv_debug(priv, "supervisor %08x %08x %d\n", priv->super, mask, head);
+        if (priv->super & 0x00000001) {
+                for (head = 0; head < priv->head.nr; head++) {
+                        if (!(mask[head] & 0x00001000))
+                                continue;
+                        nvd0_disp_intr_unk1_0(priv, head);
+                }
+        } else
+        if (priv->super & 0x00000002) {
+                for (head = 0; head < priv->head.nr; head++) {
+                        if (!(mask[head] & 0x00001000))
+                                continue;
+                        nvd0_disp_intr_unk2_0(priv, head);
+                }
+                for (head = 0; head < priv->head.nr; head++) {
+                        if (!(mask[head] & 0x00010000))
+                                continue;
+                        nvd0_disp_intr_unk2_1(priv, head);
+                }
+                for (head = 0; head < priv->head.nr; head++) {
+                        if (!(mask[head] & 0x00001000))
+                                continue;
+                        nvd0_disp_intr_unk2_2(priv, head);
+                }
+        } else
+        if (priv->super & 0x00000004) {
+                for (head = 0; head < priv->head.nr; head++) {
+                        if (!(mask[head] & 0x00001000))
+                                continue;
+                        nvd0_disp_intr_unk4_0(priv, head);
+                }
+        }
 
-        if (priv->super & 0x00000001)
-                nvd0_display_unk1_handler(priv, head, mask);
-        if (priv->super & 0x00000002)
-                nvd0_display_unk2_handler(priv, head, mask);
-        if (priv->super & 0x00000004)
-                nvd0_display_unk4_handler(priv, head, mask);
+        for (head = 0; head < priv->head.nr; head++)
+                nv_wr32(priv, 0x6101d4 + (head * 0x800), 0x00000000);
+        nv_wr32(priv, 0x6101d0, 0x80000000);
 }
 
 void
diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.c b/drivers/gpu/drm/nouveau/nouveau_debugfs.c
new file mode 100644
index 000000000000..5392e07edfc6
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2009 Red Hat <bskeggs@redhat.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/*
+ * Authors:
+ *  Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include "nouveau_debugfs.h"
+#include "nouveau_drm.h"
+
+static int
+nouveau_debugfs_vbios_image(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct nouveau_drm *drm = nouveau_drm(node->minor->dev);
+        int i;
+
+        for (i = 0; i < drm->vbios.length; i++)
+                seq_printf(m, "%c", drm->vbios.data[i]);
+        return 0;
+}
+
+static struct drm_info_list nouveau_debugfs_list[] = {
+        { "vbios.rom", nouveau_debugfs_vbios_image, 0, NULL },
+};
+#define NOUVEAU_DEBUGFS_ENTRIES ARRAY_SIZE(nouveau_debugfs_list)
+
+int
+nouveau_debugfs_init(struct drm_minor *minor)
+{
+        drm_debugfs_create_files(nouveau_debugfs_list, NOUVEAU_DEBUGFS_ENTRIES,
+                                 minor->debugfs_root, minor);
+        return 0;
+}
+
+void
+nouveau_debugfs_takedown(struct drm_minor *minor)
+{
+        drm_debugfs_remove_files(nouveau_debugfs_list, NOUVEAU_DEBUGFS_ENTRIES,
+                                 minor);
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.h b/drivers/gpu/drm/nouveau/nouveau_debugfs.h
new file mode 100644
index 000000000000..a62af6fb5f99
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.h
@@ -0,0 +1,22 @@
+#ifndef __NOUVEAU_DEBUGFS_H__
+#define __NOUVEAU_DEBUGFS_H__
+
+#include <drm/drmP.h>
+
+#if defined(CONFIG_DEBUG_FS)
+extern int  nouveau_debugfs_init(struct drm_minor *);
+extern void nouveau_debugfs_takedown(struct drm_minor *);
+#else
+static inline int
+nouveau_debugfs_init(struct drm_minor *minor)
+{
+       return 0;
+}
+
+static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
+{
+}
+
+#endif
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index ccfe2be3ae38..8a03c58ae988 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -50,6 +50,7 @@
 #include "nouveau_abi16.h"
 #include "nouveau_fbcon.h"
 #include "nouveau_fence.h"
+#include "nouveau_debugfs.h"
 
 MODULE_PARM_DESC(config, "option string to pass to driver core");
 static char *nouveau_config;
@@ -667,6 +668,11 @@ driver = {
         .postclose = nouveau_drm_postclose,
         .lastclose = nouveau_vga_lastclose,
 
+#if defined(CONFIG_DEBUG_FS)
+        .debugfs_init = nouveau_debugfs_init,
+        .debugfs_cleanup = nouveau_debugfs_takedown,
+#endif
+
         .irq_preinstall = nouveau_irq_preinstall,
         .irq_postinstall = nouveau_irq_postinstall,
         .irq_uninstall = nouveau_irq_uninstall,
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 45624c37e29f..a6237c9cbbc3 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -1519,9 +1519,6 @@ nv50_dac_disconnect(struct drm_encoder *encoder)
                                 evo_mthd(push, 0x0180 + (or * 0x020), 1);
                                 evo_data(push, 0x00000000);
                         }
-
-                        evo_mthd(push, 0x0080, 1);
-                        evo_data(push, 0x00000000);
                         evo_kick(push, mast);
                 }
         }
@@ -1735,9 +1732,6 @@ nv50_sor_disconnect(struct drm_encoder *encoder)
                                 evo_mthd(push, 0x0200 + (or * 0x20), 1);
                                 evo_data(push, 0x00000000);
                         }
-
-                        evo_mthd(push, 0x0080, 1);
-                        evo_data(push, 0x00000000);
                         evo_kick(push, mast);
                 }
 
@@ -2039,9 +2033,6 @@ nv50_pior_disconnect(struct drm_encoder *encoder)
                                 evo_mthd(push, 0x0700 + (or * 0x040), 1);
                                 evo_data(push, 0x00000000);
                         }
-
-                        evo_mthd(push, 0x0080, 1);
-                        evo_data(push, 0x00000000);
                         evo_kick(push, mast);
                 }
         }