aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJonas Gorski <jonas.gorski@gmail.com>2012-07-24 10:33:12 -0400
committerRalf Baechle <ralf@linux-mips.org>2012-07-24 10:33:12 -0400
commite5766aea5b9b7519654261c27b639f567b5415b4 (patch)
treea4c9cab5c07e5656d0199871e348765fb8a0269d
parent288752a8aa1be6cf89ee5066435a617efd97fb86 (diff)
MIPS: BCM63XX: Add basic BCM6328 support
This includes CPU speed, memory size detection and working UART, but lacking the appropriate drivers, no support for attached flash. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Cc: linux-mips@linux-mips.org Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/3951/ Reviewed-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/bcm63xx/Kconfig3
-rw-r--r--arch/mips/bcm63xx/boards/board_bcm963xx.c12
-rw-r--r--arch/mips/bcm63xx/cpu.c43
-rw-r--r--arch/mips/bcm63xx/dev-flash.c6
-rw-r--r--arch/mips/bcm63xx/dev-spi.c2
-rw-r--r--arch/mips/bcm63xx/irq.c21
-rw-r--r--arch/mips/bcm63xx/prom.c4
-rw-r--r--arch/mips/bcm63xx/setup.c13
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h111
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h54
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/ioremap.h1
13 files changed, 265 insertions, 9 deletions
diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
index 6b1b9ad8d857..09e93cab37b5 100644
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -1,6 +1,9 @@
1menu "CPU support" 1menu "CPU support"
2 depends on BCM63XX 2 depends on BCM63XX
3 3
4config BCM63XX_CPU_6328
5 bool "support 6328 CPU"
6
4config BCM63XX_CPU_6338 7config BCM63XX_CPU_6338
5 bool "support 6338 CPU" 8 bool "support 6338 CPU"
6 select HW_HAS_PCI 9 select HW_HAS_PCI
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index bdfbdf95f000..be7498a2a923 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -708,9 +708,15 @@ void __init board_prom_init(void)
708 char cfe_version[32]; 708 char cfe_version[32];
709 u32 val; 709 u32 val;
710 710
711 /* read base address of boot chip select (0) */ 711 /* read base address of boot chip select (0)
712 val = bcm_mpi_readl(MPI_CSBASE_REG(0)); 712 * 6328 does not have MPI but boots from a fixed address
713 val &= MPI_CSBASE_BASE_MASK; 713 */
714 if (BCMCPU_IS_6328())
715 val = 0x18000000;
716 else {
717 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
718 val &= MPI_CSBASE_BASE_MASK;
719 }
714 boot_addr = (u8 *)KSEG1ADDR(val); 720 boot_addr = (u8 *)KSEG1ADDR(val);
715 721
716 /* dump cfe version */ 722 /* dump cfe version */
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index e3c1da59ea13..a7afb289b15a 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -29,6 +29,14 @@ static u16 bcm63xx_cpu_rev;
29static unsigned int bcm63xx_cpu_freq; 29static unsigned int bcm63xx_cpu_freq;
30static unsigned int bcm63xx_memory_size; 30static unsigned int bcm63xx_memory_size;
31 31
32static const unsigned long bcm6328_regs_base[] = {
33 __GEN_CPU_REGS_TABLE(6328)
34};
35
36static const int bcm6328_irqs[] = {
37 __GEN_CPU_IRQ_TABLE(6328)
38};
39
32static const unsigned long bcm6338_regs_base[] = { 40static const unsigned long bcm6338_regs_base[] = {
33 __GEN_CPU_REGS_TABLE(6338) 41 __GEN_CPU_REGS_TABLE(6338)
34}; 42};
@@ -99,6 +107,33 @@ unsigned int bcm63xx_get_memory_size(void)
99static unsigned int detect_cpu_clock(void) 107static unsigned int detect_cpu_clock(void)
100{ 108{
101 switch (bcm63xx_get_cpu_id()) { 109 switch (bcm63xx_get_cpu_id()) {
110 case BCM6328_CPU_ID:
111 {
112 unsigned int tmp, mips_pll_fcvo;
113
114 tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
115 mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK)
116 >> STRAPBUS_6328_FCVO_SHIFT;
117
118 switch (mips_pll_fcvo) {
119 case 0x12:
120 case 0x14:
121 case 0x19:
122 return 160000000;
123 case 0x1c:
124 return 192000000;
125 case 0x13:
126 case 0x15:
127 return 200000000;
128 case 0x1a:
129 return 384000000;
130 case 0x16:
131 return 400000000;
132 default:
133 return 320000000;
134 }
135
136 }
102 case BCM6338_CPU_ID: 137 case BCM6338_CPU_ID:
103 /* BCM6338 has a fixed 240 Mhz frequency */ 138 /* BCM6338 has a fixed 240 Mhz frequency */
104 return 240000000; 139 return 240000000;
@@ -170,6 +205,9 @@ static unsigned int detect_memory_size(void)
170 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; 205 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
171 u32 val; 206 u32 val;
172 207
208 if (BCMCPU_IS_6328())
209 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
210
173 if (BCMCPU_IS_6345()) { 211 if (BCMCPU_IS_6345()) {
174 val = bcm_sdram_readl(SDRAM_MBASE_REG); 212 val = bcm_sdram_readl(SDRAM_MBASE_REG);
175 return (val * 8 * 1024 * 1024); 213 return (val * 8 * 1024 * 1024);
@@ -237,6 +275,11 @@ void __init bcm63xx_cpu_init(void)
237 u16 chip_id = bcm_readw(BCM_6368_PERF_BASE); 275 u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
238 276
239 switch (chip_id) { 277 switch (chip_id) {
278 case BCM6328_CPU_ID:
279 expected_cpu_id = BCM6328_CPU_ID;
280 bcm63xx_regs_base = bcm6328_regs_base;
281 bcm63xx_irqs = bcm6328_irqs;
282 break;
240 case BCM6368_CPU_ID: 283 case BCM6368_CPU_ID:
241 expected_cpu_id = BCM6368_CPU_ID; 284 expected_cpu_id = BCM6368_CPU_ID;
242 bcm63xx_regs_base = bcm6368_regs_base; 285 bcm63xx_regs_base = bcm6368_regs_base;
diff --git a/arch/mips/bcm63xx/dev-flash.c b/arch/mips/bcm63xx/dev-flash.c
index 1051faedab2d..58371c7deac2 100644
--- a/arch/mips/bcm63xx/dev-flash.c
+++ b/arch/mips/bcm63xx/dev-flash.c
@@ -60,6 +60,12 @@ static int __init bcm63xx_detect_flash_type(void)
60 u32 val; 60 u32 val;
61 61
62 switch (bcm63xx_get_cpu_id()) { 62 switch (bcm63xx_get_cpu_id()) {
63 case BCM6328_CPU_ID:
64 val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
65 if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
66 return BCM63XX_FLASH_TYPE_SERIAL;
67 else
68 return BCM63XX_FLASH_TYPE_NAND;
63 case BCM6338_CPU_ID: 69 case BCM6338_CPU_ID:
64 case BCM6345_CPU_ID: 70 case BCM6345_CPU_ID:
65 case BCM6348_CPU_ID: 71 case BCM6348_CPU_ID:
diff --git a/arch/mips/bcm63xx/dev-spi.c b/arch/mips/bcm63xx/dev-spi.c
index 67fa45b3f1cc..e39f73048d4f 100644
--- a/arch/mips/bcm63xx/dev-spi.c
+++ b/arch/mips/bcm63xx/dev-spi.c
@@ -87,7 +87,7 @@ int __init bcm63xx_spi_register(void)
87{ 87{
88 struct clk *periph_clk; 88 struct clk *periph_clk;
89 89
90 if (BCMCPU_IS_6345()) 90 if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
91 return -ENODEV; 91 return -ENODEV;
92 92
93 periph_clk = clk_get(NULL, "periph"); 93 periph_clk = clk_get(NULL, "periph");
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 9a216a451d92..18e051ad18a5 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -27,6 +27,17 @@ static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
27static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; 27static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
28 28
29#ifndef BCMCPU_RUNTIME_DETECT 29#ifndef BCMCPU_RUNTIME_DETECT
30#ifdef CONFIG_BCM63XX_CPU_6328
31#define irq_stat_reg PERF_IRQSTAT_6328_REG
32#define irq_mask_reg PERF_IRQMASK_6328_REG
33#define irq_bits 64
34#define is_ext_irq_cascaded 1
35#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
36#define ext_irq_end (BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE)
37#define ext_irq_count 4
38#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6328
39#define ext_irq_cfg_reg2 0
40#endif
30#ifdef CONFIG_BCM63XX_CPU_6338 41#ifdef CONFIG_BCM63XX_CPU_6338
31#define irq_stat_reg PERF_IRQSTAT_6338_REG 42#define irq_stat_reg PERF_IRQSTAT_6338_REG
32#define irq_mask_reg PERF_IRQMASK_6338_REG 43#define irq_mask_reg PERF_IRQMASK_6338_REG
@@ -118,6 +129,16 @@ static void bcm63xx_init_irq(void)
118 irq_mask_addr = bcm63xx_regset_address(RSET_PERF); 129 irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
119 130
120 switch (bcm63xx_get_cpu_id()) { 131 switch (bcm63xx_get_cpu_id()) {
132 case BCM6328_CPU_ID:
133 irq_stat_addr += PERF_IRQSTAT_6328_REG;
134 irq_mask_addr += PERF_IRQMASK_6328_REG;
135 irq_bits = 64;
136 ext_irq_count = 4;
137 is_ext_irq_cascaded = 1;
138 ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
139 ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
140 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
141 break;
121 case BCM6338_CPU_ID: 142 case BCM6338_CPU_ID:
122 irq_stat_addr += PERF_IRQSTAT_6338_REG; 143 irq_stat_addr += PERF_IRQSTAT_6338_REG;
123 irq_mask_addr += PERF_IRQMASK_6338_REG; 144 irq_mask_addr += PERF_IRQMASK_6338_REG;
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index 99d7f405cbeb..10eaff458071 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -26,7 +26,9 @@ void __init prom_init(void)
26 bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG); 26 bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
27 27
28 /* disable all hardware blocks clock for now */ 28 /* disable all hardware blocks clock for now */
29 if (BCMCPU_IS_6338()) 29 if (BCMCPU_IS_6328())
30 mask = CKCTL_6328_ALL_SAFE_EN;
31 else if (BCMCPU_IS_6338())
30 mask = CKCTL_6338_ALL_SAFE_EN; 32 mask = CKCTL_6338_ALL_SAFE_EN;
31 else if (BCMCPU_IS_6345()) 33 else if (BCMCPU_IS_6345())
32 mask = CKCTL_6345_ALL_SAFE_EN; 34 mask = CKCTL_6345_ALL_SAFE_EN;
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index 356b05583e14..0e74a13639cd 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void)
68 68
69 /* mask and clear all external irq */ 69 /* mask and clear all external irq */
70 switch (bcm63xx_get_cpu_id()) { 70 switch (bcm63xx_get_cpu_id()) {
71 case BCM6328_CPU_ID:
72 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
73 break;
71 case BCM6338_CPU_ID: 74 case BCM6338_CPU_ID:
72 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338; 75 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
73 break; 76 break;
@@ -95,9 +98,13 @@ void bcm63xx_machine_reboot(void)
95 bcm6348_a1_reboot(); 98 bcm6348_a1_reboot();
96 99
97 printk(KERN_INFO "triggering watchdog soft-reset...\n"); 100 printk(KERN_INFO "triggering watchdog soft-reset...\n");
98 reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG); 101 if (BCMCPU_IS_6328()) {
99 reg |= SYS_PLL_SOFT_RESET; 102 bcm_wdt_writel(1, WDT_SOFTRESET_REG);
100 bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG); 103 } else {
104 reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
105 reg |= SYS_PLL_SOFT_RESET;
106 bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
107 }
101 while (1) 108 while (1)
102 ; 109 ;
103} 110}
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 0c981aa5a013..b842b6d2ba5e 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -9,6 +9,7 @@
9 * compile time if only one CPU support is enabled (idea stolen from 9 * compile time if only one CPU support is enabled (idea stolen from
10 * arm mach-types) 10 * arm mach-types)
11 */ 11 */
12#define BCM6328_CPU_ID 0x6328
12#define BCM6338_CPU_ID 0x6338 13#define BCM6338_CPU_ID 0x6338
13#define BCM6345_CPU_ID 0x6345 14#define BCM6345_CPU_ID 0x6345
14#define BCM6348_CPU_ID 0x6348 15#define BCM6348_CPU_ID 0x6348
@@ -20,6 +21,19 @@ u16 __bcm63xx_get_cpu_id(void);
20u16 bcm63xx_get_cpu_rev(void); 21u16 bcm63xx_get_cpu_rev(void);
21unsigned int bcm63xx_get_cpu_freq(void); 22unsigned int bcm63xx_get_cpu_freq(void);
22 23
24#ifdef CONFIG_BCM63XX_CPU_6328
25# ifdef bcm63xx_get_cpu_id
26# undef bcm63xx_get_cpu_id
27# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
28# define BCMCPU_RUNTIME_DETECT
29# else
30# define bcm63xx_get_cpu_id() BCM6328_CPU_ID
31# endif
32# define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
33#else
34# define BCMCPU_IS_6328() (0)
35#endif
36
23#ifdef CONFIG_BCM63XX_CPU_6338 37#ifdef CONFIG_BCM63XX_CPU_6338
24# ifdef bcm63xx_get_cpu_id 38# ifdef bcm63xx_get_cpu_id
25# undef bcm63xx_get_cpu_id 39# undef bcm63xx_get_cpu_id
@@ -129,7 +143,8 @@ enum bcm63xx_regs_set {
129 RSET_PCMDMA, 143 RSET_PCMDMA,
130 RSET_PCMDMAC, 144 RSET_PCMDMAC,
131 RSET_PCMDMAS, 145 RSET_PCMDMAS,
132 RSET_RNG 146 RSET_RNG,
147 RSET_MISC
133}; 148};
134 149
135#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) 150#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
@@ -156,6 +171,49 @@ enum bcm63xx_regs_set {
156#define RSET_RNG_SIZE 20 171#define RSET_RNG_SIZE 20
157 172
158/* 173/*
174 * 6328 register sets base address
175 */
176#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
177#define BCM_6328_PERF_BASE (0xb0000000)
178#define BCM_6328_TIMER_BASE (0xb0000040)
179#define BCM_6328_WDT_BASE (0xb000005c)
180#define BCM_6328_UART0_BASE (0xb0000100)
181#define BCM_6328_UART1_BASE (0xb0000120)
182#define BCM_6328_GPIO_BASE (0xb0000080)
183#define BCM_6328_SPI_BASE (0xdeadbeef)
184#define BCM_6328_UDC0_BASE (0xdeadbeef)
185#define BCM_6328_USBDMA_BASE (0xdeadbeef)
186#define BCM_6328_OHCI0_BASE (0xdeadbeef)
187#define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)
188#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef)
189#define BCM_6328_MPI_BASE (0xdeadbeef)
190#define BCM_6328_PCMCIA_BASE (0xdeadbeef)
191#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
192#define BCM_6328_DSL_BASE (0xb0001900)
193#define BCM_6328_UBUS_BASE (0xdeadbeef)
194#define BCM_6328_ENET0_BASE (0xdeadbeef)
195#define BCM_6328_ENET1_BASE (0xdeadbeef)
196#define BCM_6328_ENETDMA_BASE (0xb000d800)
197#define BCM_6328_ENETDMAC_BASE (0xb000da00)
198#define BCM_6328_ENETDMAS_BASE (0xb000dc00)
199#define BCM_6328_ENETSW_BASE (0xb0e00000)
200#define BCM_6328_EHCI0_BASE (0x10002500)
201#define BCM_6328_SDRAM_BASE (0xdeadbeef)
202#define BCM_6328_MEMC_BASE (0xdeadbeef)
203#define BCM_6328_DDR_BASE (0xb0003000)
204#define BCM_6328_M2M_BASE (0xdeadbeef)
205#define BCM_6328_ATM_BASE (0xdeadbeef)
206#define BCM_6328_XTM_BASE (0xdeadbeef)
207#define BCM_6328_XTMDMA_BASE (0xb000b800)
208#define BCM_6328_XTMDMAC_BASE (0xdeadbeef)
209#define BCM_6328_XTMDMAS_BASE (0xdeadbeef)
210#define BCM_6328_PCM_BASE (0xb000a800)
211#define BCM_6328_PCMDMA_BASE (0xdeadbeef)
212#define BCM_6328_PCMDMAC_BASE (0xdeadbeef)
213#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
214#define BCM_6328_RNG_BASE (0xdeadbeef)
215#define BCM_6328_MISC_BASE (0xb0001800)
216/*
159 * 6338 register sets base address 217 * 6338 register sets base address
160 */ 218 */
161#define BCM_6338_DSL_LMEM_BASE (0xfff00000) 219#define BCM_6338_DSL_LMEM_BASE (0xfff00000)
@@ -198,6 +256,7 @@ enum bcm63xx_regs_set {
198#define BCM_6338_PCMDMAC_BASE (0xdeadbeef) 256#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
199#define BCM_6338_PCMDMAS_BASE (0xdeadbeef) 257#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
200#define BCM_6338_RNG_BASE (0xdeadbeef) 258#define BCM_6338_RNG_BASE (0xdeadbeef)
259#define BCM_6338_MISC_BASE (0xdeadbeef)
201 260
202/* 261/*
203 * 6345 register sets base address 262 * 6345 register sets base address
@@ -242,6 +301,7 @@ enum bcm63xx_regs_set {
242#define BCM_6345_PCMDMAC_BASE (0xdeadbeef) 301#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
243#define BCM_6345_PCMDMAS_BASE (0xdeadbeef) 302#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
244#define BCM_6345_RNG_BASE (0xdeadbeef) 303#define BCM_6345_RNG_BASE (0xdeadbeef)
304#define BCM_6345_MISC_BASE (0xdeadbeef)
245 305
246/* 306/*
247 * 6348 register sets base address 307 * 6348 register sets base address
@@ -283,6 +343,7 @@ enum bcm63xx_regs_set {
283#define BCM_6348_PCMDMAC_BASE (0xdeadbeef) 343#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
284#define BCM_6348_PCMDMAS_BASE (0xdeadbeef) 344#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
285#define BCM_6348_RNG_BASE (0xdeadbeef) 345#define BCM_6348_RNG_BASE (0xdeadbeef)
346#define BCM_6348_MISC_BASE (0xdeadbeef)
286 347
287/* 348/*
288 * 6358 register sets base address 349 * 6358 register sets base address
@@ -324,6 +385,7 @@ enum bcm63xx_regs_set {
324#define BCM_6358_PCMDMAC_BASE (0xfffe1900) 385#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
325#define BCM_6358_PCMDMAS_BASE (0xfffe1a00) 386#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
326#define BCM_6358_RNG_BASE (0xdeadbeef) 387#define BCM_6358_RNG_BASE (0xdeadbeef)
388#define BCM_6358_MISC_BASE (0xdeadbeef)
327 389
328 390
329/* 391/*
@@ -366,6 +428,7 @@ enum bcm63xx_regs_set {
366#define BCM_6368_PCMDMAC_BASE (0xb0005a00) 428#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
367#define BCM_6368_PCMDMAS_BASE (0xb0005c00) 429#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
368#define BCM_6368_RNG_BASE (0xb0004180) 430#define BCM_6368_RNG_BASE (0xb0004180)
431#define BCM_6368_MISC_BASE (0xdeadbeef)
369 432
370 433
371extern const unsigned long *bcm63xx_regs_base; 434extern const unsigned long *bcm63xx_regs_base;
@@ -412,6 +475,7 @@ extern const unsigned long *bcm63xx_regs_base;
412 __GEN_RSET_BASE(__cpu, PCMDMAC) \ 475 __GEN_RSET_BASE(__cpu, PCMDMAC) \
413 __GEN_RSET_BASE(__cpu, PCMDMAS) \ 476 __GEN_RSET_BASE(__cpu, PCMDMAS) \
414 __GEN_RSET_BASE(__cpu, RNG) \ 477 __GEN_RSET_BASE(__cpu, RNG) \
478 __GEN_RSET_BASE(__cpu, MISC) \
415 } 479 }
416 480
417#define __GEN_CPU_REGS_TABLE(__cpu) \ 481#define __GEN_CPU_REGS_TABLE(__cpu) \
@@ -451,6 +515,7 @@ extern const unsigned long *bcm63xx_regs_base;
451 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \ 515 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
452 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \ 516 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
453 [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \ 517 [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \
518 [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
454 519
455 520
456static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 521static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
@@ -458,6 +523,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
458#ifdef BCMCPU_RUNTIME_DETECT 523#ifdef BCMCPU_RUNTIME_DETECT
459 return bcm63xx_regs_base[set]; 524 return bcm63xx_regs_base[set];
460#else 525#else
526#ifdef CONFIG_BCM63XX_CPU_6328
527 __GEN_RSET(6328)
528#endif
461#ifdef CONFIG_BCM63XX_CPU_6338 529#ifdef CONFIG_BCM63XX_CPU_6338
462 __GEN_RSET(6338) 530 __GEN_RSET(6338)
463#endif 531#endif
@@ -512,6 +580,47 @@ enum bcm63xx_irq {
512}; 580};
513 581
514/* 582/*
583 * 6328 irqs
584 */
585#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
586
587#define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)
588#define BCM_6328_SPI_IRQ 0
589#define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28)
590#define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
591#define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
592#define BCM_6328_UDC0_IRQ 0
593#define BCM_6328_ENET0_IRQ 0
594#define BCM_6328_ENET1_IRQ 0
595#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
596#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
597#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
598#define BCM_6328_PCMCIA_IRQ 0
599#define BCM_6328_ENET0_RXDMA_IRQ 0
600#define BCM_6328_ENET0_TXDMA_IRQ 0
601#define BCM_6328_ENET1_RXDMA_IRQ 0
602#define BCM_6328_ENET1_TXDMA_IRQ 0
603#define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23)
604#define BCM_6328_ATM_IRQ 0
605#define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0)
606#define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1)
607#define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2)
608#define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3)
609#define BCM_6328_ENETSW_TXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 4)
610#define BCM_6328_ENETSW_TXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 5)
611#define BCM_6328_ENETSW_TXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 6)
612#define BCM_6328_ENETSW_TXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
613#define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31)
614#define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11)
615
616#define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)
617#define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)
618#define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)
619#define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)
620#define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)
621#define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)
622
623/*
515 * 6338 irqs 624 * 6338 irqs
516 */ 625 */
517#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 626#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 1d7dd96aa460..0a9891f7580d 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void);
9static inline unsigned long bcm63xx_gpio_count(void) 9static inline unsigned long bcm63xx_gpio_count(void)
10{ 10{
11 switch (bcm63xx_get_cpu_id()) { 11 switch (bcm63xx_get_cpu_id()) {
12 case BCM6328_CPU_ID:
13 return 32;
12 case BCM6358_CPU_ID: 14 case BCM6358_CPU_ID:
13 return 40; 15 return 40;
14 case BCM6338_CPU_ID: 16 case BCM6338_CPU_ID:
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
index 72477a6441dd..6dcd8b23592b 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -91,5 +91,7 @@
91#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o)) 91#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o))
92#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o)) 92#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o))
93#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o)) 93#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
94#define bcm_misc_readl(o) bcm_rset_readl(RSET_MISC, (o))
95#define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o))
94 96
95#endif /* ! BCM63XX_IO_H_ */ 97#endif /* ! BCM63XX_IO_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 849fd97e7798..4fc2ab2c278a 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -15,6 +15,30 @@
15/* Clock Control register */ 15/* Clock Control register */
16#define PERF_CKCTL_REG 0x4 16#define PERF_CKCTL_REG 0x4
17 17
18#define CKCTL_6328_PHYMIPS_EN (1 << 0)
19#define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
20#define CKCTL_6328_ADSL_AFE_EN (1 << 2)
21#define CKCTL_6328_ADSL_EN (1 << 3)
22#define CKCTL_6328_MIPS_EN (1 << 4)
23#define CKCTL_6328_SAR_EN (1 << 5)
24#define CKCTL_6328_PCM_EN (1 << 6)
25#define CKCTL_6328_USBD_EN (1 << 7)
26#define CKCTL_6328_USBH_EN (1 << 8)
27#define CKCTL_6328_HSSPI_EN (1 << 9)
28#define CKCTL_6328_PCIE_EN (1 << 10)
29#define CKCTL_6328_ROBOSW_EN (1 << 11)
30
31#define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \
32 CKCTL_6328_ADSL_QPROC_EN | \
33 CKCTL_6328_ADSL_AFE_EN | \
34 CKCTL_6328_ADSL_EN | \
35 CKCTL_6328_SAR_EN | \
36 CKCTL_6328_PCM_EN | \
37 CKCTL_6328_USBD_EN | \
38 CKCTL_6328_USBH_EN | \
39 CKCTL_6328_ROBOSW_EN | \
40 CKCTL_6328_PCIE_EN)
41
18#define CKCTL_6338_ADSLPHY_EN (1 << 0) 42#define CKCTL_6338_ADSLPHY_EN (1 << 0)
19#define CKCTL_6338_MPI_EN (1 << 1) 43#define CKCTL_6338_MPI_EN (1 << 1)
20#define CKCTL_6338_DRAM_EN (1 << 2) 44#define CKCTL_6338_DRAM_EN (1 << 2)
@@ -119,6 +143,7 @@
119#define SYS_PLL_SOFT_RESET 0x1 143#define SYS_PLL_SOFT_RESET 0x1
120 144
121/* Interrupt Mask register */ 145/* Interrupt Mask register */
146#define PERF_IRQMASK_6328_REG 0x20
122#define PERF_IRQMASK_6338_REG 0xc 147#define PERF_IRQMASK_6338_REG 0xc
123#define PERF_IRQMASK_6345_REG 0xc 148#define PERF_IRQMASK_6345_REG 0xc
124#define PERF_IRQMASK_6348_REG 0xc 149#define PERF_IRQMASK_6348_REG 0xc
@@ -126,6 +151,7 @@
126#define PERF_IRQMASK_6368_REG 0x20 151#define PERF_IRQMASK_6368_REG 0x20
127 152
128/* Interrupt Status register */ 153/* Interrupt Status register */
154#define PERF_IRQSTAT_6328_REG 0x28
129#define PERF_IRQSTAT_6338_REG 0x10 155#define PERF_IRQSTAT_6338_REG 0x10
130#define PERF_IRQSTAT_6345_REG 0x10 156#define PERF_IRQSTAT_6345_REG 0x10
131#define PERF_IRQSTAT_6348_REG 0x10 157#define PERF_IRQSTAT_6348_REG 0x10
@@ -133,6 +159,7 @@
133#define PERF_IRQSTAT_6368_REG 0x28 159#define PERF_IRQSTAT_6368_REG 0x28
134 160
135/* External Interrupt Configuration register */ 161/* External Interrupt Configuration register */
162#define PERF_EXTIRQ_CFG_REG_6328 0x18
136#define PERF_EXTIRQ_CFG_REG_6338 0x14 163#define PERF_EXTIRQ_CFG_REG_6338 0x14
137#define PERF_EXTIRQ_CFG_REG_6348 0x14 164#define PERF_EXTIRQ_CFG_REG_6348 0x14
138#define PERF_EXTIRQ_CFG_REG_6358 0x14 165#define PERF_EXTIRQ_CFG_REG_6358 0x14
@@ -162,8 +189,21 @@
162 189
163/* Soft Reset register */ 190/* Soft Reset register */
164#define PERF_SOFTRESET_REG 0x28 191#define PERF_SOFTRESET_REG 0x28
192#define PERF_SOFTRESET_6328_REG 0x10
165#define PERF_SOFTRESET_6368_REG 0x10 193#define PERF_SOFTRESET_6368_REG 0x10
166 194
195#define SOFTRESET_6328_SPI_MASK (1 << 0)
196#define SOFTRESET_6328_EPHY_MASK (1 << 1)
197#define SOFTRESET_6328_SAR_MASK (1 << 2)
198#define SOFTRESET_6328_ENETSW_MASK (1 << 3)
199#define SOFTRESET_6328_USBS_MASK (1 << 4)
200#define SOFTRESET_6328_USBH_MASK (1 << 5)
201#define SOFTRESET_6328_PCM_MASK (1 << 6)
202#define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7)
203#define SOFTRESET_6328_PCIE_MASK (1 << 8)
204#define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9)
205#define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10)
206
167#define SOFTRESET_6338_SPI_MASK (1 << 0) 207#define SOFTRESET_6338_SPI_MASK (1 << 0)
168#define SOFTRESET_6338_ENET_MASK (1 << 2) 208#define SOFTRESET_6338_ENET_MASK (1 << 2)
169#define SOFTRESET_6338_USBH_MASK (1 << 3) 209#define SOFTRESET_6338_USBH_MASK (1 << 3)
@@ -307,6 +347,8 @@
307/* Watchdog reset length register */ 347/* Watchdog reset length register */
308#define WDT_RSTLEN_REG 0x8 348#define WDT_RSTLEN_REG 0x8
309 349
350/* Watchdog soft reset register (BCM6328 only) */
351#define WDT_SOFTRESET_REG 0xc
310 352
311/************************************************************************* 353/*************************************************************************
312 * _REG relative to RSET_UARTx 354 * _REG relative to RSET_UARTx
@@ -933,6 +975,8 @@
933 * _REG relative to RSET_DDR 975 * _REG relative to RSET_DDR
934 *************************************************************************/ 976 *************************************************************************/
935 977
978#define DDR_CSEND_REG 0x8
979
936#define DDR_DMIPSPLLCFG_REG 0x18 980#define DDR_DMIPSPLLCFG_REG 0x18
937#define DMIPSPLLCFG_M1_SHIFT 0 981#define DMIPSPLLCFG_M1_SHIFT 0
938#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT) 982#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
@@ -1115,4 +1159,14 @@
1115#define SPI_SSOFFTIME_SHIFT 3 1159#define SPI_SSOFFTIME_SHIFT 3
1116#define SPI_BYTE_SWAP 0x80 1160#define SPI_BYTE_SWAP 0x80
1117 1161
1162/*************************************************************************
1163 * _REG relative to RSET_MISC
1164 *************************************************************************/
1165
1166#define MISC_STRAPBUS_6328_REG 0x240
1167#define STRAPBUS_6328_FCVO_SHIFT 7
1168#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
1169#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
1170#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
1171
1118#endif /* BCM63XX_REGS_H_ */ 1172#endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
index ef94ba73646e..30931c42379d 100644
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -18,6 +18,7 @@ static inline int is_bcm63xx_internal_registers(phys_t offset)
18 if (offset >= 0xfff00000) 18 if (offset >= 0xfff00000)
19 return 1; 19 return 1;
20 break; 20 break;
21 case BCM6328_CPU_ID:
21 case BCM6368_CPU_ID: 22 case BCM6368_CPU_ID:
22 if (offset >= 0xb0000000 && offset < 0xb1000000) 23 if (offset >= 0xb0000000 && offset < 0xb1000000)
23 return 1; 24 return 1;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 14:52:27 -0500