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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2013-02-19 14:21:46 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-03-04 17:16:57 -0500
commitdc0fa7181132b1fde269accc4e067b8b833f34ef (patch)
tree376bbc9ee110b3f56ed7ff84358537b1b62ff9b7
parentc20cd31252554b927ae1cce1c71ae8a769b1bd74 (diff)
drm/i915: remove duplicated SDVO/HDMI bit definitions
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h17
-rw-r--r--drivers/gpu/drm/i915/intel_display.c18
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c23
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c16
4 files changed, 29 insertions, 45 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 330b64d2614a..f62e4e5014bc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1693,6 +1693,8 @@
1693 1693
1694/* Gen 3 SDVO bits: */ 1694/* Gen 3 SDVO bits: */
1695#define SDVO_ENABLE (1 << 31) 1695#define SDVO_ENABLE (1 << 31)
1696#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
1697#define SDVO_PIPE_SEL_MASK (1 << 30)
1696#define SDVO_PIPE_B_SELECT (1 << 30) 1698#define SDVO_PIPE_B_SELECT (1 << 30)
1697#define SDVO_STALL_SELECT (1 << 29) 1699#define SDVO_STALL_SELECT (1 << 29)
1698#define SDVO_INTERRUPT_ENABLE (1 << 26) 1700#define SDVO_INTERRUPT_ENABLE (1 << 26)
@@ -1719,7 +1721,8 @@
1719#define COLOR_FORMAT_8bpc (0 << 26) 1721#define COLOR_FORMAT_8bpc (0 << 26)
1720#define SDVO_ENCODING_SDVO (0 << 10) 1722#define SDVO_ENCODING_SDVO (0 << 10)
1721#define SDVO_ENCODING_HDMI (2 << 10) 1723#define SDVO_ENCODING_HDMI (2 << 10)
1722#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) /* HDMI only */ 1724#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
1725#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
1723#define SDVO_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 1726#define SDVO_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
1724#define SDVO_AUDIO_ENABLE (1 << 6) 1727#define SDVO_AUDIO_ENABLE (1 << 6)
1725/* VSYNC/HSYNC bits new with 965, default is to be set */ 1728/* VSYNC/HSYNC bits new with 965, default is to be set */
@@ -1731,16 +1734,8 @@
1731#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 1734#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
1732 1735
1733/* Gen 6 (CPT) SDVO/HDMI bits: */ 1736/* Gen 6 (CPT) SDVO/HDMI bits: */
1734#define TRANSCODER_CPT(pipe) ((pipe) << 29) 1737#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
1735#define TRANSCODER_MASK_CPT (3 << 29) 1738#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
1736
1737/* Repeated but still used bits: */
1738#define PORT_ENABLE (1 << 31)
1739#define TRANSCODER(pipe) ((pipe) << 30)
1740#define TRANSCODER_MASK (1 << 30)
1741#define HDMI_MODE_SELECT (1 << 9)
1742#define DVI_MODE_SELECT (0 << 9)
1743#define PORT_DETECTED (1 << 2)
1744 1739
1745 1740
1746/* DVO port control */ 1741/* DVO port control */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1048046fcb6e..502cb28a46c9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1340,14 +1340,14 @@ static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1340static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, 1340static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val) 1341 enum pipe pipe, u32 val)
1342{ 1342{
1343 if ((val & PORT_ENABLE) == 0) 1343 if ((val & SDVO_ENABLE) == 0)
1344 return false; 1344 return false;
1345 1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) { 1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1347 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1348 return false; 1348 return false;
1349 } else { 1349 } else {
1350 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) 1350 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1351 return false; 1351 return false;
1352 } 1352 }
1353 return true; 1353 return true;
@@ -1405,7 +1405,7 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1405 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", 1405 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1406 reg, pipe_name(pipe)); 1406 reg, pipe_name(pipe));
1407 1407
1408 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0 1408 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1409 && (val & SDVO_PIPE_B_SELECT), 1409 && (val & SDVO_PIPE_B_SELECT),
1410 "IBX PCH hdmi port still using transcoder B\n"); 1410 "IBX PCH hdmi port still using transcoder B\n");
1411} 1411}
@@ -8352,7 +8352,7 @@ static void intel_setup_outputs(struct drm_device *dev)
8352 if (has_edp_a(dev)) 8352 if (has_edp_a(dev))
8353 intel_dp_init(dev, DP_A, PORT_A); 8353 intel_dp_init(dev, DP_A, PORT_A);
8354 8354
8355 if (I915_READ(PCH_HDMIB) & PORT_DETECTED) { 8355 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8356 /* PCH SDVOB multiplex with HDMIB */ 8356 /* PCH SDVOB multiplex with HDMIB */
8357 found = intel_sdvo_init(dev, PCH_SDVOB, true); 8357 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8358 if (!found) 8358 if (!found)
@@ -8361,10 +8361,10 @@ static void intel_setup_outputs(struct drm_device *dev)
8361 intel_dp_init(dev, PCH_DP_B, PORT_B); 8361 intel_dp_init(dev, PCH_DP_B, PORT_B);
8362 } 8362 }
8363 8363
8364 if (I915_READ(PCH_HDMIC) & PORT_DETECTED) 8364 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8365 intel_hdmi_init(dev, PCH_HDMIC, PORT_C); 8365 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8366 8366
8367 if (!dpd_is_edp && I915_READ(PCH_HDMID) & PORT_DETECTED) 8367 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8368 intel_hdmi_init(dev, PCH_HDMID, PORT_D); 8368 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8369 8369
8370 if (I915_READ(PCH_DP_C) & DP_DETECTED) 8370 if (I915_READ(PCH_DP_C) & DP_DETECTED)
@@ -8377,14 +8377,14 @@ static void intel_setup_outputs(struct drm_device *dev)
8377 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) 8377 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8378 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); 8378 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8379 8379
8380 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & PORT_DETECTED) { 8380 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8381 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, 8381 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8382 PORT_B); 8382 PORT_B);
8383 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) 8383 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8384 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); 8384 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8385 } 8385 }
8386 8386
8387 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & PORT_DETECTED) 8387 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
8388 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, 8388 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
8389 PORT_C); 8389 PORT_C);
8390 8390
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 6046db0e9f8a..0b42ba31d402 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -615,20 +615,20 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder,
615 615
616 /* Required on CPT */ 616 /* Required on CPT */
617 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) 617 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
618 hdmi_val |= HDMI_MODE_SELECT; 618 hdmi_val |= HDMI_MODE_SELECT_HDMI;
619 619
620 if (intel_hdmi->has_audio) { 620 if (intel_hdmi->has_audio) {
621 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 621 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
622 pipe_name(intel_crtc->pipe)); 622 pipe_name(intel_crtc->pipe));
623 hdmi_val |= SDVO_AUDIO_ENABLE; 623 hdmi_val |= SDVO_AUDIO_ENABLE;
624 hdmi_val |= SDVO_NULL_PACKETS_DURING_VSYNC; 624 hdmi_val |= HDMI_MODE_SELECT_HDMI;
625 intel_write_eld(encoder, adjusted_mode); 625 intel_write_eld(encoder, adjusted_mode);
626 } 626 }
627 627
628 if (HAS_PCH_CPT(dev)) 628 if (HAS_PCH_CPT(dev))
629 hdmi_val |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); 629 hdmi_val |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
630 else if (intel_crtc->pipe == PIPE_B) 630 else
631 hdmi_val |= SDVO_PIPE_B_SELECT; 631 hdmi_val |= SDVO_PIPE_SEL(intel_crtc->pipe);
632 632
633 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); 633 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
634 POSTING_READ(intel_hdmi->hdmi_reg); 634 POSTING_READ(intel_hdmi->hdmi_reg);
@@ -661,6 +661,7 @@ static void intel_enable_hdmi(struct intel_encoder *encoder)
661{ 661{
662 struct drm_device *dev = encoder->base.dev; 662 struct drm_device *dev = encoder->base.dev;
663 struct drm_i915_private *dev_priv = dev->dev_private; 663 struct drm_i915_private *dev_priv = dev->dev_private;
664 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
664 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 665 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
665 u32 temp; 666 u32 temp;
666 u32 enable_bits = SDVO_ENABLE; 667 u32 enable_bits = SDVO_ENABLE;
@@ -671,15 +672,9 @@ static void intel_enable_hdmi(struct intel_encoder *encoder)
671 temp = I915_READ(intel_hdmi->hdmi_reg); 672 temp = I915_READ(intel_hdmi->hdmi_reg);
672 673
673 /* HW workaround for IBX, we need to move the port to transcoder A 674 /* HW workaround for IBX, we need to move the port to transcoder A
674 * before disabling it. */ 675 * before disabling it, so restore the transcoder select bit here. */
675 if (HAS_PCH_IBX(dev)) { 676 if (HAS_PCH_IBX(dev))
676 struct drm_crtc *crtc = encoder->base.crtc; 677 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
677 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
678
679 /* Restore the transcoder select bit. */
680 if (pipe == PIPE_B)
681 enable_bits |= SDVO_PIPE_B_SELECT;
682 }
683 678
684 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 679 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
685 * we do this anyway which shows more stable in testing. 680 * we do this anyway which shows more stable in testing.
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 7d94db8559ee..eef073114f7a 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1193,9 +1193,9 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1193 } 1193 }
1194 1194
1195 if (INTEL_PCH_TYPE(dev) >= PCH_CPT) 1195 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1196 sdvox |= TRANSCODER_CPT(intel_crtc->pipe); 1196 sdvox |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
1197 else 1197 else
1198 sdvox |= TRANSCODER(intel_crtc->pipe); 1198 sdvox |= SDVO_PIPE_SEL(intel_crtc->pipe);
1199 1199
1200 if (intel_sdvo->has_hdmi_audio) 1200 if (intel_sdvo->has_hdmi_audio)
1201 sdvox |= SDVO_AUDIO_ENABLE; 1201 sdvox |= SDVO_AUDIO_ENABLE;
@@ -1305,15 +1305,9 @@ static void intel_enable_sdvo(struct intel_encoder *encoder)
1305 temp = I915_READ(intel_sdvo->sdvo_reg); 1305 temp = I915_READ(intel_sdvo->sdvo_reg);
1306 if ((temp & SDVO_ENABLE) == 0) { 1306 if ((temp & SDVO_ENABLE) == 0) {
1307 /* HW workaround for IBX, we need to move the port 1307 /* HW workaround for IBX, we need to move the port
1308 * to transcoder A before disabling it. */ 1308 * to transcoder A before disabling it, so restore it here. */
1309 if (HAS_PCH_IBX(dev)) { 1309 if (HAS_PCH_IBX(dev))
1310 struct drm_crtc *crtc = encoder->base.crtc; 1310 temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
1311 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1312
1313 /* Restore the transcoder select bit. */
1314 if (pipe == PIPE_B)
1315 temp |= SDVO_PIPE_B_SELECT;
1316 }
1317 1311
1318 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); 1312 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
1319 } 1313 }