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authorRobby Cai <R63905@freescale.com>2013-08-07 23:23:54 -0400
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:01:12 -0400
commitda0159b2d580a21c8c79ffdd1acbf528d8f87dce (patch)
tree42aeb51134bbdb6df2a0600c64d78b72ab4d3c4e
parentd76bb18bc03b64924401eeb9e884ff65ab3b0f54 (diff)
ENGR00274412-1 dma: pxp: Port ePxP driver to 3.10
It's ported from v3.5.7, which contains ePxP DMAENGINE driver and a client driver named pxp_device. This patch also includes the changes: - use uapi header file - remove VM_RESERVED since it's deprecated, and drop redundant VM_IO flag since it's automatically set in remap_pfn_range() - use <linux/platform_data/dma-imx.h> instead of <mach/dma.h> - use devm_kzalloc() instead in pxp_probe() - use macro __KERNEL__ in pxp_dma uapi header to avoid definition conflict Signed-off-by: Robby Cai <R63905@freescale.com>
Diffstat
-rw-r--r--drivers/dma/Kconfig13
-rw-r--r--drivers/dma/Makefile1
-rw-r--r--drivers/dma/pxp/Makefile2
-rw-r--r--drivers/dma/pxp/pxp_device.c491
-rw-r--r--drivers/dma/pxp/pxp_dma_v2.c1680
-rw-r--r--drivers/dma/pxp/regs-pxp_v2.h1152
-rw-r--r--include/linux/platform_data/dma-imx.h7
-rw-r--r--include/uapi/linux/pxp_dma.h2
8 files changed, 3347 insertions, 1 deletions
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 0ba5a95199d3..63197bdcc66d 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -152,6 +152,19 @@ config MX3_IPU_IRQS
152 To avoid bloating the irq_desc[] array we allocate a sufficient 152 To avoid bloating the irq_desc[] array we allocate a sufficient
153 number of IRQ slots and map them dynamically to specific sources. 153 number of IRQ slots and map them dynamically to specific sources.
154 154
155config MXC_PXP_V2
156 bool "MXC PxP V2 support"
157 depends on ARM
158 select DMA_ENGINE
159 help
160 Support the PxP (Pixel Pipeline) on i.MX6 DualLite and i.MX6 SoloLite.
161 If unsure, select N.
162
163config MXC_PXP_CLIENT_DEVICE
164 bool "MXC PxP Client Device"
165 default y
166 depends on MXC_PXP_V2
167
155config TXX9_DMAC 168config TXX9_DMAC
156 tristate "Toshiba TXx9 SoC DMA support" 169 tristate "Toshiba TXx9 SoC DMA support"
157 depends on MACH_TX49XX || MACH_TX39XX 170 depends on MACH_TX49XX || MACH_TX39XX
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index a2b0df591f95..2bbd7560595f 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_MV_XOR) += mv_xor.o
18obj-$(CONFIG_DW_DMAC) += dw_dmac.o 18obj-$(CONFIG_DW_DMAC) += dw_dmac.o
19obj-$(CONFIG_AT_HDMAC) += at_hdmac.o 19obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
20obj-$(CONFIG_MX3_IPU) += ipu/ 20obj-$(CONFIG_MX3_IPU) += ipu/
21obj-$(CONFIG_MXC_PXP_V2) += pxp/
21obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o 22obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
22obj-$(CONFIG_SH_DMAE_BASE) += sh/ 23obj-$(CONFIG_SH_DMAE_BASE) += sh/
23obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o 24obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
diff --git a/drivers/dma/pxp/Makefile b/drivers/dma/pxp/Makefile
new file mode 100644
index 000000000000..498cccaefeea
--- /dev/null
+++ b/drivers/dma/pxp/Makefile
@@ -0,0 +1,2 @@
1obj-$(CONFIG_MXC_PXP_V2) += pxp_dma_v2.o
2obj-$(CONFIG_MXC_PXP_CLIENT_DEVICE) += pxp_device.o
diff --git a/drivers/dma/pxp/pxp_device.c b/drivers/dma/pxp/pxp_device.c
new file mode 100644
index 000000000000..140dce0a99f6
--- /dev/null
+++ b/drivers/dma/pxp/pxp_device.c
@@ -0,0 +1,491 @@
1/*
2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 */
19#include <linux/interrupt.h>
20#include <linux/miscdevice.h>
21#include <linux/platform_device.h>
22#include <linux/fs.h>
23#include <linux/slab.h>
24#include <linux/uaccess.h>
25#include <linux/delay.h>
26#include <linux/dmaengine.h>
27#include <linux/dma-mapping.h>
28#include <linux/sched.h>
29#include <linux/module.h>
30#include <linux/pxp_dma.h>
31#include <linux/atomic.h>
32#include <linux/platform_data/dma-imx.h>
33
34static atomic_t open_count = ATOMIC_INIT(0);
35
36static DEFINE_SPINLOCK(pxp_mem_lock);
37static DEFINE_SPINLOCK(pxp_chan_lock);
38static LIST_HEAD(head);
39static LIST_HEAD(list);
40static struct pxp_irq_info irq_info[NR_PXP_VIRT_CHANNEL];
41
42struct pxp_chan_handle {
43 int chan_id;
44 int hist_status;
45};
46
47/* To track the allocated memory buffer */
48struct memalloc_record {
49 struct list_head list;
50 struct pxp_mem_desc mem;
51};
52
53struct pxp_chan_info {
54 int chan_id;
55 struct dma_chan *dma_chan;
56 struct list_head list;
57};
58
59static int pxp_alloc_dma_buffer(struct pxp_mem_desc *mem)
60{
61 mem->cpu_addr = (unsigned long)
62 dma_alloc_coherent(NULL, PAGE_ALIGN(mem->size),
63 (dma_addr_t *) (&mem->phys_addr),
64 GFP_DMA | GFP_KERNEL);
65 pr_debug("[ALLOC] mem alloc phys_addr = 0x%x\n", mem->phys_addr);
66 if ((void *)(mem->cpu_addr) == NULL) {
67 printk(KERN_ERR "Physical memory allocation error!\n");
68 return -1;
69 }
70 return 0;
71}
72
73static void pxp_free_dma_buffer(struct pxp_mem_desc *mem)
74{
75 if (mem->cpu_addr != 0) {
76 dma_free_coherent(0, PAGE_ALIGN(mem->size),
77 (void *)mem->cpu_addr, mem->phys_addr);
78 }
79}
80
81static int pxp_free_buffers(void)
82{
83 struct memalloc_record *rec, *n;
84 struct pxp_mem_desc mem;
85
86 list_for_each_entry_safe(rec, n, &head, list) {
87 mem = rec->mem;
88 if (mem.cpu_addr != 0) {
89 pxp_free_dma_buffer(&mem);
90 pr_debug("[FREE] freed paddr=0x%08X\n", mem.phys_addr);
91 /* delete from list */
92 list_del(&rec->list);
93 kfree(rec);
94 }
95 }
96
97 return 0;
98}
99
100/* Callback function triggered after PxP receives an EOF interrupt */
101static void pxp_dma_done(void *arg)
102{
103 struct pxp_tx_desc *tx_desc = to_tx_desc(arg);
104 struct dma_chan *chan = tx_desc->txd.chan;
105 struct pxp_channel *pxp_chan = to_pxp_channel(chan);
106 int chan_id = pxp_chan->dma_chan.chan_id;
107
108 pr_debug("DMA Done ISR, chan_id %d\n", chan_id);
109
110 irq_info[chan_id].irq_pending++;
111 irq_info[chan_id].hist_status = tx_desc->hist_status;
112
113 wake_up_interruptible(&(irq_info[chan_id].waitq));
114}
115
116static int pxp_ioc_config_chan(unsigned long arg)
117{
118 struct scatterlist sg[3];
119 struct pxp_tx_desc *desc;
120 struct dma_async_tx_descriptor *txd;
121 struct pxp_chan_info *info;
122 struct pxp_config_data pxp_conf;
123 dma_cookie_t cookie;
124 int chan_id;
125 int i, length, ret;
126
127 ret = copy_from_user(&pxp_conf,
128 (struct pxp_config_data *)arg,
129 sizeof(struct pxp_config_data));
130 if (ret)
131 return -EFAULT;
132
133 chan_id = pxp_conf.chan_id;
134 if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL)
135 return -ENODEV;
136
137 init_waitqueue_head(&(irq_info[chan_id].waitq));
138
139 /* find the channel */
140 spin_lock(&pxp_chan_lock);
141 list_for_each_entry(info, &list, list) {
142 if (info->dma_chan->chan_id == chan_id)
143 break;
144 }
145 spin_unlock(&pxp_chan_lock);
146
147 sg_init_table(sg, 3);
148
149 txd =
150 info->dma_chan->device->device_prep_slave_sg(info->dma_chan,
151 sg, 3,
152 DMA_TO_DEVICE,
153 DMA_PREP_INTERRUPT,
154 NULL);
155 if (!txd) {
156 pr_err("Error preparing a DMA transaction descriptor.\n");
157 return -EIO;
158 }
159
160 txd->callback_param = txd;
161 txd->callback = pxp_dma_done;
162
163 desc = to_tx_desc(txd);
164
165 length = desc->len;
166 for (i = 0; i < length; i++) {
167 if (i == 0) { /* S0 */
168 memcpy(&desc->proc_data,
169 &pxp_conf.proc_data,
170 sizeof(struct pxp_proc_data));
171 memcpy(&desc->layer_param.s0_param,
172 &pxp_conf.s0_param,
173 sizeof(struct pxp_layer_param));
174 } else if (i == 1) { /* Output */
175 memcpy(&desc->layer_param.out_param,
176 &pxp_conf.out_param,
177 sizeof(struct pxp_layer_param));
178 } else {
179 /* OverLay */
180 memcpy(&desc->layer_param.ol_param,
181 &pxp_conf.ol_param,
182 sizeof(struct pxp_layer_param));
183 }
184
185 desc = desc->next;
186 }
187
188 cookie = txd->tx_submit(txd);
189 if (cookie < 0) {
190 pr_err("Error tx_submit\n");
191 return -EIO;
192 }
193
194 return 0;
195}
196
197static int pxp_device_open(struct inode *inode, struct file *filp)
198{
199 atomic_inc(&open_count);
200
201 return 0;
202}
203
204static int pxp_device_release(struct inode *inode, struct file *filp)
205{
206 if (atomic_dec_and_test(&open_count))
207 pxp_free_buffers();
208
209 return 0;
210}
211
212static int pxp_device_mmap(struct file *file, struct vm_area_struct *vma)
213{
214 struct memalloc_record *rec, *n;
215 int request_size, found;
216
217 request_size = vma->vm_end - vma->vm_start;
218 found = 0;
219
220 pr_debug("start=0x%x, pgoff=0x%x, size=0x%x\n",
221 (unsigned int)(vma->vm_start), (unsigned int)(vma->vm_pgoff),
222 request_size);
223
224 spin_lock(&pxp_mem_lock);
225 list_for_each_entry_safe(rec, n, &head, list) {
226 if (rec->mem.phys_addr == (vma->vm_pgoff << PAGE_SHIFT) &&
227 (rec->mem.size <= request_size)) {
228 found = 1;
229 break;
230 }
231 }
232 spin_unlock(&pxp_mem_lock);
233
234 if (found == 0)
235 return -ENOMEM;
236
237 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
238
239 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
240 request_size, vma->vm_page_prot) ? -EAGAIN : 0;
241}
242
243static bool chan_filter(struct dma_chan *chan, void *arg)
244{
245 if (imx_dma_is_pxp(chan))
246 return true;
247 else
248 return false;
249}
250
251static long pxp_device_ioctl(struct file *filp,
252 unsigned int cmd, unsigned long arg)
253{
254 int ret = 0;
255
256 switch (cmd) {
257 case PXP_IOC_GET_CHAN:
258 {
259 struct pxp_chan_info *info;
260 dma_cap_mask_t mask;
261
262 pr_debug("drv: PXP_IOC_GET_CHAN Line %d\n", __LINE__);
263 info = kzalloc(sizeof(*info), GFP_KERNEL);
264 if (!info) {
265 pr_err("%d: alloc err\n", __LINE__);
266 return -ENOMEM;
267 }
268
269 dma_cap_zero(mask);
270 dma_cap_set(DMA_SLAVE, mask);
271 dma_cap_set(DMA_PRIVATE, mask);
272 info->dma_chan =
273 dma_request_channel(mask, chan_filter, NULL);
274 if (!info->dma_chan) {
275 pr_err("Unsccessfully received channel!\n");
276 kfree(info);
277 return -EBUSY;
278 }
279 pr_debug("Successfully received channel."
280 "chan_id %d\n", info->dma_chan->chan_id);
281
282 spin_lock(&pxp_chan_lock);
283 list_add_tail(&info->list, &list);
284 spin_unlock(&pxp_chan_lock);
285
286 if (put_user
287 (info->dma_chan->chan_id, (u32 __user *) arg))
288 return -EFAULT;
289
290 break;
291 }
292 case PXP_IOC_PUT_CHAN:
293 {
294 int chan_id;
295 struct pxp_chan_info *info;
296
297 if (get_user(chan_id, (u32 __user *) arg))
298 return -EFAULT;
299
300 if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL)
301 return -ENODEV;
302
303 spin_lock(&pxp_chan_lock);
304 list_for_each_entry(info, &list, list) {
305 if (info->dma_chan->chan_id == chan_id)
306 break;
307 }
308 spin_unlock(&pxp_chan_lock);
309
310 pr_debug("%d release chan_id %d\n", __LINE__,
311 info->dma_chan->chan_id);
312 /* REVISIT */
313 dma_release_channel(info->dma_chan);
314 spin_lock(&pxp_chan_lock);
315 list_del_init(&info->list);
316 spin_unlock(&pxp_chan_lock);
317 kfree(info);
318
319 break;
320 }
321 case PXP_IOC_CONFIG_CHAN:
322 {
323
324 int ret;
325
326 ret = pxp_ioc_config_chan(arg);
327 if (ret)
328 return ret;
329
330 break;
331 }
332 case PXP_IOC_START_CHAN:
333 {
334 struct pxp_chan_info *info;
335 int chan_id;
336
337 if (get_user(chan_id, (u32 __user *) arg))
338 return -EFAULT;
339
340 /* find the channel */
341 spin_lock(&pxp_chan_lock);
342 list_for_each_entry(info, &list, list) {
343 if (info->dma_chan->chan_id == chan_id)
344 break;
345 }
346 spin_unlock(&pxp_chan_lock);
347
348 dma_async_issue_pending(info->dma_chan);
349
350 break;
351 }
352 case PXP_IOC_GET_PHYMEM:
353 {
354 struct memalloc_record *rec;
355
356 rec = kzalloc(sizeof(*rec), GFP_KERNEL);
357 if (!rec)
358 return -ENOMEM;
359
360 ret = copy_from_user(&(rec->mem),
361 (struct pxp_mem_desc *)arg,
362 sizeof(struct pxp_mem_desc));
363 if (ret) {
364 kfree(rec);
365 return -EFAULT;
366 }
367
368 pr_debug("[ALLOC] mem alloc size = 0x%x\n",
369 rec->mem.size);
370
371 ret = pxp_alloc_dma_buffer(&(rec->mem));
372 if (ret == -1) {
373 kfree(rec);
374 printk(KERN_ERR
375 "Physical memory allocation error!\n");
376 break;
377 }
378 ret = copy_to_user((void __user *)arg, &(rec->mem),
379 sizeof(struct pxp_mem_desc));
380 if (ret) {
381 kfree(rec);
382 ret = -EFAULT;
383 break;
384 }
385
386 spin_lock(&pxp_mem_lock);
387 list_add(&rec->list, &head);
388 spin_unlock(&pxp_mem_lock);
389
390 break;
391 }
392 case PXP_IOC_PUT_PHYMEM:
393 {
394 struct memalloc_record *rec, *n;
395 struct pxp_mem_desc pxp_mem;
396
397 ret = copy_from_user(&pxp_mem,
398 (struct pxp_mem_desc *)arg,
399 sizeof(struct pxp_mem_desc));
400 if (ret)
401 return -EACCES;
402
403 pr_debug("[FREE] mem freed cpu_addr = 0x%x\n",
404 pxp_mem.cpu_addr);
405 if ((void *)pxp_mem.cpu_addr != NULL)
406 pxp_free_dma_buffer(&pxp_mem);
407
408 spin_lock(&pxp_mem_lock);
409 list_for_each_entry_safe(rec, n, &head, list) {
410 if (rec->mem.cpu_addr == pxp_mem.cpu_addr) {
411 /* delete from list */
412 list_del(&rec->list);
413 kfree(rec);
414 break;
415 }
416 }
417 spin_unlock(&pxp_mem_lock);
418
419 break;
420 }
421 case PXP_IOC_WAIT4CMPLT:
422 {
423 struct pxp_chan_handle chan_handle;
424 int ret, chan_id;
425
426 ret = copy_from_user(&chan_handle,
427 (struct pxp_chan_handle *)arg,
428 sizeof(struct pxp_chan_handle));
429 if (ret)
430 return -EFAULT;
431
432 chan_id = chan_handle.chan_id;
433 if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL)
434 return -ENODEV;
435
436 if (!wait_event_interruptible_timeout
437 (irq_info[chan_id].waitq,
438 (irq_info[chan_id].irq_pending != 0), 2 * HZ)) {
439 pr_warning("pxp blocking: timeout.\n");
440 return -ETIME;
441 } else if (signal_pending(current)) {
442 printk(KERN_WARNING
443 "pxp interrupt received.\n");
444 return -ERESTARTSYS;
445 } else
446 irq_info[chan_id].irq_pending--;
447
448 chan_handle.hist_status = irq_info[chan_id].hist_status;
449 ret = copy_to_user((struct pxp_chan_handle *)arg,
450 &chan_handle,
451 sizeof(struct pxp_chan_handle));
452 if (ret)
453 return -EFAULT;
454 break;
455 }
456 default:
457 break;
458 }
459
460 return 0;
461}
462
463static const struct file_operations pxp_device_fops = {
464 .open = pxp_device_open,
465 .release = pxp_device_release,
466 .unlocked_ioctl = pxp_device_ioctl,
467 .mmap = pxp_device_mmap,
468};
469
470static struct miscdevice pxp_device_miscdev = {
471 .minor = MISC_DYNAMIC_MINOR,
472 .name = "pxp_device",
473 .fops = &pxp_device_fops,
474};
475
476int register_pxp_device(void)
477{
478 int ret;
479
480 ret = misc_register(&pxp_device_miscdev);
481 if (ret)
482 return ret;
483
484 pr_debug("PxP_Device registered Successfully\n");
485 return 0;
486}
487
488void unregister_pxp_device(void)
489{
490 misc_deregister(&pxp_device_miscdev);
491}
diff --git a/drivers/dma/pxp/pxp_dma_v2.c b/drivers/dma/pxp/pxp_dma_v2.c
new file mode 100644
index 000000000000..9641adc3fca5
--- /dev/null
+++ b/drivers/dma/pxp/pxp_dma_v2.c
@@ -0,0 +1,1680 @@
1/*
2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 */
19/*
20 * Based on STMP378X PxP driver
21 * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
22 */
23
24#include <linux/dma-mapping.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/mutex.h>
31#include <linux/platform_device.h>
32#include <linux/slab.h>
33#include <linux/vmalloc.h>
34#include <linux/dmaengine.h>
35#include <linux/pxp_dma.h>
36#include <linux/timer.h>
37#include <linux/clk.h>
38#include <linux/workqueue.h>
39#include <linux/sched.h>
40#include <linux/of.h>
41
42#include "regs-pxp_v2.h"
43
44#define PXP_DOWNSCALE_THRESHOLD 0x4000
45
46static LIST_HEAD(head);
47static int timeout_in_ms = 600;
48
49struct pxp_dma {
50 struct dma_device dma;
51};
52
53struct pxps {
54 struct platform_device *pdev;
55 struct clk *clk;
56 void __iomem *base;
57 int irq; /* PXP IRQ to the CPU */
58
59 spinlock_t lock;
60 struct mutex clk_mutex;
61 int clk_stat;
62#define CLK_STAT_OFF 0
63#define CLK_STAT_ON 1
64 int pxp_ongoing;
65 int lut_state;
66
67 struct device *dev;
68 struct pxp_dma pxp_dma;
69 struct pxp_channel channel[NR_PXP_VIRT_CHANNEL];
70 wait_queue_head_t done;
71 struct work_struct work;
72
73 /* describes most recent processing configuration */
74 struct pxp_config_data pxp_conf_state;
75
76 /* to turn clock off when pxp is inactive */
77 struct timer_list clk_timer;
78};
79
80#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma)
81#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd)
82#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan)
83#define to_pxp(id) container_of(id, struct pxps, pxp_dma)
84
85#define PXP_DEF_BUFS 2
86#define PXP_MIN_PIX 8
87
88#define PXP_WAITCON ((__raw_readl(pxp->base + HW_PXP_STAT) & \
89 BM_PXP_STAT_IRQ) != BM_PXP_STAT_IRQ)
90
91static uint32_t pxp_s0_formats[] = {
92 PXP_PIX_FMT_RGB24,
93 PXP_PIX_FMT_RGB565,
94 PXP_PIX_FMT_RGB555,
95 PXP_PIX_FMT_YUV420P,
96 PXP_PIX_FMT_YUV422P,
97};
98
99/*
100 * PXP common functions
101 */
102static void dump_pxp_reg(struct pxps *pxp)
103{
104 dev_dbg(pxp->dev, "PXP_CTRL 0x%x",
105 __raw_readl(pxp->base + HW_PXP_CTRL));
106 dev_dbg(pxp->dev, "PXP_STAT 0x%x",
107 __raw_readl(pxp->base + HW_PXP_STAT));
108 dev_dbg(pxp->dev, "PXP_OUT_CTRL 0x%x",
109 __raw_readl(pxp->base + HW_PXP_OUT_CTRL));
110 dev_dbg(pxp->dev, "PXP_OUT_BUF 0x%x",
111 __raw_readl(pxp->base + HW_PXP_OUT_BUF));
112 dev_dbg(pxp->dev, "PXP_OUT_BUF2 0x%x",
113 __raw_readl(pxp->base + HW_PXP_OUT_BUF2));
114 dev_dbg(pxp->dev, "PXP_OUT_PITCH 0x%x",
115 __raw_readl(pxp->base + HW_PXP_OUT_PITCH));
116 dev_dbg(pxp->dev, "PXP_OUT_LRC 0x%x",
117 __raw_readl(pxp->base + HW_PXP_OUT_LRC));
118 dev_dbg(pxp->dev, "PXP_OUT_PS_ULC 0x%x",
119 __raw_readl(pxp->base + HW_PXP_OUT_PS_ULC));
120 dev_dbg(pxp->dev, "PXP_OUT_PS_LRC 0x%x",
121 __raw_readl(pxp->base + HW_PXP_OUT_PS_LRC));
122 dev_dbg(pxp->dev, "PXP_OUT_AS_ULC 0x%x",
123 __raw_readl(pxp->base + HW_PXP_OUT_AS_ULC));
124 dev_dbg(pxp->dev, "PXP_OUT_AS_LRC 0x%x",
125 __raw_readl(pxp->base + HW_PXP_OUT_AS_LRC));
126 dev_dbg(pxp->dev, "PXP_PS_CTRL 0x%x",
127 __raw_readl(pxp->base + HW_PXP_PS_CTRL));
128 dev_dbg(pxp->dev, "PXP_PS_BUF 0x%x",
129 __raw_readl(pxp->base + HW_PXP_PS_BUF));
130 dev_dbg(pxp->dev, "PXP_PS_UBUF 0x%x",
131 __raw_readl(pxp->base + HW_PXP_PS_UBUF));
132 dev_dbg(pxp->dev, "PXP_PS_VBUF 0x%x",
133 __raw_readl(pxp->base + HW_PXP_PS_VBUF));
134 dev_dbg(pxp->dev, "PXP_PS_PITCH 0x%x",
135 __raw_readl(pxp->base + HW_PXP_PS_PITCH));
136 dev_dbg(pxp->dev, "PXP_PS_BACKGROUND 0x%x",
137 __raw_readl(pxp->base + HW_PXP_PS_BACKGROUND));
138 dev_dbg(pxp->dev, "PXP_PS_SCALE 0x%x",
139 __raw_readl(pxp->base + HW_PXP_PS_SCALE));
140 dev_dbg(pxp->dev, "PXP_PS_OFFSET 0x%x",
141 __raw_readl(pxp->base + HW_PXP_PS_OFFSET));
142 dev_dbg(pxp->dev, "PXP_PS_CLRKEYLOW 0x%x",
143 __raw_readl(pxp->base + HW_PXP_PS_CLRKEYLOW));
144 dev_dbg(pxp->dev, "PXP_PS_CLRKEYHIGH 0x%x",
145 __raw_readl(pxp->base + HW_PXP_PS_CLRKEYHIGH));
146 dev_dbg(pxp->dev, "PXP_AS_CTRL 0x%x",
147 __raw_readl(pxp->base + HW_PXP_AS_CTRL));
148 dev_dbg(pxp->dev, "PXP_AS_BUF 0x%x",
149 __raw_readl(pxp->base + HW_PXP_AS_BUF));
150 dev_dbg(pxp->dev, "PXP_AS_PITCH 0x%x",
151 __raw_readl(pxp->base + HW_PXP_AS_PITCH));
152 dev_dbg(pxp->dev, "PXP_AS_CLRKEYLOW 0x%x",
153 __raw_readl(pxp->base + HW_PXP_AS_CLRKEYLOW));
154 dev_dbg(pxp->dev, "PXP_AS_CLRKEYHIGH 0x%x",
155 __raw_readl(pxp->base + HW_PXP_AS_CLRKEYHIGH));
156 dev_dbg(pxp->dev, "PXP_CSC1_COEF0 0x%x",
157 __raw_readl(pxp->base + HW_PXP_CSC1_COEF0));
158 dev_dbg(pxp->dev, "PXP_CSC1_COEF1 0x%x",
159 __raw_readl(pxp->base + HW_PXP_CSC1_COEF1));
160 dev_dbg(pxp->dev, "PXP_CSC1_COEF2 0x%x",
161 __raw_readl(pxp->base + HW_PXP_CSC1_COEF2));
162 dev_dbg(pxp->dev, "PXP_CSC2_CTRL 0x%x",
163 __raw_readl(pxp->base + HW_PXP_CSC2_CTRL));
164 dev_dbg(pxp->dev, "PXP_CSC2_COEF0 0x%x",
165 __raw_readl(pxp->base + HW_PXP_CSC2_COEF0));
166 dev_dbg(pxp->dev, "PXP_CSC2_COEF1 0x%x",
167 __raw_readl(pxp->base + HW_PXP_CSC2_COEF1));
168 dev_dbg(pxp->dev, "PXP_CSC2_COEF2 0x%x",
169 __raw_readl(pxp->base + HW_PXP_CSC2_COEF2));
170 dev_dbg(pxp->dev, "PXP_CSC2_COEF3 0x%x",
171 __raw_readl(pxp->base + HW_PXP_CSC2_COEF3));
172 dev_dbg(pxp->dev, "PXP_CSC2_COEF4 0x%x",
173 __raw_readl(pxp->base + HW_PXP_CSC2_COEF4));
174 dev_dbg(pxp->dev, "PXP_CSC2_COEF5 0x%x",
175 __raw_readl(pxp->base + HW_PXP_CSC2_COEF5));
176 dev_dbg(pxp->dev, "PXP_LUT_CTRL 0x%x",
177 __raw_readl(pxp->base + HW_PXP_LUT_CTRL));
178 dev_dbg(pxp->dev, "PXP_LUT_ADDR 0x%x",
179 __raw_readl(pxp->base + HW_PXP_LUT_ADDR));
180 dev_dbg(pxp->dev, "PXP_LUT_DATA 0x%x",
181 __raw_readl(pxp->base + HW_PXP_LUT_DATA));
182 dev_dbg(pxp->dev, "PXP_LUT_EXTMEM 0x%x",
183 __raw_readl(pxp->base + HW_PXP_LUT_EXTMEM));
184 dev_dbg(pxp->dev, "PXP_CFA 0x%x",
185 __raw_readl(pxp->base + HW_PXP_CFA));
186 dev_dbg(pxp->dev, "PXP_HIST_CTRL 0x%x",
187 __raw_readl(pxp->base + HW_PXP_HIST_CTRL));
188 dev_dbg(pxp->dev, "PXP_HIST2_PARAM 0x%x",
189 __raw_readl(pxp->base + HW_PXP_HIST2_PARAM));
190 dev_dbg(pxp->dev, "PXP_HIST4_PARAM 0x%x",
191 __raw_readl(pxp->base + HW_PXP_HIST4_PARAM));
192 dev_dbg(pxp->dev, "PXP_HIST8_PARAM0 0x%x",
193 __raw_readl(pxp->base + HW_PXP_HIST8_PARAM0));
194 dev_dbg(pxp->dev, "PXP_HIST8_PARAM1 0x%x",
195 __raw_readl(pxp->base + HW_PXP_HIST8_PARAM1));
196 dev_dbg(pxp->dev, "PXP_HIST16_PARAM0 0x%x",
197 __raw_readl(pxp->base + HW_PXP_HIST16_PARAM0));
198 dev_dbg(pxp->dev, "PXP_HIST16_PARAM1 0x%x",
199 __raw_readl(pxp->base + HW_PXP_HIST16_PARAM1));
200 dev_dbg(pxp->dev, "PXP_HIST16_PARAM2 0x%x",
201 __raw_readl(pxp->base + HW_PXP_HIST16_PARAM2));
202 dev_dbg(pxp->dev, "PXP_HIST16_PARAM3 0x%x",
203 __raw_readl(pxp->base + HW_PXP_HIST16_PARAM3));
204 dev_dbg(pxp->dev, "PXP_POWER 0x%x",
205 __raw_readl(pxp->base + HW_PXP_POWER));
206 dev_dbg(pxp->dev, "PXP_NEXT 0x%x",
207 __raw_readl(pxp->base + HW_PXP_NEXT));
208 dev_dbg(pxp->dev, "PXP_DEBUGCTRL 0x%x",
209 __raw_readl(pxp->base + HW_PXP_DEBUGCTRL));
210 dev_dbg(pxp->dev, "PXP_DEBUG 0x%x",
211 __raw_readl(pxp->base + HW_PXP_DEBUG));
212 dev_dbg(pxp->dev, "PXP_VERSION 0x%x",
213 __raw_readl(pxp->base + HW_PXP_VERSION));
214}
215
216static bool is_yuv(u32 pix_fmt)
217{
218 if ((pix_fmt == PXP_PIX_FMT_YUYV) |
219 (pix_fmt == PXP_PIX_FMT_UYVY) |
220 (pix_fmt == PXP_PIX_FMT_Y41P) |
221 (pix_fmt == PXP_PIX_FMT_YUV444) |
222 (pix_fmt == PXP_PIX_FMT_NV12) |
223 (pix_fmt == PXP_PIX_FMT_GREY) |
224 (pix_fmt == PXP_PIX_FMT_GY04) |
225 (pix_fmt == PXP_PIX_FMT_YVU410P) |
226 (pix_fmt == PXP_PIX_FMT_YUV410P) |
227 (pix_fmt == PXP_PIX_FMT_YVU420P) |
228 (pix_fmt == PXP_PIX_FMT_YUV420P) |
229 (pix_fmt == PXP_PIX_FMT_YUV420P2) |
230 (pix_fmt == PXP_PIX_FMT_YVU422P) |
231 (pix_fmt == PXP_PIX_FMT_YUV422P)) {
232 return true;
233 } else {
234 return false;
235 }
236}
237
238static void pxp_set_ctrl(struct pxps *pxp)
239{
240 struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
241 struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
242 u32 ctrl;
243 u32 fmt_ctrl;
244
245 /* Configure S0 input format */
246 switch (pxp_conf->s0_param.pixel_fmt) {
247 case PXP_PIX_FMT_RGB24:
248 fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB888;
249 break;
250 case PXP_PIX_FMT_RGB565:
251 fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB565;
252 break;
253 case PXP_PIX_FMT_RGB555:
254 fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB555;
255 break;
256 case PXP_PIX_FMT_YUV420P:
257 fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420;
258 break;
259 case PXP_PIX_FMT_GREY:
260 fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y8;
261 break;
262 case PXP_PIX_FMT_GY04:
263 fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y4;
264 break;
265 case PXP_PIX_FMT_YUV422P:
266 fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV422;
267 break;
268 case PXP_PIX_FMT_UYVY:
269 fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
270 break;
271 default:
272 fmt_ctrl = 0;
273 }
274
275 ctrl = BF_PXP_PS_CTRL_FORMAT(fmt_ctrl);
276 __raw_writel(ctrl, pxp->base + HW_PXP_PS_CTRL);
277
278 /* Configure output format based on out_channel format */
279 switch (pxp_conf->out_param.pixel_fmt) {
280 case PXP_PIX_FMT_RGB24:
281 fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888;
282 break;
283 case PXP_PIX_FMT_RGB565:
284 fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB565;
285 break;
286 case PXP_PIX_FMT_RGB555:
287 fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB555;
288 break;
289 case PXP_PIX_FMT_YUV420P:
290 fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P420;
291 break;
292 case PXP_PIX_FMT_YUV422P:
293 fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P422;
294 break;
295 case PXP_PIX_FMT_GREY:
296 fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y8;
297 break;
298 case PXP_PIX_FMT_GY04:
299 fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y4;
300 break;
301 default:
302 fmt_ctrl = 0;
303 }
304
305 ctrl = BF_PXP_OUT_CTRL_FORMAT(fmt_ctrl);
306 __raw_writel(ctrl, pxp->base + HW_PXP_OUT_CTRL);
307
308 ctrl = 0;
309 if (proc_data->scaling)
310 ;
311 if (proc_data->vflip)
312 ctrl |= BM_PXP_CTRL_VFLIP;
313 if (proc_data->hflip)
314 ctrl |= BM_PXP_CTRL_HFLIP;
315 if (proc_data->rotate)
316 ctrl |= BF_PXP_CTRL_ROTATE(proc_data->rotate / 90);
317
318 /* H/W support: controls where rotation will occur in the PXP datapath,
319 * will export an interfance if needed
320 */
321 /* ctrl |= BM_PXP_CTRL_ROT_POS; post rotation */
322
323 __raw_writel(ctrl, pxp->base + HW_PXP_CTRL);
324}
325
326static int pxp_start(struct pxps *pxp)
327{
328 __raw_writel(BM_PXP_CTRL_IRQ_ENABLE, pxp->base + HW_PXP_CTRL_SET);
329 __raw_writel(BM_PXP_CTRL_ENABLE, pxp->base + HW_PXP_CTRL_SET);
330 dump_pxp_reg(pxp);
331
332 return 0;
333}
334
335static void pxp_set_outbuf(struct pxps *pxp)
336{
337 struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
338 struct pxp_layer_param *out_params = &pxp_conf->out_param;
339
340 __raw_writel(out_params->paddr, pxp->base + HW_PXP_OUT_BUF);
341
342 __raw_writel(BF_PXP_OUT_LRC_X(out_params->width - 1) |
343 BF_PXP_OUT_LRC_Y(out_params->height - 1),
344 pxp->base + HW_PXP_OUT_LRC);
345
346 if (out_params->pixel_fmt == PXP_PIX_FMT_RGB24)
347 __raw_writel(out_params->stride << 2,
348 pxp->base + HW_PXP_OUT_PITCH);
349 else if (out_params->pixel_fmt == PXP_PIX_FMT_RGB565)
350 __raw_writel(out_params->stride << 1,
351 pxp->base + HW_PXP_OUT_PITCH);
352 else
353 __raw_writel(out_params->stride, pxp->base + HW_PXP_OUT_PITCH);
354}
355
356static void pxp_set_s0colorkey(struct pxps *pxp)
357{
358 struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
359 struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
360
361 /* Low and high are set equal. V4L does not allow a chromakey range */
362 if (s0_params->color_key == -1) {
363 /* disable color key */
364 __raw_writel(0xFFFFFF, pxp->base + HW_PXP_PS_CLRKEYLOW);
365 __raw_writel(0, pxp->base + HW_PXP_PS_CLRKEYHIGH);
366 } else {
367 __raw_writel(s0_params->color_key,
368 pxp->base + HW_PXP_PS_CLRKEYLOW);
369 __raw_writel(s0_params->color_key,
370 pxp->base + HW_PXP_PS_CLRKEYHIGH);
371 }
372}
373
374static void pxp_set_olcolorkey(int layer_no, struct pxps *pxp)
375{
376 struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
377 struct pxp_layer_param *ol_params = &pxp_conf->ol_param[layer_no];
378
379 /* Low and high are set equal. V4L does not allow a chromakey range */
380 if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) {
381 __raw_writel(ol_params->color_key,
382 pxp->base + HW_PXP_AS_CLRKEYLOW);
383 __raw_writel(ol_params->color_key,
384 pxp->base + HW_PXP_AS_CLRKEYHIGH);
385 } else {
386 /* disable color key */
387 __raw_writel(0xFFFFFF, pxp->base + HW_PXP_AS_CLRKEYLOW);
388 __raw_writel(0, pxp->base + HW_PXP_AS_CLRKEYHIGH);
389 }
390}
391
392static void pxp_set_oln(int layer_no, struct pxps *pxp)
393{
394 struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
395 struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no];
396 dma_addr_t phys_addr = olparams_data->paddr;
397 __raw_writel(phys_addr, pxp->base + HW_PXP_AS_BUF);
398
399 /* Fixme */
400 __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_ULC);
401 __raw_writel(BF_PXP_OUT_AS_LRC_X(olparams_data->width) |
402 BF_PXP_OUT_AS_LRC_Y(olparams_data->height),
403 pxp->base + HW_PXP_OUT_AS_LRC);
404
405 if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB24)
406 __raw_writel(olparams_data->width << 2,
407 pxp->base + HW_PXP_AS_PITCH);
408 else
409 __raw_writel(olparams_data->width << 1,
410 pxp->base + HW_PXP_AS_PITCH);
411}
412
413static void pxp_set_olparam(int layer_no, struct pxps *pxp)
414{
415 struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
416 struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no];
417 u32 olparam;
418
419 olparam = BF_PXP_AS_CTRL_ALPHA(olparams_data->global_alpha);
420 if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB24)
421 olparam |=
422 BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB888);
423 else
424 olparam |=
425 BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB565);
426 if (olparams_data->global_alpha_enable)
427 olparam |=
428 BF_PXP_AS_CTRL_ALPHA_CTRL
429 (BV_PXP_AS_CTRL_ALPHA_CTRL__Override);
430 if (olparams_data->color_key_enable)
431 olparam |= BM_PXP_AS_CTRL_ENABLE_COLORKEY;
432 if (olparams_data->combine_enable)
433 ;
434 __raw_writel(olparam, pxp->base + HW_PXP_AS_CTRL);
435}
436
437static void pxp_set_s0param(struct pxps *pxp)
438{
439 struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
440 struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
441 u32 s0param;
442
443 /* contains the coordinate for the PS in the OUTPUT buffer. */
444 s0param = BF_PXP_OUT_PS_ULC_X(proc_data->drect.left);
445 s0param |= BF_PXP_OUT_PS_ULC_Y(proc_data->drect.top);
446 __raw_writel(s0param, pxp->base + HW_PXP_OUT_PS_ULC);
447 s0param = BF_PXP_OUT_PS_LRC_X(proc_data->drect.left +
448 proc_data->drect.width - 1);
449 s0param |= BF_PXP_OUT_PS_LRC_Y(proc_data->drect.top +
450 proc_data->drect.height - 1);
451 __raw_writel(s0param, pxp->base + HW_PXP_OUT_PS_LRC);
452}
453
454/* crop behavior is re-designed in h/w. */
455static void pxp_set_s0crop(struct pxps *pxp)
456{
457 /*
458 * place-holder, it's implemented in other functions in this driver.
459 * Refer to "Clipping source images" section in RM for detail.
460 */
461}
462
463static int pxp_set_scaling(struct pxps *pxp)
464{
465 int ret = 0;
466 u32 xscale, yscale, s0scale;
467 struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data;
468
469 if ((proc_data->srect.width == proc_data->drect.width) &&
470 (proc_data->srect.height == proc_data->drect.height)) {
471 proc_data->scaling = 0;
472 __raw_writel(0x10001000, pxp->base + HW_PXP_PS_SCALE);
473 goto out;
474 }
475
476 proc_data->scaling = 1;
477 xscale = proc_data->srect.width * 0x1000 / proc_data->drect.width;
478 yscale = proc_data->srect.height * 0x1000 / proc_data->drect.height;
479 if (xscale > PXP_DOWNSCALE_THRESHOLD)
480 xscale = PXP_DOWNSCALE_THRESHOLD;
481 if (yscale > PXP_DOWNSCALE_THRESHOLD)
482 yscale = PXP_DOWNSCALE_THRESHOLD;
483 s0scale = BF_PXP_PS_SCALE_YSCALE(yscale) |
484 BF_PXP_PS_SCALE_XSCALE(xscale);
485 __raw_writel(s0scale, pxp->base + HW_PXP_PS_SCALE);
486
487out:
488 pxp_set_ctrl(pxp);
489
490 return ret;
491}
492
493static void pxp_set_bg(struct pxps *pxp)
494{
495 __raw_writel(pxp->pxp_conf_state.proc_data.bgcolor,
496 pxp->base + HW_PXP_PS_BACKGROUND);
497}
498
499static void pxp_set_lut(struct pxps *pxp)
500{
501 struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
502 int lut_op = pxp_conf->proc_data.lut_transform;
503 u32 reg_val;
504 int i;
505 bool use_cmap = (lut_op & PXP_LUT_USE_CMAP) ? true : false;
506 u8 *cmap = pxp_conf->proc_data.lut_map;
507 u32 entry_src;
508 u32 pix_val;
509 u8 entry[4];
510
511 /*
512 * If LUT already configured as needed, return...
513 * Unless CMAP is needed and it has been updated.
514 */
515 if ((pxp->lut_state == lut_op) &&
516 !(use_cmap && pxp_conf->proc_data.lut_map_updated))
517 return;
518
519 if (lut_op == PXP_LUT_NONE) {
520 __raw_writel(BM_PXP_LUT_CTRL_BYPASS,
521 pxp->base + HW_PXP_LUT_CTRL);
522 } else if (((lut_op & PXP_LUT_INVERT) != 0)
523 && ((lut_op & PXP_LUT_BLACK_WHITE) != 0)) {
524 /* Fill out LUT table with inverted monochromized values */
525
526 /* clear bypass bit, set lookup mode & out mode */
527 __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE
528 (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) |
529 BF_PXP_LUT_CTRL_OUT_MODE
530 (BV_PXP_LUT_CTRL_OUT_MODE__Y8),
531 pxp->base + HW_PXP_LUT_CTRL);
532
533 /* Initialize LUT address to 0 and set NUM_BYTES to 0 */
534 __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR);
535
536 /* LUT address pointer auto-increments after each data write */
537 for (pix_val = 0; pix_val < 256; pix_val += 4) {
538 for (i = 0; i < 4; i++) {
539 entry_src = use_cmap ?
540 cmap[pix_val + i] : pix_val + i;
541 entry[i] = (entry_src < 0x80) ? 0xFF : 0x00;
542 }
543 reg_val = (entry[3] << 24) | (entry[2] << 16) |
544 (entry[1] << 8) | entry[0];
545 __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA);
546 }
547 } else if ((lut_op & PXP_LUT_INVERT) != 0) {
548 /* Fill out LUT table with 8-bit inverted values */
549
550 /* clear bypass bit, set lookup mode & out mode */
551 __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE
552 (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) |
553 BF_PXP_LUT_CTRL_OUT_MODE
554 (BV_PXP_LUT_CTRL_OUT_MODE__Y8),
555 pxp->base + HW_PXP_LUT_CTRL);
556
557 /* Initialize LUT address to 0 and set NUM_BYTES to 0 */
558 __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR);
559
560 /* LUT address pointer auto-increments after each data write */
561 for (pix_val = 0; pix_val < 256; pix_val += 4) {
562 for (i = 0; i < 4; i++) {
563 entry_src = use_cmap ?
564 cmap[pix_val + i] : pix_val + i;
565 entry[i] = ~entry_src & 0xFF;
566 }
567 reg_val = (entry[3] << 24) | (entry[2] << 16) |
568 (entry[1] << 8) | entry[0];
569 __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA);
570 }
571 } else if ((lut_op & PXP_LUT_BLACK_WHITE) != 0) {
572 /* Fill out LUT table with 8-bit monochromized values */
573
574 /* clear bypass bit, set lookup mode & out mode */
575 __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE
576 (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) |
577 BF_PXP_LUT_CTRL_OUT_MODE
578 (BV_PXP_LUT_CTRL_OUT_MODE__Y8),
579 pxp->base + HW_PXP_LUT_CTRL);
580
581 /* Initialize LUT address to 0 and set NUM_BYTES to 0 */
582 __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR);
583
584 /* LUT address pointer auto-increments after each data write */
585 for (pix_val = 0; pix_val < 256; pix_val += 4) {
586 for (i = 0; i < 4; i++) {
587 entry_src = use_cmap ?
588 cmap[pix_val + i] : pix_val + i;
589 entry[i] = (entry_src < 0x80) ? 0x00 : 0xFF;
590 }
591 reg_val = (entry[3] << 24) | (entry[2] << 16) |
592 (entry[1] << 8) | entry[0];
593 __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA);
594 }
595 } else if (use_cmap) {
596 /* Fill out LUT table using colormap values */
597
598 /* clear bypass bit, set lookup mode & out mode */
599 __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE
600 (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) |
601 BF_PXP_LUT_CTRL_OUT_MODE
602 (BV_PXP_LUT_CTRL_OUT_MODE__Y8),
603 pxp->base + HW_PXP_LUT_CTRL);
604
605 /* Initialize LUT address to 0 and set NUM_BYTES to 0 */
606 __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR);
607
608 /* LUT address pointer auto-increments after each data write */
609 for (pix_val = 0; pix_val < 256; pix_val += 4) {
610 for (i = 0; i < 4; i++)
611 entry[i] = cmap[pix_val + i];
612 reg_val = (entry[3] << 24) | (entry[2] << 16) |
613 (entry[1] << 8) | entry[0];
614 __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA);
615 }
616 }
617
618 pxp->lut_state = lut_op;
619}
620
621static void pxp_set_csc(struct pxps *pxp)
622{
623 struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
624 struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
625 struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0];
626 struct pxp_layer_param *out_params = &pxp_conf->out_param;
627
628 bool input_is_YUV = is_yuv(s0_params->pixel_fmt);
629 bool output_is_YUV = is_yuv(out_params->pixel_fmt);
630
631 if (input_is_YUV && output_is_YUV) {
632 /*
633 * Input = YUV, Output = YUV
634 * No CSC unless we need to do combining
635 */
636 if (ol_params->combine_enable) {
637 /* Must convert to RGB for combining with RGB overlay */
638
639 /* CSC1 - YUV->RGB */
640 __raw_writel(0x04030000, pxp->base + HW_PXP_CSC1_COEF0);
641 __raw_writel(0x01230208, pxp->base + HW_PXP_CSC1_COEF1);
642 __raw_writel(0x076b079c, pxp->base + HW_PXP_CSC1_COEF2);
643
644 /* CSC2 - RGB->YUV */
645 __raw_writel(0x4, pxp->base + HW_PXP_CSC2_CTRL);
646 __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2_COEF0);
647 __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2_COEF1);
648 __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2_COEF2);
649 __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2_COEF3);
650 __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2_COEF4);
651 __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2_COEF5);
652 } else {
653 /* Input & Output both YUV, so bypass both CSCs */
654
655 /* CSC1 - Bypass */
656 __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0);
657
658 /* CSC2 - Bypass */
659 __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL);
660 }
661 } else if (input_is_YUV && !output_is_YUV) {
662 /*
663 * Input = YUV, Output = RGB
664 * Use CSC1 to convert to RGB
665 */
666
667 /* CSC1 - YUV->RGB */
668 __raw_writel(0x84ab01f0, pxp->base + HW_PXP_CSC1_COEF0);
669 __raw_writel(0x01980204, pxp->base + HW_PXP_CSC1_COEF1);
670 __raw_writel(0x0730079c, pxp->base + HW_PXP_CSC1_COEF2);
671
672 /* CSC2 - Bypass */
673 __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL);
674 } else if (!input_is_YUV && output_is_YUV) {
675 /*
676 * Input = RGB, Output = YUV
677 * Use CSC2 to convert to YUV
678 */
679
680 /* CSC1 - Bypass */
681 __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0);
682
683 /* CSC2 - RGB->YUV */
684 __raw_writel(0x4, pxp->base + HW_PXP_CSC2_CTRL);
685 __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2_COEF0);
686 __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2_COEF1);
687 __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2_COEF2);
688 __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2_COEF3);
689 __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2_COEF4);
690 __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2_COEF5);
691 } else {
692 /*
693 * Input = RGB, Output = RGB
694 * Input & Output both RGB, so bypass both CSCs
695 */
696
697 /* CSC1 - Bypass */
698 __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0);
699
700 /* CSC2 - Bypass */
701 __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL);
702 }
703
704 /* YCrCb colorspace */
705 /* Not sure when we use this...no YCrCb formats are defined for PxP */
706 /*
707 __raw_writel(0x84ab01f0, HW_PXP_CSCCOEFF0_ADDR);
708 __raw_writel(0x01230204, HW_PXP_CSCCOEFF1_ADDR);
709 __raw_writel(0x0730079c, HW_PXP_CSCCOEFF2_ADDR);
710 */
711
712}
713
714static void pxp_set_s0buf(struct pxps *pxp)
715{
716 struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
717 struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
718 struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
719 dma_addr_t Y, U, V;
720 dma_addr_t Y1, U1, V1;
721 u32 offset, bpp = 1;
722
723 Y = s0_params->paddr;
724
725 if (s0_params->pixel_fmt == PXP_PIX_FMT_RGB565)
726 bpp = 2;
727 else if (s0_params->pixel_fmt == PXP_PIX_FMT_RGB24)
728 bpp = 4;
729 offset = (proc_data->srect.top * s0_params->width +
730 proc_data->srect.left) * bpp;
731 /* clipping or cropping */
732 Y1 = Y + offset;
733 __raw_writel(Y1, pxp->base + HW_PXP_PS_BUF);
734 if ((s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P) ||
735 (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) ||
736 (s0_params->pixel_fmt == PXP_PIX_FMT_GREY)) {
737 /* Set to 1 if YUV format is 4:2:2 rather than 4:2:0 */
738 int s = 2;
739
740 offset = proc_data->srect.top * s0_params->width / 4 +
741 proc_data->srect.left / 2;
742 U = Y + (s0_params->width * s0_params->height);
743 U1 = U + offset;
744 V = U + ((s0_params->width * s0_params->height) >> s);
745 V1 = V + offset;
746 __raw_writel(U1, pxp->base + HW_PXP_PS_UBUF);
747 __raw_writel(V1, pxp->base + HW_PXP_PS_VBUF);
748 }
749
750 /* TODO: only support RGB565, Y8, Y4, YUV420 */
751 if (s0_params->pixel_fmt == PXP_PIX_FMT_GREY ||
752 s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P)
753 __raw_writel(s0_params->width, pxp->base + HW_PXP_PS_PITCH);
754 else if (s0_params->pixel_fmt == PXP_PIX_FMT_GY04)
755 __raw_writel(s0_params->width >> 1,
756 pxp->base + HW_PXP_PS_PITCH);
757 else
758 __raw_writel(s0_params->width * 2, pxp->base + HW_PXP_PS_PITCH);
759}
760
761/**
762 * pxp_config() - configure PxP for a processing task
763 * @pxps: PXP context.
764 * @pxp_chan: PXP channel.
765 * @return: 0 on success or negative error code on failure.
766 */
767static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan)
768{
769 struct pxp_config_data *pxp_conf_data = &pxp->pxp_conf_state;
770 int ol_nr;
771 int i;
772
773 /* Configure PxP regs */
774 pxp_set_ctrl(pxp);
775 pxp_set_s0param(pxp);
776 pxp_set_s0crop(pxp);
777 pxp_set_scaling(pxp);
778 ol_nr = pxp_conf_data->layer_nr - 2;
779 while (ol_nr > 0) {
780 i = pxp_conf_data->layer_nr - 2 - ol_nr;
781 pxp_set_oln(i, pxp);
782 pxp_set_olparam(i, pxp);
783 /* only the color key in higher overlay will take effect. */
784 pxp_set_olcolorkey(i, pxp);
785 ol_nr--;
786 }
787 pxp_set_s0colorkey(pxp);
788 pxp_set_csc(pxp);
789 pxp_set_bg(pxp);
790 pxp_set_lut(pxp);
791
792 pxp_set_s0buf(pxp);
793 pxp_set_outbuf(pxp);
794
795 return 0;
796}
797
798static void pxp_clk_enable(struct pxps *pxp)
799{
800 mutex_lock(&pxp->clk_mutex);
801
802 if (pxp->clk_stat == CLK_STAT_ON) {
803 mutex_unlock(&pxp->clk_mutex);
804 return;
805 }
806
807 clk_prepare_enable(pxp->clk);
808 pxp->clk_stat = CLK_STAT_ON;
809
810 mutex_unlock(&pxp->clk_mutex);
811}
812
813static void pxp_clk_disable(struct pxps *pxp)
814{
815 unsigned long flags;
816
817 mutex_lock(&pxp->clk_mutex);
818
819 if (pxp->clk_stat == CLK_STAT_OFF) {
820 mutex_unlock(&pxp->clk_mutex);
821 return;
822 }
823
824 spin_lock_irqsave(&pxp->lock, flags);
825 if ((pxp->pxp_ongoing == 0) && list_empty(&head)) {
826 spin_unlock_irqrestore(&pxp->lock, flags);
827 clk_disable_unprepare(pxp->clk);
828 pxp->clk_stat = CLK_STAT_OFF;
829 } else
830 spin_unlock_irqrestore(&pxp->lock, flags);
831
832 mutex_unlock(&pxp->clk_mutex);
833}
834
835static inline void clkoff_callback(struct work_struct *w)
836{
837 struct pxps *pxp = container_of(w, struct pxps, work);
838
839 pxp_clk_disable(pxp);
840}
841
842static void pxp_clkoff_timer(unsigned long arg)
843{
844 struct pxps *pxp = (struct pxps *)arg;
845
846 if ((pxp->pxp_ongoing == 0) && list_empty(&head))
847 schedule_work(&pxp->work);
848 else
849 mod_timer(&pxp->clk_timer,
850 jiffies + msecs_to_jiffies(timeout_in_ms));
851}
852
853static struct pxp_tx_desc *pxpdma_first_active(struct pxp_channel *pxp_chan)
854{
855 return list_entry(pxp_chan->active_list.next, struct pxp_tx_desc, list);
856}
857
858static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan)
859{
860 return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list);
861}
862
863/* called with pxp_chan->lock held */
864static void __pxpdma_dostart(struct pxp_channel *pxp_chan)
865{
866 struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device);
867 struct pxps *pxp = to_pxp(pxp_dma);
868 struct pxp_tx_desc *desc;
869 struct pxp_tx_desc *child;
870 int i = 0;
871
872 /* so far we presume only one transaction on active_list */
873 /* S0 */
874 desc = pxpdma_first_active(pxp_chan);
875 memcpy(&pxp->pxp_conf_state.s0_param,
876 &desc->layer_param.s0_param, sizeof(struct pxp_layer_param));
877 memcpy(&pxp->pxp_conf_state.proc_data,
878 &desc->proc_data, sizeof(struct pxp_proc_data));
879
880 /* Save PxP configuration */
881 list_for_each_entry(child, &desc->tx_list, list) {
882 if (i == 0) { /* Output */
883 memcpy(&pxp->pxp_conf_state.out_param,
884 &child->layer_param.out_param,
885 sizeof(struct pxp_layer_param));
886 } else { /* Overlay */
887 memcpy(&pxp->pxp_conf_state.ol_param[i - 1],
888 &child->layer_param.ol_param,
889 sizeof(struct pxp_layer_param));
890 }
891
892 i++;
893 }
894 pr_debug("%s:%d S0 w/h %d/%d paddr %08x\n", __func__, __LINE__,
895 pxp->pxp_conf_state.s0_param.width,
896 pxp->pxp_conf_state.s0_param.height,
897 pxp->pxp_conf_state.s0_param.paddr);
898 pr_debug("%s:%d OUT w/h %d/%d paddr %08x\n", __func__, __LINE__,
899 pxp->pxp_conf_state.out_param.width,
900 pxp->pxp_conf_state.out_param.height,
901 pxp->pxp_conf_state.out_param.paddr);
902}
903
904static void pxpdma_dostart_work(struct pxps *pxp)
905{
906 struct pxp_channel *pxp_chan = NULL;
907 unsigned long flags, flags1;
908
909 while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE)
910 ;
911
912 spin_lock_irqsave(&pxp->lock, flags);
913 if (list_empty(&head)) {
914 pxp->pxp_ongoing = 0;
915 spin_unlock_irqrestore(&pxp->lock, flags);
916 return;
917 }
918
919 pxp_chan = list_entry(head.next, struct pxp_channel, list);
920
921 spin_lock_irqsave(&pxp_chan->lock, flags1);
922 if (!list_empty(&pxp_chan->active_list)) {
923 struct pxp_tx_desc *desc;
924 /* REVISIT */
925 desc = pxpdma_first_active(pxp_chan);
926 __pxpdma_dostart(pxp_chan);
927 }
928 spin_unlock_irqrestore(&pxp_chan->lock, flags1);
929
930 /* Configure PxP */
931 pxp_config(pxp, pxp_chan);
932
933 pxp_start(pxp);
934
935 spin_unlock_irqrestore(&pxp->lock, flags);
936}
937
938static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct list_head *list)
939{
940 struct pxp_tx_desc *desc = NULL;
941 do {
942 desc = pxpdma_first_queued(pxp_chan);
943 list_move_tail(&desc->list, list);
944 } while (!list_empty(&pxp_chan->queue));
945}
946
947static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx)
948{
949 struct pxp_tx_desc *desc = to_tx_desc(tx);
950 struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan);
951 dma_cookie_t cookie;
952 unsigned long flags;
953
954 dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n");
955
956 mutex_lock(&pxp_chan->chan_mutex);
957
958 cookie = pxp_chan->dma_chan.cookie;
959
960 if (++cookie < 0)
961 cookie = 1;
962
963 /* from dmaengine.h: "last cookie value returned to client" */
964 pxp_chan->dma_chan.cookie = cookie;
965 tx->cookie = cookie;
966
967 /* pxp_chan->lock can be taken under ichan->lock, but not v.v. */
968 spin_lock_irqsave(&pxp_chan->lock, flags);
969
970 /* Here we add the tx descriptor to our PxP task queue. */
971 list_add_tail(&desc->list, &pxp_chan->queue);
972
973 spin_unlock_irqrestore(&pxp_chan->lock, flags);
974
975 dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n");
976
977 mutex_unlock(&pxp_chan->chan_mutex);
978 return cookie;
979}
980
981/* Called with pxp_chan->chan_mutex held */
982static int pxp_desc_alloc(struct pxp_channel *pxp_chan, int n)
983{
984 struct pxp_tx_desc *desc = vmalloc(n * sizeof(struct pxp_tx_desc));
985
986 if (!desc)
987 return -ENOMEM;
988
989 pxp_chan->n_tx_desc = n;
990 pxp_chan->desc = desc;
991 INIT_LIST_HEAD(&pxp_chan->active_list);
992 INIT_LIST_HEAD(&pxp_chan->queue);
993 INIT_LIST_HEAD(&pxp_chan->free_list);
994
995 while (n--) {
996 struct dma_async_tx_descriptor *txd = &desc->txd;
997
998 memset(txd, 0, sizeof(*txd));
999 INIT_LIST_HEAD(&desc->tx_list);
1000 dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan);
1001 txd->tx_submit = pxp_tx_submit;
1002
1003 list_add(&desc->list, &pxp_chan->free_list);
1004
1005 desc++;
1006 }
1007
1008 return 0;
1009}
1010
1011/**
1012 * pxp_init_channel() - initialize a PXP channel.
1013 * @pxp_dma: PXP DMA context.
1014 * @pchan: pointer to the channel object.
1015 * @return 0 on success or negative error code on failure.
1016 */
1017static int pxp_init_channel(struct pxp_dma *pxp_dma,
1018 struct pxp_channel *pxp_chan)
1019{
1020 unsigned long flags;
1021 struct pxps *pxp = to_pxp(pxp_dma);
1022 int ret = 0, n_desc = 0;
1023
1024 /*
1025 * We are using _virtual_ channel here.
1026 * Each channel contains all parameters of corresponding layers
1027 * for one transaction; each layer is represented as one descriptor
1028 * (i.e., pxp_tx_desc) here.
1029 */
1030
1031 spin_lock_irqsave(&pxp->lock, flags);
1032
1033 /* max desc nr: S0+OL+OUT = 1+8+1 */
1034 n_desc = 16;
1035
1036 spin_unlock_irqrestore(&pxp->lock, flags);
1037
1038 if (n_desc && !pxp_chan->desc)
1039 ret = pxp_desc_alloc(pxp_chan, n_desc);
1040
1041 return ret;
1042}
1043
1044/**
1045 * pxp_uninit_channel() - uninitialize a PXP channel.
1046 * @pxp_dma: PXP DMA context.
1047 * @pchan: pointer to the channel object.
1048 * @return 0 on success or negative error code on failure.
1049 */
1050static int pxp_uninit_channel(struct pxp_dma *pxp_dma,
1051 struct pxp_channel *pxp_chan)
1052{
1053 int ret = 0;
1054
1055 if (pxp_chan->desc)
1056 vfree(pxp_chan->desc);
1057
1058 pxp_chan->desc = NULL;
1059
1060 return ret;
1061}
1062
1063static irqreturn_t pxp_irq(int irq, void *dev_id)
1064{
1065 struct pxps *pxp = dev_id;
1066 struct pxp_channel *pxp_chan;
1067 struct pxp_tx_desc *desc;
1068 dma_async_tx_callback callback;
1069 void *callback_param;
1070 unsigned long flags;
1071 u32 hist_status;
1072
1073 dump_pxp_reg(pxp);
1074
1075 hist_status =
1076 __raw_readl(pxp->base + HW_PXP_HIST_CTRL) & BM_PXP_HIST_CTRL_STATUS;
1077
1078 __raw_writel(BM_PXP_STAT_IRQ, pxp->base + HW_PXP_STAT_CLR);
1079
1080 spin_lock_irqsave(&pxp->lock, flags);
1081
1082 if (list_empty(&head)) {
1083 pxp->pxp_ongoing = 0;
1084 spin_unlock_irqrestore(&pxp->lock, flags);
1085 return IRQ_NONE;
1086 }
1087
1088 pxp_chan = list_entry(head.next, struct pxp_channel, list);
1089 list_del_init(&pxp_chan->list);
1090
1091 if (list_empty(&pxp_chan->active_list)) {
1092 pr_debug("PXP_IRQ pxp_chan->active_list empty. chan_id %d\n",
1093 pxp_chan->dma_chan.chan_id);
1094 pxp->pxp_ongoing = 0;
1095 spin_unlock_irqrestore(&pxp->lock, flags);
1096 return IRQ_NONE;
1097 }
1098
1099 /* Get descriptor and call callback */
1100 desc = pxpdma_first_active(pxp_chan);
1101
1102 pxp_chan->completed = desc->txd.cookie;
1103
1104 callback = desc->txd.callback;
1105 callback_param = desc->txd.callback_param;
1106
1107 /* Send histogram status back to caller */
1108 desc->hist_status = hist_status;
1109
1110 if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback)
1111 callback(callback_param);
1112
1113 pxp_chan->status = PXP_CHANNEL_INITIALIZED;
1114
1115 list_splice_init(&desc->tx_list, &pxp_chan->free_list);
1116 list_move(&desc->list, &pxp_chan->free_list);
1117
1118 wake_up(&pxp->done);
1119 pxp->pxp_ongoing = 0;
1120 mod_timer(&pxp->clk_timer, jiffies + msecs_to_jiffies(timeout_in_ms));
1121
1122 spin_unlock_irqrestore(&pxp->lock, flags);
1123
1124 return IRQ_HANDLED;
1125}
1126
1127/* called with pxp_chan->lock held */
1128static struct pxp_tx_desc *pxpdma_desc_get(struct pxp_channel *pxp_chan)
1129{
1130 struct pxp_tx_desc *desc, *_desc;
1131 struct pxp_tx_desc *ret = NULL;
1132
1133 list_for_each_entry_safe(desc, _desc, &pxp_chan->free_list, list) {
1134 list_del_init(&desc->list);
1135 ret = desc;
1136 break;
1137 }
1138
1139 return ret;
1140}
1141
1142/* called with pxp_chan->lock held */
1143static void pxpdma_desc_put(struct pxp_channel *pxp_chan,
1144 struct pxp_tx_desc *desc)
1145{
1146 if (desc) {
1147 struct device *dev = &pxp_chan->dma_chan.dev->device;
1148 struct pxp_tx_desc *child;
1149
1150 list_for_each_entry(child, &desc->tx_list, list)
1151 dev_info(dev, "moving child desc %p to freelist\n", child);
1152 list_splice_init(&desc->tx_list, &pxp_chan->free_list);
1153 dev_info(dev, "moving desc %p to freelist\n", desc);
1154 list_add(&desc->list, &pxp_chan->free_list);
1155 }
1156}
1157
1158/* Allocate and initialise a transfer descriptor. */
1159static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan,
1160 struct scatterlist
1161 *sgl,
1162 unsigned int sg_len,
1163 enum
1164 dma_transfer_direction
1165 direction,
1166 unsigned long tx_flags,
1167 void *context)
1168{
1169 struct pxp_channel *pxp_chan = to_pxp_channel(chan);
1170 struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
1171 struct pxps *pxp = to_pxp(pxp_dma);
1172 struct pxp_tx_desc *desc = NULL;
1173 struct pxp_tx_desc *first = NULL, *prev = NULL;
1174 struct scatterlist *sg;
1175 unsigned long flags;
1176 dma_addr_t phys_addr;
1177 int i;
1178
1179 if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) {
1180 dev_err(chan->device->dev, "Invalid DMA direction %d!\n",
1181 direction);
1182 return NULL;
1183 }
1184
1185 if (unlikely(sg_len < 2))
1186 return NULL;
1187
1188 spin_lock_irqsave(&pxp_chan->lock, flags);
1189 for_each_sg(sgl, sg, sg_len, i) {
1190 desc = pxpdma_desc_get(pxp_chan);
1191 if (!desc) {
1192 pxpdma_desc_put(pxp_chan, first);
1193 dev_err(chan->device->dev, "Can't get DMA desc.\n");
1194 spin_unlock_irqrestore(&pxp_chan->lock, flags);
1195 return NULL;
1196 }
1197
1198 phys_addr = sg_dma_address(sg);
1199
1200 if (!first) {
1201 first = desc;
1202
1203 desc->layer_param.s0_param.paddr = phys_addr;
1204 } else {
1205 list_add_tail(&desc->list, &first->tx_list);
1206 prev->next = desc;
1207 desc->next = NULL;
1208
1209 if (i == 1)
1210 desc->layer_param.out_param.paddr = phys_addr;
1211 else
1212 desc->layer_param.ol_param.paddr = phys_addr;
1213 }
1214
1215 prev = desc;
1216 }
1217 spin_unlock_irqrestore(&pxp_chan->lock, flags);
1218
1219 pxp->pxp_conf_state.layer_nr = sg_len;
1220 first->txd.flags = tx_flags;
1221 first->len = sg_len;
1222 pr_debug("%s:%d first %p, first->len %d, flags %08x\n",
1223 __func__, __LINE__, first, first->len, first->txd.flags);
1224
1225 return &first->txd;
1226}
1227
1228static void pxp_issue_pending(struct dma_chan *chan)
1229{
1230 struct pxp_channel *pxp_chan = to_pxp_channel(chan);
1231 struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
1232 struct pxps *pxp = to_pxp(pxp_dma);
1233 unsigned long flags0, flags;
1234
1235 spin_lock_irqsave(&pxp->lock, flags0);
1236 spin_lock_irqsave(&pxp_chan->lock, flags);
1237
1238 if (!list_empty(&pxp_chan->queue)) {
1239 pxpdma_dequeue(pxp_chan, &pxp_chan->active_list);
1240 pxp_chan->status = PXP_CHANNEL_READY;
1241 list_add_tail(&pxp_chan->list, &head);
1242 } else {
1243 spin_unlock_irqrestore(&pxp_chan->lock, flags);
1244 spin_unlock_irqrestore(&pxp->lock, flags0);
1245 return;
1246 }
1247 spin_unlock_irqrestore(&pxp_chan->lock, flags);
1248 spin_unlock_irqrestore(&pxp->lock, flags0);
1249
1250 pxp_clk_enable(pxp);
1251 if (!wait_event_interruptible_timeout(pxp->done, PXP_WAITCON, 2 * HZ) ||
1252 signal_pending(current)) {
1253 pxp_clk_disable(pxp);
1254 return;
1255 }
1256
1257 spin_lock_irqsave(&pxp->lock, flags);
1258 pxp->pxp_ongoing = 1;
1259 spin_unlock_irqrestore(&pxp->lock, flags);
1260 pxpdma_dostart_work(pxp);
1261}
1262
1263static void __pxp_terminate_all(struct dma_chan *chan)
1264{
1265 struct pxp_channel *pxp_chan = to_pxp_channel(chan);
1266 unsigned long flags;
1267
1268 /* pchan->queue is modified in ISR, have to spinlock */
1269 spin_lock_irqsave(&pxp_chan->lock, flags);
1270 list_splice_init(&pxp_chan->queue, &pxp_chan->free_list);
1271 list_splice_init(&pxp_chan->active_list, &pxp_chan->free_list);
1272
1273 spin_unlock_irqrestore(&pxp_chan->lock, flags);
1274
1275 pxp_chan->status = PXP_CHANNEL_INITIALIZED;
1276}
1277
1278static int pxp_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1279 unsigned long arg)
1280{
1281 struct pxp_channel *pxp_chan = to_pxp_channel(chan);
1282
1283 /* Only supports DMA_TERMINATE_ALL */
1284 if (cmd != DMA_TERMINATE_ALL)
1285 return -ENXIO;
1286
1287 mutex_lock(&pxp_chan->chan_mutex);
1288 __pxp_terminate_all(chan);
1289 mutex_unlock(&pxp_chan->chan_mutex);
1290
1291 return 0;
1292}
1293
1294static int pxp_alloc_chan_resources(struct dma_chan *chan)
1295{
1296 struct pxp_channel *pxp_chan = to_pxp_channel(chan);
1297 struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
1298 int ret;
1299
1300 /* dmaengine.c now guarantees to only offer free channels */
1301 BUG_ON(chan->client_count > 1);
1302 WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE);
1303
1304 chan->cookie = 1;
1305 pxp_chan->completed = -ENXIO;
1306
1307 pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id);
1308 ret = pxp_init_channel(pxp_dma, pxp_chan);
1309 if (ret < 0)
1310 goto err_chan;
1311
1312 pxp_chan->status = PXP_CHANNEL_INITIALIZED;
1313
1314 dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n",
1315 chan->chan_id, pxp_chan->eof_irq);
1316
1317 return ret;
1318
1319err_chan:
1320 return ret;
1321}
1322
1323static void pxp_free_chan_resources(struct dma_chan *chan)
1324{
1325 struct pxp_channel *pxp_chan = to_pxp_channel(chan);
1326 struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
1327
1328 mutex_lock(&pxp_chan->chan_mutex);
1329
1330 __pxp_terminate_all(chan);
1331
1332 pxp_chan->status = PXP_CHANNEL_FREE;
1333
1334 pxp_uninit_channel(pxp_dma, pxp_chan);
1335
1336 mutex_unlock(&pxp_chan->chan_mutex);
1337}
1338
1339static enum dma_status pxp_tx_status(struct dma_chan *chan,
1340 dma_cookie_t cookie,
1341 struct dma_tx_state *txstate)
1342{
1343 struct pxp_channel *pxp_chan = to_pxp_channel(chan);
1344
1345 if (cookie != chan->cookie)
1346 return DMA_ERROR;
1347
1348 if (txstate) {
1349 txstate->last = pxp_chan->completed;
1350 txstate->used = chan->cookie;
1351 txstate->residue = 0;
1352 }
1353 return DMA_SUCCESS;
1354}
1355
1356static int pxp_hw_init(struct pxps *pxp)
1357{
1358 struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
1359 struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
1360 u32 reg_val;
1361
1362 /* Pull PxP out of reset */
1363 __raw_writel(0, pxp->base + HW_PXP_CTRL);
1364
1365 /* Config defaults */
1366
1367 /* Initialize non-channel-specific PxP parameters */
1368 proc_data->drect.left = proc_data->srect.left = 0;
1369 proc_data->drect.top = proc_data->srect.top = 0;
1370 proc_data->drect.width = proc_data->srect.width = 0;
1371 proc_data->drect.height = proc_data->srect.height = 0;
1372 proc_data->scaling = 0;
1373 proc_data->hflip = 0;
1374 proc_data->vflip = 0;
1375 proc_data->rotate = 0;
1376 proc_data->bgcolor = 0;
1377
1378 /* Initialize S0 channel parameters */
1379 pxp_conf->s0_param.pixel_fmt = pxp_s0_formats[0];
1380 pxp_conf->s0_param.width = 0;
1381 pxp_conf->s0_param.height = 0;
1382 pxp_conf->s0_param.color_key = -1;
1383 pxp_conf->s0_param.color_key_enable = false;
1384
1385 /* Initialize OL channel parameters */
1386 pxp_conf->ol_param[0].combine_enable = false;
1387 pxp_conf->ol_param[0].width = 0;
1388 pxp_conf->ol_param[0].height = 0;
1389 pxp_conf->ol_param[0].pixel_fmt = PXP_PIX_FMT_RGB565;
1390 pxp_conf->ol_param[0].color_key_enable = false;
1391 pxp_conf->ol_param[0].color_key = -1;
1392 pxp_conf->ol_param[0].global_alpha_enable = false;
1393 pxp_conf->ol_param[0].global_alpha = 0;
1394 pxp_conf->ol_param[0].local_alpha_enable = false;
1395
1396 /* Initialize Output channel parameters */
1397 pxp_conf->out_param.width = 0;
1398 pxp_conf->out_param.height = 0;
1399 pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_RGB565;
1400
1401 proc_data->overlay_state = 0;
1402
1403 /* Write default h/w config */
1404 pxp_set_ctrl(pxp);
1405 pxp_set_s0param(pxp);
1406 pxp_set_s0crop(pxp);
1407 /*
1408 * simply program the ULC to a higher value than the LRC
1409 * to avoid any AS pixels to show up in the output buffer.
1410 */
1411 __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_OUT_AS_ULC);
1412 pxp_set_olparam(0, pxp);
1413 pxp_set_olcolorkey(0, pxp);
1414
1415 pxp_set_s0colorkey(pxp);
1416 pxp_set_csc(pxp);
1417 pxp_set_bg(pxp);
1418 pxp_set_lut(pxp);
1419
1420 /* One-time histogram configuration */
1421 reg_val =
1422 BF_PXP_HIST_CTRL_PANEL_MODE(BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16);
1423 __raw_writel(reg_val, pxp->base + HW_PXP_HIST_CTRL);
1424
1425 reg_val = BF_PXP_HIST2_PARAM_VALUE0(0x00) |
1426 BF_PXP_HIST2_PARAM_VALUE1(0x00F);
1427 __raw_writel(reg_val, pxp->base + HW_PXP_HIST2_PARAM);
1428
1429 reg_val = BF_PXP_HIST4_PARAM_VALUE0(0x00) |
1430 BF_PXP_HIST4_PARAM_VALUE1(0x05) |
1431 BF_PXP_HIST4_PARAM_VALUE2(0x0A) | BF_PXP_HIST4_PARAM_VALUE3(0x0F);
1432 __raw_writel(reg_val, pxp->base + HW_PXP_HIST4_PARAM);
1433
1434 reg_val = BF_PXP_HIST8_PARAM0_VALUE0(0x00) |
1435 BF_PXP_HIST8_PARAM0_VALUE1(0x02) |
1436 BF_PXP_HIST8_PARAM0_VALUE2(0x04) | BF_PXP_HIST8_PARAM0_VALUE3(0x06);
1437 __raw_writel(reg_val, pxp->base + HW_PXP_HIST8_PARAM0);
1438 reg_val = BF_PXP_HIST8_PARAM1_VALUE4(0x09) |
1439 BF_PXP_HIST8_PARAM1_VALUE5(0x0B) |
1440 BF_PXP_HIST8_PARAM1_VALUE6(0x0D) | BF_PXP_HIST8_PARAM1_VALUE7(0x0F);
1441 __raw_writel(reg_val, pxp->base + HW_PXP_HIST8_PARAM1);
1442
1443 reg_val = BF_PXP_HIST16_PARAM0_VALUE0(0x00) |
1444 BF_PXP_HIST16_PARAM0_VALUE1(0x01) |
1445 BF_PXP_HIST16_PARAM0_VALUE2(0x02) |
1446 BF_PXP_HIST16_PARAM0_VALUE3(0x03);
1447 __raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM0);
1448 reg_val = BF_PXP_HIST16_PARAM1_VALUE4(0x04) |
1449 BF_PXP_HIST16_PARAM1_VALUE5(0x05) |
1450 BF_PXP_HIST16_PARAM1_VALUE6(0x06) |
1451 BF_PXP_HIST16_PARAM1_VALUE7(0x07);
1452 __raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM1);
1453 reg_val = BF_PXP_HIST16_PARAM2_VALUE8(0x08) |
1454 BF_PXP_HIST16_PARAM2_VALUE9(0x09) |
1455 BF_PXP_HIST16_PARAM2_VALUE10(0x0A) |
1456 BF_PXP_HIST16_PARAM2_VALUE11(0x0B);
1457 __raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM2);
1458 reg_val = BF_PXP_HIST16_PARAM3_VALUE12(0x0C) |
1459 BF_PXP_HIST16_PARAM3_VALUE13(0x0D) |
1460 BF_PXP_HIST16_PARAM3_VALUE14(0x0E) |
1461 BF_PXP_HIST16_PARAM3_VALUE15(0x0F);
1462 __raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM3);
1463
1464 return 0;
1465}
1466
1467static int pxp_dma_init(struct pxps *pxp)
1468{
1469 struct pxp_dma *pxp_dma = &pxp->pxp_dma;
1470 struct dma_device *dma = &pxp_dma->dma;
1471 int i;
1472
1473 dma_cap_set(DMA_SLAVE, dma->cap_mask);
1474 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1475
1476 /* Compulsory common fields */
1477 dma->dev = pxp->dev;
1478 dma->device_alloc_chan_resources = pxp_alloc_chan_resources;
1479 dma->device_free_chan_resources = pxp_free_chan_resources;
1480 dma->device_tx_status = pxp_tx_status;
1481 dma->device_issue_pending = pxp_issue_pending;
1482
1483 /* Compulsory for DMA_SLAVE fields */
1484 dma->device_prep_slave_sg = pxp_prep_slave_sg;
1485 dma->device_control = pxp_control;
1486
1487 /* Initialize PxP Channels */
1488 INIT_LIST_HEAD(&dma->channels);
1489 for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) {
1490 struct pxp_channel *pxp_chan = pxp->channel + i;
1491 struct dma_chan *dma_chan = &pxp_chan->dma_chan;
1492
1493 spin_lock_init(&pxp_chan->lock);
1494 mutex_init(&pxp_chan->chan_mutex);
1495
1496 /* Only one EOF IRQ for PxP, shared by all channels */
1497 pxp_chan->eof_irq = pxp->irq;
1498 pxp_chan->status = PXP_CHANNEL_FREE;
1499 pxp_chan->completed = -ENXIO;
1500 snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name),
1501 "PXP EOF %d", i);
1502
1503 dma_chan->device = &pxp_dma->dma;
1504 dma_chan->cookie = 1;
1505 dma_chan->chan_id = i;
1506 list_add_tail(&dma_chan->device_node, &dma->channels);
1507 }
1508
1509 return dma_async_device_register(&pxp_dma->dma);
1510}
1511
1512static ssize_t clk_off_timeout_show(struct device *dev,
1513 struct device_attribute *attr, char *buf)
1514{
1515 return sprintf(buf, "%d\n", timeout_in_ms);
1516}
1517
1518static ssize_t clk_off_timeout_store(struct device *dev,
1519 struct device_attribute *attr,
1520 const char *buf, size_t count)
1521{
1522 int val;
1523 if (sscanf(buf, "%d", &val) > 0) {
1524 timeout_in_ms = val;
1525 return count;
1526 }
1527 return -EINVAL;
1528}
1529
1530static DEVICE_ATTR(clk_off_timeout, 0644, clk_off_timeout_show,
1531 clk_off_timeout_store);
1532
1533static const struct of_device_id imx_pxpdma_dt_ids[] = {
1534 { .compatible = "fsl,imx6dl-pxp-dma", },
1535 { /* sentinel */ }
1536};
1537MODULE_DEVICE_TABLE(of, imx_pxpdma_dt_ids);
1538
1539static int pxp_probe(struct platform_device *pdev)
1540{
1541 struct pxps *pxp;
1542 struct resource *res;
1543 int irq;
1544 int err = 0;
1545
1546 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1547 irq = platform_get_irq(pdev, 0);
1548 if (!res || irq < 0) {
1549 err = -ENODEV;
1550 goto exit;
1551 }
1552
1553 pxp = devm_kzalloc(&pdev->dev, sizeof(*pxp), GFP_KERNEL);
1554 if (!pxp) {
1555 dev_err(&pdev->dev, "failed to allocate control object\n");
1556 err = -ENOMEM;
1557 goto exit;
1558 }
1559
1560 pxp->dev = &pdev->dev;
1561
1562 platform_set_drvdata(pdev, pxp);
1563 pxp->irq = irq;
1564
1565 pxp->pxp_ongoing = 0;
1566 pxp->lut_state = 0;
1567
1568 spin_lock_init(&pxp->lock);
1569 mutex_init(&pxp->clk_mutex);
1570
1571 pxp->base = devm_request_and_ioremap(&pdev->dev, res);
1572 if (pxp->base == NULL) {
1573 dev_err(&pdev->dev, "Couldn't ioremap regs\n");
1574 err = -ENODEV;
1575 goto exit;
1576 }
1577
1578 pxp->pdev = pdev;
1579
1580 pxp->clk = devm_clk_get(&pdev->dev, "pxp-axi");
1581 clk_prepare_enable(pxp->clk);
1582
1583 err = pxp_hw_init(pxp);
1584 clk_disable_unprepare(pxp->clk);
1585 if (err) {
1586 dev_err(&pdev->dev, "failed to initialize hardware\n");
1587 goto exit;
1588 }
1589
1590 err = devm_request_irq(&pdev->dev, pxp->irq, pxp_irq, 0,
1591 "pxp-dmaengine", pxp);
1592 if (err)
1593 goto exit;
1594 /* Initialize DMA engine */
1595 err = pxp_dma_init(pxp);
1596 if (err < 0)
1597 goto exit;
1598
1599 if (device_create_file(&pdev->dev, &dev_attr_clk_off_timeout)) {
1600 dev_err(&pdev->dev,
1601 "Unable to create file from clk_off_timeout\n");
1602 goto exit;
1603 }
1604 dump_pxp_reg(pxp);
1605
1606 INIT_WORK(&pxp->work, clkoff_callback);
1607 init_waitqueue_head(&pxp->done);
1608 init_timer(&pxp->clk_timer);
1609 pxp->clk_timer.function = pxp_clkoff_timer;
1610 pxp->clk_timer.data = (unsigned long)pxp;
1611
1612 register_pxp_device();
1613
1614exit:
1615 if (err)
1616 dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe()\n");
1617 return err;
1618}
1619
1620static int pxp_remove(struct platform_device *pdev)
1621{
1622 struct pxps *pxp = platform_get_drvdata(pdev);
1623
1624 unregister_pxp_device();
1625 cancel_work_sync(&pxp->work);
1626 del_timer_sync(&pxp->clk_timer);
1627 clk_disable_unprepare(pxp->clk);
1628 device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout);
1629
1630 return 0;
1631}
1632
1633#ifdef CONFIG_PM
1634static int pxp_suspend(struct platform_device *pdev, pm_message_t state)
1635{
1636 struct pxps *pxp = platform_get_drvdata(pdev);
1637
1638 pxp_clk_enable(pxp);
1639 while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE)
1640 ;
1641
1642 __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL);
1643 pxp_clk_disable(pxp);
1644
1645 return 0;
1646}
1647
1648static int pxp_resume(struct platform_device *pdev)
1649{
1650 struct pxps *pxp = platform_get_drvdata(pdev);
1651
1652 pxp_clk_enable(pxp);
1653 /* Pull PxP out of reset */
1654 __raw_writel(0, pxp->base + HW_PXP_CTRL);
1655 pxp_clk_disable(pxp);
1656
1657 return 0;
1658}
1659#else
1660#define pxp_suspend NULL
1661#define pxp_resume NULL
1662#endif
1663
1664static struct platform_driver pxp_driver = {
1665 .driver = {
1666 .name = "imx-pxp",
1667 .of_match_table = of_match_ptr(imx_pxpdma_dt_ids),
1668 },
1669 .probe = pxp_probe,
1670 .remove = pxp_remove,
1671 .suspend = pxp_suspend,
1672 .resume = pxp_resume,
1673};
1674
1675module_platform_driver(pxp_driver);
1676
1677
1678MODULE_DESCRIPTION("i.MX PxP driver");
1679MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1680MODULE_LICENSE("GPL");
diff --git a/drivers/dma/pxp/regs-pxp_v2.h b/drivers/dma/pxp/regs-pxp_v2.h
new file mode 100644
index 000000000000..37c832db3c19
--- /dev/null
+++ b/drivers/dma/pxp/regs-pxp_v2.h
@@ -0,0 +1,1152 @@
1/*
2 * Freescale PXP Register Definitions
3 *
4 * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * This file is created by xml file. Don't Edit it.
21 *
22 * Xml Revision: 1.29
23 * Template revision: 1.3
24 */
25
26#ifndef __ARCH_ARM___PXP_H
27#define __ARCH_ARM___PXP_H
28
29#define HW_PXP_CTRL (0x00000000)
30#define HW_PXP_CTRL_SET (0x00000004)
31#define HW_PXP_CTRL_CLR (0x00000008)
32#define HW_PXP_CTRL_TOG (0x0000000c)
33
34#define BM_PXP_CTRL_SFTRST 0x80000000
35#define BM_PXP_CTRL_CLKGATE 0x40000000
36#define BM_PXP_CTRL_RSVD4 0x20000000
37#define BM_PXP_CTRL_EN_REPEAT 0x10000000
38#define BP_PXP_CTRL_RSVD3 26
39#define BM_PXP_CTRL_RSVD3 0x0C000000
40#define BF_PXP_CTRL_RSVD3(v) \
41 (((v) << 26) & BM_PXP_CTRL_RSVD3)
42#define BP_PXP_CTRL_INTERLACED_INPUT 24
43#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000
44#define BF_PXP_CTRL_INTERLACED_INPUT(v) \
45 (((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT)
46#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0
47#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2
48#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3
49#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000
50#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0
51#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1
52#define BM_PXP_CTRL_ROT_POS 0x00400000
53#define BM_PXP_CTRL_IN_PLACE 0x00200000
54#define BP_PXP_CTRL_RSVD1 12
55#define BM_PXP_CTRL_RSVD1 0x001FF000
56#define BF_PXP_CTRL_RSVD1(v) \
57 (((v) << 12) & BM_PXP_CTRL_RSVD1)
58#define BM_PXP_CTRL_VFLIP 0x00000800
59#define BM_PXP_CTRL_HFLIP 0x00000400
60#define BP_PXP_CTRL_ROTATE 8
61#define BM_PXP_CTRL_ROTATE 0x00000300
62#define BF_PXP_CTRL_ROTATE(v) \
63 (((v) << 8) & BM_PXP_CTRL_ROTATE)
64#define BV_PXP_CTRL_ROTATE__ROT_0 0x0
65#define BV_PXP_CTRL_ROTATE__ROT_90 0x1
66#define BV_PXP_CTRL_ROTATE__ROT_180 0x2
67#define BV_PXP_CTRL_ROTATE__ROT_270 0x3
68#define BP_PXP_CTRL_RSVD0 5
69#define BM_PXP_CTRL_RSVD0 0x000000E0
70#define BF_PXP_CTRL_RSVD0(v) \
71 (((v) << 5) & BM_PXP_CTRL_RSVD0)
72#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000010
73#define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008
74#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004
75#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
76#define BM_PXP_CTRL_ENABLE 0x00000001
77
78#define HW_PXP_STAT (0x00000010)
79#define HW_PXP_STAT_SET (0x00000014)
80#define HW_PXP_STAT_CLR (0x00000018)
81#define HW_PXP_STAT_TOG (0x0000001c)
82
83#define BP_PXP_STAT_BLOCKX 24
84#define BM_PXP_STAT_BLOCKX 0xFF000000
85#define BF_PXP_STAT_BLOCKX(v) \
86 (((v) << 24) & BM_PXP_STAT_BLOCKX)
87#define BP_PXP_STAT_BLOCKY 16
88#define BM_PXP_STAT_BLOCKY 0x00FF0000
89#define BF_PXP_STAT_BLOCKY(v) \
90 (((v) << 16) & BM_PXP_STAT_BLOCKY)
91#define BP_PXP_STAT_RSVD2 9
92#define BM_PXP_STAT_RSVD2 0x0000FE00
93#define BF_PXP_STAT_RSVD2(v) \
94 (((v) << 9) & BM_PXP_STAT_RSVD2)
95#define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100
96#define BP_PXP_STAT_AXI_ERROR_ID 4
97#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0
98#define BF_PXP_STAT_AXI_ERROR_ID(v) \
99 (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID)
100#define BM_PXP_STAT_NEXT_IRQ 0x00000008
101#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004
102#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002
103#define BM_PXP_STAT_IRQ 0x00000001
104
105#define HW_PXP_OUT_CTRL (0x00000020)
106#define HW_PXP_OUT_CTRL_SET (0x00000024)
107#define HW_PXP_OUT_CTRL_CLR (0x00000028)
108#define HW_PXP_OUT_CTRL_TOG (0x0000002c)
109
110#define BP_PXP_OUT_CTRL_ALPHA 24
111#define BM_PXP_OUT_CTRL_ALPHA 0xFF000000
112#define BF_PXP_OUT_CTRL_ALPHA(v) \
113 (((v) << 24) & BM_PXP_OUT_CTRL_ALPHA)
114#define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000
115#define BP_PXP_OUT_CTRL_RSVD1 10
116#define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00
117#define BF_PXP_OUT_CTRL_RSVD1(v) \
118 (((v) << 10) & BM_PXP_OUT_CTRL_RSVD1)
119#define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT 8
120#define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300
121#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \
122 (((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT)
123#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0
124#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1
125#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2
126#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3
127#define BP_PXP_OUT_CTRL_RSVD0 5
128#define BM_PXP_OUT_CTRL_RSVD0 0x000000E0
129#define BF_PXP_OUT_CTRL_RSVD0(v) \
130 (((v) << 5) & BM_PXP_OUT_CTRL_RSVD0)
131#define BP_PXP_OUT_CTRL_FORMAT 0
132#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F
133#define BF_PXP_OUT_CTRL_FORMAT(v) \
134 (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT)
135#define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0
136#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4
137#define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5
138#define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8
139#define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9
140#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC
141#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD
142#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE
143#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10
144#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12
145#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13
146#define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14
147#define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15
148#define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18
149#define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19
150#define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A
151#define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B
152
153#define HW_PXP_OUT_BUF (0x00000030)
154
155#define BP_PXP_OUT_BUF_ADDR 0
156#define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF
157#define BF_PXP_OUT_BUF_ADDR(v) (v)
158
159#define HW_PXP_OUT_BUF2 (0x00000040)
160
161#define BP_PXP_OUT_BUF2_ADDR 0
162#define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF
163#define BF_PXP_OUT_BUF2_ADDR(v) (v)
164
165#define HW_PXP_OUT_PITCH (0x00000050)
166
167#define BP_PXP_OUT_PITCH_RSVD 16
168#define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000
169#define BF_PXP_OUT_PITCH_RSVD(v) \
170 (((v) << 16) & BM_PXP_OUT_PITCH_RSVD)
171#define BP_PXP_OUT_PITCH_PITCH 0
172#define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF
173#define BF_PXP_OUT_PITCH_PITCH(v) \
174 (((v) << 0) & BM_PXP_OUT_PITCH_PITCH)
175
176#define HW_PXP_OUT_LRC (0x00000060)
177
178#define BP_PXP_OUT_LRC_RSVD1 30
179#define BM_PXP_OUT_LRC_RSVD1 0xC0000000
180#define BF_PXP_OUT_LRC_RSVD1(v) \
181 (((v) << 30) & BM_PXP_OUT_LRC_RSVD1)
182#define BP_PXP_OUT_LRC_X 16
183#define BM_PXP_OUT_LRC_X 0x3FFF0000
184#define BF_PXP_OUT_LRC_X(v) \
185 (((v) << 16) & BM_PXP_OUT_LRC_X)
186#define BP_PXP_OUT_LRC_RSVD0 14
187#define BM_PXP_OUT_LRC_RSVD0 0x0000C000
188#define BF_PXP_OUT_LRC_RSVD0(v) \
189 (((v) << 14) & BM_PXP_OUT_LRC_RSVD0)
190#define BP_PXP_OUT_LRC_Y 0
191#define BM_PXP_OUT_LRC_Y 0x00003FFF
192#define BF_PXP_OUT_LRC_Y(v) \
193 (((v) << 0) & BM_PXP_OUT_LRC_Y)
194
195#define HW_PXP_OUT_PS_ULC (0x00000070)
196
197#define BP_PXP_OUT_PS_ULC_RSVD1 30
198#define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000
199#define BF_PXP_OUT_PS_ULC_RSVD1(v) \
200 (((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1)
201#define BP_PXP_OUT_PS_ULC_X 16
202#define BM_PXP_OUT_PS_ULC_X 0x3FFF0000
203#define BF_PXP_OUT_PS_ULC_X(v) \
204 (((v) << 16) & BM_PXP_OUT_PS_ULC_X)
205#define BP_PXP_OUT_PS_ULC_RSVD0 14
206#define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000
207#define BF_PXP_OUT_PS_ULC_RSVD0(v) \
208 (((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0)
209#define BP_PXP_OUT_PS_ULC_Y 0
210#define BM_PXP_OUT_PS_ULC_Y 0x00003FFF
211#define BF_PXP_OUT_PS_ULC_Y(v) \
212 (((v) << 0) & BM_PXP_OUT_PS_ULC_Y)
213
214#define HW_PXP_OUT_PS_LRC (0x00000080)
215
216#define BP_PXP_OUT_PS_LRC_RSVD1 30
217#define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000
218#define BF_PXP_OUT_PS_LRC_RSVD1(v) \
219 (((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1)
220#define BP_PXP_OUT_PS_LRC_X 16
221#define BM_PXP_OUT_PS_LRC_X 0x3FFF0000
222#define BF_PXP_OUT_PS_LRC_X(v) \
223 (((v) << 16) & BM_PXP_OUT_PS_LRC_X)
224#define BP_PXP_OUT_PS_LRC_RSVD0 14
225#define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000
226#define BF_PXP_OUT_PS_LRC_RSVD0(v) \
227 (((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0)
228#define BP_PXP_OUT_PS_LRC_Y 0
229#define BM_PXP_OUT_PS_LRC_Y 0x00003FFF
230#define BF_PXP_OUT_PS_LRC_Y(v) \
231 (((v) << 0) & BM_PXP_OUT_PS_LRC_Y)
232
233#define HW_PXP_OUT_AS_ULC (0x00000090)
234
235#define BP_PXP_OUT_AS_ULC_RSVD1 30
236#define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000
237#define BF_PXP_OUT_AS_ULC_RSVD1(v) \
238 (((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1)
239#define BP_PXP_OUT_AS_ULC_X 16
240#define BM_PXP_OUT_AS_ULC_X 0x3FFF0000
241#define BF_PXP_OUT_AS_ULC_X(v) \
242 (((v) << 16) & BM_PXP_OUT_AS_ULC_X)
243#define BP_PXP_OUT_AS_ULC_RSVD0 14
244#define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000
245#define BF_PXP_OUT_AS_ULC_RSVD0(v) \
246 (((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0)
247#define BP_PXP_OUT_AS_ULC_Y 0
248#define BM_PXP_OUT_AS_ULC_Y 0x00003FFF
249#define BF_PXP_OUT_AS_ULC_Y(v) \
250 (((v) << 0) & BM_PXP_OUT_AS_ULC_Y)
251
252#define HW_PXP_OUT_AS_LRC (0x000000a0)
253
254#define BP_PXP_OUT_AS_LRC_RSVD1 30
255#define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000
256#define BF_PXP_OUT_AS_LRC_RSVD1(v) \
257 (((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1)
258#define BP_PXP_OUT_AS_LRC_X 16
259#define BM_PXP_OUT_AS_LRC_X 0x3FFF0000
260#define BF_PXP_OUT_AS_LRC_X(v) \
261 (((v) << 16) & BM_PXP_OUT_AS_LRC_X)
262#define BP_PXP_OUT_AS_LRC_RSVD0 14
263#define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000
264#define BF_PXP_OUT_AS_LRC_RSVD0(v) \
265 (((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0)
266#define BP_PXP_OUT_AS_LRC_Y 0
267#define BM_PXP_OUT_AS_LRC_Y 0x00003FFF
268#define BF_PXP_OUT_AS_LRC_Y(v) \
269 (((v) << 0) & BM_PXP_OUT_AS_LRC_Y)
270
271#define HW_PXP_PS_CTRL (0x000000b0)
272#define HW_PXP_PS_CTRL_SET (0x000000b4)
273#define HW_PXP_PS_CTRL_CLR (0x000000b8)
274#define HW_PXP_PS_CTRL_TOG (0x000000bc)
275
276#define BP_PXP_PS_CTRL_RSVD1 12
277#define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000
278#define BF_PXP_PS_CTRL_RSVD1(v) \
279 (((v) << 12) & BM_PXP_PS_CTRL_RSVD1)
280#define BP_PXP_PS_CTRL_DECX 10
281#define BM_PXP_PS_CTRL_DECX 0x00000C00
282#define BF_PXP_PS_CTRL_DECX(v) \
283 (((v) << 10) & BM_PXP_PS_CTRL_DECX)
284#define BV_PXP_PS_CTRL_DECX__DISABLE 0x0
285#define BV_PXP_PS_CTRL_DECX__DECX2 0x1
286#define BV_PXP_PS_CTRL_DECX__DECX4 0x2
287#define BV_PXP_PS_CTRL_DECX__DECX8 0x3
288#define BP_PXP_PS_CTRL_DECY 8
289#define BM_PXP_PS_CTRL_DECY 0x00000300
290#define BF_PXP_PS_CTRL_DECY(v) \
291 (((v) << 8) & BM_PXP_PS_CTRL_DECY)
292#define BV_PXP_PS_CTRL_DECY__DISABLE 0x0
293#define BV_PXP_PS_CTRL_DECY__DECY2 0x1
294#define BV_PXP_PS_CTRL_DECY__DECY4 0x2
295#define BV_PXP_PS_CTRL_DECY__DECY8 0x3
296#define BP_PXP_PS_CTRL_RSVD0 5
297#define BM_PXP_PS_CTRL_RSVD0 0x000000E0
298#define BF_PXP_PS_CTRL_RSVD0(v) \
299 (((v) << 5) & BM_PXP_PS_CTRL_RSVD0)
300#define BP_PXP_PS_CTRL_FORMAT 0
301#define BM_PXP_PS_CTRL_FORMAT 0x0000001F
302#define BF_PXP_PS_CTRL_FORMAT(v) \
303 (((v) << 0) & BM_PXP_PS_CTRL_FORMAT)
304#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4
305#define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC
306#define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD
307#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE
308#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10
309#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12
310#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13
311#define BV_PXP_PS_CTRL_FORMAT__Y8 0x14
312#define BV_PXP_PS_CTRL_FORMAT__Y4 0x15
313#define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18
314#define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19
315#define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A
316#define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B
317#define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E
318#define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F
319
320#define HW_PXP_PS_BUF (0x000000c0)
321
322#define BP_PXP_PS_BUF_ADDR 0
323#define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF
324#define BF_PXP_PS_BUF_ADDR(v) (v)
325
326#define HW_PXP_PS_UBUF (0x000000d0)
327
328#define BP_PXP_PS_UBUF_ADDR 0
329#define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF
330#define BF_PXP_PS_UBUF_ADDR(v) (v)
331
332#define HW_PXP_PS_VBUF (0x000000e0)
333
334#define BP_PXP_PS_VBUF_ADDR 0
335#define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF
336#define BF_PXP_PS_VBUF_ADDR(v) (v)
337
338#define HW_PXP_PS_PITCH (0x000000f0)
339
340#define BP_PXP_PS_PITCH_RSVD 16
341#define BM_PXP_PS_PITCH_RSVD 0xFFFF0000
342#define BF_PXP_PS_PITCH_RSVD(v) \
343 (((v) << 16) & BM_PXP_PS_PITCH_RSVD)
344#define BP_PXP_PS_PITCH_PITCH 0
345#define BM_PXP_PS_PITCH_PITCH 0x0000FFFF
346#define BF_PXP_PS_PITCH_PITCH(v) \
347 (((v) << 0) & BM_PXP_PS_PITCH_PITCH)
348
349#define HW_PXP_PS_BACKGROUND (0x00000100)
350
351#define BP_PXP_PS_BACKGROUND_RSVD 24
352#define BM_PXP_PS_BACKGROUND_RSVD 0xFF000000
353#define BF_PXP_PS_BACKGROUND_RSVD(v) \
354 (((v) << 24) & BM_PXP_PS_BACKGROUND_RSVD)
355#define BP_PXP_PS_BACKGROUND_COLOR 0
356#define BM_PXP_PS_BACKGROUND_COLOR 0x00FFFFFF
357#define BF_PXP_PS_BACKGROUND_COLOR(v) \
358 (((v) << 0) & BM_PXP_PS_BACKGROUND_COLOR)
359
360#define HW_PXP_PS_SCALE (0x00000110)
361
362#define BM_PXP_PS_SCALE_RSVD2 0x80000000
363#define BP_PXP_PS_SCALE_YSCALE 16
364#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000
365#define BF_PXP_PS_SCALE_YSCALE(v) \
366 (((v) << 16) & BM_PXP_PS_SCALE_YSCALE)
367#define BM_PXP_PS_SCALE_RSVD1 0x00008000
368#define BP_PXP_PS_SCALE_XSCALE 0
369#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF
370#define BF_PXP_PS_SCALE_XSCALE(v) \
371 (((v) << 0) & BM_PXP_PS_SCALE_XSCALE)
372
373#define HW_PXP_PS_OFFSET (0x00000120)
374
375#define BP_PXP_PS_OFFSET_RSVD2 28
376#define BM_PXP_PS_OFFSET_RSVD2 0xF0000000
377#define BF_PXP_PS_OFFSET_RSVD2(v) \
378 (((v) << 28) & BM_PXP_PS_OFFSET_RSVD2)
379#define BP_PXP_PS_OFFSET_YOFFSET 16
380#define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000
381#define BF_PXP_PS_OFFSET_YOFFSET(v) \
382 (((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET)
383#define BP_PXP_PS_OFFSET_RSVD1 12
384#define BM_PXP_PS_OFFSET_RSVD1 0x0000F000
385#define BF_PXP_PS_OFFSET_RSVD1(v) \
386 (((v) << 12) & BM_PXP_PS_OFFSET_RSVD1)
387#define BP_PXP_PS_OFFSET_XOFFSET 0
388#define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF
389#define BF_PXP_PS_OFFSET_XOFFSET(v) \
390 (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET)
391
392#define HW_PXP_PS_CLRKEYLOW (0x00000130)
393
394#define BP_PXP_PS_CLRKEYLOW_RSVD1 24
395#define BM_PXP_PS_CLRKEYLOW_RSVD1 0xFF000000
396#define BF_PXP_PS_CLRKEYLOW_RSVD1(v) \
397 (((v) << 24) & BM_PXP_PS_CLRKEYLOW_RSVD1)
398#define BP_PXP_PS_CLRKEYLOW_PIXEL 0
399#define BM_PXP_PS_CLRKEYLOW_PIXEL 0x00FFFFFF
400#define BF_PXP_PS_CLRKEYLOW_PIXEL(v) \
401 (((v) << 0) & BM_PXP_PS_CLRKEYLOW_PIXEL)
402
403#define HW_PXP_PS_CLRKEYHIGH (0x00000140)
404
405#define BP_PXP_PS_CLRKEYHIGH_RSVD1 24
406#define BM_PXP_PS_CLRKEYHIGH_RSVD1 0xFF000000
407#define BF_PXP_PS_CLRKEYHIGH_RSVD1(v) \
408 (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_RSVD1)
409#define BP_PXP_PS_CLRKEYHIGH_PIXEL 0
410#define BM_PXP_PS_CLRKEYHIGH_PIXEL 0x00FFFFFF
411#define BF_PXP_PS_CLRKEYHIGH_PIXEL(v) \
412 (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_PIXEL)
413
414#define HW_PXP_AS_CTRL (0x00000150)
415
416#define BP_PXP_AS_CTRL_RSVD1 21
417#define BM_PXP_AS_CTRL_RSVD1 0xFFE00000
418#define BF_PXP_AS_CTRL_RSVD1(v) \
419 (((v) << 21) & BM_PXP_AS_CTRL_RSVD1)
420#define BM_PXP_AS_CTRL_ALPHA_INVERT 0x00100000
421#define BP_PXP_AS_CTRL_ROP 16
422#define BM_PXP_AS_CTRL_ROP 0x000F0000
423#define BF_PXP_AS_CTRL_ROP(v) \
424 (((v) << 16) & BM_PXP_AS_CTRL_ROP)
425#define BV_PXP_AS_CTRL_ROP__MASKAS 0x0
426#define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1
427#define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2
428#define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3
429#define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4
430#define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5
431#define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6
432#define BV_PXP_AS_CTRL_ROP__NOT 0x7
433#define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8
434#define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9
435#define BV_PXP_AS_CTRL_ROP__XORAS 0xA
436#define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB
437#define BP_PXP_AS_CTRL_ALPHA 8
438#define BM_PXP_AS_CTRL_ALPHA 0x0000FF00
439#define BF_PXP_AS_CTRL_ALPHA(v) \
440 (((v) << 8) & BM_PXP_AS_CTRL_ALPHA)
441#define BP_PXP_AS_CTRL_FORMAT 4
442#define BM_PXP_AS_CTRL_FORMAT 0x000000F0
443#define BF_PXP_AS_CTRL_FORMAT(v) \
444 (((v) << 4) & BM_PXP_AS_CTRL_FORMAT)
445#define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0
446#define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4
447#define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8
448#define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9
449#define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC
450#define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD
451#define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE
452#define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008
453#define BP_PXP_AS_CTRL_ALPHA_CTRL 1
454#define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006
455#define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \
456 (((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL)
457#define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0
458#define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1
459#define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2
460#define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3
461#define BM_PXP_AS_CTRL_RSVD0 0x00000001
462
463#define HW_PXP_AS_BUF (0x00000160)
464
465#define BP_PXP_AS_BUF_ADDR 0
466#define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF
467#define BF_PXP_AS_BUF_ADDR(v) (v)
468
469#define HW_PXP_AS_PITCH (0x00000170)
470
471#define BP_PXP_AS_PITCH_RSVD 16
472#define BM_PXP_AS_PITCH_RSVD 0xFFFF0000
473#define BF_PXP_AS_PITCH_RSVD(v) \
474 (((v) << 16) & BM_PXP_AS_PITCH_RSVD)
475#define BP_PXP_AS_PITCH_PITCH 0
476#define BM_PXP_AS_PITCH_PITCH 0x0000FFFF
477#define BF_PXP_AS_PITCH_PITCH(v) \
478 (((v) << 0) & BM_PXP_AS_PITCH_PITCH)
479
480#define HW_PXP_AS_CLRKEYLOW (0x00000180)
481
482#define BP_PXP_AS_CLRKEYLOW_RSVD1 24
483#define BM_PXP_AS_CLRKEYLOW_RSVD1 0xFF000000
484#define BF_PXP_AS_CLRKEYLOW_RSVD1(v) \
485 (((v) << 24) & BM_PXP_AS_CLRKEYLOW_RSVD1)
486#define BP_PXP_AS_CLRKEYLOW_PIXEL 0
487#define BM_PXP_AS_CLRKEYLOW_PIXEL 0x00FFFFFF
488#define BF_PXP_AS_CLRKEYLOW_PIXEL(v) \
489 (((v) << 0) & BM_PXP_AS_CLRKEYLOW_PIXEL)
490
491#define HW_PXP_AS_CLRKEYHIGH (0x00000190)
492
493#define BP_PXP_AS_CLRKEYHIGH_RSVD1 24
494#define BM_PXP_AS_CLRKEYHIGH_RSVD1 0xFF000000
495#define BF_PXP_AS_CLRKEYHIGH_RSVD1(v) \
496 (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_RSVD1)
497#define BP_PXP_AS_CLRKEYHIGH_PIXEL 0
498#define BM_PXP_AS_CLRKEYHIGH_PIXEL 0x00FFFFFF
499#define BF_PXP_AS_CLRKEYHIGH_PIXEL(v) \
500 (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_PIXEL)
501
502#define HW_PXP_CSC1_COEF0 (0x000001a0)
503
504#define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000
505#define BM_PXP_CSC1_COEF0_BYPASS 0x40000000
506#define BM_PXP_CSC1_COEF0_RSVD1 0x20000000
507#define BP_PXP_CSC1_COEF0_C0 18
508#define BM_PXP_CSC1_COEF0_C0 0x1FFC0000
509#define BF_PXP_CSC1_COEF0_C0(v) \
510 (((v) << 18) & BM_PXP_CSC1_COEF0_C0)
511#define BP_PXP_CSC1_COEF0_UV_OFFSET 9
512#define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00
513#define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \
514 (((v) << 9) & BM_PXP_CSC1_COEF0_UV_OFFSET)
515#define BP_PXP_CSC1_COEF0_Y_OFFSET 0
516#define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF
517#define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \
518 (((v) << 0) & BM_PXP_CSC1_COEF0_Y_OFFSET)
519
520#define HW_PXP_CSC1_COEF1 (0x000001b0)
521
522#define BP_PXP_CSC1_COEF1_RSVD1 27
523#define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000
524#define BF_PXP_CSC1_COEF1_RSVD1(v) \
525 (((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1)
526#define BP_PXP_CSC1_COEF1_C1 16
527#define BM_PXP_CSC1_COEF1_C1 0x07FF0000
528#define BF_PXP_CSC1_COEF1_C1(v) \
529 (((v) << 16) & BM_PXP_CSC1_COEF1_C1)
530#define BP_PXP_CSC1_COEF1_RSVD0 11
531#define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800
532#define BF_PXP_CSC1_COEF1_RSVD0(v) \
533 (((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0)
534#define BP_PXP_CSC1_COEF1_C4 0
535#define BM_PXP_CSC1_COEF1_C4 0x000007FF
536#define BF_PXP_CSC1_COEF1_C4(v) \
537 (((v) << 0) & BM_PXP_CSC1_COEF1_C4)
538
539#define HW_PXP_CSC1_COEF2 (0x000001c0)
540
541#define BP_PXP_CSC1_COEF2_RSVD1 27
542#define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000
543#define BF_PXP_CSC1_COEF2_RSVD1(v) \
544 (((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1)
545#define BP_PXP_CSC1_COEF2_C2 16
546#define BM_PXP_CSC1_COEF2_C2 0x07FF0000
547#define BF_PXP_CSC1_COEF2_C2(v) \
548 (((v) << 16) & BM_PXP_CSC1_COEF2_C2)
549#define BP_PXP_CSC1_COEF2_RSVD0 11
550#define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800
551#define BF_PXP_CSC1_COEF2_RSVD0(v) \
552 (((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0)
553#define BP_PXP_CSC1_COEF2_C3 0
554#define BM_PXP_CSC1_COEF2_C3 0x000007FF
555#define BF_PXP_CSC1_COEF2_C3(v) \
556 (((v) << 0) & BM_PXP_CSC1_COEF2_C3)
557
558#define HW_PXP_CSC2_CTRL (0x000001d0)
559
560#define BP_PXP_CSC2_CTRL_RSVD 3
561#define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8
562#define BF_PXP_CSC2_CTRL_RSVD(v) \
563 (((v) << 3) & BM_PXP_CSC2_CTRL_RSVD)
564#define BP_PXP_CSC2_CTRL_CSC_MODE 1
565#define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006
566#define BF_PXP_CSC2_CTRL_CSC_MODE(v) \
567 (((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE)
568#define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0
569#define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1
570#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2
571#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3
572#define BM_PXP_CSC2_CTRL_BYPASS 0x00000001
573
574#define HW_PXP_CSC2_COEF0 (0x000001e0)
575
576#define BP_PXP_CSC2_COEF0_RSVD1 27
577#define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000
578#define BF_PXP_CSC2_COEF0_RSVD1(v) \
579 (((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1)
580#define BP_PXP_CSC2_COEF0_A2 16
581#define BM_PXP_CSC2_COEF0_A2 0x07FF0000
582#define BF_PXP_CSC2_COEF0_A2(v) \
583 (((v) << 16) & BM_PXP_CSC2_COEF0_A2)
584#define BP_PXP_CSC2_COEF0_RSVD0 11
585#define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800
586#define BF_PXP_CSC2_COEF0_RSVD0(v) \
587 (((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0)
588#define BP_PXP_CSC2_COEF0_A1 0
589#define BM_PXP_CSC2_COEF0_A1 0x000007FF
590#define BF_PXP_CSC2_COEF0_A1(v) \
591 (((v) << 0) & BM_PXP_CSC2_COEF0_A1)
592
593#define HW_PXP_CSC2_COEF1 (0x000001f0)
594
595#define BP_PXP_CSC2_COEF1_RSVD1 27
596#define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000
597#define BF_PXP_CSC2_COEF1_RSVD1(v) \
598 (((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1)
599#define BP_PXP_CSC2_COEF1_B1 16
600#define BM_PXP_CSC2_COEF1_B1 0x07FF0000
601#define BF_PXP_CSC2_COEF1_B1(v) \
602 (((v) << 16) & BM_PXP_CSC2_COEF1_B1)
603#define BP_PXP_CSC2_COEF1_RSVD0 11
604#define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800
605#define BF_PXP_CSC2_COEF1_RSVD0(v) \
606 (((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0)
607#define BP_PXP_CSC2_COEF1_A3 0
608#define BM_PXP_CSC2_COEF1_A3 0x000007FF
609#define BF_PXP_CSC2_COEF1_A3(v) \
610 (((v) << 0) & BM_PXP_CSC2_COEF1_A3)
611
612#define HW_PXP_CSC2_COEF2 (0x00000200)
613
614#define BP_PXP_CSC2_COEF2_RSVD1 27
615#define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000
616#define BF_PXP_CSC2_COEF2_RSVD1(v) \
617 (((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1)
618#define BP_PXP_CSC2_COEF2_B3 16
619#define BM_PXP_CSC2_COEF2_B3 0x07FF0000
620#define BF_PXP_CSC2_COEF2_B3(v) \
621 (((v) << 16) & BM_PXP_CSC2_COEF2_B3)
622#define BP_PXP_CSC2_COEF2_RSVD0 11
623#define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800
624#define BF_PXP_CSC2_COEF2_RSVD0(v) \
625 (((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0)
626#define BP_PXP_CSC2_COEF2_B2 0
627#define BM_PXP_CSC2_COEF2_B2 0x000007FF
628#define BF_PXP_CSC2_COEF2_B2(v) \
629 (((v) << 0) & BM_PXP_CSC2_COEF2_B2)
630
631#define HW_PXP_CSC2_COEF3 (0x00000210)
632
633#define BP_PXP_CSC2_COEF3_RSVD1 27
634#define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000
635#define BF_PXP_CSC2_COEF3_RSVD1(v) \
636 (((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1)
637#define BP_PXP_CSC2_COEF3_C2 16
638#define BM_PXP_CSC2_COEF3_C2 0x07FF0000
639#define BF_PXP_CSC2_COEF3_C2(v) \
640 (((v) << 16) & BM_PXP_CSC2_COEF3_C2)
641#define BP_PXP_CSC2_COEF3_RSVD0 11
642#define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800
643#define BF_PXP_CSC2_COEF3_RSVD0(v) \
644 (((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0)
645#define BP_PXP_CSC2_COEF3_C1 0
646#define BM_PXP_CSC2_COEF3_C1 0x000007FF
647#define BF_PXP_CSC2_COEF3_C1(v) \
648 (((v) << 0) & BM_PXP_CSC2_COEF3_C1)
649
650#define HW_PXP_CSC2_COEF4 (0x00000220)
651
652#define BP_PXP_CSC2_COEF4_RSVD1 25
653#define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000
654#define BF_PXP_CSC2_COEF4_RSVD1(v) \
655 (((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1)
656#define BP_PXP_CSC2_COEF4_D1 16
657#define BM_PXP_CSC2_COEF4_D1 0x01FF0000
658#define BF_PXP_CSC2_COEF4_D1(v) \
659 (((v) << 16) & BM_PXP_CSC2_COEF4_D1)
660#define BP_PXP_CSC2_COEF4_RSVD0 11
661#define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800
662#define BF_PXP_CSC2_COEF4_RSVD0(v) \
663 (((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0)
664#define BP_PXP_CSC2_COEF4_C3 0
665#define BM_PXP_CSC2_COEF4_C3 0x000007FF
666#define BF_PXP_CSC2_COEF4_C3(v) \
667 (((v) << 0) & BM_PXP_CSC2_COEF4_C3)
668
669#define HW_PXP_CSC2_COEF5 (0x00000230)
670
671#define BP_PXP_CSC2_COEF5_RSVD1 25
672#define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000
673#define BF_PXP_CSC2_COEF5_RSVD1(v) \
674 (((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1)
675#define BP_PXP_CSC2_COEF5_D3 16
676#define BM_PXP_CSC2_COEF5_D3 0x01FF0000
677#define BF_PXP_CSC2_COEF5_D3(v) \
678 (((v) << 16) & BM_PXP_CSC2_COEF5_D3)
679#define BP_PXP_CSC2_COEF5_RSVD0 9
680#define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00
681#define BF_PXP_CSC2_COEF5_RSVD0(v) \
682 (((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0)
683#define BP_PXP_CSC2_COEF5_D2 0
684#define BM_PXP_CSC2_COEF5_D2 0x000001FF
685#define BF_PXP_CSC2_COEF5_D2(v) \
686 (((v) << 0) & BM_PXP_CSC2_COEF5_D2)
687
688#define HW_PXP_LUT_CTRL (0x00000240)
689
690#define BM_PXP_LUT_CTRL_BYPASS 0x80000000
691#define BP_PXP_LUT_CTRL_RSVD3 26
692#define BM_PXP_LUT_CTRL_RSVD3 0x7C000000
693#define BF_PXP_LUT_CTRL_RSVD3(v) \
694 (((v) << 26) & BM_PXP_LUT_CTRL_RSVD3)
695#define BP_PXP_LUT_CTRL_LOOKUP_MODE 24
696#define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000
697#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \
698 (((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE)
699#define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0
700#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1
701#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2
702#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3
703#define BP_PXP_LUT_CTRL_RSVD2 18
704#define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000
705#define BF_PXP_LUT_CTRL_RSVD2(v) \
706 (((v) << 18) & BM_PXP_LUT_CTRL_RSVD2)
707#define BP_PXP_LUT_CTRL_OUT_MODE 16
708#define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000
709#define BF_PXP_LUT_CTRL_OUT_MODE(v) \
710 (((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE)
711#define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0
712#define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1
713#define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2
714#define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3
715#define BP_PXP_LUT_CTRL_RSVD1 11
716#define BM_PXP_LUT_CTRL_RSVD1 0x0000F800
717#define BF_PXP_LUT_CTRL_RSVD1(v) \
718 (((v) << 11) & BM_PXP_LUT_CTRL_RSVD1)
719#define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400
720#define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200
721#define BM_PXP_LUT_CTRL_INVALID 0x00000100
722#define BP_PXP_LUT_CTRL_RSVD0 1
723#define BM_PXP_LUT_CTRL_RSVD0 0x000000FE
724#define BF_PXP_LUT_CTRL_RSVD0(v) \
725 (((v) << 1) & BM_PXP_LUT_CTRL_RSVD0)
726#define BM_PXP_LUT_CTRL_DMA_START 0x00000001
727
728#define HW_PXP_LUT_ADDR (0x00000250)
729
730#define BM_PXP_LUT_ADDR_RSVD2 0x80000000
731#define BP_PXP_LUT_ADDR_NUM_BYTES 16
732#define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000
733#define BF_PXP_LUT_ADDR_NUM_BYTES(v) \
734 (((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES)
735#define BP_PXP_LUT_ADDR_RSVD1 14
736#define BM_PXP_LUT_ADDR_RSVD1 0x0000C000
737#define BF_PXP_LUT_ADDR_RSVD1(v) \
738 (((v) << 14) & BM_PXP_LUT_ADDR_RSVD1)
739#define BP_PXP_LUT_ADDR_ADDR 0
740#define BM_PXP_LUT_ADDR_ADDR 0x00003FFF
741#define BF_PXP_LUT_ADDR_ADDR(v) \
742 (((v) << 0) & BM_PXP_LUT_ADDR_ADDR)
743
744#define HW_PXP_LUT_DATA (0x00000260)
745
746#define BP_PXP_LUT_DATA_DATA 0
747#define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF
748#define BF_PXP_LUT_DATA_DATA(v) (v)
749
750#define HW_PXP_LUT_EXTMEM (0x00000270)
751
752#define BP_PXP_LUT_EXTMEM_ADDR 0
753#define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF
754#define BF_PXP_LUT_EXTMEM_ADDR(v) (v)
755
756#define HW_PXP_CFA (0x00000280)
757
758#define BP_PXP_CFA_DATA 0
759#define BM_PXP_CFA_DATA 0xFFFFFFFF
760#define BF_PXP_CFA_DATA(v) (v)
761
762#define HW_PXP_HIST_CTRL (0x00000290)
763
764#define BP_PXP_HIST_CTRL_RSVD 6
765#define BM_PXP_HIST_CTRL_RSVD 0xFFFFFFC0
766#define BF_PXP_HIST_CTRL_RSVD(v) \
767 (((v) << 6) & BM_PXP_HIST_CTRL_RSVD)
768#define BP_PXP_HIST_CTRL_PANEL_MODE 4
769#define BM_PXP_HIST_CTRL_PANEL_MODE 0x00000030
770#define BF_PXP_HIST_CTRL_PANEL_MODE(v) \
771 (((v) << 4) & BM_PXP_HIST_CTRL_PANEL_MODE)
772#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY4 0x0
773#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY8 0x1
774#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16 0x2
775#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY32 0x3
776#define BP_PXP_HIST_CTRL_STATUS 0
777#define BM_PXP_HIST_CTRL_STATUS 0x0000000F
778#define BF_PXP_HIST_CTRL_STATUS(v) \
779 (((v) << 0) & BM_PXP_HIST_CTRL_STATUS)
780
781#define HW_PXP_HIST2_PARAM (0x000002a0)
782
783#define BP_PXP_HIST2_PARAM_RSVD 16
784#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000
785#define BF_PXP_HIST2_PARAM_RSVD(v) \
786 (((v) << 16) & BM_PXP_HIST2_PARAM_RSVD)
787#define BP_PXP_HIST2_PARAM_RSVD1 13
788#define BM_PXP_HIST2_PARAM_RSVD1 0x0000E000
789#define BF_PXP_HIST2_PARAM_RSVD1(v) \
790 (((v) << 13) & BM_PXP_HIST2_PARAM_RSVD1)
791#define BP_PXP_HIST2_PARAM_VALUE1 8
792#define BM_PXP_HIST2_PARAM_VALUE1 0x00001F00
793#define BF_PXP_HIST2_PARAM_VALUE1(v) \
794 (((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1)
795#define BP_PXP_HIST2_PARAM_RSVD0 5
796#define BM_PXP_HIST2_PARAM_RSVD0 0x000000E0
797#define BF_PXP_HIST2_PARAM_RSVD0(v) \
798 (((v) << 5) & BM_PXP_HIST2_PARAM_RSVD0)
799#define BP_PXP_HIST2_PARAM_VALUE0 0
800#define BM_PXP_HIST2_PARAM_VALUE0 0x0000001F
801#define BF_PXP_HIST2_PARAM_VALUE0(v) \
802 (((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0)
803
804#define HW_PXP_HIST4_PARAM (0x000002b0)
805
806#define BP_PXP_HIST4_PARAM_RSVD3 29
807#define BM_PXP_HIST4_PARAM_RSVD3 0xE0000000
808#define BF_PXP_HIST4_PARAM_RSVD3(v) \
809 (((v) << 29) & BM_PXP_HIST4_PARAM_RSVD3)
810#define BP_PXP_HIST4_PARAM_VALUE3 24
811#define BM_PXP_HIST4_PARAM_VALUE3 0x1F000000
812#define BF_PXP_HIST4_PARAM_VALUE3(v) \
813 (((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3)
814#define BP_PXP_HIST4_PARAM_RSVD2 21
815#define BM_PXP_HIST4_PARAM_RSVD2 0x00E00000
816#define BF_PXP_HIST4_PARAM_RSVD2(v) \
817 (((v) << 21) & BM_PXP_HIST4_PARAM_RSVD2)
818#define BP_PXP_HIST4_PARAM_VALUE2 16
819#define BM_PXP_HIST4_PARAM_VALUE2 0x001F0000
820#define BF_PXP_HIST4_PARAM_VALUE2(v) \
821 (((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2)
822#define BP_PXP_HIST4_PARAM_RSVD1 13
823#define BM_PXP_HIST4_PARAM_RSVD1 0x0000E000
824#define BF_PXP_HIST4_PARAM_RSVD1(v) \
825 (((v) << 13) & BM_PXP_HIST4_PARAM_RSVD1)
826#define BP_PXP_HIST4_PARAM_VALUE1 8
827#define BM_PXP_HIST4_PARAM_VALUE1 0x00001F00
828#define BF_PXP_HIST4_PARAM_VALUE1(v) \
829 (((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1)
830#define BP_PXP_HIST4_PARAM_RSVD0 5
831#define BM_PXP_HIST4_PARAM_RSVD0 0x000000E0
832#define BF_PXP_HIST4_PARAM_RSVD0(v) \
833 (((v) << 5) & BM_PXP_HIST4_PARAM_RSVD0)
834#define BP_PXP_HIST4_PARAM_VALUE0 0
835#define BM_PXP_HIST4_PARAM_VALUE0 0x0000001F
836#define BF_PXP_HIST4_PARAM_VALUE0(v) \
837 (((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0)
838
839#define HW_PXP_HIST8_PARAM0 (0x000002c0)
840
841#define BP_PXP_HIST8_PARAM0_RSVD3 29
842#define BM_PXP_HIST8_PARAM0_RSVD3 0xE0000000
843#define BF_PXP_HIST8_PARAM0_RSVD3(v) \
844 (((v) << 29) & BM_PXP_HIST8_PARAM0_RSVD3)
845#define BP_PXP_HIST8_PARAM0_VALUE3 24
846#define BM_PXP_HIST8_PARAM0_VALUE3 0x1F000000
847#define BF_PXP_HIST8_PARAM0_VALUE3(v) \
848 (((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3)
849#define BP_PXP_HIST8_PARAM0_RSVD2 21
850#define BM_PXP_HIST8_PARAM0_RSVD2 0x00E00000
851#define BF_PXP_HIST8_PARAM0_RSVD2(v) \
852 (((v) << 21) & BM_PXP_HIST8_PARAM0_RSVD2)
853#define BP_PXP_HIST8_PARAM0_VALUE2 16
854#define BM_PXP_HIST8_PARAM0_VALUE2 0x001F0000
855#define BF_PXP_HIST8_PARAM0_VALUE2(v) \
856 (((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2)
857#define BP_PXP_HIST8_PARAM0_RSVD1 13
858#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000E000
859#define BF_PXP_HIST8_PARAM0_RSVD1(v) \
860 (((v) << 13) & BM_PXP_HIST8_PARAM0_RSVD1)
861#define BP_PXP_HIST8_PARAM0_VALUE1 8
862#define BM_PXP_HIST8_PARAM0_VALUE1 0x00001F00
863#define BF_PXP_HIST8_PARAM0_VALUE1(v) \
864 (((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1)
865#define BP_PXP_HIST8_PARAM0_RSVD0 5
866#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000E0
867#define BF_PXP_HIST8_PARAM0_RSVD0(v) \
868 (((v) << 5) & BM_PXP_HIST8_PARAM0_RSVD0)
869#define BP_PXP_HIST8_PARAM0_VALUE0 0
870#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000001F
871#define BF_PXP_HIST8_PARAM0_VALUE0(v) \
872 (((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0)
873
874#define HW_PXP_HIST8_PARAM1 (0x000002d0)
875
876#define BP_PXP_HIST8_PARAM1_RSVD7 29
877#define BM_PXP_HIST8_PARAM1_RSVD7 0xE0000000
878#define BF_PXP_HIST8_PARAM1_RSVD7(v) \
879 (((v) << 29) & BM_PXP_HIST8_PARAM1_RSVD7)
880#define BP_PXP_HIST8_PARAM1_VALUE7 24
881#define BM_PXP_HIST8_PARAM1_VALUE7 0x1F000000
882#define BF_PXP_HIST8_PARAM1_VALUE7(v) \
883 (((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7)
884#define BP_PXP_HIST8_PARAM1_RSVD6 21
885#define BM_PXP_HIST8_PARAM1_RSVD6 0x00E00000
886#define BF_PXP_HIST8_PARAM1_RSVD6(v) \
887 (((v) << 21) & BM_PXP_HIST8_PARAM1_RSVD6)
888#define BP_PXP_HIST8_PARAM1_VALUE6 16
889#define BM_PXP_HIST8_PARAM1_VALUE6 0x001F0000
890#define BF_PXP_HIST8_PARAM1_VALUE6(v) \
891 (((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6)
892#define BP_PXP_HIST8_PARAM1_RSVD5 13
893#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000E000
894#define BF_PXP_HIST8_PARAM1_RSVD5(v) \
895 (((v) << 13) & BM_PXP_HIST8_PARAM1_RSVD5)
896#define BP_PXP_HIST8_PARAM1_VALUE5 8
897#define BM_PXP_HIST8_PARAM1_VALUE5 0x00001F00
898#define BF_PXP_HIST8_PARAM1_VALUE5(v) \
899 (((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5)
900#define BP_PXP_HIST8_PARAM1_RSVD4 5
901#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000E0
902#define BF_PXP_HIST8_PARAM1_RSVD4(v) \
903 (((v) << 5) & BM_PXP_HIST8_PARAM1_RSVD4)
904#define BP_PXP_HIST8_PARAM1_VALUE4 0
905#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000001F
906#define BF_PXP_HIST8_PARAM1_VALUE4(v) \
907 (((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4)
908
909#define HW_PXP_HIST16_PARAM0 (0x000002e0)
910
911#define BP_PXP_HIST16_PARAM0_RSVD3 29
912#define BM_PXP_HIST16_PARAM0_RSVD3 0xE0000000
913#define BF_PXP_HIST16_PARAM0_RSVD3(v) \
914 (((v) << 29) & BM_PXP_HIST16_PARAM0_RSVD3)
915#define BP_PXP_HIST16_PARAM0_VALUE3 24
916#define BM_PXP_HIST16_PARAM0_VALUE3 0x1F000000
917#define BF_PXP_HIST16_PARAM0_VALUE3(v) \
918 (((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3)
919#define BP_PXP_HIST16_PARAM0_RSVD2 21
920#define BM_PXP_HIST16_PARAM0_RSVD2 0x00E00000
921#define BF_PXP_HIST16_PARAM0_RSVD2(v) \
922 (((v) << 21) & BM_PXP_HIST16_PARAM0_RSVD2)
923#define BP_PXP_HIST16_PARAM0_VALUE2 16
924#define BM_PXP_HIST16_PARAM0_VALUE2 0x001F0000
925#define BF_PXP_HIST16_PARAM0_VALUE2(v) \
926 (((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2)
927#define BP_PXP_HIST16_PARAM0_RSVD1 13
928#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000E000
929#define BF_PXP_HIST16_PARAM0_RSVD1(v) \
930 (((v) << 13) & BM_PXP_HIST16_PARAM0_RSVD1)
931#define BP_PXP_HIST16_PARAM0_VALUE1 8
932#define BM_PXP_HIST16_PARAM0_VALUE1 0x00001F00
933#define BF_PXP_HIST16_PARAM0_VALUE1(v) \
934 (((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1)
935#define BP_PXP_HIST16_PARAM0_RSVD0 5
936#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000E0
937#define BF_PXP_HIST16_PARAM0_RSVD0(v) \
938 (((v) << 5) & BM_PXP_HIST16_PARAM0_RSVD0)
939#define BP_PXP_HIST16_PARAM0_VALUE0 0
940#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000001F
941#define BF_PXP_HIST16_PARAM0_VALUE0(v) \
942 (((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0)
943
944#define HW_PXP_HIST16_PARAM1 (0x000002f0)
945
946#define BP_PXP_HIST16_PARAM1_RSVD7 29
947#define BM_PXP_HIST16_PARAM1_RSVD7 0xE0000000
948#define BF_PXP_HIST16_PARAM1_RSVD7(v) \
949 (((v) << 29) & BM_PXP_HIST16_PARAM1_RSVD7)
950#define BP_PXP_HIST16_PARAM1_VALUE7 24
951#define BM_PXP_HIST16_PARAM1_VALUE7 0x1F000000
952#define BF_PXP_HIST16_PARAM1_VALUE7(v) \
953 (((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7)
954#define BP_PXP_HIST16_PARAM1_RSVD6 21
955#define BM_PXP_HIST16_PARAM1_RSVD6 0x00E00000
956#define BF_PXP_HIST16_PARAM1_RSVD6(v) \
957 (((v) << 21) & BM_PXP_HIST16_PARAM1_RSVD6)
958#define BP_PXP_HIST16_PARAM1_VALUE6 16
959#define BM_PXP_HIST16_PARAM1_VALUE6 0x001F0000
960#define BF_PXP_HIST16_PARAM1_VALUE6(v) \
961 (((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6)
962#define BP_PXP_HIST16_PARAM1_RSVD5 13
963#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000E000
964#define BF_PXP_HIST16_PARAM1_RSVD5(v) \
965 (((v) << 13) & BM_PXP_HIST16_PARAM1_RSVD5)
966#define BP_PXP_HIST16_PARAM1_VALUE5 8
967#define BM_PXP_HIST16_PARAM1_VALUE5 0x00001F00
968#define BF_PXP_HIST16_PARAM1_VALUE5(v) \
969 (((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5)
970#define BP_PXP_HIST16_PARAM1_RSVD4 5
971#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000E0
972#define BF_PXP_HIST16_PARAM1_RSVD4(v) \
973 (((v) << 5) & BM_PXP_HIST16_PARAM1_RSVD4)
974#define BP_PXP_HIST16_PARAM1_VALUE4 0
975#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000001F
976#define BF_PXP_HIST16_PARAM1_VALUE4(v) \
977 (((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4)
978
979#define HW_PXP_HIST16_PARAM2 (0x00000300)
980
981#define BP_PXP_HIST16_PARAM2_RSVD11 29
982#define BM_PXP_HIST16_PARAM2_RSVD11 0xE0000000
983#define BF_PXP_HIST16_PARAM2_RSVD11(v) \
984 (((v) << 29) & BM_PXP_HIST16_PARAM2_RSVD11)
985#define BP_PXP_HIST16_PARAM2_VALUE11 24
986#define BM_PXP_HIST16_PARAM2_VALUE11 0x1F000000
987#define BF_PXP_HIST16_PARAM2_VALUE11(v) \
988 (((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11)
989#define BP_PXP_HIST16_PARAM2_RSVD10 21
990#define BM_PXP_HIST16_PARAM2_RSVD10 0x00E00000
991#define BF_PXP_HIST16_PARAM2_RSVD10(v) \
992 (((v) << 21) & BM_PXP_HIST16_PARAM2_RSVD10)
993#define BP_PXP_HIST16_PARAM2_VALUE10 16
994#define BM_PXP_HIST16_PARAM2_VALUE10 0x001F0000
995#define BF_PXP_HIST16_PARAM2_VALUE10(v) \
996 (((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10)
997#define BP_PXP_HIST16_PARAM2_RSVD9 13
998#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000E000
999#define BF_PXP_HIST16_PARAM2_RSVD9(v) \
1000 (((v) << 13) & BM_PXP_HIST16_PARAM2_RSVD9)
1001#define BP_PXP_HIST16_PARAM2_VALUE9 8
1002#define BM_PXP_HIST16_PARAM2_VALUE9 0x00001F00
1003#define BF_PXP_HIST16_PARAM2_VALUE9(v) \
1004 (((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9)
1005#define BP_PXP_HIST16_PARAM2_RSVD8 5
1006#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000E0
1007#define BF_PXP_HIST16_PARAM2_RSVD8(v) \
1008 (((v) << 5) & BM_PXP_HIST16_PARAM2_RSVD8)
1009#define BP_PXP_HIST16_PARAM2_VALUE8 0
1010#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000001F
1011#define BF_PXP_HIST16_PARAM2_VALUE8(v) \
1012 (((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8)
1013
1014#define HW_PXP_HIST16_PARAM3 (0x00000310)
1015
1016#define BP_PXP_HIST16_PARAM3_RSVD15 29
1017#define BM_PXP_HIST16_PARAM3_RSVD15 0xE0000000
1018#define BF_PXP_HIST16_PARAM3_RSVD15(v) \
1019 (((v) << 29) & BM_PXP_HIST16_PARAM3_RSVD15)
1020#define BP_PXP_HIST16_PARAM3_VALUE15 24
1021#define BM_PXP_HIST16_PARAM3_VALUE15 0x1F000000
1022#define BF_PXP_HIST16_PARAM3_VALUE15(v) \
1023 (((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15)
1024#define BP_PXP_HIST16_PARAM3_RSVD14 21
1025#define BM_PXP_HIST16_PARAM3_RSVD14 0x00E00000
1026#define BF_PXP_HIST16_PARAM3_RSVD14(v) \
1027 (((v) << 21) & BM_PXP_HIST16_PARAM3_RSVD14)
1028#define BP_PXP_HIST16_PARAM3_VALUE14 16
1029#define BM_PXP_HIST16_PARAM3_VALUE14 0x001F0000
1030#define BF_PXP_HIST16_PARAM3_VALUE14(v) \
1031 (((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14)
1032#define BP_PXP_HIST16_PARAM3_RSVD13 13
1033#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000E000
1034#define BF_PXP_HIST16_PARAM3_RSVD13(v) \
1035 (((v) << 13) & BM_PXP_HIST16_PARAM3_RSVD13)
1036#define BP_PXP_HIST16_PARAM3_VALUE13 8
1037#define BM_PXP_HIST16_PARAM3_VALUE13 0x00001F00
1038#define BF_PXP_HIST16_PARAM3_VALUE13(v) \
1039 (((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13)
1040#define BP_PXP_HIST16_PARAM3_RSVD12 5
1041#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000E0
1042#define BF_PXP_HIST16_PARAM3_RSVD12(v) \
1043 (((v) << 5) & BM_PXP_HIST16_PARAM3_RSVD12)
1044#define BP_PXP_HIST16_PARAM3_VALUE12 0
1045#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000001F
1046#define BF_PXP_HIST16_PARAM3_VALUE12(v) \
1047 (((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12)
1048
1049#define HW_PXP_POWER (0x00000320)
1050
1051#define BP_PXP_POWER_CTRL 12
1052#define BM_PXP_POWER_CTRL 0xFFFFF000
1053#define BF_PXP_POWER_CTRL(v) \
1054 (((v) << 12) & BM_PXP_POWER_CTRL)
1055#define BP_PXP_POWER_ROT_MEM_LP_STATE 9
1056#define BM_PXP_POWER_ROT_MEM_LP_STATE 0x00000E00
1057#define BF_PXP_POWER_ROT_MEM_LP_STATE(v) \
1058 (((v) << 9) & BM_PXP_POWER_ROT_MEM_LP_STATE)
1059#define BV_PXP_POWER_ROT_MEM_LP_STATE__NONE 0x0
1060#define BV_PXP_POWER_ROT_MEM_LP_STATE__LS 0x1
1061#define BV_PXP_POWER_ROT_MEM_LP_STATE__DS 0x2
1062#define BV_PXP_POWER_ROT_MEM_LP_STATE__SD 0x4
1063#define BP_PXP_POWER_LUT_LP_STATE_WAY1_BANKN 6
1064#define BM_PXP_POWER_LUT_LP_STATE_WAY1_BANKN 0x000001C0
1065#define BF_PXP_POWER_LUT_LP_STATE_WAY1_BANKN(v) \
1066 (((v) << 6) & BM_PXP_POWER_LUT_LP_STATE_WAY1_BANKN)
1067#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__NONE 0x0
1068#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__LS 0x1
1069#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__DS 0x2
1070#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__SD 0x4
1071#define BP_PXP_POWER_LUT_LP_STATE_WAY0_BANKN 3
1072#define BM_PXP_POWER_LUT_LP_STATE_WAY0_BANKN 0x00000038
1073#define BF_PXP_POWER_LUT_LP_STATE_WAY0_BANKN(v) \
1074 (((v) << 3) & BM_PXP_POWER_LUT_LP_STATE_WAY0_BANKN)
1075#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__NONE 0x0
1076#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__LS 0x1
1077#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__DS 0x2
1078#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__SD 0x4
1079#define BP_PXP_POWER_LUT_LP_STATE_WAY0_BANK0 0
1080#define BM_PXP_POWER_LUT_LP_STATE_WAY0_BANK0 0x00000007
1081#define BF_PXP_POWER_LUT_LP_STATE_WAY0_BANK0(v) \
1082 (((v) << 0) & BM_PXP_POWER_LUT_LP_STATE_WAY0_BANK0)
1083#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__NONE 0x0
1084#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__LS 0x1
1085#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__DS 0x2
1086#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__SD 0x4
1087
1088#define HW_PXP_NEXT (0x00000400)
1089
1090#define BP_PXP_NEXT_POINTER 2
1091#define BM_PXP_NEXT_POINTER 0xFFFFFFFC
1092#define BF_PXP_NEXT_POINTER(v) \
1093 (((v) << 2) & BM_PXP_NEXT_POINTER)
1094#define BM_PXP_NEXT_RSVD 0x00000002
1095#define BM_PXP_NEXT_ENABLED 0x00000001
1096
1097#define HW_PXP_DEBUGCTRL (0x00000410)
1098
1099#define BP_PXP_DEBUGCTRL_RSVD 12
1100#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000
1101#define BF_PXP_DEBUGCTRL_RSVD(v) \
1102 (((v) << 12) & BM_PXP_DEBUGCTRL_RSVD)
1103#define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 8
1104#define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00
1105#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \
1106 (((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT)
1107#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x0
1108#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1
1109#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x2
1110#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x4
1111#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x8
1112#define BP_PXP_DEBUGCTRL_SELECT 0
1113#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF
1114#define BF_PXP_DEBUGCTRL_SELECT(v) \
1115 (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT)
1116#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0
1117#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1
1118#define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x2
1119#define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x3
1120#define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x4
1121#define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x5
1122#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6
1123#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x7
1124#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x8
1125#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x9
1126#define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x10
1127#define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x11
1128#define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x12
1129#define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x13
1130#define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14
1131
1132#define HW_PXP_DEBUG (0x00000420)
1133
1134#define BP_PXP_DEBUG_DATA 0
1135#define BM_PXP_DEBUG_DATA 0xFFFFFFFF
1136#define BF_PXP_DEBUG_DATA(v) (v)
1137
1138#define HW_PXP_VERSION (0x00000430)
1139
1140#define BP_PXP_VERSION_MAJOR 24
1141#define BM_PXP_VERSION_MAJOR 0xFF000000
1142#define BF_PXP_VERSION_MAJOR(v) \
1143 (((v) << 24) & BM_PXP_VERSION_MAJOR)
1144#define BP_PXP_VERSION_MINOR 16
1145#define BM_PXP_VERSION_MINOR 0x00FF0000
1146#define BF_PXP_VERSION_MINOR(v) \
1147 (((v) << 16) & BM_PXP_VERSION_MINOR)
1148#define BP_PXP_VERSION_STEP 0
1149#define BM_PXP_VERSION_STEP 0x0000FFFF
1150#define BF_PXP_VERSION_STEP(v) \
1151 (((v) << 0) & BM_PXP_VERSION_STEP)
1152#endif /* __ARCH_ARM___PXP_H */
diff --git a/include/linux/platform_data/dma-imx.h b/include/linux/platform_data/dma-imx.h
index f6d30cc1cb77..3558f05273a3 100644
--- a/include/linux/platform_data/dma-imx.h
+++ b/include/linux/platform_data/dma-imx.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
@@ -58,6 +58,11 @@ static inline int imx_dma_is_ipu(struct dma_chan *chan)
58 return !strcmp(dev_name(chan->device->dev), "ipu-core"); 58 return !strcmp(dev_name(chan->device->dev), "ipu-core");
59} 59}
60 60
61static inline int imx_dma_is_pxp(struct dma_chan *chan)
62{
63 return strstr(dev_name(chan->device->dev), "pxp") != NULL;
64}
65
61static inline int imx_dma_is_general_purpose(struct dma_chan *chan) 66static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
62{ 67{
63 return strstr(dev_name(chan->device->dev), "sdma") || 68 return strstr(dev_name(chan->device->dev), "sdma") ||
diff --git a/include/uapi/linux/pxp_dma.h b/include/uapi/linux/pxp_dma.h
index 87fcdc7c9451..bc280a70c856 100644
--- a/include/uapi/linux/pxp_dma.h
+++ b/include/uapi/linux/pxp_dma.h
@@ -21,8 +21,10 @@
21 21
22#include <linux/posix_types.h> 22#include <linux/posix_types.h>
23 23
24#ifndef __KERNEL__
24typedef unsigned long dma_addr_t; 25typedef unsigned long dma_addr_t;
25typedef unsigned char bool; 26typedef unsigned char bool;
27#endif
26 28
27/* PXP Pixel format definitions */ 29/* PXP Pixel format definitions */
28/* Four-character-code (FOURCC) */ 30/* Four-character-code (FOURCC) */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 06:54:05 -0500