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authorjohnnyhsu@realtek.com <johnnyhsu@realtek.com>2011-09-06 23:16:35 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2011-09-21 10:52:23 -0400
commitd80852223ecabd1ab433a9c71436d81b697ef1fc (patch)
tree445a116437cdc9bf40f2b9847336b713e336a772
parent49acf73bd03a22d1a0e866b244a4003c222aabee (diff)
ASoC: Add driver for rt5631
Signed-off-by: Johnny Hsu <johnnyhsu@realtek.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat
-rw-r--r--sound/soc/codecs/rt5631.c1789
-rw-r--r--sound/soc/codecs/rt5631.h701
2 files changed, 2490 insertions, 0 deletions
diff --git a/sound/soc/codecs/rt5631.c b/sound/soc/codecs/rt5631.c
new file mode 100644
index 000000000000..110b3d852d0f
--- /dev/null
+++ b/sound/soc/codecs/rt5631.c
@@ -0,0 +1,1789 @@
1/*
2 * rt5631.c -- RT5631 ALSA Soc Audio driver
3 *
4 * Copyright 2011 Realtek Microelectronics
5 *
6 * Author: flove <flove@realtek.com>
7 *
8 * Based on WM8753.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
22#include <linux/spi/spi.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30
31#include "rt5631.h"
32
33struct rt5631_priv {
34 struct snd_soc_codec *codec;
35 int codec_version;
36 int master;
37 int sysclk;
38 int rx_rate;
39 int bclk_rate;
40 int dmic_used_flag;
41};
42
43static const u16 rt5631_reg[RT5631_VENDOR_ID2 + 1] = {
44 [RT5631_SPK_OUT_VOL] = 0x8888,
45 [RT5631_HP_OUT_VOL] = 0x8080,
46 [RT5631_MONO_AXO_1_2_VOL] = 0xa080,
47 [RT5631_AUX_IN_VOL] = 0x0808,
48 [RT5631_ADC_REC_MIXER] = 0xf0f0,
49 [RT5631_VDAC_DIG_VOL] = 0x0010,
50 [RT5631_OUTMIXER_L_CTRL] = 0xffc0,
51 [RT5631_OUTMIXER_R_CTRL] = 0xffc0,
52 [RT5631_AXO1MIXER_CTRL] = 0x88c0,
53 [RT5631_AXO2MIXER_CTRL] = 0x88c0,
54 [RT5631_DIG_MIC_CTRL] = 0x3000,
55 [RT5631_MONO_INPUT_VOL] = 0x8808,
56 [RT5631_SPK_MIXER_CTRL] = 0xf8f8,
57 [RT5631_SPK_MONO_OUT_CTRL] = 0xfc00,
58 [RT5631_SPK_MONO_HP_OUT_CTRL] = 0x4440,
59 [RT5631_SDP_CTRL] = 0x8000,
60 [RT5631_MONO_SDP_CTRL] = 0x8000,
61 [RT5631_STEREO_AD_DA_CLK_CTRL] = 0x2010,
62 [RT5631_GEN_PUR_CTRL_REG] = 0x0e00,
63 [RT5631_INT_ST_IRQ_CTRL_2] = 0x071a,
64 [RT5631_MISC_CTRL] = 0x2040,
65 [RT5631_DEPOP_FUN_CTRL_2] = 0x8000,
66 [RT5631_SOFT_VOL_CTRL] = 0x07e0,
67 [RT5631_ALC_CTRL_1] = 0x0206,
68 [RT5631_ALC_CTRL_3] = 0x2000,
69 [RT5631_PSEUDO_SPATL_CTRL] = 0x0553,
70};
71
72/**
73 * rt5631_write_index - write index register of 2nd layer
74 */
75static void rt5631_write_index(struct snd_soc_codec *codec,
76 unsigned int reg, unsigned int value)
77{
78 snd_soc_write(codec, RT5631_INDEX_ADD, reg);
79 snd_soc_write(codec, RT5631_INDEX_DATA, value);
80}
81
82/**
83 * rt5631_read_index - read index register of 2nd layer
84 */
85static unsigned int rt5631_read_index(struct snd_soc_codec *codec,
86 unsigned int reg)
87{
88 unsigned int value;
89
90 snd_soc_write(codec, RT5631_INDEX_ADD, reg);
91 value = snd_soc_read(codec, RT5631_INDEX_DATA);
92
93 return value;
94}
95
96static int rt5631_reset(struct snd_soc_codec *codec)
97{
98 return snd_soc_write(codec, RT5631_RESET, 0);
99}
100
101static int rt5631_volatile_register(struct snd_soc_codec *codec,
102 unsigned int reg)
103{
104 switch (reg) {
105 case RT5631_RESET:
106 case RT5631_INT_ST_IRQ_CTRL_2:
107 case RT5631_INDEX_ADD:
108 case RT5631_INDEX_DATA:
109 case RT5631_EQ_CTRL:
110 return 1;
111 default:
112 return 0;
113 }
114}
115
116static int rt5631_readable_register(struct snd_soc_codec *codec,
117 unsigned int reg)
118{
119 switch (reg) {
120 case RT5631_RESET:
121 case RT5631_SPK_OUT_VOL:
122 case RT5631_HP_OUT_VOL:
123 case RT5631_MONO_AXO_1_2_VOL:
124 case RT5631_AUX_IN_VOL:
125 case RT5631_STEREO_DAC_VOL_1:
126 case RT5631_MIC_CTRL_1:
127 case RT5631_STEREO_DAC_VOL_2:
128 case RT5631_ADC_CTRL_1:
129 case RT5631_ADC_REC_MIXER:
130 case RT5631_ADC_CTRL_2:
131 case RT5631_VDAC_DIG_VOL:
132 case RT5631_OUTMIXER_L_CTRL:
133 case RT5631_OUTMIXER_R_CTRL:
134 case RT5631_AXO1MIXER_CTRL:
135 case RT5631_AXO2MIXER_CTRL:
136 case RT5631_MIC_CTRL_2:
137 case RT5631_DIG_MIC_CTRL:
138 case RT5631_MONO_INPUT_VOL:
139 case RT5631_SPK_MIXER_CTRL:
140 case RT5631_SPK_MONO_OUT_CTRL:
141 case RT5631_SPK_MONO_HP_OUT_CTRL:
142 case RT5631_SDP_CTRL:
143 case RT5631_MONO_SDP_CTRL:
144 case RT5631_STEREO_AD_DA_CLK_CTRL:
145 case RT5631_PWR_MANAG_ADD1:
146 case RT5631_PWR_MANAG_ADD2:
147 case RT5631_PWR_MANAG_ADD3:
148 case RT5631_PWR_MANAG_ADD4:
149 case RT5631_GEN_PUR_CTRL_REG:
150 case RT5631_GLOBAL_CLK_CTRL:
151 case RT5631_PLL_CTRL:
152 case RT5631_INT_ST_IRQ_CTRL_1:
153 case RT5631_INT_ST_IRQ_CTRL_2:
154 case RT5631_GPIO_CTRL:
155 case RT5631_MISC_CTRL:
156 case RT5631_DEPOP_FUN_CTRL_1:
157 case RT5631_DEPOP_FUN_CTRL_2:
158 case RT5631_JACK_DET_CTRL:
159 case RT5631_SOFT_VOL_CTRL:
160 case RT5631_ALC_CTRL_1:
161 case RT5631_ALC_CTRL_2:
162 case RT5631_ALC_CTRL_3:
163 case RT5631_PSEUDO_SPATL_CTRL:
164 case RT5631_INDEX_ADD:
165 case RT5631_INDEX_DATA:
166 case RT5631_EQ_CTRL:
167 case RT5631_VENDOR_ID:
168 case RT5631_VENDOR_ID1:
169 case RT5631_VENDOR_ID2:
170 return 1;
171 default:
172 return 0;
173 }
174}
175
176static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
177static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -95625, 375, 0);
178static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
179/* {0, +20, +24, +30, +35, +40, +44, +50, +52}dB */
180static unsigned int mic_bst_tlv[] = {
181 TLV_DB_RANGE_HEAD(6),
182 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
183 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
184 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
185 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
186 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
187 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
188 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
189};
190
191static int rt5631_dmic_get(struct snd_kcontrol *kcontrol,
192 struct snd_ctl_elem_value *ucontrol)
193{
194 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
195 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
196
197 ucontrol->value.integer.value[0] = rt5631->dmic_used_flag;
198
199 return 0;
200}
201
202static int rt5631_dmic_put(struct snd_kcontrol *kcontrol,
203 struct snd_ctl_elem_value *ucontrol)
204{
205 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
206 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
207
208 rt5631->dmic_used_flag = ucontrol->value.integer.value[0];
209 return 0;
210}
211
212/* MIC Input Type */
213static const char *rt5631_input_mode[] = {
214 "Single ended", "Differential"};
215
216static const SOC_ENUM_SINGLE_DECL(
217 rt5631_mic1_mode_enum, RT5631_MIC_CTRL_1,
218 RT5631_MIC1_DIFF_INPUT_SHIFT, rt5631_input_mode);
219
220static const SOC_ENUM_SINGLE_DECL(
221 rt5631_mic2_mode_enum, RT5631_MIC_CTRL_1,
222 RT5631_MIC2_DIFF_INPUT_SHIFT, rt5631_input_mode);
223
224/* MONO Input Type */
225static const SOC_ENUM_SINGLE_DECL(
226 rt5631_monoin_mode_enum, RT5631_MONO_INPUT_VOL,
227 RT5631_MONO_DIFF_INPUT_SHIFT, rt5631_input_mode);
228
229/* SPK Ratio Gain Control */
230static const char *rt5631_spk_ratio[] = {"1.00x", "1.09x", "1.27x", "1.44x",
231 "1.56x", "1.68x", "1.99x", "2.34x"};
232
233static const SOC_ENUM_SINGLE_DECL(
234 rt5631_spk_ratio_enum, RT5631_GEN_PUR_CTRL_REG,
235 RT5631_SPK_AMP_RATIO_CTRL_SHIFT, rt5631_spk_ratio);
236
237static const struct snd_kcontrol_new rt5631_snd_controls[] = {
238 /* MIC */
239 SOC_ENUM("MIC1 Mode Control", rt5631_mic1_mode_enum),
240 SOC_SINGLE_TLV("MIC1 Boost", RT5631_MIC_CTRL_2,
241 RT5631_MIC1_BOOST_SHIFT, 8, 0, mic_bst_tlv),
242 SOC_ENUM("MIC2 Mode Control", rt5631_mic2_mode_enum),
243 SOC_SINGLE_TLV("MIC2 Boost", RT5631_MIC_CTRL_2,
244 RT5631_MIC2_BOOST_SHIFT, 8, 0, mic_bst_tlv),
245 /* MONO IN */
246 SOC_ENUM("MONOIN Mode Control", rt5631_monoin_mode_enum),
247 SOC_DOUBLE_TLV("MONOIN_RX Capture Volume", RT5631_MONO_INPUT_VOL,
248 RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT,
249 RT5631_VOL_MASK, 1, in_vol_tlv),
250 /* AXI */
251 SOC_DOUBLE_TLV("AXI Capture Volume", RT5631_AUX_IN_VOL,
252 RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT,
253 RT5631_VOL_MASK, 1, in_vol_tlv),
254 /* DAC */
255 SOC_DOUBLE_TLV("PCM Playback Volume", RT5631_STEREO_DAC_VOL_2,
256 RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT,
257 RT5631_DAC_VOL_MASK, 1, dac_vol_tlv),
258 SOC_DOUBLE("PCM Playback Switch", RT5631_STEREO_DAC_VOL_1,
259 RT5631_L_MUTE_SHIFT, RT5631_R_MUTE_SHIFT, 1, 1),
260 /* AXO */
261 SOC_SINGLE("AXO1 Playback Switch", RT5631_MONO_AXO_1_2_VOL,
262 RT5631_L_MUTE_SHIFT, 1, 1),
263 SOC_SINGLE("AXO2 Playback Switch", RT5631_MONO_AXO_1_2_VOL,
264 RT5631_R_VOL_SHIFT, 1, 1),
265 /* OUTVOL */
266 SOC_DOUBLE("OUTVOL Channel Switch", RT5631_SPK_OUT_VOL,
267 RT5631_L_EN_SHIFT, RT5631_R_EN_SHIFT, 1, 0),
268
269 /* SPK */
270 SOC_DOUBLE("Speaker Playback Switch", RT5631_SPK_OUT_VOL,
271 RT5631_L_MUTE_SHIFT, RT5631_R_MUTE_SHIFT, 1, 1),
272 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5631_SPK_OUT_VOL,
273 RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT, 39, 1, out_vol_tlv),
274 /* MONO OUT */
275 SOC_SINGLE("MONO Playback Switch", RT5631_MONO_AXO_1_2_VOL,
276 RT5631_MUTE_MONO_SHIFT, 1, 1),
277 /* HP */
278 SOC_DOUBLE("HP Playback Switch", RT5631_HP_OUT_VOL,
279 RT5631_L_MUTE_SHIFT, RT5631_R_MUTE_SHIFT, 1, 1),
280 SOC_DOUBLE_TLV("HP Playback Volume", RT5631_HP_OUT_VOL,
281 RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT,
282 RT5631_VOL_MASK, 1, out_vol_tlv),
283 /* DMIC */
284 SOC_SINGLE_EXT("DMIC Switch", 0, 0, 1, 0,
285 rt5631_dmic_get, rt5631_dmic_put),
286 SOC_DOUBLE("DMIC Capture Switch", RT5631_DIG_MIC_CTRL,
287 RT5631_DMIC_L_CH_MUTE_SHIFT,
288 RT5631_DMIC_R_CH_MUTE_SHIFT, 1, 1),
289
290 /* SPK Ratio Gain Control */
291 SOC_ENUM("SPK Ratio Control", rt5631_spk_ratio_enum),
292};
293
294static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
295 struct snd_soc_dapm_widget *sink)
296{
297 unsigned int reg;
298
299 reg = snd_soc_read(source->codec, RT5631_GLOBAL_CLK_CTRL);
300 return reg & RT5631_SYSCLK_SOUR_SEL_PLL;
301}
302
303static int check_dmic_used(struct snd_soc_dapm_widget *source,
304 struct snd_soc_dapm_widget *sink)
305{
306 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(source->codec);
307 return rt5631->dmic_used_flag;
308}
309
310static int check_dacl_to_outmixl(struct snd_soc_dapm_widget *source,
311 struct snd_soc_dapm_widget *sink)
312{
313 unsigned int reg;
314
315 reg = snd_soc_read(source->codec, RT5631_OUTMIXER_L_CTRL);
316 return !(reg & RT5631_M_DAC_L_TO_OUTMIXER_L);
317}
318
319static int check_dacr_to_outmixr(struct snd_soc_dapm_widget *source,
320 struct snd_soc_dapm_widget *sink)
321{
322 unsigned int reg;
323
324 reg = snd_soc_read(source->codec, RT5631_OUTMIXER_R_CTRL);
325 return !(reg & RT5631_M_DAC_R_TO_OUTMIXER_R);
326}
327
328static int check_dacl_to_spkmixl(struct snd_soc_dapm_widget *source,
329 struct snd_soc_dapm_widget *sink)
330{
331 unsigned int reg;
332
333 reg = snd_soc_read(source->codec, RT5631_SPK_MIXER_CTRL);
334 return !(reg & RT5631_M_DAC_L_TO_SPKMIXER_L);
335}
336
337static int check_dacr_to_spkmixr(struct snd_soc_dapm_widget *source,
338 struct snd_soc_dapm_widget *sink)
339{
340 unsigned int reg;
341
342 reg = snd_soc_read(source->codec, RT5631_SPK_MIXER_CTRL);
343 return !(reg & RT5631_M_DAC_R_TO_SPKMIXER_R);
344}
345
346static int check_vdac_to_outmix(struct snd_soc_dapm_widget *source,
347 struct snd_soc_dapm_widget *sink)
348{
349 unsigned int reg, ret = 1;
350
351 reg = snd_soc_read(source->codec, RT5631_OUTMIXER_L_CTRL);
352 if (reg & RT5631_M_VDAC_TO_OUTMIXER_L) {
353 reg = snd_soc_read(source->codec, RT5631_OUTMIXER_R_CTRL);
354 if (reg & RT5631_M_VDAC_TO_OUTMIXER_R)
355 ret = 0;
356 }
357 return ret;
358}
359
360static int check_adcl_select(struct snd_soc_dapm_widget *source,
361 struct snd_soc_dapm_widget *sink)
362{
363 unsigned int reg;
364
365 reg = snd_soc_read(source->codec, RT5631_ADC_REC_MIXER);
366 return !(reg & RT5631_M_MIC1_TO_RECMIXER_L);
367}
368
369static int check_adcr_select(struct snd_soc_dapm_widget *source,
370 struct snd_soc_dapm_widget *sink)
371{
372 unsigned int reg;
373
374 reg = snd_soc_read(source->codec, RT5631_ADC_REC_MIXER);
375 return !(reg & RT5631_M_MIC2_TO_RECMIXER_R);
376}
377
378/**
379 * onebit_depop_power_stage - auto depop in power stage.
380 * @enable: power on/off
381 *
382 * When power on/off headphone, the depop sequence is done by hardware.
383 */
384static void onebit_depop_power_stage(struct snd_soc_codec *codec, int enable)
385{
386 unsigned int soft_vol, hp_zc;
387
388 /* enable one-bit depop function */
389 snd_soc_update_bits(codec, RT5631_DEPOP_FUN_CTRL_2,
390 RT5631_EN_ONE_BIT_DEPOP, 0);
391
392 /* keep soft volume and zero crossing setting */
393 soft_vol = snd_soc_read(codec, RT5631_SOFT_VOL_CTRL);
394 snd_soc_write(codec, RT5631_SOFT_VOL_CTRL, 0);
395 hp_zc = snd_soc_read(codec, RT5631_INT_ST_IRQ_CTRL_2);
396 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, hp_zc & 0xf7ff);
397 if (enable) {
398 /* config one-bit depop parameter */
399 rt5631_write_index(codec, RT5631_TEST_MODE_CTRL, 0x84c0);
400 rt5631_write_index(codec, RT5631_SPK_INTL_CTRL, 0x309f);
401 rt5631_write_index(codec, RT5631_CP_INTL_REG2, 0x6530);
402 /* power on capless block */
403 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_2,
404 RT5631_EN_CAP_FREE_DEPOP);
405 } else {
406 /* power off capless block */
407 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_2, 0);
408 msleep(100);
409 }
410
411 /* recover soft volume and zero crossing setting */
412 snd_soc_write(codec, RT5631_SOFT_VOL_CTRL, soft_vol);
413 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, hp_zc);
414}
415
416/**
417 * onebit_depop_mute_stage - auto depop in mute stage.
418 * @enable: mute/unmute
419 *
420 * When mute/unmute headphone, the depop sequence is done by hardware.
421 */
422static void onebit_depop_mute_stage(struct snd_soc_codec *codec, int enable)
423{
424 unsigned int soft_vol, hp_zc;
425
426 /* enable one-bit depop function */
427 snd_soc_update_bits(codec, RT5631_DEPOP_FUN_CTRL_2,
428 RT5631_EN_ONE_BIT_DEPOP, 0);
429
430 /* keep soft volume and zero crossing setting */
431 soft_vol = snd_soc_read(codec, RT5631_SOFT_VOL_CTRL);
432 snd_soc_write(codec, RT5631_SOFT_VOL_CTRL, 0);
433 hp_zc = snd_soc_read(codec, RT5631_INT_ST_IRQ_CTRL_2);
434 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, hp_zc & 0xf7ff);
435 if (enable) {
436 schedule_timeout_uninterruptible(msecs_to_jiffies(10));
437 /* config one-bit depop parameter */
438 rt5631_write_index(codec, RT5631_SPK_INTL_CTRL, 0x307f);
439 snd_soc_update_bits(codec, RT5631_HP_OUT_VOL,
440 RT5631_L_MUTE | RT5631_R_MUTE, 0);
441 msleep(300);
442 } else {
443 snd_soc_update_bits(codec, RT5631_HP_OUT_VOL,
444 RT5631_L_MUTE | RT5631_R_MUTE,
445 RT5631_L_MUTE | RT5631_R_MUTE);
446 msleep(100);
447 }
448
449 /* recover soft volume and zero crossing setting */
450 snd_soc_write(codec, RT5631_SOFT_VOL_CTRL, soft_vol);
451 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, hp_zc);
452}
453
454/**
455 * onebit_depop_power_stage - step by step depop sequence in power stage.
456 * @enable: power on/off
457 *
458 * When power on/off headphone, the depop sequence is done in step by step.
459 */
460static void depop_seq_power_stage(struct snd_soc_codec *codec, int enable)
461{
462 unsigned int soft_vol, hp_zc;
463
464 /* depop control by register */
465 snd_soc_update_bits(codec, RT5631_DEPOP_FUN_CTRL_2,
466 RT5631_EN_ONE_BIT_DEPOP, RT5631_EN_ONE_BIT_DEPOP);
467
468 /* keep soft volume and zero crossing setting */
469 soft_vol = snd_soc_read(codec, RT5631_SOFT_VOL_CTRL);
470 snd_soc_write(codec, RT5631_SOFT_VOL_CTRL, 0);
471 hp_zc = snd_soc_read(codec, RT5631_INT_ST_IRQ_CTRL_2);
472 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, hp_zc & 0xf7ff);
473 if (enable) {
474 /* config depop sequence parameter */
475 rt5631_write_index(codec, RT5631_SPK_INTL_CTRL, 0x303e);
476
477 /* power on headphone and charge pump */
478 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
479 RT5631_PWR_CHARGE_PUMP | RT5631_PWR_HP_L_AMP |
480 RT5631_PWR_HP_R_AMP,
481 RT5631_PWR_CHARGE_PUMP | RT5631_PWR_HP_L_AMP |
482 RT5631_PWR_HP_R_AMP);
483
484 /* power on soft generator and depop mode2 */
485 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_1,
486 RT5631_POW_ON_SOFT_GEN | RT5631_EN_DEPOP2_FOR_HP);
487 msleep(100);
488
489 /* stop depop mode */
490 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
491 RT5631_PWR_HP_DEPOP_DIS, RT5631_PWR_HP_DEPOP_DIS);
492 } else {
493 /* config depop sequence parameter */
494 rt5631_write_index(codec, RT5631_SPK_INTL_CTRL, 0x303F);
495 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_1,
496 RT5631_POW_ON_SOFT_GEN | RT5631_EN_MUTE_UNMUTE_DEPOP |
497 RT5631_PD_HPAMP_L_ST_UP | RT5631_PD_HPAMP_R_ST_UP);
498 msleep(75);
499 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_1,
500 RT5631_POW_ON_SOFT_GEN | RT5631_PD_HPAMP_L_ST_UP |
501 RT5631_PD_HPAMP_R_ST_UP);
502
503 /* start depop mode */
504 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
505 RT5631_PWR_HP_DEPOP_DIS, 0);
506
507 /* config depop sequence parameter */
508 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_1,
509 RT5631_POW_ON_SOFT_GEN | RT5631_EN_DEPOP2_FOR_HP |
510 RT5631_PD_HPAMP_L_ST_UP | RT5631_PD_HPAMP_R_ST_UP);
511 msleep(80);
512 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_1,
513 RT5631_POW_ON_SOFT_GEN);
514
515 /* power down headphone and charge pump */
516 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
517 RT5631_PWR_CHARGE_PUMP | RT5631_PWR_HP_L_AMP |
518 RT5631_PWR_HP_R_AMP, 0);
519 }
520
521 /* recover soft volume and zero crossing setting */
522 snd_soc_write(codec, RT5631_SOFT_VOL_CTRL, soft_vol);
523 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, hp_zc);
524}
525
526/**
527 * depop_seq_mute_stage - step by step depop sequence in mute stage.
528 * @enable: mute/unmute
529 *
530 * When mute/unmute headphone, the depop sequence is done in step by step.
531 */
532static void depop_seq_mute_stage(struct snd_soc_codec *codec, int enable)
533{
534 unsigned int soft_vol, hp_zc;
535
536 /* depop control by register */
537 snd_soc_update_bits(codec, RT5631_DEPOP_FUN_CTRL_2,
538 RT5631_EN_ONE_BIT_DEPOP, RT5631_EN_ONE_BIT_DEPOP);
539
540 /* keep soft volume and zero crossing setting */
541 soft_vol = snd_soc_read(codec, RT5631_SOFT_VOL_CTRL);
542 snd_soc_write(codec, RT5631_SOFT_VOL_CTRL, 0);
543 hp_zc = snd_soc_read(codec, RT5631_INT_ST_IRQ_CTRL_2);
544 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, hp_zc & 0xf7ff);
545 if (enable) {
546 schedule_timeout_uninterruptible(msecs_to_jiffies(10));
547
548 /* config depop sequence parameter */
549 rt5631_write_index(codec, RT5631_SPK_INTL_CTRL, 0x302f);
550 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_1,
551 RT5631_POW_ON_SOFT_GEN | RT5631_EN_MUTE_UNMUTE_DEPOP |
552 RT5631_EN_HP_R_M_UN_MUTE_DEPOP |
553 RT5631_EN_HP_L_M_UN_MUTE_DEPOP);
554
555 snd_soc_update_bits(codec, RT5631_HP_OUT_VOL,
556 RT5631_L_MUTE | RT5631_R_MUTE, 0);
557 msleep(160);
558 } else {
559 /* config depop sequence parameter */
560 rt5631_write_index(codec, RT5631_SPK_INTL_CTRL, 0x302f);
561 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_1,
562 RT5631_POW_ON_SOFT_GEN | RT5631_EN_MUTE_UNMUTE_DEPOP |
563 RT5631_EN_HP_R_M_UN_MUTE_DEPOP |
564 RT5631_EN_HP_L_M_UN_MUTE_DEPOP);
565
566 snd_soc_update_bits(codec, RT5631_HP_OUT_VOL,
567 RT5631_L_MUTE | RT5631_R_MUTE,
568 RT5631_L_MUTE | RT5631_R_MUTE);
569 msleep(150);
570 }
571
572 /* recover soft volume and zero crossing setting */
573 snd_soc_write(codec, RT5631_SOFT_VOL_CTRL, soft_vol);
574 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, hp_zc);
575}
576
577static int hp_event(struct snd_soc_dapm_widget *w,
578 struct snd_kcontrol *kcontrol, int event)
579{
580 struct snd_soc_codec *codec = w->codec;
581 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
582
583 switch (event) {
584 case SND_SOC_DAPM_PRE_PMD:
585 if (rt5631->codec_version) {
586 onebit_depop_mute_stage(codec, 0);
587 onebit_depop_power_stage(codec, 0);
588 } else {
589 depop_seq_mute_stage(codec, 0);
590 depop_seq_power_stage(codec, 0);
591 }
592 break;
593
594 case SND_SOC_DAPM_POST_PMU:
595 if (rt5631->codec_version) {
596 onebit_depop_power_stage(codec, 1);
597 onebit_depop_mute_stage(codec, 1);
598 } else {
599 depop_seq_power_stage(codec, 1);
600 depop_seq_mute_stage(codec, 1);
601 }
602 break;
603
604 default:
605 break;
606 }
607
608 return 0;
609}
610
611static int set_dmic_params(struct snd_soc_dapm_widget *w,
612 struct snd_kcontrol *kcontrol, int event)
613{
614 struct snd_soc_codec *codec = w->codec;
615 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
616
617 switch (rt5631->rx_rate) {
618 case 44100:
619 case 48000:
620 snd_soc_update_bits(codec, RT5631_DIG_MIC_CTRL,
621 RT5631_DMIC_CLK_CTRL_MASK,
622 RT5631_DMIC_CLK_CTRL_TO_32FS);
623 break;
624
625 case 32000:
626 case 22050:
627 snd_soc_update_bits(codec, RT5631_DIG_MIC_CTRL,
628 RT5631_DMIC_CLK_CTRL_MASK,
629 RT5631_DMIC_CLK_CTRL_TO_64FS);
630 break;
631
632 case 16000:
633 case 11025:
634 case 8000:
635 snd_soc_update_bits(codec, RT5631_DIG_MIC_CTRL,
636 RT5631_DMIC_CLK_CTRL_MASK,
637 RT5631_DMIC_CLK_CTRL_TO_128FS);
638 break;
639
640 default:
641 return -EINVAL;
642 }
643
644 return 0;
645}
646
647static const struct snd_kcontrol_new rt5631_recmixl_mixer_controls[] = {
648 SOC_DAPM_SINGLE("OUTMIXL Capture Switch", RT5631_ADC_REC_MIXER,
649 RT5631_M_OUTMIXL_RECMIXL_BIT, 1, 1),
650 SOC_DAPM_SINGLE("MIC1_BST1 Capture Switch", RT5631_ADC_REC_MIXER,
651 RT5631_M_MIC1_RECMIXL_BIT, 1, 1),
652 SOC_DAPM_SINGLE("AXILVOL Capture Switch", RT5631_ADC_REC_MIXER,
653 RT5631_M_AXIL_RECMIXL_BIT, 1, 1),
654 SOC_DAPM_SINGLE("MONOIN_RX Capture Switch", RT5631_ADC_REC_MIXER,
655 RT5631_M_MONO_IN_RECMIXL_BIT, 1, 1),
656};
657
658static const struct snd_kcontrol_new rt5631_recmixr_mixer_controls[] = {
659 SOC_DAPM_SINGLE("MONOIN_RX Capture Switch", RT5631_ADC_REC_MIXER,
660 RT5631_M_MONO_IN_RECMIXR_BIT, 1, 1),
661 SOC_DAPM_SINGLE("AXIRVOL Capture Switch", RT5631_ADC_REC_MIXER,
662 RT5631_M_AXIR_RECMIXR_BIT, 1, 1),
663 SOC_DAPM_SINGLE("MIC2_BST2 Capture Switch", RT5631_ADC_REC_MIXER,
664 RT5631_M_MIC2_RECMIXR_BIT, 1, 1),
665 SOC_DAPM_SINGLE("OUTMIXR Capture Switch", RT5631_ADC_REC_MIXER,
666 RT5631_M_OUTMIXR_RECMIXR_BIT, 1, 1),
667};
668
669static const struct snd_kcontrol_new rt5631_spkmixl_mixer_controls[] = {
670 SOC_DAPM_SINGLE("RECMIXL Playback Switch", RT5631_SPK_MIXER_CTRL,
671 RT5631_M_RECMIXL_SPKMIXL_BIT, 1, 1),
672 SOC_DAPM_SINGLE("MIC1_P Playback Switch", RT5631_SPK_MIXER_CTRL,
673 RT5631_M_MIC1P_SPKMIXL_BIT, 1, 1),
674 SOC_DAPM_SINGLE("DACL Playback Switch", RT5631_SPK_MIXER_CTRL,
675 RT5631_M_DACL_SPKMIXL_BIT, 1, 1),
676 SOC_DAPM_SINGLE("OUTMIXL Playback Switch", RT5631_SPK_MIXER_CTRL,
677 RT5631_M_OUTMIXL_SPKMIXL_BIT, 1, 1),
678};
679
680static const struct snd_kcontrol_new rt5631_spkmixr_mixer_controls[] = {
681 SOC_DAPM_SINGLE("OUTMIXR Playback Switch", RT5631_SPK_MIXER_CTRL,
682 RT5631_M_OUTMIXR_SPKMIXR_BIT, 1, 1),
683 SOC_DAPM_SINGLE("DACR Playback Switch", RT5631_SPK_MIXER_CTRL,
684 RT5631_M_DACR_SPKMIXR_BIT, 1, 1),
685 SOC_DAPM_SINGLE("MIC2_P Playback Switch", RT5631_SPK_MIXER_CTRL,
686 RT5631_M_MIC2P_SPKMIXR_BIT, 1, 1),
687 SOC_DAPM_SINGLE("RECMIXR Playback Switch", RT5631_SPK_MIXER_CTRL,
688 RT5631_M_RECMIXR_SPKMIXR_BIT, 1, 1),
689};
690
691static const struct snd_kcontrol_new rt5631_outmixl_mixer_controls[] = {
692 SOC_DAPM_SINGLE("RECMIXL Playback Switch", RT5631_OUTMIXER_L_CTRL,
693 RT5631_M_RECMIXL_OUTMIXL_BIT, 1, 1),
694 SOC_DAPM_SINGLE("RECMIXR Playback Switch", RT5631_OUTMIXER_L_CTRL,
695 RT5631_M_RECMIXR_OUTMIXL_BIT, 1, 1),
696 SOC_DAPM_SINGLE("DACL Playback Switch", RT5631_OUTMIXER_L_CTRL,
697 RT5631_M_DACL_OUTMIXL_BIT, 1, 1),
698 SOC_DAPM_SINGLE("MIC1_BST1 Playback Switch", RT5631_OUTMIXER_L_CTRL,
699 RT5631_M_MIC1_OUTMIXL_BIT, 1, 1),
700 SOC_DAPM_SINGLE("MIC2_BST2 Playback Switch", RT5631_OUTMIXER_L_CTRL,
701 RT5631_M_MIC2_OUTMIXL_BIT, 1, 1),
702 SOC_DAPM_SINGLE("MONOIN_RXP Playback Switch", RT5631_OUTMIXER_L_CTRL,
703 RT5631_M_MONO_INP_OUTMIXL_BIT, 1, 1),
704 SOC_DAPM_SINGLE("AXILVOL Playback Switch", RT5631_OUTMIXER_L_CTRL,
705 RT5631_M_AXIL_OUTMIXL_BIT, 1, 1),
706 SOC_DAPM_SINGLE("AXIRVOL Playback Switch", RT5631_OUTMIXER_L_CTRL,
707 RT5631_M_AXIR_OUTMIXL_BIT, 1, 1),
708 SOC_DAPM_SINGLE("VDAC Playback Switch", RT5631_OUTMIXER_L_CTRL,
709 RT5631_M_VDAC_OUTMIXL_BIT, 1, 1),
710};
711
712static const struct snd_kcontrol_new rt5631_outmixr_mixer_controls[] = {
713 SOC_DAPM_SINGLE("VDAC Playback Switch", RT5631_OUTMIXER_R_CTRL,
714 RT5631_M_VDAC_OUTMIXR_BIT, 1, 1),
715 SOC_DAPM_SINGLE("AXIRVOL Playback Switch", RT5631_OUTMIXER_R_CTRL,
716 RT5631_M_AXIR_OUTMIXR_BIT, 1, 1),
717 SOC_DAPM_SINGLE("AXILVOL Playback Switch", RT5631_OUTMIXER_R_CTRL,
718 RT5631_M_AXIL_OUTMIXR_BIT, 1, 1),
719 SOC_DAPM_SINGLE("MONOIN_RXN Playback Switch", RT5631_OUTMIXER_R_CTRL,
720 RT5631_M_MONO_INN_OUTMIXR_BIT, 1, 1),
721 SOC_DAPM_SINGLE("MIC2_BST2 Playback Switch", RT5631_OUTMIXER_R_CTRL,
722 RT5631_M_MIC2_OUTMIXR_BIT, 1, 1),
723 SOC_DAPM_SINGLE("MIC1_BST1 Playback Switch", RT5631_OUTMIXER_R_CTRL,
724 RT5631_M_MIC1_OUTMIXR_BIT, 1, 1),
725 SOC_DAPM_SINGLE("DACR Playback Switch", RT5631_OUTMIXER_R_CTRL,
726 RT5631_M_DACR_OUTMIXR_BIT, 1, 1),
727 SOC_DAPM_SINGLE("RECMIXR Playback Switch", RT5631_OUTMIXER_R_CTRL,
728 RT5631_M_RECMIXR_OUTMIXR_BIT, 1, 1),
729 SOC_DAPM_SINGLE("RECMIXL Playback Switch", RT5631_OUTMIXER_R_CTRL,
730 RT5631_M_RECMIXL_OUTMIXR_BIT, 1, 1),
731};
732
733static const struct snd_kcontrol_new rt5631_AXO1MIX_mixer_controls[] = {
734 SOC_DAPM_SINGLE("MIC1_BST1 Playback Switch", RT5631_AXO1MIXER_CTRL,
735 RT5631_M_MIC1_AXO1MIX_BIT , 1, 1),
736 SOC_DAPM_SINGLE("MIC2_BST2 Playback Switch", RT5631_AXO1MIXER_CTRL,
737 RT5631_M_MIC2_AXO1MIX_BIT, 1, 1),
738 SOC_DAPM_SINGLE("OUTVOLL Playback Switch", RT5631_AXO1MIXER_CTRL,
739 RT5631_M_OUTMIXL_AXO1MIX_BIT , 1 , 1),
740 SOC_DAPM_SINGLE("OUTVOLR Playback Switch", RT5631_AXO1MIXER_CTRL,
741 RT5631_M_OUTMIXR_AXO1MIX_BIT, 1, 1),
742};
743
744static const struct snd_kcontrol_new rt5631_AXO2MIX_mixer_controls[] = {
745 SOC_DAPM_SINGLE("MIC1_BST1 Playback Switch", RT5631_AXO2MIXER_CTRL,
746 RT5631_M_MIC1_AXO2MIX_BIT, 1, 1),
747 SOC_DAPM_SINGLE("MIC2_BST2 Playback Switch", RT5631_AXO2MIXER_CTRL,
748 RT5631_M_MIC2_AXO2MIX_BIT, 1, 1),
749 SOC_DAPM_SINGLE("OUTVOLL Playback Switch", RT5631_AXO2MIXER_CTRL,
750 RT5631_M_OUTMIXL_AXO2MIX_BIT, 1, 1),
751 SOC_DAPM_SINGLE("OUTVOLR Playback Switch", RT5631_AXO2MIXER_CTRL,
752 RT5631_M_OUTMIXR_AXO2MIX_BIT, 1 , 1),
753};
754
755static const struct snd_kcontrol_new rt5631_spolmix_mixer_controls[] = {
756 SOC_DAPM_SINGLE("SPKVOLL Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
757 RT5631_M_SPKVOLL_SPOLMIX_BIT, 1, 1),
758 SOC_DAPM_SINGLE("SPKVOLR Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
759 RT5631_M_SPKVOLR_SPOLMIX_BIT, 1, 1),
760};
761
762static const struct snd_kcontrol_new rt5631_spormix_mixer_controls[] = {
763 SOC_DAPM_SINGLE("SPKVOLL Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
764 RT5631_M_SPKVOLL_SPORMIX_BIT, 1, 1),
765 SOC_DAPM_SINGLE("SPKVOLR Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
766 RT5631_M_SPKVOLR_SPORMIX_BIT, 1, 1),
767};
768
769static const struct snd_kcontrol_new rt5631_monomix_mixer_controls[] = {
770 SOC_DAPM_SINGLE("OUTVOLL Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
771 RT5631_M_OUTVOLL_MONOMIX_BIT, 1, 1),
772 SOC_DAPM_SINGLE("OUTVOLR Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
773 RT5631_M_OUTVOLR_MONOMIX_BIT, 1, 1),
774};
775
776/* Left SPK Volume Input */
777static const char *rt5631_spkvoll_sel[] = {"Vmid", "SPKMIXL"};
778
779static const SOC_ENUM_SINGLE_DECL(
780 rt5631_spkvoll_enum, RT5631_SPK_OUT_VOL,
781 RT5631_L_EN_SHIFT, rt5631_spkvoll_sel);
782
783static const struct snd_kcontrol_new rt5631_spkvoll_mux_control =
784 SOC_DAPM_ENUM("Left SPKVOL SRC", rt5631_spkvoll_enum);
785
786/* Left HP Volume Input */
787static const char *rt5631_hpvoll_sel[] = {"Vmid", "OUTMIXL"};
788
789static const SOC_ENUM_SINGLE_DECL(
790 rt5631_hpvoll_enum, RT5631_HP_OUT_VOL,
791 RT5631_L_EN_SHIFT, rt5631_hpvoll_sel);
792
793static const struct snd_kcontrol_new rt5631_hpvoll_mux_control =
794 SOC_DAPM_ENUM("Left HPVOL SRC", rt5631_hpvoll_enum);
795
796/* Left Out Volume Input */
797static const char *rt5631_outvoll_sel[] = {"Vmid", "OUTMIXL"};
798
799static const SOC_ENUM_SINGLE_DECL(
800 rt5631_outvoll_enum, RT5631_MONO_AXO_1_2_VOL,
801 RT5631_L_EN_SHIFT, rt5631_outvoll_sel);
802
803static const struct snd_kcontrol_new rt5631_outvoll_mux_control =
804 SOC_DAPM_ENUM("Left OUTVOL SRC", rt5631_outvoll_enum);
805
806/* Right Out Volume Input */
807static const char *rt5631_outvolr_sel[] = {"Vmid", "OUTMIXR"};
808
809static const SOC_ENUM_SINGLE_DECL(
810 rt5631_outvolr_enum, RT5631_MONO_AXO_1_2_VOL,
811 RT5631_R_EN_SHIFT, rt5631_outvolr_sel);
812
813static const struct snd_kcontrol_new rt5631_outvolr_mux_control =
814 SOC_DAPM_ENUM("Right OUTVOL SRC", rt5631_outvolr_enum);
815
816/* Right HP Volume Input */
817static const char *rt5631_hpvolr_sel[] = {"Vmid", "OUTMIXR"};
818
819static const SOC_ENUM_SINGLE_DECL(
820 rt5631_hpvolr_enum, RT5631_HP_OUT_VOL,
821 RT5631_R_EN_SHIFT, rt5631_hpvolr_sel);
822
823static const struct snd_kcontrol_new rt5631_hpvolr_mux_control =
824 SOC_DAPM_ENUM("Right HPVOL SRC", rt5631_hpvolr_enum);
825
826/* Right SPK Volume Input */
827static const char *rt5631_spkvolr_sel[] = {"Vmid", "SPKMIXR"};
828
829static const SOC_ENUM_SINGLE_DECL(
830 rt5631_spkvolr_enum, RT5631_SPK_OUT_VOL,
831 RT5631_R_EN_SHIFT, rt5631_spkvolr_sel);
832
833static const struct snd_kcontrol_new rt5631_spkvolr_mux_control =
834 SOC_DAPM_ENUM("Right SPKVOL SRC", rt5631_spkvolr_enum);
835
836/* SPO Left Channel Input */
837static const char *rt5631_spol_src_sel[] = {
838 "SPOLMIX", "MONOIN_RX", "VDAC", "DACL"};
839
840static const SOC_ENUM_SINGLE_DECL(
841 rt5631_spol_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
842 RT5631_SPK_L_MUX_SEL_SHIFT, rt5631_spol_src_sel);
843
844static const struct snd_kcontrol_new rt5631_spol_mux_control =
845 SOC_DAPM_ENUM("SPOL SRC", rt5631_spol_src_enum);
846
847/* SPO Right Channel Input */
848static const char *rt5631_spor_src_sel[] = {
849 "SPORMIX", "MONOIN_RX", "VDAC", "DACR"};
850
851static const SOC_ENUM_SINGLE_DECL(
852 rt5631_spor_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
853 RT5631_SPK_R_MUX_SEL_SHIFT, rt5631_spor_src_sel);
854
855static const struct snd_kcontrol_new rt5631_spor_mux_control =
856 SOC_DAPM_ENUM("SPOR SRC", rt5631_spor_src_enum);
857
858/* MONO Input */
859static const char *rt5631_mono_src_sel[] = {"MONOMIX", "MONOIN_RX", "VDAC"};
860
861static const SOC_ENUM_SINGLE_DECL(
862 rt5631_mono_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
863 RT5631_MONO_MUX_SEL_SHIFT, rt5631_mono_src_sel);
864
865static const struct snd_kcontrol_new rt5631_mono_mux_control =
866 SOC_DAPM_ENUM("MONO SRC", rt5631_mono_src_enum);
867
868/* Left HPO Input */
869static const char *rt5631_hpl_src_sel[] = {"Left HPVOL", "Left DAC"};
870
871static const SOC_ENUM_SINGLE_DECL(
872 rt5631_hpl_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
873 RT5631_HP_L_MUX_SEL_SHIFT, rt5631_hpl_src_sel);
874
875static const struct snd_kcontrol_new rt5631_hpl_mux_control =
876 SOC_DAPM_ENUM("HPL SRC", rt5631_hpl_src_enum);
877
878/* Right HPO Input */
879static const char *rt5631_hpr_src_sel[] = {"Right HPVOL", "Right DAC"};
880
881static const SOC_ENUM_SINGLE_DECL(
882 rt5631_hpr_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
883 RT5631_HP_R_MUX_SEL_SHIFT, rt5631_hpr_src_sel);
884
885static const struct snd_kcontrol_new rt5631_hpr_mux_control =
886 SOC_DAPM_ENUM("HPR SRC", rt5631_hpr_src_enum);
887
888static const struct snd_soc_dapm_widget rt5631_dapm_widgets[] = {
889 /* Vmid */
890 SND_SOC_DAPM_VMID("Vmid"),
891 /* PLL1 */
892 SND_SOC_DAPM_SUPPLY("PLL1", RT5631_PWR_MANAG_ADD2,
893 RT5631_PWR_PLL1_BIT, 0, NULL, 0),
894
895 /* Input Side */
896 /* Input Lines */
897 SND_SOC_DAPM_INPUT("MIC1"),
898 SND_SOC_DAPM_INPUT("MIC2"),
899 SND_SOC_DAPM_INPUT("AXIL"),
900 SND_SOC_DAPM_INPUT("AXIR"),
901 SND_SOC_DAPM_INPUT("MONOIN_RXN"),
902 SND_SOC_DAPM_INPUT("MONOIN_RXP"),
903 SND_SOC_DAPM_INPUT("DMIC"),
904
905 /* MICBIAS */
906 SND_SOC_DAPM_MICBIAS("MIC Bias1", RT5631_PWR_MANAG_ADD2,
907 RT5631_PWR_MICBIAS1_VOL_BIT, 0),
908 SND_SOC_DAPM_MICBIAS("MIC Bias2", RT5631_PWR_MANAG_ADD2,
909 RT5631_PWR_MICBIAS2_VOL_BIT, 0),
910
911 /* Boost */
912 SND_SOC_DAPM_PGA("MIC1 Boost", RT5631_PWR_MANAG_ADD2,
913 RT5631_PWR_MIC1_BOOT_GAIN_BIT, 0, NULL, 0),
914 SND_SOC_DAPM_PGA("MIC2 Boost", RT5631_PWR_MANAG_ADD2,
915 RT5631_PWR_MIC2_BOOT_GAIN_BIT, 0, NULL, 0),
916 SND_SOC_DAPM_PGA("MONOIN_RXP Boost", RT5631_PWR_MANAG_ADD4,
917 RT5631_PWR_MONO_IN_P_VOL_BIT, 0, NULL, 0),
918 SND_SOC_DAPM_PGA("MONOIN_RXN Boost", RT5631_PWR_MANAG_ADD4,
919 RT5631_PWR_MONO_IN_N_VOL_BIT, 0, NULL, 0),
920 SND_SOC_DAPM_PGA("AXIL Boost", RT5631_PWR_MANAG_ADD4,
921 RT5631_PWR_AXIL_IN_VOL_BIT, 0, NULL, 0),
922 SND_SOC_DAPM_PGA("AXIR Boost", RT5631_PWR_MANAG_ADD4,
923 RT5631_PWR_AXIR_IN_VOL_BIT, 0, NULL, 0),
924
925 /* MONO In */
926 SND_SOC_DAPM_MIXER("MONO_IN", SND_SOC_NOPM, 0, 0, NULL, 0),
927
928 /* REC Mixer */
929 SND_SOC_DAPM_MIXER("RECMIXL Mixer", RT5631_PWR_MANAG_ADD2,
930 RT5631_PWR_RECMIXER_L_BIT, 0,
931 &rt5631_recmixl_mixer_controls[0],
932 ARRAY_SIZE(rt5631_recmixl_mixer_controls)),
933 SND_SOC_DAPM_MIXER("RECMIXR Mixer", RT5631_PWR_MANAG_ADD2,
934 RT5631_PWR_RECMIXER_R_BIT, 0,
935 &rt5631_recmixr_mixer_controls[0],
936 ARRAY_SIZE(rt5631_recmixr_mixer_controls)),
937 /* Because of record duplication for L/R channel,
938 * L/R ADCs need power up at the same time */
939 SND_SOC_DAPM_MIXER("ADC Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
940
941 /* DMIC */
942 SND_SOC_DAPM_SUPPLY("DMIC Supply", RT5631_DIG_MIC_CTRL,
943 RT5631_DMIC_ENA_SHIFT, 0,
944 set_dmic_params, SND_SOC_DAPM_PRE_PMU),
945 /* ADC Data Srouce */
946 SND_SOC_DAPM_SUPPLY("Left ADC Select", RT5631_INT_ST_IRQ_CTRL_2,
947 RT5631_ADC_DATA_SEL_MIC1_SHIFT, 0, NULL, 0),
948 SND_SOC_DAPM_SUPPLY("Right ADC Select", RT5631_INT_ST_IRQ_CTRL_2,
949 RT5631_ADC_DATA_SEL_MIC2_SHIFT, 0, NULL, 0),
950
951 /* ADCs */
952 SND_SOC_DAPM_ADC("Left ADC", "HIFI Capture",
953 RT5631_PWR_MANAG_ADD1, RT5631_PWR_ADC_L_CLK_BIT, 0),
954 SND_SOC_DAPM_ADC("Right ADC", "HIFI Capture",
955 RT5631_PWR_MANAG_ADD1, RT5631_PWR_ADC_R_CLK_BIT, 0),
956
957 /* DAC and ADC supply power */
958 SND_SOC_DAPM_SUPPLY("I2S", RT5631_PWR_MANAG_ADD1,
959 RT5631_PWR_MAIN_I2S_BIT, 0, NULL, 0),
960 SND_SOC_DAPM_SUPPLY("DAC REF", RT5631_PWR_MANAG_ADD1,
961 RT5631_PWR_DAC_REF_BIT, 0, NULL, 0),
962
963 /* Output Side */
964 /* DACs */
965 SND_SOC_DAPM_DAC("Left DAC", "HIFI Playback",
966 RT5631_PWR_MANAG_ADD1, RT5631_PWR_DAC_L_CLK_BIT, 0),
967 SND_SOC_DAPM_DAC("Right DAC", "HIFI Playback",
968 RT5631_PWR_MANAG_ADD1, RT5631_PWR_DAC_R_CLK_BIT, 0),
969 SND_SOC_DAPM_DAC("Voice DAC", "Voice DAC Mono Playback",
970 SND_SOC_NOPM, 0, 0),
971 SND_SOC_DAPM_PGA("Voice DAC Boost", SND_SOC_NOPM, 0, 0, NULL, 0),
972 /* DAC supply power */
973 SND_SOC_DAPM_SUPPLY("Left DAC To Mixer", RT5631_PWR_MANAG_ADD1,
974 RT5631_PWR_DAC_L_TO_MIXER_BIT, 0, NULL, 0),
975 SND_SOC_DAPM_SUPPLY("Right DAC To Mixer", RT5631_PWR_MANAG_ADD1,
976 RT5631_PWR_DAC_R_TO_MIXER_BIT, 0, NULL, 0),
977
978 /* Left SPK Mixer */
979 SND_SOC_DAPM_MIXER("SPKMIXL Mixer", RT5631_PWR_MANAG_ADD2,
980 RT5631_PWR_SPKMIXER_L_BIT, 0,
981 &rt5631_spkmixl_mixer_controls[0],
982 ARRAY_SIZE(rt5631_spkmixl_mixer_controls)),
983 /* Left Out Mixer */
984 SND_SOC_DAPM_MIXER("OUTMIXL Mixer", RT5631_PWR_MANAG_ADD2,
985 RT5631_PWR_OUTMIXER_L_BIT, 0,
986 &rt5631_outmixl_mixer_controls[0],
987 ARRAY_SIZE(rt5631_outmixl_mixer_controls)),
988 /* Right Out Mixer */
989 SND_SOC_DAPM_MIXER("OUTMIXR Mixer", RT5631_PWR_MANAG_ADD2,
990 RT5631_PWR_OUTMIXER_R_BIT, 0,
991 &rt5631_outmixr_mixer_controls[0],
992 ARRAY_SIZE(rt5631_outmixr_mixer_controls)),
993 /* Right SPK Mixer */
994 SND_SOC_DAPM_MIXER("SPKMIXR Mixer", RT5631_PWR_MANAG_ADD2,
995 RT5631_PWR_SPKMIXER_R_BIT, 0,
996 &rt5631_spkmixr_mixer_controls[0],
997 ARRAY_SIZE(rt5631_spkmixr_mixer_controls)),
998
999 /* Volume Mux */
1000 SND_SOC_DAPM_MUX("Left SPKVOL Mux", RT5631_PWR_MANAG_ADD4,
1001 RT5631_PWR_SPK_L_VOL_BIT, 0,
1002 &rt5631_spkvoll_mux_control),
1003 SND_SOC_DAPM_MUX("Left HPVOL Mux", RT5631_PWR_MANAG_ADD4,
1004 RT5631_PWR_HP_L_OUT_VOL_BIT, 0,
1005 &rt5631_hpvoll_mux_control),
1006 SND_SOC_DAPM_MUX("Left OUTVOL Mux", RT5631_PWR_MANAG_ADD4,
1007 RT5631_PWR_LOUT_VOL_BIT, 0,
1008 &rt5631_outvoll_mux_control),
1009 SND_SOC_DAPM_MUX("Right OUTVOL Mux", RT5631_PWR_MANAG_ADD4,
1010 RT5631_PWR_ROUT_VOL_BIT, 0,
1011 &rt5631_outvolr_mux_control),
1012 SND_SOC_DAPM_MUX("Right HPVOL Mux", RT5631_PWR_MANAG_ADD4,
1013 RT5631_PWR_HP_R_OUT_VOL_BIT, 0,
1014 &rt5631_hpvolr_mux_control),
1015 SND_SOC_DAPM_MUX("Right SPKVOL Mux", RT5631_PWR_MANAG_ADD4,
1016 RT5631_PWR_SPK_R_VOL_BIT, 0,
1017 &rt5631_spkvolr_mux_control),
1018
1019 /* DAC To HP */
1020 SND_SOC_DAPM_PGA_S("Left DAC_HP", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
1021 SND_SOC_DAPM_PGA_S("Right DAC_HP", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
1022
1023 /* HP Depop */
1024 SND_SOC_DAPM_PGA_S("HP Depop", 1, SND_SOC_NOPM, 0, 0,
1025 hp_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1026
1027 /* AXO1 Mixer */
1028 SND_SOC_DAPM_MIXER("AXO1MIX Mixer", RT5631_PWR_MANAG_ADD3,
1029 RT5631_PWR_AXO1MIXER_BIT, 0,
1030 &rt5631_AXO1MIX_mixer_controls[0],
1031 ARRAY_SIZE(rt5631_AXO1MIX_mixer_controls)),
1032 /* SPOL Mixer */
1033 SND_SOC_DAPM_MIXER("SPOLMIX Mixer", SND_SOC_NOPM, 0, 0,
1034 &rt5631_spolmix_mixer_controls[0],
1035 ARRAY_SIZE(rt5631_spolmix_mixer_controls)),
1036 /* MONO Mixer */
1037 SND_SOC_DAPM_MIXER("MONOMIX Mixer", RT5631_PWR_MANAG_ADD3,
1038 RT5631_PWR_MONOMIXER_BIT, 0,
1039 &rt5631_monomix_mixer_controls[0],
1040 ARRAY_SIZE(rt5631_monomix_mixer_controls)),
1041 /* SPOR Mixer */
1042 SND_SOC_DAPM_MIXER("SPORMIX Mixer", SND_SOC_NOPM, 0, 0,
1043 &rt5631_spormix_mixer_controls[0],
1044 ARRAY_SIZE(rt5631_spormix_mixer_controls)),
1045 /* AXO2 Mixer */
1046 SND_SOC_DAPM_MIXER("AXO2MIX Mixer", RT5631_PWR_MANAG_ADD3,
1047 RT5631_PWR_AXO2MIXER_BIT, 0,
1048 &rt5631_AXO2MIX_mixer_controls[0],
1049 ARRAY_SIZE(rt5631_AXO2MIX_mixer_controls)),
1050
1051 /* Mux */
1052 SND_SOC_DAPM_MUX("SPOL Mux", SND_SOC_NOPM, 0, 0,
1053 &rt5631_spol_mux_control),
1054 SND_SOC_DAPM_MUX("SPOR Mux", SND_SOC_NOPM, 0, 0,
1055 &rt5631_spor_mux_control),
1056 SND_SOC_DAPM_MUX("MONO Mux", SND_SOC_NOPM, 0, 0,
1057 &rt5631_mono_mux_control),
1058 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0,
1059 &rt5631_hpl_mux_control),
1060 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0,
1061 &rt5631_hpr_mux_control),
1062
1063 /* AMP supply */
1064 SND_SOC_DAPM_SUPPLY("MONO Depop", RT5631_PWR_MANAG_ADD3,
1065 RT5631_PWR_MONO_DEPOP_DIS_BIT, 0, NULL, 0),
1066 SND_SOC_DAPM_SUPPLY("Class D", RT5631_PWR_MANAG_ADD1,
1067 RT5631_PWR_CLASS_D_BIT, 0, NULL, 0),
1068
1069 /* Output Lines */
1070 SND_SOC_DAPM_OUTPUT("AUXO1"),
1071 SND_SOC_DAPM_OUTPUT("AUXO2"),
1072 SND_SOC_DAPM_OUTPUT("SPOL"),
1073 SND_SOC_DAPM_OUTPUT("SPOR"),
1074 SND_SOC_DAPM_OUTPUT("HPOL"),
1075 SND_SOC_DAPM_OUTPUT("HPOR"),
1076 SND_SOC_DAPM_OUTPUT("MONO"),
1077};
1078
1079static const struct snd_soc_dapm_route rt5631_dapm_routes[] = {
1080 {"MIC1 Boost", NULL, "MIC1"},
1081 {"MIC2 Boost", NULL, "MIC2"},
1082 {"MONOIN_RXP Boost", NULL, "MONOIN_RXP"},
1083 {"MONOIN_RXN Boost", NULL, "MONOIN_RXN"},
1084 {"AXIL Boost", NULL, "AXIL"},
1085 {"AXIR Boost", NULL, "AXIR"},
1086
1087 {"MONO_IN", NULL, "MONOIN_RXP Boost"},
1088 {"MONO_IN", NULL, "MONOIN_RXN Boost"},
1089
1090 {"RECMIXL Mixer", "OUTMIXL Capture Switch", "OUTMIXL Mixer"},
1091 {"RECMIXL Mixer", "MIC1_BST1 Capture Switch", "MIC1 Boost"},
1092 {"RECMIXL Mixer", "AXILVOL Capture Switch", "AXIL Boost"},
1093 {"RECMIXL Mixer", "MONOIN_RX Capture Switch", "MONO_IN"},
1094
1095 {"RECMIXR Mixer", "OUTMIXR Capture Switch", "OUTMIXR Mixer"},
1096 {"RECMIXR Mixer", "MIC2_BST2 Capture Switch", "MIC2 Boost"},
1097 {"RECMIXR Mixer", "AXIRVOL Capture Switch", "AXIR Boost"},
1098 {"RECMIXR Mixer", "MONOIN_RX Capture Switch", "MONO_IN"},
1099
1100 {"ADC Mixer", NULL, "RECMIXL Mixer"},
1101 {"ADC Mixer", NULL, "RECMIXR Mixer"},
1102
1103 {"Left ADC", NULL, "ADC Mixer"},
1104 {"Left ADC", NULL, "Left ADC Select", check_adcl_select},
1105 {"Left ADC", NULL, "PLL1", check_sysclk1_source},
1106 {"Left ADC", NULL, "I2S"},
1107 {"Left ADC", NULL, "DAC REF"},
1108
1109 {"Right ADC", NULL, "ADC Mixer"},
1110 {"Right ADC", NULL, "Right ADC Select", check_adcr_select},
1111 {"Right ADC", NULL, "PLL1", check_sysclk1_source},
1112 {"Right ADC", NULL, "I2S"},
1113 {"Right ADC", NULL, "DAC REF"},
1114
1115 {"DMIC", NULL, "DMIC Supply", check_dmic_used},
1116 {"Left ADC", NULL, "DMIC"},
1117 {"Right ADC", NULL, "DMIC"},
1118
1119 {"Left DAC", NULL, "PLL1", check_sysclk1_source},
1120 {"Left DAC", NULL, "I2S"},
1121 {"Left DAC", NULL, "DAC REF"},
1122 {"Right DAC", NULL, "PLL1", check_sysclk1_source},
1123 {"Right DAC", NULL, "I2S"},
1124 {"Right DAC", NULL, "DAC REF"},
1125
1126 {"Voice DAC Boost", NULL, "Voice DAC"},
1127
1128 {"SPKMIXL Mixer", NULL, "Left DAC To Mixer", check_dacl_to_spkmixl},
1129 {"SPKMIXL Mixer", "RECMIXL Playback Switch", "RECMIXL Mixer"},
1130 {"SPKMIXL Mixer", "MIC1_P Playback Switch", "MIC1"},
1131 {"SPKMIXL Mixer", "DACL Playback Switch", "Left DAC"},
1132 {"SPKMIXL Mixer", "OUTMIXL Playback Switch", "OUTMIXL Mixer"},
1133
1134 {"SPKMIXR Mixer", NULL, "Right DAC To Mixer", check_dacr_to_spkmixr},
1135 {"SPKMIXR Mixer", "OUTMIXR Playback Switch", "OUTMIXR Mixer"},
1136 {"SPKMIXR Mixer", "DACR Playback Switch", "Right DAC"},
1137 {"SPKMIXR Mixer", "MIC2_P Playback Switch", "MIC2"},
1138 {"SPKMIXR Mixer", "RECMIXR Playback Switch", "RECMIXR Mixer"},
1139
1140 {"OUTMIXL Mixer", NULL, "Left DAC To Mixer", check_dacl_to_outmixl},
1141 {"OUTMIXL Mixer", "RECMIXL Playback Switch", "RECMIXL Mixer"},
1142 {"OUTMIXL Mixer", "RECMIXR Playback Switch", "RECMIXR Mixer"},
1143 {"OUTMIXL Mixer", "DACL Playback Switch", "Left DAC"},
1144 {"OUTMIXL Mixer", "MIC1_BST1 Playback Switch", "MIC1 Boost"},
1145 {"OUTMIXL Mixer", "MIC2_BST2 Playback Switch", "MIC2 Boost"},
1146 {"OUTMIXL Mixer", "MONOIN_RXP Playback Switch", "MONOIN_RXP Boost"},
1147 {"OUTMIXL Mixer", "AXILVOL Playback Switch", "AXIL Boost"},
1148 {"OUTMIXL Mixer", "AXIRVOL Playback Switch", "AXIR Boost"},
1149 {"OUTMIXL Mixer", "VDAC Playback Switch", "Voice DAC Boost"},
1150
1151 {"OUTMIXR Mixer", NULL, "Right DAC To Mixer", check_dacr_to_outmixr},
1152 {"OUTMIXR Mixer", "RECMIXL Playback Switch", "RECMIXL Mixer"},
1153 {"OUTMIXR Mixer", "RECMIXR Playback Switch", "RECMIXR Mixer"},
1154 {"OUTMIXR Mixer", "DACR Playback Switch", "Right DAC"},
1155 {"OUTMIXR Mixer", "MIC1_BST1 Playback Switch", "MIC1 Boost"},
1156 {"OUTMIXR Mixer", "MIC2_BST2 Playback Switch", "MIC2 Boost"},
1157 {"OUTMIXR Mixer", "MONOIN_RXN Playback Switch", "MONOIN_RXN Boost"},
1158 {"OUTMIXR Mixer", "AXILVOL Playback Switch", "AXIL Boost"},
1159 {"OUTMIXR Mixer", "AXIRVOL Playback Switch", "AXIR Boost"},
1160 {"OUTMIXR Mixer", "VDAC Playback Switch", "Voice DAC Boost"},
1161
1162 {"Left SPKVOL Mux", "SPKMIXL", "SPKMIXL Mixer"},
1163 {"Left SPKVOL Mux", "Vmid", "Vmid"},
1164 {"Left HPVOL Mux", "OUTMIXL", "OUTMIXL Mixer"},
1165 {"Left HPVOL Mux", "Vmid", "Vmid"},
1166 {"Left OUTVOL Mux", "OUTMIXL", "OUTMIXL Mixer"},
1167 {"Left OUTVOL Mux", "Vmid", "Vmid"},
1168 {"Right OUTVOL Mux", "OUTMIXR", "OUTMIXR Mixer"},
1169 {"Right OUTVOL Mux", "Vmid", "Vmid"},
1170 {"Right HPVOL Mux", "OUTMIXR", "OUTMIXR Mixer"},
1171 {"Right HPVOL Mux", "Vmid", "Vmid"},
1172 {"Right SPKVOL Mux", "SPKMIXR", "SPKMIXR Mixer"},
1173 {"Right SPKVOL Mux", "Vmid", "Vmid"},
1174
1175 {"AXO1MIX Mixer", "MIC1_BST1 Playback Switch", "MIC1 Boost"},
1176 {"AXO1MIX Mixer", "OUTVOLL Playback Switch", "Left OUTVOL Mux"},
1177 {"AXO1MIX Mixer", "OUTVOLR Playback Switch", "Right OUTVOL Mux"},
1178 {"AXO1MIX Mixer", "MIC2_BST2 Playback Switch", "MIC2 Boost"},
1179
1180 {"AXO2MIX Mixer", "MIC1_BST1 Playback Switch", "MIC1 Boost"},
1181 {"AXO2MIX Mixer", "OUTVOLL Playback Switch", "Left OUTVOL Mux"},
1182 {"AXO2MIX Mixer", "OUTVOLR Playback Switch", "Right OUTVOL Mux"},
1183 {"AXO2MIX Mixer", "MIC2_BST2 Playback Switch", "MIC2 Boost"},
1184
1185 {"SPOLMIX Mixer", "SPKVOLL Playback Switch", "Left SPKVOL Mux"},
1186 {"SPOLMIX Mixer", "SPKVOLR Playback Switch", "Right SPKVOL Mux"},
1187
1188 {"SPORMIX Mixer", "SPKVOLL Playback Switch", "Left SPKVOL Mux"},
1189 {"SPORMIX Mixer", "SPKVOLR Playback Switch", "Right SPKVOL Mux"},
1190
1191 {"MONOMIX Mixer", "OUTVOLL Playback Switch", "Left OUTVOL Mux"},
1192 {"MONOMIX Mixer", "OUTVOLR Playback Switch", "Right OUTVOL Mux"},
1193
1194 {"SPOL Mux", "SPOLMIX", "SPOLMIX Mixer"},
1195 {"SPOL Mux", "MONOIN_RX", "MONO_IN"},
1196 {"SPOL Mux", "VDAC", "Voice DAC Boost"},
1197 {"SPOL Mux", "DACL", "Left DAC"},
1198
1199 {"SPOR Mux", "SPORMIX", "SPORMIX Mixer"},
1200 {"SPOR Mux", "MONOIN_RX", "MONO_IN"},
1201 {"SPOR Mux", "VDAC", "Voice DAC Boost"},
1202 {"SPOR Mux", "DACR", "Right DAC"},
1203
1204 {"MONO Mux", "MONOMIX", "MONOMIX Mixer"},
1205 {"MONO Mux", "MONOIN_RX", "MONO_IN"},
1206 {"MONO Mux", "VDAC", "Voice DAC Boost"},
1207
1208 {"Right DAC_HP", NULL, "Right DAC"},
1209 {"Left DAC_HP", NULL, "Left DAC"},
1210
1211 {"HPL Mux", "Left HPVOL", "Left HPVOL Mux"},
1212 {"HPL Mux", "Left DAC", "Left DAC_HP"},
1213 {"HPR Mux", "Right HPVOL", "Right HPVOL Mux"},
1214 {"HPR Mux", "Right DAC", "Right DAC_HP"},
1215
1216 {"HP Depop", NULL, "HPL Mux"},
1217 {"HP Depop", NULL, "HPR Mux"},
1218
1219 {"AUXO1", NULL, "AXO1MIX Mixer"},
1220 {"AUXO2", NULL, "AXO2MIX Mixer"},
1221
1222 {"SPOL", NULL, "Class D"},
1223 {"SPOL", NULL, "SPOL Mux"},
1224 {"SPOR", NULL, "Class D"},
1225 {"SPOR", NULL, "SPOR Mux"},
1226
1227 {"HPOL", NULL, "HP Depop"},
1228 {"HPOR", NULL, "HP Depop"},
1229
1230 {"MONO", NULL, "MONO Depop"},
1231 {"MONO", NULL, "MONO Mux"},
1232};
1233
1234struct coeff_clk_div {
1235 u32 mclk;
1236 u32 bclk;
1237 u32 rate;
1238 u16 reg_val;
1239};
1240
1241/* PLL divisors */
1242struct pll_div {
1243 u32 pll_in;
1244 u32 pll_out;
1245 u16 reg_val;
1246};
1247
1248static const struct pll_div codec_master_pll_div[] = {
1249 {2048000, 8192000, 0x0ea0},
1250 {3686400, 8192000, 0x4e27},
1251 {12000000, 8192000, 0x456b},
1252 {13000000, 8192000, 0x495f},
1253 {13100000, 8192000, 0x0320},
1254 {2048000, 11289600, 0xf637},
1255 {3686400, 11289600, 0x2f22},
1256 {12000000, 11289600, 0x3e2f},
1257 {13000000, 11289600, 0x4d5b},
1258 {13100000, 11289600, 0x363b},
1259 {2048000, 16384000, 0x1ea0},
1260 {3686400, 16384000, 0x9e27},
1261 {12000000, 16384000, 0x452b},
1262 {13000000, 16384000, 0x542f},
1263 {13100000, 16384000, 0x03a0},
1264 {2048000, 16934400, 0xe625},
1265 {3686400, 16934400, 0x9126},
1266 {12000000, 16934400, 0x4d2c},
1267 {13000000, 16934400, 0x742f},
1268 {13100000, 16934400, 0x3c27},
1269 {2048000, 22579200, 0x2aa0},
1270 {3686400, 22579200, 0x2f20},
1271 {12000000, 22579200, 0x7e2f},
1272 {13000000, 22579200, 0x742f},
1273 {13100000, 22579200, 0x3c27},
1274 {2048000, 24576000, 0x2ea0},
1275 {3686400, 24576000, 0xee27},
1276 {12000000, 24576000, 0x2915},
1277 {13000000, 24576000, 0x772e},
1278 {13100000, 24576000, 0x0d20},
1279 {26000000, 24576000, 0x2027},
1280 {26000000, 22579200, 0x392f},
1281 {24576000, 22579200, 0x0921},
1282 {24576000, 24576000, 0x02a0},
1283};
1284
1285static const struct pll_div codec_slave_pll_div[] = {
1286 {256000, 2048000, 0x46f0},
1287 {256000, 4096000, 0x3ea0},
1288 {352800, 5644800, 0x3ea0},
1289 {512000, 8192000, 0x3ea0},
1290 {1024000, 8192000, 0x46f0},
1291 {705600, 11289600, 0x3ea0},
1292 {1024000, 16384000, 0x3ea0},
1293 {1411200, 22579200, 0x3ea0},
1294 {1536000, 24576000, 0x3ea0},
1295 {2048000, 16384000, 0x1ea0},
1296 {2822400, 22579200, 0x1ea0},
1297 {2822400, 45158400, 0x5ec0},
1298 {5644800, 45158400, 0x46f0},
1299 {3072000, 24576000, 0x1ea0},
1300 {3072000, 49152000, 0x5ec0},
1301 {6144000, 49152000, 0x46f0},
1302 {705600, 11289600, 0x3ea0},
1303 {705600, 8467200, 0x3ab0},
1304 {24576000, 24576000, 0x02a0},
1305 {1411200, 11289600, 0x1690},
1306 {2822400, 11289600, 0x0a90},
1307 {1536000, 12288000, 0x1690},
1308 {3072000, 12288000, 0x0a90},
1309};
1310
1311struct coeff_clk_div coeff_div[] = {
1312 /* sysclk is 256fs */
1313 {2048000, 8000 * 32, 8000, 0x1000},
1314 {2048000, 8000 * 64, 8000, 0x0000},
1315 {2822400, 11025 * 32, 11025, 0x1000},
1316 {2822400, 11025 * 64, 11025, 0x0000},
1317 {4096000, 16000 * 32, 16000, 0x1000},
1318 {4096000, 16000 * 64, 16000, 0x0000},
1319 {5644800, 22050 * 32, 22050, 0x1000},
1320 {5644800, 22050 * 64, 22050, 0x0000},
1321 {8192000, 32000 * 32, 32000, 0x1000},
1322 {8192000, 32000 * 64, 32000, 0x0000},
1323 {11289600, 44100 * 32, 44100, 0x1000},
1324 {11289600, 44100 * 64, 44100, 0x0000},
1325 {12288000, 48000 * 32, 48000, 0x1000},
1326 {12288000, 48000 * 64, 48000, 0x0000},
1327 {22579200, 88200 * 32, 88200, 0x1000},
1328 {22579200, 88200 * 64, 88200, 0x0000},
1329 {24576000, 96000 * 32, 96000, 0x1000},
1330 {24576000, 96000 * 64, 96000, 0x0000},
1331 /* sysclk is 512fs */
1332 {4096000, 8000 * 32, 8000, 0x3000},
1333 {4096000, 8000 * 64, 8000, 0x2000},
1334 {5644800, 11025 * 32, 11025, 0x3000},
1335 {5644800, 11025 * 64, 11025, 0x2000},
1336 {8192000, 16000 * 32, 16000, 0x3000},
1337 {8192000, 16000 * 64, 16000, 0x2000},
1338 {11289600, 22050 * 32, 22050, 0x3000},
1339 {11289600, 22050 * 64, 22050, 0x2000},
1340 {16384000, 32000 * 32, 32000, 0x3000},
1341 {16384000, 32000 * 64, 32000, 0x2000},
1342 {22579200, 44100 * 32, 44100, 0x3000},
1343 {22579200, 44100 * 64, 44100, 0x2000},
1344 {24576000, 48000 * 32, 48000, 0x3000},
1345 {24576000, 48000 * 64, 48000, 0x2000},
1346 {45158400, 88200 * 32, 88200, 0x3000},
1347 {45158400, 88200 * 64, 88200, 0x2000},
1348 {49152000, 96000 * 32, 96000, 0x3000},
1349 {49152000, 96000 * 64, 96000, 0x2000},
1350 /* sysclk is 24.576Mhz or 22.5792Mhz */
1351 {24576000, 8000 * 32, 8000, 0x7080},
1352 {24576000, 8000 * 64, 8000, 0x6080},
1353 {24576000, 16000 * 32, 16000, 0x5080},
1354 {24576000, 16000 * 64, 16000, 0x4080},
1355 {24576000, 24000 * 32, 24000, 0x5000},
1356 {24576000, 24000 * 64, 24000, 0x4000},
1357 {24576000, 32000 * 32, 32000, 0x3080},
1358 {24576000, 32000 * 64, 32000, 0x2080},
1359 {22579200, 11025 * 32, 11025, 0x7000},
1360 {22579200, 11025 * 64, 11025, 0x6000},
1361 {22579200, 22050 * 32, 22050, 0x5000},
1362 {22579200, 22050 * 64, 22050, 0x4000},
1363};
1364
1365static int get_coeff(int mclk, int rate, int timesofbclk)
1366{
1367 int i;
1368
1369 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
1370 if (coeff_div[i].mclk == mclk && coeff_div[i].rate == rate &&
1371 (coeff_div[i].bclk / coeff_div[i].rate) == timesofbclk)
1372 return i;
1373 }
1374 return -EINVAL;
1375}
1376
1377static int rt5631_hifi_pcm_params(struct snd_pcm_substream *substream,
1378 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1379{
1380 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1381 struct snd_soc_codec *codec = rtd->codec;
1382 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
1383 int timesofbclk = 32, coeff;
1384 unsigned int iface = 0;
1385
1386 dev_dbg(codec->dev, "enter %s\n", __func__);
1387
1388 rt5631->bclk_rate = snd_soc_params_to_bclk(params);
1389 if (rt5631->bclk_rate < 0) {
1390 dev_err(codec->dev, "Fail to get BCLK rate\n");
1391 return rt5631->bclk_rate;
1392 }
1393 rt5631->rx_rate = params_rate(params);
1394
1395 if (rt5631->master)
1396 coeff = get_coeff(rt5631->sysclk, rt5631->rx_rate,
1397 rt5631->bclk_rate / rt5631->rx_rate);
1398 else
1399 coeff = get_coeff(rt5631->sysclk, rt5631->rx_rate,
1400 timesofbclk);
1401 if (coeff < 0) {
1402 dev_err(codec->dev, "Fail to get coeff\n");
1403 return -EINVAL;
1404 }
1405
1406 switch (params_format(params)) {
1407 case SNDRV_PCM_FORMAT_S16_LE:
1408 break;
1409 case SNDRV_PCM_FORMAT_S20_3LE:
1410 iface |= RT5631_SDP_I2S_DL_20;
1411 break;
1412 case SNDRV_PCM_FORMAT_S24_LE:
1413 iface |= RT5631_SDP_I2S_DL_24;
1414 break;
1415 case SNDRV_PCM_FORMAT_S8:
1416 iface |= RT5631_SDP_I2S_DL_8;
1417 break;
1418 default:
1419 return -EINVAL;
1420 }
1421
1422 snd_soc_update_bits(codec, RT5631_SDP_CTRL,
1423 RT5631_SDP_I2S_DL_MASK, iface);
1424 snd_soc_write(codec, RT5631_STEREO_AD_DA_CLK_CTRL,
1425 coeff_div[coeff].reg_val);
1426
1427 return 0;
1428}
1429
1430static int rt5631_hifi_codec_set_dai_fmt(struct snd_soc_dai *codec_dai,
1431 unsigned int fmt)
1432{
1433 struct snd_soc_codec *codec = codec_dai->codec;
1434 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
1435 unsigned int iface = 0;
1436
1437 dev_dbg(codec->dev, "enter %s\n", __func__);
1438
1439 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1440 case SND_SOC_DAIFMT_CBM_CFM:
1441 rt5631->master = 1;
1442 break;
1443 case SND_SOC_DAIFMT_CBS_CFS:
1444 iface |= RT5631_SDP_MODE_SEL_SLAVE;
1445 rt5631->master = 0;
1446 break;
1447 default:
1448 return -EINVAL;
1449 }
1450
1451 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1452 case SND_SOC_DAIFMT_I2S:
1453 break;
1454 case SND_SOC_DAIFMT_LEFT_J:
1455 iface |= RT5631_SDP_I2S_DF_LEFT;
1456 break;
1457 case SND_SOC_DAIFMT_DSP_A:
1458 iface |= RT5631_SDP_I2S_DF_PCM_A;
1459 break;
1460 case SND_SOC_DAIFMT_DSP_B:
1461 iface |= RT5631_SDP_I2S_DF_PCM_B;
1462 break;
1463 default:
1464 return -EINVAL;
1465 }
1466
1467 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1468 case SND_SOC_DAIFMT_NB_NF:
1469 break;
1470 case SND_SOC_DAIFMT_IB_NF:
1471 iface |= RT5631_SDP_I2S_BCLK_POL_CTRL;
1472 break;
1473 default:
1474 return -EINVAL;
1475 }
1476
1477 snd_soc_write(codec, RT5631_SDP_CTRL, iface);
1478
1479 return 0;
1480}
1481
1482static int rt5631_hifi_codec_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1483 int clk_id, unsigned int freq, int dir)
1484{
1485 struct snd_soc_codec *codec = codec_dai->codec;
1486 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
1487
1488 dev_dbg(codec->dev, "enter %s, syclk=%d\n", __func__, freq);
1489
1490 if ((freq >= (256 * 8000)) && (freq <= (512 * 96000))) {
1491 rt5631->sysclk = freq;
1492 return 0;
1493 }
1494
1495 return -EINVAL;
1496}
1497
1498static int rt5631_codec_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1499 int source, unsigned int freq_in, unsigned int freq_out)
1500{
1501 struct snd_soc_codec *codec = codec_dai->codec;
1502 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
1503 int i, ret = -EINVAL;
1504
1505 dev_dbg(codec->dev, "enter %s\n", __func__);
1506
1507 if (!freq_in || !freq_out) {
1508 dev_dbg(codec->dev, "PLL disabled\n");
1509
1510 snd_soc_update_bits(codec, RT5631_GLOBAL_CLK_CTRL,
1511 RT5631_SYSCLK_SOUR_SEL_MASK,
1512 RT5631_SYSCLK_SOUR_SEL_MCLK);
1513
1514 return 0;
1515 }
1516
1517 if (rt5631->master) {
1518 for (i = 0; i < ARRAY_SIZE(codec_master_pll_div); i++)
1519 if (freq_in == codec_master_pll_div[i].pll_in &&
1520 freq_out == codec_master_pll_div[i].pll_out) {
1521 dev_info(codec->dev,
1522 "change PLL in master mode\n");
1523 snd_soc_write(codec, RT5631_PLL_CTRL,
1524 codec_master_pll_div[i].reg_val);
1525 schedule_timeout_uninterruptible(
1526 msecs_to_jiffies(20));
1527 snd_soc_update_bits(codec,
1528 RT5631_GLOBAL_CLK_CTRL,
1529 RT5631_SYSCLK_SOUR_SEL_MASK |
1530 RT5631_PLLCLK_SOUR_SEL_MASK,
1531 RT5631_SYSCLK_SOUR_SEL_PLL |
1532 RT5631_PLLCLK_SOUR_SEL_MCLK);
1533 ret = 0;
1534 break;
1535 }
1536 } else {
1537 for (i = 0; i < ARRAY_SIZE(codec_slave_pll_div); i++)
1538 if (freq_in == codec_slave_pll_div[i].pll_in &&
1539 freq_out == codec_slave_pll_div[i].pll_out) {
1540 dev_info(codec->dev,
1541 "change PLL in slave mode\n");
1542 snd_soc_write(codec, RT5631_PLL_CTRL,
1543 codec_slave_pll_div[i].reg_val);
1544 schedule_timeout_uninterruptible(
1545 msecs_to_jiffies(20));
1546 snd_soc_update_bits(codec,
1547 RT5631_GLOBAL_CLK_CTRL,
1548 RT5631_SYSCLK_SOUR_SEL_MASK |
1549 RT5631_PLLCLK_SOUR_SEL_MASK,
1550 RT5631_SYSCLK_SOUR_SEL_PLL |
1551 RT5631_PLLCLK_SOUR_SEL_BCLK);
1552 ret = 0;
1553 break;
1554 }
1555 }
1556
1557 return ret;
1558}
1559
1560static int rt5631_set_bias_level(struct snd_soc_codec *codec,
1561 enum snd_soc_bias_level level)
1562{
1563 switch (level) {
1564 case SND_SOC_BIAS_ON:
1565 case SND_SOC_BIAS_PREPARE:
1566 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD2,
1567 RT5631_PWR_MICBIAS1_VOL | RT5631_PWR_MICBIAS2_VOL,
1568 RT5631_PWR_MICBIAS1_VOL | RT5631_PWR_MICBIAS2_VOL);
1569 break;
1570
1571 case SND_SOC_BIAS_STANDBY:
1572 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1573 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
1574 RT5631_PWR_VREF | RT5631_PWR_MAIN_BIAS,
1575 RT5631_PWR_VREF | RT5631_PWR_MAIN_BIAS);
1576 msleep(80);
1577 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
1578 RT5631_PWR_FAST_VREF_CTRL,
1579 RT5631_PWR_FAST_VREF_CTRL);
1580 codec->cache_only = false;
1581 snd_soc_cache_sync(codec);
1582 }
1583 break;
1584
1585 case SND_SOC_BIAS_OFF:
1586 snd_soc_write(codec, RT5631_PWR_MANAG_ADD1, 0x0000);
1587 snd_soc_write(codec, RT5631_PWR_MANAG_ADD2, 0x0000);
1588 snd_soc_write(codec, RT5631_PWR_MANAG_ADD3, 0x0000);
1589 snd_soc_write(codec, RT5631_PWR_MANAG_ADD4, 0x0000);
1590 break;
1591
1592 default:
1593 break;
1594 }
1595 codec->dapm.bias_level = level;
1596
1597 return 0;
1598}
1599
1600static int rt5631_probe(struct snd_soc_codec *codec)
1601{
1602 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
1603 unsigned int val;
1604 int ret;
1605
1606 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1607 if (ret != 0) {
1608 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1609 return ret;
1610 }
1611
1612 val = rt5631_read_index(codec, RT5631_ADDA_MIXER_INTL_REG3);
1613 if (val & 0x0002)
1614 rt5631->codec_version = 1;
1615 else
1616 rt5631->codec_version = 0;
1617
1618 rt5631_reset(codec);
1619 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
1620 RT5631_PWR_VREF | RT5631_PWR_MAIN_BIAS,
1621 RT5631_PWR_VREF | RT5631_PWR_MAIN_BIAS);
1622 msleep(80);
1623 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
1624 RT5631_PWR_FAST_VREF_CTRL, RT5631_PWR_FAST_VREF_CTRL);
1625 /* enable HP zero cross */
1626 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, 0x0f18);
1627 /* power off ClassD auto Recovery */
1628 if (rt5631->codec_version)
1629 snd_soc_update_bits(codec, RT5631_INT_ST_IRQ_CTRL_2,
1630 0x2000, 0x2000);
1631 else
1632 snd_soc_update_bits(codec, RT5631_INT_ST_IRQ_CTRL_2,
1633 0x2000, 0);
1634 /* DMIC */
1635 if (rt5631->dmic_used_flag) {
1636 snd_soc_update_bits(codec, RT5631_GPIO_CTRL,
1637 RT5631_GPIO_PIN_FUN_SEL_MASK |
1638 RT5631_GPIO_DMIC_FUN_SEL_MASK,
1639 RT5631_GPIO_PIN_FUN_SEL_GPIO_DIMC |
1640 RT5631_GPIO_DMIC_FUN_SEL_DIMC);
1641 snd_soc_update_bits(codec, RT5631_DIG_MIC_CTRL,
1642 RT5631_DMIC_L_CH_LATCH_MASK |
1643 RT5631_DMIC_R_CH_LATCH_MASK,
1644 RT5631_DMIC_L_CH_LATCH_FALLING |
1645 RT5631_DMIC_R_CH_LATCH_RISING);
1646 }
1647
1648 codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
1649 rt5631->codec = codec;
1650
1651 return 0;
1652}
1653
1654static int rt5631_remove(struct snd_soc_codec *codec)
1655{
1656 rt5631_set_bias_level(codec, SND_SOC_BIAS_OFF);
1657 return 0;
1658}
1659
1660#ifdef CONFIG_PM
1661static int rt5631_suspend(struct snd_soc_codec *codec, pm_message_t state)
1662{
1663 rt5631_set_bias_level(codec, SND_SOC_BIAS_OFF);
1664 return 0;
1665}
1666
1667static int rt5631_resume(struct snd_soc_codec *codec)
1668{
1669 rt5631_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1670 return 0;
1671}
1672#else
1673#define rt5631_suspend NULL
1674#define rt5631_resume NULL
1675#endif
1676
1677#define RT5631_STEREO_RATES SNDRV_PCM_RATE_8000_96000
1678#define RT5631_FORMAT (SNDRV_PCM_FMTBIT_S16_LE | \
1679 SNDRV_PCM_FMTBIT_S20_3LE | \
1680 SNDRV_PCM_FMTBIT_S24_LE | \
1681 SNDRV_PCM_FMTBIT_S8)
1682
1683struct snd_soc_dai_ops rt5631_ops = {
1684 .hw_params = rt5631_hifi_pcm_params,
1685 .set_fmt = rt5631_hifi_codec_set_dai_fmt,
1686 .set_sysclk = rt5631_hifi_codec_set_dai_sysclk,
1687 .set_pll = rt5631_codec_set_dai_pll,
1688};
1689
1690struct snd_soc_dai_driver rt5631_dai[] = {
1691 {
1692 .name = "rt5631-hifi",
1693 .id = 1,
1694 .playback = {
1695 .stream_name = "HIFI Playback",
1696 .channels_min = 1,
1697 .channels_max = 2,
1698 .rates = RT5631_STEREO_RATES,
1699 .formats = RT5631_FORMAT,
1700 },
1701 .capture = {
1702 .stream_name = "HIFI Capture",
1703 .channels_min = 1,
1704 .channels_max = 2,
1705 .rates = RT5631_STEREO_RATES,
1706 .formats = RT5631_FORMAT,
1707 },
1708 .ops = &rt5631_ops,
1709 },
1710};
1711
1712static struct snd_soc_codec_driver soc_codec_dev_rt5631 = {
1713 .probe = rt5631_probe,
1714 .remove = rt5631_remove,
1715 .suspend = rt5631_suspend,
1716 .resume = rt5631_resume,
1717 .set_bias_level = rt5631_set_bias_level,
1718 .reg_cache_size = RT5631_VENDOR_ID2 + 1,
1719 .reg_word_size = sizeof(u16),
1720 .reg_cache_default = rt5631_reg,
1721 .volatile_register = rt5631_volatile_register,
1722 .readable_register = rt5631_readable_register,
1723 .reg_cache_step = 1,
1724 .controls = rt5631_snd_controls,
1725 .num_controls = ARRAY_SIZE(rt5631_snd_controls),
1726 .dapm_widgets = rt5631_dapm_widgets,
1727 .num_dapm_widgets = ARRAY_SIZE(rt5631_dapm_widgets),
1728 .dapm_routes = rt5631_dapm_routes,
1729 .num_dapm_routes = ARRAY_SIZE(rt5631_dapm_routes),
1730};
1731
1732static const struct i2c_device_id rt5631_i2c_id[] = {
1733 { "rt5631", 0 },
1734 { }
1735};
1736MODULE_DEVICE_TABLE(i2c, rt5631_i2c_id);
1737
1738static int rt5631_i2c_probe(struct i2c_client *i2c,
1739 const struct i2c_device_id *id)
1740{
1741 struct rt5631_priv *rt5631;
1742 int ret;
1743
1744 rt5631 = kzalloc(sizeof(struct rt5631_priv), GFP_KERNEL);
1745 if (NULL == rt5631)
1746 return -ENOMEM;
1747
1748 i2c_set_clientdata(i2c, rt5631);
1749
1750 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5631,
1751 rt5631_dai, ARRAY_SIZE(rt5631_dai));
1752 if (ret < 0)
1753 kfree(rt5631);
1754
1755 return ret;
1756}
1757
1758static __devexit int rt5631_i2c_remove(struct i2c_client *client)
1759{
1760 snd_soc_unregister_codec(&client->dev);
1761 kfree(i2c_get_clientdata(client));
1762 return 0;
1763}
1764
1765struct i2c_driver rt5631_i2c_driver = {
1766 .driver = {
1767 .name = "rt5631",
1768 .owner = THIS_MODULE,
1769 },
1770 .probe = rt5631_i2c_probe,
1771 .remove = __devexit_p(rt5631_i2c_remove),
1772 .id_table = rt5631_i2c_id,
1773};
1774
1775static int __init rt5631_modinit(void)
1776{
1777 return i2c_add_driver(&rt5631_i2c_driver);
1778}
1779module_init(rt5631_modinit);
1780
1781static void __exit rt5631_modexit(void)
1782{
1783 i2c_del_driver(&rt5631_i2c_driver);
1784}
1785module_exit(rt5631_modexit);
1786
1787MODULE_DESCRIPTION("ASoC RT5631 driver");
1788MODULE_AUTHOR("flove <flove@realtek.com>");
1789MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/rt5631.h b/sound/soc/codecs/rt5631.h
new file mode 100644
index 000000000000..13401581b0df
--- /dev/null
+++ b/sound/soc/codecs/rt5631.h
@@ -0,0 +1,701 @@
1#ifndef __RTCODEC5631_H__
2#define __RTCODEC5631_H__
3
4
5#define RT5631_RESET 0x00
6#define RT5631_SPK_OUT_VOL 0x02
7#define RT5631_HP_OUT_VOL 0x04
8#define RT5631_MONO_AXO_1_2_VOL 0x06
9#define RT5631_AUX_IN_VOL 0x0A
10#define RT5631_STEREO_DAC_VOL_1 0x0C
11#define RT5631_MIC_CTRL_1 0x0E
12#define RT5631_STEREO_DAC_VOL_2 0x10
13#define RT5631_ADC_CTRL_1 0x12
14#define RT5631_ADC_REC_MIXER 0x14
15#define RT5631_ADC_CTRL_2 0x16
16#define RT5631_VDAC_DIG_VOL 0x18
17#define RT5631_OUTMIXER_L_CTRL 0x1A
18#define RT5631_OUTMIXER_R_CTRL 0x1C
19#define RT5631_AXO1MIXER_CTRL 0x1E
20#define RT5631_AXO2MIXER_CTRL 0x20
21#define RT5631_MIC_CTRL_2 0x22
22#define RT5631_DIG_MIC_CTRL 0x24
23#define RT5631_MONO_INPUT_VOL 0x26
24#define RT5631_SPK_MIXER_CTRL 0x28
25#define RT5631_SPK_MONO_OUT_CTRL 0x2A
26#define RT5631_SPK_MONO_HP_OUT_CTRL 0x2C
27#define RT5631_SDP_CTRL 0x34
28#define RT5631_MONO_SDP_CTRL 0x36
29#define RT5631_STEREO_AD_DA_CLK_CTRL 0x38
30#define RT5631_PWR_MANAG_ADD1 0x3A
31#define RT5631_PWR_MANAG_ADD2 0x3B
32#define RT5631_PWR_MANAG_ADD3 0x3C
33#define RT5631_PWR_MANAG_ADD4 0x3E
34#define RT5631_GEN_PUR_CTRL_REG 0x40
35#define RT5631_GLOBAL_CLK_CTRL 0x42
36#define RT5631_PLL_CTRL 0x44
37#define RT5631_INT_ST_IRQ_CTRL_1 0x48
38#define RT5631_INT_ST_IRQ_CTRL_2 0x4A
39#define RT5631_GPIO_CTRL 0x4C
40#define RT5631_MISC_CTRL 0x52
41#define RT5631_DEPOP_FUN_CTRL_1 0x54
42#define RT5631_DEPOP_FUN_CTRL_2 0x56
43#define RT5631_JACK_DET_CTRL 0x5A
44#define RT5631_SOFT_VOL_CTRL 0x5C
45#define RT5631_ALC_CTRL_1 0x64
46#define RT5631_ALC_CTRL_2 0x65
47#define RT5631_ALC_CTRL_3 0x66
48#define RT5631_PSEUDO_SPATL_CTRL 0x68
49#define RT5631_INDEX_ADD 0x6A
50#define RT5631_INDEX_DATA 0x6C
51#define RT5631_EQ_CTRL 0x6E
52#define RT5631_VENDOR_ID 0x7A
53#define RT5631_VENDOR_ID1 0x7C
54#define RT5631_VENDOR_ID2 0x7E
55
56/* Index of Codec Private Register definition */
57#define RT5631_EQ_BW_LOP 0x00
58#define RT5631_EQ_GAIN_LOP 0x01
59#define RT5631_EQ_FC_BP1 0x02
60#define RT5631_EQ_BW_BP1 0x03
61#define RT5631_EQ_GAIN_BP1 0x04
62#define RT5631_EQ_FC_BP2 0x05
63#define RT5631_EQ_BW_BP2 0x06
64#define RT5631_EQ_GAIN_BP2 0x07
65#define RT5631_EQ_FC_BP3 0x08
66#define RT5631_EQ_BW_BP3 0x09
67#define RT5631_EQ_GAIN_BP3 0x0a
68#define RT5631_EQ_BW_HIP 0x0b
69#define RT5631_EQ_GAIN_HIP 0x0c
70#define RT5631_EQ_HPF_A1 0x0d
71#define RT5631_EQ_HPF_A2 0x0e
72#define RT5631_EQ_HPF_GAIN 0x0f
73#define RT5631_EQ_PRE_VOL_CTRL 0x11
74#define RT5631_EQ_POST_VOL_CTRL 0x12
75#define RT5631_TEST_MODE_CTRL 0x39
76#define RT5631_CP_INTL_REG2 0x45
77#define RT5631_ADDA_MIXER_INTL_REG3 0x52
78#define RT5631_SPK_INTL_CTRL 0x56
79
80
81/* global definition */
82#define RT5631_L_MUTE (0x1 << 15)
83#define RT5631_L_MUTE_SHIFT 15
84#define RT5631_L_EN (0x1 << 14)
85#define RT5631_L_EN_SHIFT 14
86#define RT5631_R_MUTE (0x1 << 7)
87#define RT5631_R_MUTE_SHIFT 7
88#define RT5631_R_EN (0x1 << 6)
89#define RT5631_R_EN_SHIFT 6
90#define RT5631_VOL_MASK 0x1f
91#define RT5631_L_VOL_SHIFT 8
92#define RT5631_R_VOL_SHIFT 0
93
94/* Speaker Output Control(0x02) */
95#define RT5631_SPK_L_VOL_SEL_MASK (0x1 << 14)
96#define RT5631_SPK_L_VOL_SEL_VMID (0x0 << 14)
97#define RT5631_SPK_L_VOL_SEL_SPKMIX_L (0x1 << 14)
98#define RT5631_SPK_R_VOL_SEL_MASK (0x1 << 6)
99#define RT5631_SPK_R_VOL_SEL_VMID (0x0 << 6)
100#define RT5631_SPK_R_VOL_SEL_SPKMIX_R (0x1 << 6)
101
102/* Headphone Output Control(0x04) */
103#define RT5631_HP_L_VOL_SEL_MASK (0x1 << 14)
104#define RT5631_HP_L_VOL_SEL_VMID (0x0 << 14)
105#define RT5631_HP_L_VOL_SEL_OUTMIX_L (0x1 << 14)
106#define RT5631_HP_R_VOL_SEL_MASK (0x1 << 6)
107#define RT5631_HP_R_VOL_SEL_VMID (0x0 << 6)
108#define RT5631_HP_R_VOL_SEL_OUTMIX_R (0x1 << 6)
109
110/* Output Control for AUXOUT/MONO(0x06) */
111#define RT5631_AUXOUT_1_VOL_SEL_MASK (0x1 << 14)
112#define RT5631_AUXOUT_1_VOL_SEL_VMID (0x0 << 14)
113#define RT5631_AUXOUT_1_VOL_SEL_OUTMIX_L (0x1 << 14)
114#define RT5631_MUTE_MONO (0x1 << 13)
115#define RT5631_MUTE_MONO_SHIFT 13
116#define RT5631_AUXOUT_2_VOL_SEL_MASK (0x1 << 6)
117#define RT5631_AUXOUT_2_VOL_SEL_VMID (0x0 << 6)
118#define RT5631_AUXOUT_2_VOL_SEL_OUTMIX_R (0x1 << 6)
119
120/* Microphone Input Control 1(0x0E) */
121#define RT5631_MIC1_DIFF_INPUT_CTRL (0x1 << 15)
122#define RT5631_MIC1_DIFF_INPUT_SHIFT 15
123#define RT5631_MIC2_DIFF_INPUT_CTRL (0x1 << 7)
124#define RT5631_MIC2_DIFF_INPUT_SHIFT 7
125
126/* Stereo DAC Digital Volume2(0x10) */
127#define RT5631_DAC_VOL_MASK 0xff
128
129/* ADC Recording Mixer Control(0x14) */
130#define RT5631_M_OUTMIXER_L_TO_RECMIXER_L (0x1 << 15)
131#define RT5631_M_OUTMIXL_RECMIXL_BIT 15
132#define RT5631_M_MIC1_TO_RECMIXER_L (0x1 << 14)
133#define RT5631_M_MIC1_RECMIXL_BIT 14
134#define RT5631_M_AXIL_TO_RECMIXER_L (0x1 << 13)
135#define RT5631_M_AXIL_RECMIXL_BIT 13
136#define RT5631_M_MONO_IN_TO_RECMIXER_L (0x1 << 12)
137#define RT5631_M_MONO_IN_RECMIXL_BIT 12
138#define RT5631_M_OUTMIXER_R_TO_RECMIXER_R (0x1 << 7)
139#define RT5631_M_OUTMIXR_RECMIXR_BIT 7
140#define RT5631_M_MIC2_TO_RECMIXER_R (0x1 << 6)
141#define RT5631_M_MIC2_RECMIXR_BIT 6
142#define RT5631_M_AXIR_TO_RECMIXER_R (0x1 << 5)
143#define RT5631_M_AXIR_RECMIXR_BIT 5
144#define RT5631_M_MONO_IN_TO_RECMIXER_R (0x1 << 4)
145#define RT5631_M_MONO_IN_RECMIXR_BIT 4
146
147/* Left Output Mixer Control(0x1A) */
148#define RT5631_M_RECMIXER_L_TO_OUTMIXER_L (0x1 << 15)
149#define RT5631_M_RECMIXL_OUTMIXL_BIT 15
150#define RT5631_M_RECMIXER_R_TO_OUTMIXER_L (0x1 << 14)
151#define RT5631_M_RECMIXR_OUTMIXL_BIT 14
152#define RT5631_M_DAC_L_TO_OUTMIXER_L (0x1 << 13)
153#define RT5631_M_DACL_OUTMIXL_BIT 13
154#define RT5631_M_MIC1_TO_OUTMIXER_L (0x1 << 12)
155#define RT5631_M_MIC1_OUTMIXL_BIT 12
156#define RT5631_M_MIC2_TO_OUTMIXER_L (0x1 << 11)
157#define RT5631_M_MIC2_OUTMIXL_BIT 11
158#define RT5631_M_MONO_IN_P_TO_OUTMIXER_L (0x1 << 10)
159#define RT5631_M_MONO_INP_OUTMIXL_BIT 10
160#define RT5631_M_AXIL_TO_OUTMIXER_L (0x1 << 9)
161#define RT5631_M_AXIL_OUTMIXL_BIT 9
162#define RT5631_M_AXIR_TO_OUTMIXER_L (0x1 << 8)
163#define RT5631_M_AXIR_OUTMIXL_BIT 8
164#define RT5631_M_VDAC_TO_OUTMIXER_L (0x1 << 7)
165#define RT5631_M_VDAC_OUTMIXL_BIT 7
166
167/* Right Output Mixer Control(0x1C) */
168#define RT5631_M_RECMIXER_L_TO_OUTMIXER_R (0x1 << 15)
169#define RT5631_M_RECMIXL_OUTMIXR_BIT 15
170#define RT5631_M_RECMIXER_R_TO_OUTMIXER_R (0x1 << 14)
171#define RT5631_M_RECMIXR_OUTMIXR_BIT 14
172#define RT5631_M_DAC_R_TO_OUTMIXER_R (0x1 << 13)
173#define RT5631_M_DACR_OUTMIXR_BIT 13
174#define RT5631_M_MIC1_TO_OUTMIXER_R (0x1 << 12)
175#define RT5631_M_MIC1_OUTMIXR_BIT 12
176#define RT5631_M_MIC2_TO_OUTMIXER_R (0x1 << 11)
177#define RT5631_M_MIC2_OUTMIXR_BIT 11
178#define RT5631_M_MONO_IN_N_TO_OUTMIXER_R (0x1 << 10)
179#define RT5631_M_MONO_INN_OUTMIXR_BIT 10
180#define RT5631_M_AXIL_TO_OUTMIXER_R (0x1 << 9)
181#define RT5631_M_AXIL_OUTMIXR_BIT 9
182#define RT5631_M_AXIR_TO_OUTMIXER_R (0x1 << 8)
183#define RT5631_M_AXIR_OUTMIXR_BIT 8
184#define RT5631_M_VDAC_TO_OUTMIXER_R (0x1 << 7)
185#define RT5631_M_VDAC_OUTMIXR_BIT 7
186
187/* Lout Mixer Control(0x1E) */
188#define RT5631_M_MIC1_TO_AXO1MIXER (0x1 << 15)
189#define RT5631_M_MIC1_AXO1MIX_BIT 15
190#define RT5631_M_MIC2_TO_AXO1MIXER (0x1 << 11)
191#define RT5631_M_MIC2_AXO1MIX_BIT 11
192#define RT5631_M_OUTMIXER_L_TO_AXO1MIXER (0x1 << 7)
193#define RT5631_M_OUTMIXL_AXO1MIX_BIT 7
194#define RT5631_M_OUTMIXER_R_TO_AXO1MIXER (0x1 << 6)
195#define RT5631_M_OUTMIXR_AXO1MIX_BIT 6
196
197/* Rout Mixer Control(0x20) */
198#define RT5631_M_MIC1_TO_AXO2MIXER (0x1 << 15)
199#define RT5631_M_MIC1_AXO2MIX_BIT 15
200#define RT5631_M_MIC2_TO_AXO2MIXER (0x1 << 11)
201#define RT5631_M_MIC2_AXO2MIX_BIT 11
202#define RT5631_M_OUTMIXER_L_TO_AXO2MIXER (0x1 << 7)
203#define RT5631_M_OUTMIXL_AXO2MIX_BIT 7
204#define RT5631_M_OUTMIXER_R_TO_AXO2MIXER (0x1 << 6)
205#define RT5631_M_OUTMIXR_AXO2MIX_BIT 6
206
207/* Micphone Input Control 2(0x22) */
208#define RT5631_MIC_BIAS_90_PRECNET_AVDD 1
209#define RT5631_MIC_BIAS_75_PRECNET_AVDD 2
210
211#define RT5631_MIC1_BOOST_CTRL_MASK (0xf << 12)
212#define RT5631_MIC1_BOOST_CTRL_BYPASS (0x0 << 12)
213#define RT5631_MIC1_BOOST_CTRL_20DB (0x1 << 12)
214#define RT5631_MIC1_BOOST_CTRL_24DB (0x2 << 12)
215#define RT5631_MIC1_BOOST_CTRL_30DB (0x3 << 12)
216#define RT5631_MIC1_BOOST_CTRL_35DB (0x4 << 12)
217#define RT5631_MIC1_BOOST_CTRL_40DB (0x5 << 12)
218#define RT5631_MIC1_BOOST_CTRL_34DB (0x6 << 12)
219#define RT5631_MIC1_BOOST_CTRL_50DB (0x7 << 12)
220#define RT5631_MIC1_BOOST_CTRL_52DB (0x8 << 12)
221#define RT5631_MIC1_BOOST_SHIFT 12
222
223#define RT5631_MIC2_BOOST_CTRL_MASK (0xf << 8)
224#define RT5631_MIC2_BOOST_CTRL_BYPASS (0x0 << 8)
225#define RT5631_MIC2_BOOST_CTRL_20DB (0x1 << 8)
226#define RT5631_MIC2_BOOST_CTRL_24DB (0x2 << 8)
227#define RT5631_MIC2_BOOST_CTRL_30DB (0x3 << 8)
228#define RT5631_MIC2_BOOST_CTRL_35DB (0x4 << 8)
229#define RT5631_MIC2_BOOST_CTRL_40DB (0x5 << 8)
230#define RT5631_MIC2_BOOST_CTRL_34DB (0x6 << 8)
231#define RT5631_MIC2_BOOST_CTRL_50DB (0x7 << 8)
232#define RT5631_MIC2_BOOST_CTRL_52DB (0x8 << 8)
233#define RT5631_MIC2_BOOST_SHIFT 8
234
235#define RT5631_MICBIAS1_VOLT_CTRL_MASK (0x1 << 7)
236#define RT5631_MICBIAS1_VOLT_CTRL_90P (0x0 << 7)
237#define RT5631_MICBIAS1_VOLT_CTRL_75P (0x1 << 7)
238
239#define RT5631_MICBIAS1_S_C_DET_MASK (0x1 << 6)
240#define RT5631_MICBIAS1_S_C_DET_DIS (0x0 << 6)
241#define RT5631_MICBIAS1_S_C_DET_ENA (0x1 << 6)
242
243#define RT5631_MICBIAS1_SHORT_CURR_DET_MASK (0x3 << 4)
244#define RT5631_MICBIAS1_SHORT_CURR_DET_600UA (0x0 << 4)
245#define RT5631_MICBIAS1_SHORT_CURR_DET_1500UA (0x1 << 4)
246#define RT5631_MICBIAS1_SHORT_CURR_DET_2000UA (0x2 << 4)
247
248#define RT5631_MICBIAS2_VOLT_CTRL_MASK (0x1 << 3)
249#define RT5631_MICBIAS2_VOLT_CTRL_90P (0x0 << 3)
250#define RT5631_MICBIAS2_VOLT_CTRL_75P (0x1 << 3)
251
252#define RT5631_MICBIAS2_S_C_DET_MASK (0x1 << 2)
253#define RT5631_MICBIAS2_S_C_DET_DIS (0x0 << 2)
254#define RT5631_MICBIAS2_S_C_DET_ENA (0x1 << 2)
255
256#define RT5631_MICBIAS2_SHORT_CURR_DET_MASK (0x3)
257#define RT5631_MICBIAS2_SHORT_CURR_DET_600UA (0x0)
258#define RT5631_MICBIAS2_SHORT_CURR_DET_1500UA (0x1)
259#define RT5631_MICBIAS2_SHORT_CURR_DET_2000UA (0x2)
260
261
262/* Digital Microphone Control(0x24) */
263#define RT5631_DMIC_ENA_MASK (0x1 << 15)
264#define RT5631_DMIC_ENA_SHIFT 15
265/* DMIC_ENA: DMIC to ADC Digital filter */
266#define RT5631_DMIC_ENA (0x1 << 15)
267/* DMIC_DIS: ADC mixer to ADC Digital filter */
268#define RT5631_DMIC_DIS (0x0 << 15)
269#define RT5631_DMIC_L_CH_MUTE (0x1 << 13)
270#define RT5631_DMIC_L_CH_MUTE_SHIFT 13
271#define RT5631_DMIC_R_CH_MUTE (0x1 << 12)
272#define RT5631_DMIC_R_CH_MUTE_SHIFT 12
273#define RT5631_DMIC_L_CH_LATCH_MASK (0x1 << 9)
274#define RT5631_DMIC_L_CH_LATCH_RISING (0x1 << 9)
275#define RT5631_DMIC_L_CH_LATCH_FALLING (0x0 << 9)
276#define RT5631_DMIC_R_CH_LATCH_MASK (0x1 << 8)
277#define RT5631_DMIC_R_CH_LATCH_RISING (0x1 << 8)
278#define RT5631_DMIC_R_CH_LATCH_FALLING (0x0 << 8)
279#define RT5631_DMIC_CLK_CTRL_MASK (0x3 << 4)
280#define RT5631_DMIC_CLK_CTRL_TO_128FS (0x0 << 4)
281#define RT5631_DMIC_CLK_CTRL_TO_64FS (0x1 << 4)
282#define RT5631_DMIC_CLK_CTRL_TO_32FS (0x2 << 4)
283
284/* Microphone Input Volume(0x26) */
285#define RT5631_MONO_DIFF_INPUT_SHIFT 15
286
287/* Speaker Mixer Control(0x28) */
288#define RT5631_M_RECMIXER_L_TO_SPKMIXER_L (0x1 << 15)
289#define RT5631_M_RECMIXL_SPKMIXL_BIT 15
290#define RT5631_M_MIC1_P_TO_SPKMIXER_L (0x1 << 14)
291#define RT5631_M_MIC1P_SPKMIXL_BIT 14
292#define RT5631_M_DAC_L_TO_SPKMIXER_L (0x1 << 13)
293#define RT5631_M_DACL_SPKMIXL_BIT 13
294#define RT5631_M_OUTMIXER_L_TO_SPKMIXER_L (0x1 << 12)
295#define RT5631_M_OUTMIXL_SPKMIXL_BIT 12
296
297#define RT5631_M_RECMIXER_R_TO_SPKMIXER_R (0x1 << 7)
298#define RT5631_M_RECMIXR_SPKMIXR_BIT 7
299#define RT5631_M_MIC2_P_TO_SPKMIXER_R (0x1 << 6)
300#define RT5631_M_MIC2P_SPKMIXR_BIT 6
301#define RT5631_M_DAC_R_TO_SPKMIXER_R (0x1 << 5)
302#define RT5631_M_DACR_SPKMIXR_BIT 5
303#define RT5631_M_OUTMIXER_R_TO_SPKMIXER_R (0x1 << 4)
304#define RT5631_M_OUTMIXR_SPKMIXR_BIT 4
305
306/* Speaker/Mono Output Control(0x2A) */
307#define RT5631_M_SPKVOL_L_TO_SPOL_MIXER (0x1 << 15)
308#define RT5631_M_SPKVOLL_SPOLMIX_BIT 15
309#define RT5631_M_SPKVOL_R_TO_SPOL_MIXER (0x1 << 14)
310#define RT5631_M_SPKVOLR_SPOLMIX_BIT 14
311#define RT5631_M_SPKVOL_L_TO_SPOR_MIXER (0x1 << 13)
312#define RT5631_M_SPKVOLL_SPORMIX_BIT 13
313#define RT5631_M_SPKVOL_R_TO_SPOR_MIXER (0x1 << 12)
314#define RT5631_M_SPKVOLR_SPORMIX_BIT 12
315#define RT5631_M_OUTVOL_L_TO_MONOMIXER (0x1 << 11)
316#define RT5631_M_OUTVOLL_MONOMIX_BIT 11
317#define RT5631_M_OUTVOL_R_TO_MONOMIXER (0x1 << 10)
318#define RT5631_M_OUTVOLR_MONOMIX_BIT 10
319
320/* Speaker/Mono/HP Output Control(0x2C) */
321#define RT5631_SPK_L_MUX_SEL_MASK (0x3 << 14)
322#define RT5631_SPK_L_MUX_SEL_SPKMIXER_L (0x0 << 14)
323#define RT5631_SPK_L_MUX_SEL_MONO_IN (0x1 << 14)
324#define RT5631_SPK_L_MUX_SEL_DAC_L (0x3 << 14)
325#define RT5631_SPK_L_MUX_SEL_SHIFT 14
326
327#define RT5631_SPK_R_MUX_SEL_MASK (0x3 << 10)
328#define RT5631_SPK_R_MUX_SEL_SPKMIXER_R (0x0 << 10)
329#define RT5631_SPK_R_MUX_SEL_MONO_IN (0x1 << 10)
330#define RT5631_SPK_R_MUX_SEL_DAC_R (0x3 << 10)
331#define RT5631_SPK_R_MUX_SEL_SHIFT 10
332
333#define RT5631_MONO_MUX_SEL_MASK (0x3 << 6)
334#define RT5631_MONO_MUX_SEL_MONOMIXER (0x0 << 6)
335#define RT5631_MONO_MUX_SEL_MONO_IN (0x1 << 6)
336#define RT5631_MONO_MUX_SEL_SHIFT 6
337
338#define RT5631_HP_L_MUX_SEL_MASK (0x1 << 3)
339#define RT5631_HP_L_MUX_SEL_HPVOL_L (0x0 << 3)
340#define RT5631_HP_L_MUX_SEL_DAC_L (0x1 << 3)
341#define RT5631_HP_L_MUX_SEL_SHIFT 3
342
343#define RT5631_HP_R_MUX_SEL_MASK (0x1 << 2)
344#define RT5631_HP_R_MUX_SEL_HPVOL_R (0x0 << 2)
345#define RT5631_HP_R_MUX_SEL_DAC_R (0x1 << 2)
346#define RT5631_HP_R_MUX_SEL_SHIFT 2
347
348/* Stereo I2S Serial Data Port Control(0x34) */
349#define RT5631_SDP_MODE_SEL_MASK (0x1 << 15)
350#define RT5631_SDP_MODE_SEL_MASTER (0x0 << 15)
351#define RT5631_SDP_MODE_SEL_SLAVE (0x1 << 15)
352
353#define RT5631_SDP_ADC_CPS_SEL_MASK (0x3 << 10)
354#define RT5631_SDP_ADC_CPS_SEL_OFF (0x0 << 10)
355#define RT5631_SDP_ADC_CPS_SEL_U_LAW (0x1 << 10)
356#define RT5631_SDP_ADC_CPS_SEL_A_LAW (0x2 << 10)
357
358#define RT5631_SDP_DAC_CPS_SEL_MASK (0x3 << 8)
359#define RT5631_SDP_DAC_CPS_SEL_OFF (0x0 << 8)
360#define RT5631_SDP_DAC_CPS_SEL_U_LAW (0x1 << 8)
361#define RT5631_SDP_DAC_CPS_SEL_A_LAW (0x2 << 8)
362/* 0:Normal 1:Invert */
363#define RT5631_SDP_I2S_BCLK_POL_CTRL (0x1 << 7)
364/* 0:Normal 1:Invert */
365#define RT5631_SDP_DAC_R_INV (0x1 << 6)
366/* 0:ADC data appear at left phase of LRCK
367 * 1:ADC data appear at right phase of LRCK
368 */
369#define RT5631_SDP_ADC_DATA_L_R_SWAP (0x1 << 5)
370/* 0:DAC data appear at left phase of LRCK
371 * 1:DAC data appear at right phase of LRCK
372 */
373#define RT5631_SDP_DAC_DATA_L_R_SWAP (0x1 << 4)
374
375/* Data Length Slection */
376#define RT5631_SDP_I2S_DL_MASK (0x3 << 2)
377#define RT5631_SDP_I2S_DL_16 (0x0 << 2)
378#define RT5631_SDP_I2S_DL_20 (0x1 << 2)
379#define RT5631_SDP_I2S_DL_24 (0x2 << 2)
380#define RT5631_SDP_I2S_DL_8 (0x3 << 2)
381
382/* PCM Data Format Selection */
383#define RT5631_SDP_I2S_DF_MASK (0x3)
384#define RT5631_SDP_I2S_DF_I2S (0x0)
385#define RT5631_SDP_I2S_DF_LEFT (0x1)
386#define RT5631_SDP_I2S_DF_PCM_A (0x2)
387#define RT5631_SDP_I2S_DF_PCM_B (0x3)
388
389/* Stereo AD/DA Clock Control(0x38h) */
390#define RT5631_I2S_PRE_DIV_MASK (0x7 << 13)
391#define RT5631_I2S_PRE_DIV_1 (0x0 << 13)
392#define RT5631_I2S_PRE_DIV_2 (0x1 << 13)
393#define RT5631_I2S_PRE_DIV_4 (0x2 << 13)
394#define RT5631_I2S_PRE_DIV_8 (0x3 << 13)
395#define RT5631_I2S_PRE_DIV_16 (0x4 << 13)
396#define RT5631_I2S_PRE_DIV_32 (0x5 << 13)
397/* CLOCK RELATIVE OF BCLK AND LCRK */
398#define RT5631_I2S_LRCK_SEL_N_BCLK_MASK (0x1 << 12)
399#define RT5631_I2S_LRCK_SEL_64_BCLK (0x0 << 12) /* 64FS */
400#define RT5631_I2S_LRCK_SEL_32_BCLK (0x1 << 12) /* 32FS */
401
402#define RT5631_DAC_OSR_SEL_MASK (0x3 << 10)
403#define RT5631_DAC_OSR_SEL_128FS (0x3 << 10)
404#define RT5631_DAC_OSR_SEL_64FS (0x3 << 10)
405#define RT5631_DAC_OSR_SEL_32FS (0x3 << 10)
406#define RT5631_DAC_OSR_SEL_16FS (0x3 << 10)
407
408#define RT5631_ADC_OSR_SEL_MASK (0x3 << 8)
409#define RT5631_ADC_OSR_SEL_128FS (0x3 << 8)
410#define RT5631_ADC_OSR_SEL_64FS (0x3 << 8)
411#define RT5631_ADC_OSR_SEL_32FS (0x3 << 8)
412#define RT5631_ADC_OSR_SEL_16FS (0x3 << 8)
413
414#define RT5631_ADDA_FILTER_CLK_SEL_256FS (0 << 7) /* 256FS */
415#define RT5631_ADDA_FILTER_CLK_SEL_384FS (1 << 7) /* 384FS */
416
417/* Power managment addition 1 (0x3A) */
418#define RT5631_PWR_MAIN_I2S_EN (0x1 << 15)
419#define RT5631_PWR_MAIN_I2S_BIT 15
420#define RT5631_PWR_CLASS_D (0x1 << 12)
421#define RT5631_PWR_CLASS_D_BIT 12
422#define RT5631_PWR_ADC_L_CLK (0x1 << 11)
423#define RT5631_PWR_ADC_L_CLK_BIT 11
424#define RT5631_PWR_ADC_R_CLK (0x1 << 10)
425#define RT5631_PWR_ADC_R_CLK_BIT 10
426#define RT5631_PWR_DAC_L_CLK (0x1 << 9)
427#define RT5631_PWR_DAC_L_CLK_BIT 9
428#define RT5631_PWR_DAC_R_CLK (0x1 << 8)
429#define RT5631_PWR_DAC_R_CLK_BIT 8
430#define RT5631_PWR_DAC_REF (0x1 << 7)
431#define RT5631_PWR_DAC_REF_BIT 7
432#define RT5631_PWR_DAC_L_TO_MIXER (0x1 << 6)
433#define RT5631_PWR_DAC_L_TO_MIXER_BIT 6
434#define RT5631_PWR_DAC_R_TO_MIXER (0x1 << 5)
435#define RT5631_PWR_DAC_R_TO_MIXER_BIT 5
436
437/* Power managment addition 2 (0x3B) */
438#define RT5631_PWR_OUTMIXER_L (0x1 << 15)
439#define RT5631_PWR_OUTMIXER_L_BIT 15
440#define RT5631_PWR_OUTMIXER_R (0x1 << 14)
441#define RT5631_PWR_OUTMIXER_R_BIT 14
442#define RT5631_PWR_SPKMIXER_L (0x1 << 13)
443#define RT5631_PWR_SPKMIXER_L_BIT 13
444#define RT5631_PWR_SPKMIXER_R (0x1 << 12)
445#define RT5631_PWR_SPKMIXER_R_BIT 12
446#define RT5631_PWR_RECMIXER_L (0x1 << 11)
447#define RT5631_PWR_RECMIXER_L_BIT 11
448#define RT5631_PWR_RECMIXER_R (0x1 << 10)
449#define RT5631_PWR_RECMIXER_R_BIT 10
450#define RT5631_PWR_MIC1_BOOT_GAIN (0x1 << 5)
451#define RT5631_PWR_MIC1_BOOT_GAIN_BIT 5
452#define RT5631_PWR_MIC2_BOOT_GAIN (0x1 << 4)
453#define RT5631_PWR_MIC2_BOOT_GAIN_BIT 4
454#define RT5631_PWR_MICBIAS1_VOL (0x1 << 3)
455#define RT5631_PWR_MICBIAS1_VOL_BIT 3
456#define RT5631_PWR_MICBIAS2_VOL (0x1 << 2)
457#define RT5631_PWR_MICBIAS2_VOL_BIT 2
458#define RT5631_PWR_PLL1 (0x1 << 1)
459#define RT5631_PWR_PLL1_BIT 1
460#define RT5631_PWR_PLL2 (0x1 << 0)
461#define RT5631_PWR_PLL2_BIT 0
462
463/* Power managment addition 3(0x3C) */
464#define RT5631_PWR_VREF (0x1 << 15)
465#define RT5631_PWR_VREF_BIT 15
466#define RT5631_PWR_FAST_VREF_CTRL (0x1 << 14)
467#define RT5631_PWR_FAST_VREF_CTRL_BIT 14
468#define RT5631_PWR_MAIN_BIAS (0x1 << 13)
469#define RT5631_PWR_MAIN_BIAS_BIT 13
470#define RT5631_PWR_AXO1MIXER (0x1 << 11)
471#define RT5631_PWR_AXO1MIXER_BIT 11
472#define RT5631_PWR_AXO2MIXER (0x1 << 10)
473#define RT5631_PWR_AXO2MIXER_BIT 10
474#define RT5631_PWR_MONOMIXER (0x1 << 9)
475#define RT5631_PWR_MONOMIXER_BIT 9
476#define RT5631_PWR_MONO_DEPOP_DIS (0x1 << 8)
477#define RT5631_PWR_MONO_DEPOP_DIS_BIT 8
478#define RT5631_PWR_MONO_AMP_EN (0x1 << 7)
479#define RT5631_PWR_MONO_AMP_EN_BIT 7
480#define RT5631_PWR_CHARGE_PUMP (0x1 << 4)
481#define RT5631_PWR_CHARGE_PUMP_BIT 4
482#define RT5631_PWR_HP_L_AMP (0x1 << 3)
483#define RT5631_PWR_HP_L_AMP_BIT 3
484#define RT5631_PWR_HP_R_AMP (0x1 << 2)
485#define RT5631_PWR_HP_R_AMP_BIT 2
486#define RT5631_PWR_HP_DEPOP_DIS (0x1 << 1)
487#define RT5631_PWR_HP_DEPOP_DIS_BIT 1
488#define RT5631_PWR_HP_AMP_DRIVING (0x1 << 0)
489#define RT5631_PWR_HP_AMP_DRIVING_BIT 0
490
491/* Power managment addition 4(0x3E) */
492#define RT5631_PWR_SPK_L_VOL (0x1 << 15)
493#define RT5631_PWR_SPK_L_VOL_BIT 15
494#define RT5631_PWR_SPK_R_VOL (0x1 << 14)
495#define RT5631_PWR_SPK_R_VOL_BIT 14
496#define RT5631_PWR_LOUT_VOL (0x1 << 13)
497#define RT5631_PWR_LOUT_VOL_BIT 13
498#define RT5631_PWR_ROUT_VOL (0x1 << 12)
499#define RT5631_PWR_ROUT_VOL_BIT 12
500#define RT5631_PWR_HP_L_OUT_VOL (0x1 << 11)
501#define RT5631_PWR_HP_L_OUT_VOL_BIT 11
502#define RT5631_PWR_HP_R_OUT_VOL (0x1 << 10)
503#define RT5631_PWR_HP_R_OUT_VOL_BIT 10
504#define RT5631_PWR_AXIL_IN_VOL (0x1 << 9)
505#define RT5631_PWR_AXIL_IN_VOL_BIT 9
506#define RT5631_PWR_AXIR_IN_VOL (0x1 << 8)
507#define RT5631_PWR_AXIR_IN_VOL_BIT 8
508#define RT5631_PWR_MONO_IN_P_VOL (0x1 << 7)
509#define RT5631_PWR_MONO_IN_P_VOL_BIT 7
510#define RT5631_PWR_MONO_IN_N_VOL (0x1 << 6)
511#define RT5631_PWR_MONO_IN_N_VOL_BIT 6
512
513/* General Purpose Control Register(0x40) */
514#define RT5631_SPK_AMP_AUTO_RATIO_EN (0x1 << 15)
515
516#define RT5631_SPK_AMP_RATIO_CTRL_MASK (0x7 << 12)
517#define RT5631_SPK_AMP_RATIO_CTRL_2_34 (0x0 << 12) /* 7.40DB */
518#define RT5631_SPK_AMP_RATIO_CTRL_1_99 (0x1 << 12) /* 5.99DB */
519#define RT5631_SPK_AMP_RATIO_CTRL_1_68 (0x2 << 12) /* 4.50DB */
520#define RT5631_SPK_AMP_RATIO_CTRL_1_56 (0x3 << 12) /* 3.86DB */
521#define RT5631_SPK_AMP_RATIO_CTRL_1_44 (0x4 << 12) /* 3.16DB */
522#define RT5631_SPK_AMP_RATIO_CTRL_1_27 (0x5 << 12) /* 2.10DB */
523#define RT5631_SPK_AMP_RATIO_CTRL_1_09 (0x6 << 12) /* 0.80DB */
524#define RT5631_SPK_AMP_RATIO_CTRL_1_00 (0x7 << 12) /* 0.00DB */
525#define RT5631_SPK_AMP_RATIO_CTRL_SHIFT 12
526
527#define RT5631_STEREO_DAC_HI_PASS_FILT_EN (0x1 << 11)
528#define RT5631_STEREO_ADC_HI_PASS_FILT_EN (0x1 << 10)
529/* Select ADC Wind Filter Clock type */
530#define RT5631_ADC_WIND_FILT_MASK (0x3 << 4)
531#define RT5631_ADC_WIND_FILT_8_16_32K (0x0 << 4) /*8/16/32k*/
532#define RT5631_ADC_WIND_FILT_11_22_44K (0x1 << 4) /*11/22/44k*/
533#define RT5631_ADC_WIND_FILT_12_24_48K (0x2 << 4) /*12/24/48k*/
534#define RT5631_ADC_WIND_FILT_EN (0x1 << 3)
535/* SelectADC Wind Filter Corner Frequency */
536#define RT5631_ADC_WIND_CNR_FREQ_MASK (0x7 << 0)
537#define RT5631_ADC_WIND_CNR_FREQ_82_113_122 (0x0 << 0) /* 82/113/122 Hz */
538#define RT5631_ADC_WIND_CNR_FREQ_102_141_153 (0x1 << 0) /* 102/141/153 Hz */
539#define RT5631_ADC_WIND_CNR_FREQ_131_180_156 (0x2 << 0) /* 131/180/156 Hz */
540#define RT5631_ADC_WIND_CNR_FREQ_163_225_245 (0x3 << 0) /* 163/225/245 Hz */
541#define RT5631_ADC_WIND_CNR_FREQ_204_281_306 (0x4 << 0) /* 204/281/306 Hz */
542#define RT5631_ADC_WIND_CNR_FREQ_261_360_392 (0x5 << 0) /* 261/360/392 Hz */
543#define RT5631_ADC_WIND_CNR_FREQ_327_450_490 (0x6 << 0) /* 327/450/490 Hz */
544#define RT5631_ADC_WIND_CNR_FREQ_408_563_612 (0x7 << 0) /* 408/563/612 Hz */
545
546/* Global Clock Control Register(0x42) */
547#define RT5631_SYSCLK_SOUR_SEL_MASK (0x3 << 14)
548#define RT5631_SYSCLK_SOUR_SEL_MCLK (0x0 << 14)
549#define RT5631_SYSCLK_SOUR_SEL_PLL (0x1 << 14)
550#define RT5631_SYSCLK_SOUR_SEL_PLL_TCK (0x2 << 14)
551
552#define RT5631_PLLCLK_SOUR_SEL_MASK (0x3 << 12)
553#define RT5631_PLLCLK_SOUR_SEL_MCLK (0x0 << 12)
554#define RT5631_PLLCLK_SOUR_SEL_BCLK (0x1 << 12)
555#define RT5631_PLLCLK_SOUR_SEL_VBCLK (0x2 << 12)
556
557#define RT5631_PLLCLK_PRE_DIV1 (0x0 << 11)
558#define RT5631_PLLCLK_PRE_DIV2 (0x1 << 11)
559
560/* PLL Control(0x44) */
561#define RT5631_PLL_CTRL_M_VAL(m) ((m)&0xf)
562#define RT5631_PLL_CTRL_K_VAL(k) (((k)&0x7) << 4)
563#define RT5631_PLL_CTRL_N_VAL(n) (((n)&0xff) << 8)
564
565/* Internal Status and IRQ Control2(0x4A) */
566#define RT5631_ADC_DATA_SEL_MASK (0x3 << 14)
567#define RT5631_ADC_DATA_SEL_Disable (0x0 << 14)
568#define RT5631_ADC_DATA_SEL_MIC1 (0x1 << 14)
569#define RT5631_ADC_DATA_SEL_MIC1_SHIFT 14
570#define RT5631_ADC_DATA_SEL_MIC2 (0x2 << 14)
571#define RT5631_ADC_DATA_SEL_MIC2_SHIFT 15
572#define RT5631_ADC_DATA_SEL_STO (0x3 << 14)
573#define RT5631_ADC_DATA_SEL_SHIFT 14
574
575/* GPIO Pin Configuration(0x4C) */
576#define RT5631_GPIO_PIN_FUN_SEL_MASK (0x1 << 15)
577#define RT5631_GPIO_PIN_FUN_SEL_IRQ (0x1 << 15)
578#define RT5631_GPIO_PIN_FUN_SEL_GPIO_DIMC (0x0 << 15)
579
580#define RT5631_GPIO_DMIC_FUN_SEL_MASK (0x1 << 3)
581#define RT5631_GPIO_DMIC_FUN_SEL_DIMC (0x1 << 3)
582#define RT5631_GPIO_DMIC_FUN_SEL_GPIO (0x0 << 3)
583
584#define RT5631_GPIO_PIN_CON_MASK (0x1 << 2)
585#define RT5631_GPIO_PIN_SET_INPUT (0x0 << 2)
586#define RT5631_GPIO_PIN_SET_OUTPUT (0x1 << 2)
587
588/* De-POP function Control 1(0x54) */
589#define RT5631_POW_ON_SOFT_GEN (0x1 << 15)
590#define RT5631_EN_MUTE_UNMUTE_DEPOP (0x1 << 14)
591#define RT5631_EN_DEPOP2_FOR_HP (0x1 << 7)
592/* Power Down HPAMP_L Starts Up Signal */
593#define RT5631_PD_HPAMP_L_ST_UP (0x1 << 5)
594/* Power Down HPAMP_R Starts Up Signal */
595#define RT5631_PD_HPAMP_R_ST_UP (0x1 << 4)
596/* Enable left HP mute/unmute depop */
597#define RT5631_EN_HP_L_M_UN_MUTE_DEPOP (0x1 << 1)
598/* Enable right HP mute/unmute depop */
599#define RT5631_EN_HP_R_M_UN_MUTE_DEPOP (0x1 << 0)
600
601/* De-POP Fnction Control(0x56) */
602#define RT5631_EN_ONE_BIT_DEPOP (0x1 << 15)
603#define RT5631_EN_CAP_FREE_DEPOP (0x1 << 14)
604
605/* Jack Detect Control Register(0x5A) */
606#define RT5631_JD_USE_MASK (0x3 << 14)
607#define RT5631_JD_USE_JD2 (0x3 << 14)
608#define RT5631_JD_USE_JD1 (0x2 << 14)
609#define RT5631_JD_USE_GPIO (0x1 << 14)
610#define RT5631_JD_OFF (0x0 << 14)
611/* JD trigger enable for HP */
612#define RT5631_JD_HP_EN (0x1 << 11)
613#define RT5631_JD_HP_TRI_MASK (0x1 << 10)
614#define RT5631_JD_HP_TRI_HI (0x1 << 10)
615#define RT5631_JD_HP_TRI_LO (0x1 << 10)
616/* JD trigger enable for speaker LP/LN */
617#define RT5631_JD_SPK_L_EN (0x1 << 9)
618#define RT5631_JD_SPK_L_TRI_MASK (0x1 << 8)
619#define RT5631_JD_SPK_L_TRI_HI (0x1 << 8)
620#define RT5631_JD_SPK_L_TRI_LO (0x0 << 8)
621/* JD trigger enable for speaker RP/RN */
622#define RT5631_JD_SPK_R_EN (0x1 << 7)
623#define RT5631_JD_SPK_R_TRI_MASK (0x1 << 6)
624#define RT5631_JD_SPK_R_TRI_HI (0x1 << 6)
625#define RT5631_JD_SPK_R_TRI_LO (0x0 << 6)
626/* JD trigger enable for monoout */
627#define RT5631_JD_MONO_EN (0x1 << 5)
628#define RT5631_JD_MONO_TRI_MASK (0x1 << 4)
629#define RT5631_JD_MONO_TRI_HI (0x1 << 4)
630#define RT5631_JD_MONO_TRI_LO (0x0 << 4)
631/* JD trigger enable for Lout */
632#define RT5631_JD_AUX_1_EN (0x1 << 3)
633#define RT5631_JD_AUX_1_MASK (0x1 << 2)
634#define RT5631_JD_AUX_1_TRI_HI (0x1 << 2)
635#define RT5631_JD_AUX_1_TRI_LO (0x0 << 2)
636/* JD trigger enable for Rout */
637#define RT5631_JD_AUX_2_EN (0x1 << 1)
638#define RT5631_JD_AUX_2_MASK (0x1 << 0)
639#define RT5631_JD_AUX_2_TRI_HI (0x1 << 0)
640#define RT5631_JD_AUX_2_TRI_LO (0x0 << 0)
641
642/* ALC CONTROL 1(0x64) */
643#define RT5631_ALC_ATTACK_RATE_MASK (0x1F << 8)
644#define RT5631_ALC_RECOVERY_RATE_MASK (0x1F << 0)
645
646/* ALC CONTROL 2(0x65) */
647/* select Compensation gain for Noise gate function */
648#define RT5631_ALC_COM_NOISE_GATE_MASK (0xF << 0)
649
650/* ALC CONTROL 3(0x66) */
651#define RT5631_ALC_FUN_MASK (0x3 << 14)
652#define RT5631_ALC_FUN_DIS (0x0 << 14)
653#define RT5631_ALC_ENA_DAC_PATH (0x1 << 14)
654#define RT5631_ALC_ENA_ADC_PATH (0x3 << 14)
655#define RT5631_ALC_PARA_UPDATE (0x1 << 13)
656#define RT5631_ALC_LIMIT_LEVEL_MASK (0x1F << 8)
657#define RT5631_ALC_NOISE_GATE_FUN_MASK (0x1 << 7)
658#define RT5631_ALC_NOISE_GATE_FUN_DIS (0x0 << 7)
659#define RT5631_ALC_NOISE_GATE_FUN_ENA (0x1 << 7)
660/* ALC noise gate hold data function */
661#define RT5631_ALC_NOISE_GATE_H_D_MASK (0x1 << 6)
662#define RT5631_ALC_NOISE_GATE_H_D_DIS (0x0 << 6)
663#define RT5631_ALC_NOISE_GATE_H_D_ENA (0x1 << 6)
664
665/* Psedueo Stereo & Spatial Effect Block Control(0x68) */
666#define RT5631_SPATIAL_CTRL_EN (0x1 << 15)
667#define RT5631_ALL_PASS_FILTER_EN (0x1 << 14)
668#define RT5631_PSEUDO_STEREO_EN (0x1 << 13)
669#define RT5631_STEREO_EXPENSION_EN (0x1 << 12)
670/* 3D gain parameter */
671#define RT5631_GAIN_3D_PARA_MASK (0x3 << 6)
672#define RT5631_GAIN_3D_PARA_1_00 (0x0 << 6) /* 3D gain 1.0 */
673#define RT5631_GAIN_3D_PARA_1_50 (0x1 << 6) /* 3D gain 1.5 */
674#define RT5631_GAIN_3D_PARA_2_00 (0x2 << 6) /* 3D gain 2.0 */
675/* 3D ratio parameter */
676#define RT5631_RATIO_3D_MASK (0x3 << 4)
677#define RT5631_RATIO_3D_0_0 (0x0 << 4) /* 3D ratio 0.0 */
678#define RT5631_RATIO_3D_0_66 (0x1 << 4) /* 3D ratio 0.66 */
679#define RT5631_RATIO_3D_1_0 (0x2 << 4) /* 3D ratio 1.0 */
680/* select samplerate for all pass filter */
681#define RT5631_APF_FUN_SLE_MASK (0x3 << 0)
682#define RT5631_APF_FUN_SEL_48K (0x3 << 0)
683#define RT5631_APF_FUN_SEL_44_1K (0x2 << 0)
684#define RT5631_APF_FUN_SEL_32K (0x1 << 0)
685#define RT5631_APF_FUN_DIS (0x0 << 0)
686
687/* EQ CONTROL 1(0x6E) */
688#define RT5631_HW_EQ_PATH_SEL_MASK (0x1 << 15)
689#define RT5631_HW_EQ_PATH_SEL_DAC (0x0 << 15)
690#define RT5631_HW_EQ_PATH_SEL_ADC (0x1 << 15)
691#define RT5631_HW_EQ_UPDATE_CTRL (0x1 << 14)
692
693#define RT5631_EN_HW_EQ_HPF2 (0x1 << 5)
694#define RT5631_EN_HW_EQ_HPF1 (0x1 << 4)
695#define RT5631_EN_HW_EQ_BP3 (0x1 << 3)
696#define RT5631_EN_HW_EQ_BP2 (0x1 << 2)
697#define RT5631_EN_HW_EQ_BP1 (0x1 << 1)
698#define RT5631_EN_HW_EQ_LPF (0x1 << 0)
699
700
701#endif /* __RTCODEC5631_H__ */
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