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authorMagnus Damm <damm@opensource.se>2010-05-11 03:05:09 -0400
committerPaul Mundt <lethal@linux-sh.org>2010-05-13 04:34:10 -0400
commitd40db0c4a63c3af44fd31a7c47cc4a11a44befc7 (patch)
treef456e74ede8b195fc6b8d36245cdb9e1322d8031
parentc77a9c3edee079fe0411d98cfb9d872bc336ee32 (diff)
sh: div4 reparent workaround
Update the div4 set_parent() callback to use the flags instead of name to determine parent index. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--arch/sh/kernel/cpu/clock-cpg.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c
index 17a73ad7a20d..0b165f6ae08c 100644
--- a/arch/sh/kernel/cpu/clock-cpg.c
+++ b/arch/sh/kernel/cpu/clock-cpg.c
@@ -168,7 +168,12 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
168 u32 value; 168 u32 value;
169 int ret; 169 int ret;
170 170
171 if (!strcmp("pll_clk", parent->name)) 171 /* we really need a better way to determine parent index, but for
172 * now assume internal parent comes with CLK_ENABLE_ON_INIT set,
173 * no CLK_ENABLE_ON_INIT means external clock...
174 */
175
176 if (parent->flags & CLK_ENABLE_ON_INIT)
172 value = __raw_readl(clk->enable_reg) & ~(1 << 7); 177 value = __raw_readl(clk->enable_reg) & ~(1 << 7);
173 else 178 else
174 value = __raw_readl(clk->enable_reg) | (1 << 7); 179 value = __raw_readl(clk->enable_reg) | (1 << 7);