diff options
| author | Richard Genoud <richard.genoud@gmail.com> | 2013-01-18 11:41:21 -0500 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2013-01-23 04:30:54 -0500 |
| commit | c89cec3a4037f4aebf948d0f9c984c4823478c66 (patch) | |
| tree | f7a2893198a918ef152dc020027ccb5fa4e4a077 | |
| parent | 45976c01b7be338efc9d3c911293491a981ed87a (diff) | |
ARM: at91/at91sam9x5 DTS: correct wrong PIO BANK values on u(s)arts
The PIN_BANK 3 is for PDxx pins, not PCxx pins.
And PIN_BANK 1 is for PBxx, not PIN_BANK 0.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| -rw-r--r-- | arch/arm/boot/dts/at91sam9x5.dtsi | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 3a47cf952146..e9c42908da88 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi | |||
| @@ -154,12 +154,12 @@ | |||
| 154 | 154 | ||
| 155 | pinctrl_usart1_rts: usart1_rts-0 { | 155 | pinctrl_usart1_rts: usart1_rts-0 { |
| 156 | atmel,pins = | 156 | atmel,pins = |
| 157 | <3 27 0x3 0x0>; /* PC27 periph C */ | 157 | <2 27 0x3 0x0>; /* PC27 periph C */ |
| 158 | }; | 158 | }; |
| 159 | 159 | ||
| 160 | pinctrl_usart1_cts: usart1_cts-0 { | 160 | pinctrl_usart1_cts: usart1_cts-0 { |
| 161 | atmel,pins = | 161 | atmel,pins = |
| 162 | <3 28 0x3 0x0>; /* PC28 periph C */ | 162 | <2 28 0x3 0x0>; /* PC28 periph C */ |
| 163 | }; | 163 | }; |
| 164 | }; | 164 | }; |
| 165 | 165 | ||
| @@ -172,46 +172,46 @@ | |||
| 172 | 172 | ||
| 173 | pinctrl_uart2_rts: uart2_rts-0 { | 173 | pinctrl_uart2_rts: uart2_rts-0 { |
| 174 | atmel,pins = | 174 | atmel,pins = |
| 175 | <0 0 0x2 0x0>; /* PB0 periph B */ | 175 | <1 0 0x2 0x0>; /* PB0 periph B */ |
| 176 | }; | 176 | }; |
| 177 | 177 | ||
| 178 | pinctrl_uart2_cts: uart2_cts-0 { | 178 | pinctrl_uart2_cts: uart2_cts-0 { |
| 179 | atmel,pins = | 179 | atmel,pins = |
| 180 | <0 1 0x2 0x0>; /* PB1 periph B */ | 180 | <1 1 0x2 0x0>; /* PB1 periph B */ |
| 181 | }; | 181 | }; |
| 182 | }; | 182 | }; |
| 183 | 183 | ||
| 184 | usart3 { | 184 | usart3 { |
| 185 | pinctrl_uart3: usart3-0 { | 185 | pinctrl_uart3: usart3-0 { |
| 186 | atmel,pins = | 186 | atmel,pins = |
| 187 | <3 23 0x2 0x1 /* PC22 periph B with pullup */ | 187 | <2 23 0x2 0x1 /* PC22 periph B with pullup */ |
| 188 | 3 23 0x2 0x0>; /* PC23 periph B */ | 188 | 2 23 0x2 0x0>; /* PC23 periph B */ |
| 189 | }; | 189 | }; |
| 190 | 190 | ||
| 191 | pinctrl_usart3_rts: usart3_rts-0 { | 191 | pinctrl_usart3_rts: usart3_rts-0 { |
| 192 | atmel,pins = | 192 | atmel,pins = |
| 193 | <3 24 0x2 0x0>; /* PC24 periph B */ | 193 | <2 24 0x2 0x0>; /* PC24 periph B */ |
| 194 | }; | 194 | }; |
| 195 | 195 | ||
| 196 | pinctrl_usart3_cts: usart3_cts-0 { | 196 | pinctrl_usart3_cts: usart3_cts-0 { |
| 197 | atmel,pins = | 197 | atmel,pins = |
| 198 | <3 25 0x2 0x0>; /* PC25 periph B */ | 198 | <2 25 0x2 0x0>; /* PC25 periph B */ |
| 199 | }; | 199 | }; |
| 200 | }; | 200 | }; |
| 201 | 201 | ||
| 202 | uart0 { | 202 | uart0 { |
| 203 | pinctrl_uart0: uart0-0 { | 203 | pinctrl_uart0: uart0-0 { |
| 204 | atmel,pins = | 204 | atmel,pins = |
| 205 | <3 8 0x3 0x0 /* PC8 periph C */ | 205 | <2 8 0x3 0x0 /* PC8 periph C */ |
| 206 | 3 9 0x3 0x1>; /* PC9 periph C with pullup */ | 206 | 2 9 0x3 0x1>; /* PC9 periph C with pullup */ |
| 207 | }; | 207 | }; |
| 208 | }; | 208 | }; |
| 209 | 209 | ||
| 210 | uart1 { | 210 | uart1 { |
| 211 | pinctrl_uart1: uart1-0 { | 211 | pinctrl_uart1: uart1-0 { |
| 212 | atmel,pins = | 212 | atmel,pins = |
| 213 | <3 16 0x3 0x0 /* PC16 periph C */ | 213 | <2 16 0x3 0x0 /* PC16 periph C */ |
| 214 | 3 17 0x3 0x1>; /* PC17 periph C with pullup */ | 214 | 2 17 0x3 0x1>; /* PC17 periph C with pullup */ |
| 215 | }; | 215 | }; |
| 216 | }; | 216 | }; |
| 217 | 217 | ||