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authorBruce Allan <bruce.w.allan@intel.com>2013-02-05 03:30:59 -0500
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2013-02-05 03:30:59 -0500
commitc556d6072d99c96bbc091ea64712cf71468ce533 (patch)
treec0346962676ffa0635bdcfe39706ecc02900d85b
parent948f97aca6700ea96647719185d83a0b7c312fc1 (diff)
e1000e: convert enums of register offsets and move #defines to regs.h
There are enough register offsets to warrant being in their own header file, and doing so logically separates them from other header file content. They have been converted from an enumerated data type to #defines as is done in all the other Intel wired ethernet drivers. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat
-rw-r--r--drivers/net/ethernet/intel/e1000e/hw.h212
-rw-r--r--drivers/net/ethernet/intel/e1000e/netdev.c12
-rw-r--r--drivers/net/ethernet/intel/e1000e/regs.h252
3 files changed, 253 insertions, 223 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/hw.h b/drivers/net/ethernet/intel/e1000e/hw.h
index de876bd85cdf..1e6b889aee87 100644
--- a/drivers/net/ethernet/intel/e1000e/hw.h
+++ b/drivers/net/ethernet/intel/e1000e/hw.h
@@ -29,221 +29,11 @@
29#ifndef _E1000_HW_H_ 29#ifndef _E1000_HW_H_
30#define _E1000_HW_H_ 30#define _E1000_HW_H_
31 31
32#include "regs.h"
32#include "defines.h" 33#include "defines.h"
33 34
34struct e1000_hw; 35struct e1000_hw;
35 36
36enum e1e_registers {
37 E1000_CTRL = 0x00000, /* Device Control - RW */
38 E1000_STATUS = 0x00008, /* Device Status - RO */
39 E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */
40 E1000_EERD = 0x00014, /* EEPROM Read - RW */
41 E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
42 E1000_FLA = 0x0001C, /* Flash Access - RW */
43 E1000_MDIC = 0x00020, /* MDI Control - RW */
44 E1000_SCTL = 0x00024, /* SerDes Control - RW */
45 E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
46 E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
47 E1000_FEXTNVM4 = 0x00024, /* Future Extended NVM 4 - RW */
48 E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
49 E1000_FCT = 0x00030, /* Flow Control Type - RW */
50 E1000_VET = 0x00038, /* VLAN Ether Type - RW */
51 E1000_FEXTNVM3 = 0x0003C, /* Future Extended NVM 3 - RW */
52 E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
53 E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */
54 E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */
55 E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
56 E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
57 E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
58 E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */
59 E1000_FEXTNVM7 = 0x000E4, /* Future Extended NVM 7 - RW */
60 E1000_LPIC = 0x000FC, /* Low Power Idle Control - RW */
61 E1000_RCTL = 0x00100, /* Rx Control - RW */
62 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
63 E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */
64 E1000_RXCW = 0x00180, /* Rx Configuration Word - RO */
65 E1000_TCTL = 0x00400, /* Tx Control - RW */
66 E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
67 E1000_TIPG = 0x00410, /* Tx Inter-packet gap -RW */
68 E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
69 E1000_LEDCTL = 0x00E00, /* LED Control - RW */
70 E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
71 E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
72 E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */
73#define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
74 E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
75 E1000_PBS = 0x01008, /* Packet Buffer Size */
76 E1000_PBECCSTS = 0x0100C, /* Packet Buffer ECC Status - RW */
77 E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
78 E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
79 E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
80 E1000_PBA_ECC = 0x01100, /* PBA ECC Register */
81 E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
82 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
83 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
84 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
85/* Convenience macros
86 *
87 * Note: "_n" is the queue number of the register to be written to.
88 *
89 * Example usage:
90 * E1000_RDBAL(current_rx_queue)
91 */
92 E1000_RDBAL_BASE = 0x02800, /* Rx Descriptor Base Address Low - RW */
93#define E1000_RDBAL(_n) (E1000_RDBAL_BASE + (_n << 8))
94 E1000_RDBAH_BASE = 0x02804, /* Rx Descriptor Base Address High - RW */
95#define E1000_RDBAH(_n) (E1000_RDBAH_BASE + (_n << 8))
96 E1000_RDLEN_BASE = 0x02808, /* Rx Descriptor Length - RW */
97#define E1000_RDLEN(_n) (E1000_RDLEN_BASE + (_n << 8))
98 E1000_RDH_BASE = 0x02810, /* Rx Descriptor Head - RW */
99#define E1000_RDH(_n) (E1000_RDH_BASE + (_n << 8))
100 E1000_RDT_BASE = 0x02818, /* Rx Descriptor Tail - RW */
101#define E1000_RDT(_n) (E1000_RDT_BASE + (_n << 8))
102 E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */
103 E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
104#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
105 E1000_RADV = 0x0282C, /* Rx Interrupt Absolute Delay Timer - RW */
106
107 E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
108 E1000_TDBAL_BASE = 0x03800, /* Tx Descriptor Base Address Low - RW */
109#define E1000_TDBAL(_n) (E1000_TDBAL_BASE + (_n << 8))
110 E1000_TDBAH_BASE = 0x03804, /* Tx Descriptor Base Address High - RW */
111#define E1000_TDBAH(_n) (E1000_TDBAH_BASE + (_n << 8))
112 E1000_TDLEN_BASE = 0x03808, /* Tx Descriptor Length - RW */
113#define E1000_TDLEN(_n) (E1000_TDLEN_BASE + (_n << 8))
114 E1000_TDH_BASE = 0x03810, /* Tx Descriptor Head - RW */
115#define E1000_TDH(_n) (E1000_TDH_BASE + (_n << 8))
116 E1000_TDT_BASE = 0x03818, /* Tx Descriptor Tail - RW */
117#define E1000_TDT(_n) (E1000_TDT_BASE + (_n << 8))
118 E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */
119 E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
120#define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
121 E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
122 E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
123#define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8))
124 E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
125 E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
126 E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
127 E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */
128 E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */
129 E1000_SCC = 0x04014, /* Single Collision Count - R/clr */
130 E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */
131 E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */
132 E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
133 E1000_COLC = 0x04028, /* Collision Count - R/clr */
134 E1000_DC = 0x04030, /* Defer Count - R/clr */
135 E1000_TNCRS = 0x04034, /* Tx-No CRS - R/clr */
136 E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
137 E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
138 E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
139 E1000_XONRXC = 0x04048, /* XON Rx Count - R/clr */
140 E1000_XONTXC = 0x0404C, /* XON Tx Count - R/clr */
141 E1000_XOFFRXC = 0x04050, /* XOFF Rx Count - R/clr */
142 E1000_XOFFTXC = 0x04054, /* XOFF Tx Count - R/clr */
143 E1000_FCRUC = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
144 E1000_PRC64 = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
145 E1000_PRC127 = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
146 E1000_PRC255 = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
147 E1000_PRC511 = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
148 E1000_PRC1023 = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
149 E1000_PRC1522 = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
150 E1000_GPRC = 0x04074, /* Good Packets Rx Count - R/clr */
151 E1000_BPRC = 0x04078, /* Broadcast Packets Rx Count - R/clr */
152 E1000_MPRC = 0x0407C, /* Multicast Packets Rx Count - R/clr */
153 E1000_GPTC = 0x04080, /* Good Packets Tx Count - R/clr */
154 E1000_GORCL = 0x04088, /* Good Octets Rx Count Low - R/clr */
155 E1000_GORCH = 0x0408C, /* Good Octets Rx Count High - R/clr */
156 E1000_GOTCL = 0x04090, /* Good Octets Tx Count Low - R/clr */
157 E1000_GOTCH = 0x04094, /* Good Octets Tx Count High - R/clr */
158 E1000_RNBC = 0x040A0, /* Rx No Buffers Count - R/clr */
159 E1000_RUC = 0x040A4, /* Rx Undersize Count - R/clr */
160 E1000_RFC = 0x040A8, /* Rx Fragment Count - R/clr */
161 E1000_ROC = 0x040AC, /* Rx Oversize Count - R/clr */
162 E1000_RJC = 0x040B0, /* Rx Jabber Count - R/clr */
163 E1000_MGTPRC = 0x040B4, /* Management Packets Rx Count - R/clr */
164 E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
165 E1000_MGTPTC = 0x040BC, /* Management Packets Tx Count - R/clr */
166 E1000_TORL = 0x040C0, /* Total Octets Rx Low - R/clr */
167 E1000_TORH = 0x040C4, /* Total Octets Rx High - R/clr */
168 E1000_TOTL = 0x040C8, /* Total Octets Tx Low - R/clr */
169 E1000_TOTH = 0x040CC, /* Total Octets Tx High - R/clr */
170 E1000_TPR = 0x040D0, /* Total Packets Rx - R/clr */
171 E1000_TPT = 0x040D4, /* Total Packets Tx - R/clr */
172 E1000_PTC64 = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
173 E1000_PTC127 = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
174 E1000_PTC255 = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
175 E1000_PTC511 = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
176 E1000_PTC1023 = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
177 E1000_PTC1522 = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
178 E1000_MPTC = 0x040F0, /* Multicast Packets Tx Count - R/clr */
179 E1000_BPTC = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
180 E1000_TSCTC = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
181 E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
182 E1000_IAC = 0x04100, /* Interrupt Assertion Count */
183 E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
184 E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
185 E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
186 E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
187 E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */
188 E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
189 E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
190 E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
191 E1000_PCS_LCTL = 0x04208, /* PCS Link Control - RW */
192 E1000_PCS_LSTAT = 0x0420C, /* PCS Link Status - RO */
193 E1000_PCS_ANADV = 0x04218, /* AN advertisement - RW */
194 E1000_PCS_LPAB = 0x0421C, /* Link Partner Ability - RW */
195 E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */
196 E1000_RFCTL = 0x05008, /* Receive Filter Control */
197 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
198 E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */
199#define E1000_RAL(_n) (E1000_RAL_BASE + ((_n) * 8))
200#define E1000_RA (E1000_RAL(0))
201 E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
202#define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8))
203 E1000_SHRAL_BASE = 0x05438, /* Shared Receive Address Low - RW */
204#define E1000_SHRAL(_n) (E1000_SHRAL_BASE + ((_n) * 8))
205 E1000_SHRAH_BASE = 0x0543C, /* Shared Receive Address High - RW */
206#define E1000_SHRAH(_n) (E1000_SHRAH_BASE + ((_n) * 8))
207 E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
208 E1000_WUC = 0x05800, /* Wakeup Control - RW */
209 E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
210 E1000_WUS = 0x05810, /* Wakeup Status - RO */
211 E1000_MRQC = 0x05818, /* Multiple Receive Control - RW */
212 E1000_MANC = 0x05820, /* Management Control - RW */
213 E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
214 E1000_CRC_OFFSET = 0x05F50, /* CRC Offset register */
215 E1000_HOST_IF = 0x08800, /* Host Interface */
216
217 E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
218 E1000_MANC2H = 0x05860, /* Management Control To Host - RW */
219 E1000_MDEF_BASE = 0x05890, /* Management Decision Filters */
220#define E1000_MDEF(_n) (E1000_MDEF_BASE + ((_n) * 4))
221 E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
222 E1000_GCR = 0x05B00, /* PCI-Ex Control */
223 E1000_GCR2 = 0x05B64, /* PCI-Ex Control #2 */
224 E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */
225 E1000_SWSM = 0x05B50, /* SW Semaphore */
226 E1000_FWSM = 0x05B54, /* FW Semaphore */
227 E1000_SWSM2 = 0x05B58, /* Driver-only SW semaphore */
228 E1000_RETA_BASE = 0x05C00, /* Redirection Table - RW */
229#define E1000_RETA(_n) (E1000_RETA_BASE + ((_n) * 4))
230 E1000_RSSRK_BASE = 0x05C80, /* RSS Random Key - RW */
231#define E1000_RSSRK(_n) (E1000_RSSRK_BASE + ((_n) * 4))
232 E1000_FFLT_DBG = 0x05F04, /* Debug Register */
233 E1000_HICR = 0x08F00, /* Host Interface Control */
234 E1000_SYSTIML = 0x0B600, /* System time register Low - RO */
235 E1000_SYSTIMH = 0x0B604, /* System time register High - RO */
236 E1000_TIMINCA = 0x0B608, /* Increment attributes register - RW */
237 E1000_TSYNCTXCTL = 0x0B614, /* Tx Time Sync Control register - RW */
238 E1000_TXSTMPL = 0x0B618, /* Tx timestamp value Low - RO */
239 E1000_TXSTMPH = 0x0B61C, /* Tx timestamp value High - RO */
240 E1000_TSYNCRXCTL = 0x0B620, /* Rx Time Sync Control register - RW */
241 E1000_RXSTMPL = 0x0B624, /* Rx timestamp Low - RO */
242 E1000_RXSTMPH = 0x0B628, /* Rx timestamp High - RO */
243 E1000_RXMTRL = 0x0B634, /* Timesync Rx EtherType and Msg Type - RW */
244 E1000_RXUDP = 0x0B638, /* Timesync Rx UDP Port - RW */
245};
246
247#define E1000_DEV_ID_82571EB_COPPER 0x105E 37#define E1000_DEV_ID_82571EB_COPPER 0x105E
248#define E1000_DEV_ID_82571EB_FIBER 0x105F 38#define E1000_DEV_ID_82571EB_FIBER 0x105F
249#define E1000_DEV_ID_82571EB_SERDES 0x1060 39#define E1000_DEV_ID_82571EB_SERDES 0x1060
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index 6fcf9e8008c0..382b031e7b2a 100644
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -86,18 +86,6 @@ struct e1000_reg_info {
86 char *name; 86 char *name;
87}; 87};
88 88
89#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
90#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
91#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
92#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
93#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
94
95#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
96#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
97#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
98#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
99#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
100
101static const struct e1000_reg_info e1000_reg_info_tbl[] = { 89static const struct e1000_reg_info e1000_reg_info_tbl[] = {
102 90
103 /* General Registers */ 91 /* General Registers */
diff --git a/drivers/net/ethernet/intel/e1000e/regs.h b/drivers/net/ethernet/intel/e1000e/regs.h
new file mode 100644
index 000000000000..794fe1497666
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000e/regs.h
@@ -0,0 +1,252 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000E_REGS_H_
30#define _E1000E_REGS_H_
31
32#define E1000_CTRL 0x00000 /* Device Control - RW */
33#define E1000_STATUS 0x00008 /* Device Status - RO */
34#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
35#define E1000_EERD 0x00014 /* EEPROM Read - RW */
36#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
37#define E1000_FLA 0x0001C /* Flash Access - RW */
38#define E1000_MDIC 0x00020 /* MDI Control - RW */
39#define E1000_SCTL 0x00024 /* SerDes Control - RW */
40#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
41#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
42#define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */
43#define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */
44#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */
45#define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */
46#define E1000_FCT 0x00030 /* Flow Control Type - RW */
47#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
48#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
49#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
50#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
51#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
52#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
53#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
54#define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
55#define E1000_SVCR 0x000F0
56#define E1000_SVT 0x000F4
57#define E1000_LPIC 0x000FC /* Low Power IDLE control */
58#define E1000_RCTL 0x00100 /* Rx Control - RW */
59#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
60#define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */
61#define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */
62#define E1000_PBA_ECC 0x01100 /* PBA ECC Register */
63#define E1000_TCTL 0x00400 /* Tx Control - RW */
64#define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */
65#define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */
66#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
67#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
68#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
69#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
70#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
71#define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
72#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
73#define E1000_PBS 0x01008 /* Packet Buffer Size */
74#define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */
75#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
76#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
77#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
78#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
79#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
80#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
81#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
82#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
83#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
84#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
85#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
86#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
87/* Split and Replication Rx Control - RW */
88#define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */
89#define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */
90/* Convenience macros
91 *
92 * Note: "_n" is the queue number of the register to be written to.
93 *
94 * Example usage:
95 * E1000_RDBAL_REG(current_rx_queue)
96 */
97#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
98 (0x0C000 + ((_n) * 0x40)))
99#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
100 (0x0C004 + ((_n) * 0x40)))
101#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
102 (0x0C008 + ((_n) * 0x40)))
103#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
104 (0x0C010 + ((_n) * 0x40)))
105#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
106 (0x0C018 + ((_n) * 0x40)))
107#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
108 (0x0C028 + ((_n) * 0x40)))
109#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
110 (0x0E000 + ((_n) * 0x40)))
111#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
112 (0x0E004 + ((_n) * 0x40)))
113#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
114 (0x0E008 + ((_n) * 0x40)))
115#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
116 (0x0E010 + ((_n) * 0x40)))
117#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
118 (0x0E018 + ((_n) * 0x40)))
119#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
120 (0x0E028 + ((_n) * 0x40)))
121#define E1000_TARC(_n) (0x03840 + ((_n) * 0x100))
122#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
123#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
124 (0x054E0 + ((_i - 16) * 8)))
125#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
126 (0x054E4 + ((_i - 16) * 8)))
127#define E1000_SHRAL(_i) (0x05438 + ((_i) * 8))
128#define E1000_SHRAH(_i) (0x0543C + ((_i) * 8))
129#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
130#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
131#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
132#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
133#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
134#define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */
135#define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */
136#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
137#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
138#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
139#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
140#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
141#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
142#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
143#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
144#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
145#define E1000_COLC 0x04028 /* Collision Count - R/clr */
146#define E1000_DC 0x04030 /* Defer Count - R/clr */
147#define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */
148#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
149#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
150#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
151#define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */
152#define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */
153#define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */
154#define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */
155#define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */
156#define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */
157#define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */
158#define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */
159#define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */
160#define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */
161#define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */
162#define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */
163#define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */
164#define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */
165#define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */
166#define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */
167#define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */
168#define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */
169#define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */
170#define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */
171#define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */
172#define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */
173#define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */
174#define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */
175#define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */
176#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
177#define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */
178#define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */
179#define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */
180#define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */
181#define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */
182#define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */
183#define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */
184#define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */
185#define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */
186#define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */
187#define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */
188#define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */
189#define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */
190#define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */
191#define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */
192#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */
193#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */
194#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
195#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */
196#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */
197#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */
198#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */
199#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
200#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */
201#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */
202#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
203#define E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */
204
205#define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */
206#define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */
207#define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */
208#define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
209#define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */
210#define E1000_RFCTL 0x05008 /* Receive Filter Control */
211#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
212#define E1000_RA 0x05400 /* Receive Address - RW Array */
213#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
214#define E1000_WUC 0x05800 /* Wakeup Control - RW */
215#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
216#define E1000_WUS 0x05810 /* Wakeup Status - RO */
217#define E1000_MANC 0x05820 /* Management Control - RW */
218#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
219#define E1000_HOST_IF 0x08800 /* Host Interface */
220
221#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
222#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
223/* Management Decision Filters */
224#define E1000_MDEF(_n) (0x05890 + (4 * (_n)))
225#define E1000_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */
226#define E1000_GCR 0x05B00 /* PCI-Ex Control */
227#define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */
228#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
229#define E1000_SWSM 0x05B50 /* SW Semaphore */
230#define E1000_FWSM 0x05B54 /* FW Semaphore */
231/* Driver-only SW semaphore (not used by BOOT agents) */
232#define E1000_SWSM2 0x05B58
233#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
234#define E1000_HICR 0x08F00 /* Host Interface Control */
235
236/* RSS registers */
237#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
238#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
239#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
240#define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
241#define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
242#define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */
243#define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */
244#define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */
245#define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */
246#define E1000_SYSTIML 0x0B600 /* System time register Low - RO */
247#define E1000_SYSTIMH 0x0B604 /* System time register High - RO */
248#define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */
249#define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
250#define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */
251
252#endif
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