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authorRanjani Vaidyanathan <ra5478@freescale.com>2013-11-05 15:44:20 -0500
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:47:08 -0400
commitc2ca29e3a88bec24a6e307255cab74af14f1b168 (patch)
tree5fe9eb4d2ea63d88fb6ec7523cd20b0ea09edfd7
parentdb38e54b7a63df0dcf30e1621615c447548c81b1 (diff)
ENGR00286345 [iMX6DL] Fixed random hang bug in bus freq driver
Incorrect clock disable of PLL2 caused random hangs during DDR freq change in iMX6DL. Remove PERCLK freq change code as this is not required for TO1.1 and later. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat
-rw-r--r--arch/arm/mach-imx/busfreq-imx6.c10
-rw-r--r--arch/arm/mach-imx/ddr3_freq_imx6.S28
2 files changed, 4 insertions, 34 deletions
diff --git a/arch/arm/mach-imx/busfreq-imx6.c b/arch/arm/mach-imx/busfreq-imx6.c
index a32b1d25fbc1..bc9265293477 100644
--- a/arch/arm/mach-imx/busfreq-imx6.c
+++ b/arch/arm/mach-imx/busfreq-imx6.c
@@ -48,7 +48,8 @@
48#include "hardware.h" 48#include "hardware.h"
49 49
50#define LPAPM_CLK 24000000 50#define LPAPM_CLK 24000000
51#define DDR_AUDIO_CLK 100000000 51#define DDR3_AUDIO_CLK 50000000
52#define LPDDR2_AUDIO_CLK 100000000
52 53
53int high_bus_freq_mode; 54int high_bus_freq_mode;
54int med_bus_freq_mode; 55int med_bus_freq_mode;
@@ -114,7 +115,7 @@ static void enter_lpm_imx6sl(void)
114 if (audio_bus_count) { 115 if (audio_bus_count) {
115 /* Set up DDR to 100MHz. */ 116 /* Set up DDR to 100MHz. */
116 spin_lock_irqsave(&freq_lock, flags); 117 spin_lock_irqsave(&freq_lock, flags);
117 update_lpddr2_freq(DDR_AUDIO_CLK); 118 update_lpddr2_freq(LPDDR2_AUDIO_CLK);
118 spin_unlock_irqrestore(&freq_lock, flags); 119 spin_unlock_irqrestore(&freq_lock, flags);
119 120
120 /* Fix the clock tree in kernel */ 121 /* Fix the clock tree in kernel */
@@ -245,7 +246,7 @@ int reduce_bus_freq(void)
245 if (audio_bus_count) { 246 if (audio_bus_count) {
246 /* Need to ensure that PLL2_PFD_400M is kept ON. */ 247 /* Need to ensure that PLL2_PFD_400M is kept ON. */
247 clk_prepare_enable(pll2_400); 248 clk_prepare_enable(pll2_400);
248 update_ddr_freq(DDR_AUDIO_CLK); 249 update_ddr_freq(DDR3_AUDIO_CLK);
249 /* Make sure periph clk's parent also got updated */ 250 /* Make sure periph clk's parent also got updated */
250 ret = clk_set_parent(periph_clk2_sel, pll3); 251 ret = clk_set_parent(periph_clk2_sel, pll3);
251 if (ret) 252 if (ret)
@@ -283,9 +284,6 @@ int reduce_bus_freq(void)
283 low_bus_freq_mode = 1; 284 low_bus_freq_mode = 1;
284 audio_bus_freq_mode = 0; 285 audio_bus_freq_mode = 0;
285 } 286 }
286 if (high_bus_freq_mode && cpu_is_imx6dl())
287 clk_disable_unprepare(pll2_400);
288
289 } 287 }
290 clk_disable_unprepare(pll3); 288 clk_disable_unprepare(pll3);
291 289
diff --git a/arch/arm/mach-imx/ddr3_freq_imx6.S b/arch/arm/mach-imx/ddr3_freq_imx6.S
index e7e67ce34382..699f32fbe118 100644
--- a/arch/arm/mach-imx/ddr3_freq_imx6.S
+++ b/arch/arm/mach-imx/ddr3_freq_imx6.S
@@ -64,7 +64,6 @@
64 * set the AHB dividers before the switch, 64 * set the AHB dividers before the switch,
65 * don't change AXI clock divider, 65 * don't change AXI clock divider,
66 * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4, 66 * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4,
67 * (need to maintain GPT divider).
68 */ 67 */
69 ldr r0, [r6, #CCM_CBCDR] 68 ldr r0, [r6, #CCM_CBCDR]
70 ldr r2, =0x3f1f00 69 ldr r2, =0x3f1f00
@@ -93,7 +92,6 @@ periph_clk_switch3:
93set_ahb_podf_before_switch: 92set_ahb_podf_before_switch:
94 /* 93 /*
95 * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4, 94 * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4,
96 * (need to maintain GPT divider).
97 */ 95 */
98 ldr r0, [r6, #CCM_CBCDR] 96 ldr r0, [r6, #CCM_CBCDR]
99 ldr r2, =0x3f1f00 97 ldr r2, =0x3f1f00
@@ -124,11 +122,6 @@ periph_clk_switch4:
124 cmp r0, #0 122 cmp r0, #0
125 bne periph_clk_switch4 123 bne periph_clk_switch4
126 124
127 /* change the perclk divider so that its at 6MHz. */
128 ldr r0, [r6, #CCM_CSCMR1]
129 bic r0, r0, #0x3F
130 orr r0, r0, #0xA
131 str r0, [r6, #CCM_CSCMR1]
132 .endm 125 .endm
133 126
134 .macro switch_to_400MHz 127 .macro switch_to_400MHz
@@ -163,7 +156,6 @@ periph_clk_switch5:
163set_ahb_podf_before_switch1: 156set_ahb_podf_before_switch1:
164 /* 157 /*
165 * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4, 158 * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4,
166 * (need to maintain GPT divider).
167 */ 159 */
168 ldr r0, [r6, #CCM_CBCDR] 160 ldr r0, [r6, #CCM_CBCDR]
169 ldr r2, =0x3f1f00 161 ldr r2, =0x3f1f00
@@ -199,7 +191,6 @@ periph_clk_switch6:
199 * change AHB divider so that we are at 400/3=133MHz. 191 * change AHB divider so that we are at 400/3=133MHz.
200 * don't change AXI clock divider. 192 * don't change AXI clock divider.
201 * set the MMDC_DIV=1, AXI_DIV=2, AHB_DIV=3, 193 * set the MMDC_DIV=1, AXI_DIV=2, AHB_DIV=3,
202 * (need to maintain GPT divider).
203 */ 194 */
204 ldr r0, [r6, #CCM_CBCDR] 195 ldr r0, [r6, #CCM_CBCDR]
205 ldr r2, =0x3f1f00 196 ldr r2, =0x3f1f00
@@ -213,12 +204,6 @@ wait_div_update400_2:
213 cmp r0, #0 204 cmp r0, #0
214 bne wait_div_update400_2 205 bne wait_div_update400_2
215 206
216 /* change the perclk divider so that its at 6MHz. */
217 ldr r0, [r6, #CCM_CSCMR1]
218 bic r0, r0, #0x3F
219 orr r0, r0, #0xA
220 str r0, [r6, #CCM_CSCMR1]
221
222 .endm 207 .endm
223 208
224 .macro switch_to_50MHz 209 .macro switch_to_50MHz
@@ -261,7 +246,6 @@ switch_pre_periph_clk_50:
261 246
262 /* 247 /*
263 * set the MMDC_DIV=4, AXI_DIV = 4, AHB_DIV=8, 248 * set the MMDC_DIV=4, AXI_DIV = 4, AHB_DIV=8,
264 * (need to maintain GPT divider).
265 */ 249 */
266 ldr r0, [r6, #CCM_CBCDR] 250 ldr r0, [r6, #CCM_CBCDR]
267 ldr r2, =0x3f1f00 251 ldr r2, =0x3f1f00
@@ -291,12 +275,6 @@ periph_clk_switch2:
291 cmp r0, #0 275 cmp r0, #0
292 bne periph_clk_switch2 276 bne periph_clk_switch2
293 277
294 /* change the perclk divider so that its at 6MHz. */
295 ldr r0, [r6, #CCM_CSCMR1]
296 bic r0, r0, #0x3F
297 orr r0, r0, #0x1
298 str r0, [r6, #CCM_CSCMR1]
299
300 .endm 278 .endm
301 279
302 .macro switch_to_24MHz 280 .macro switch_to_24MHz
@@ -339,12 +317,6 @@ wait_div_update:
339 cmp r0, #0 317 cmp r0, #0
340 bne wait_div_update 318 bne wait_div_update
341 319
342 /* change the perclk divider so that its at 6MHz. */
343 ldr r0, [r6, #CCM_CSCMR1]
344 bic r0, r0, #0x3F
345 orr r0, r0, #0x1
346 str r0, [r6, #CCM_CSCMR1]
347
348 .endm 320 .endm
349 321
350/* 322/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-23 11:50:13 -0400