diff options
| author | Shengjiu Wang <b02247@freescale.com> | 2014-04-10 02:50:15 -0400 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-04-16 09:58:20 -0400 |
| commit | bf7902d0cae3d90dfda6e9f6e463955dfde9c382 (patch) | |
| tree | 992b8750f4ac5a396cbcf3a63eb9fb97f70a9550 | |
| parent | 24bd975f29aef39658f50ca9805e272795538eae (diff) | |
ENGR00307835-1 ASoC: fsl: refine esai driver for sync mode
1. PCRC and PRRC should be set after the setting of control register
according the RM. Then no need init TCCR and RCCR in init function.
Signed-off-by: Shengjiu Wang <b02247@freescale.com>
| -rw-r--r-- | sound/soc/fsl/fsl_esai.c | 24 |
1 files changed, 18 insertions, 6 deletions
diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c index 44ba41072b37..6f6adcec7d41 100644 --- a/sound/soc/fsl/fsl_esai.c +++ b/sound/soc/fsl/fsl_esai.c | |||
| @@ -307,10 +307,7 @@ static int fsl_esai_startup(struct snd_pcm_substream *substream, | |||
| 307 | 307 | ||
| 308 | clk_enable(esai->clk); | 308 | clk_enable(esai->clk); |
| 309 | clk_prepare_enable(esai->dmaclk); | 309 | clk_prepare_enable(esai->dmaclk); |
| 310 | if (!cpu_dai->active) { | 310 | |
| 311 | writel(ESAI_GPIO_ESAI, esai->base + ESAI_PRRC); | ||
| 312 | writel(ESAI_GPIO_ESAI, esai->base + ESAI_PCRC); | ||
| 313 | } | ||
| 314 | ESAI_DUMP(); | 311 | ESAI_DUMP(); |
| 315 | return 0; | 312 | return 0; |
| 316 | } | 313 | } |
| @@ -431,19 +428,29 @@ static int fsl_esai_hw_params(struct snd_pcm_substream *substream, | |||
| 431 | struct snd_soc_dai *cpu_dai) | 428 | struct snd_soc_dai *cpu_dai) |
| 432 | { | 429 | { |
| 433 | struct fsl_esai *esai = snd_soc_dai_get_drvdata(cpu_dai); | 430 | struct fsl_esai *esai = snd_soc_dai_get_drvdata(cpu_dai); |
| 431 | int ret = 0; | ||
| 434 | 432 | ||
| 435 | /* Tx/Rx config */ | 433 | /* Tx/Rx config */ |
| 436 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | 434 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 437 | if (readl(esai->base + ESAI_TCR) & ESAI_TCR_TE0) | 435 | if (readl(esai->base + ESAI_TCR) & ESAI_TCR_TE0) |
| 438 | return 0; | 436 | return 0; |
| 439 | 437 | ||
| 440 | return fsl_esai_hw_tx_params(substream, params, cpu_dai); | 438 | ret = fsl_esai_hw_tx_params(substream, params, cpu_dai); |
| 441 | } else { | 439 | } else { |
| 442 | if (readl(esai->base + ESAI_RCR) & ESAI_RCR_RE1) | 440 | if (readl(esai->base + ESAI_RCR) & ESAI_RCR_RE1) |
| 443 | return 0; | 441 | return 0; |
| 444 | 442 | ||
| 445 | return fsl_esai_hw_rx_params(substream, params, cpu_dai); | 443 | ret = fsl_esai_hw_rx_params(substream, params, cpu_dai); |
| 446 | } | 444 | } |
| 445 | |||
| 446 | /* | ||
| 447 | * PRRC and PCRC should be set after control register has been set, | ||
| 448 | * before the trigger() be called, according the reference manual. | ||
| 449 | */ | ||
| 450 | writel(ESAI_GPIO_ESAI, esai->base + ESAI_PRRC); | ||
| 451 | writel(ESAI_GPIO_ESAI, esai->base + ESAI_PCRC); | ||
| 452 | |||
| 453 | return ret; | ||
| 447 | } | 454 | } |
| 448 | 455 | ||
| 449 | static void fsl_esai_shutdown(struct snd_pcm_substream *substream, | 456 | static void fsl_esai_shutdown(struct snd_pcm_substream *substream, |
| @@ -451,6 +458,11 @@ static void fsl_esai_shutdown(struct snd_pcm_substream *substream, | |||
| 451 | { | 458 | { |
| 452 | struct fsl_esai *esai = snd_soc_dai_get_drvdata(cpu_dai); | 459 | struct fsl_esai *esai = snd_soc_dai_get_drvdata(cpu_dai); |
| 453 | 460 | ||
| 461 | if (!cpu_dai->active) { | ||
| 462 | writel(0, esai->base + ESAI_PRRC); | ||
| 463 | writel(0, esai->base + ESAI_PCRC); | ||
| 464 | } | ||
| 465 | |||
| 454 | clk_disable_unprepare(esai->dmaclk); | 466 | clk_disable_unprepare(esai->dmaclk); |
| 455 | clk_disable(esai->clk); | 467 | clk_disable(esai->clk); |
| 456 | } | 468 | } |