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authorAnson Huang <b20788@freescale.com>2014-02-11 02:35:22 -0500
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:57:24 -0400
commitbb6d7d3aac68587c745ff020817ec1ca646c00dc (patch)
treef5cdf4e5f70ea246ceccf4282f346fde386eedc4
parent19eb029e0eabedabcac3021a5cfc53d7eb1ee652 (diff)
ENGR00298524-2 ARM: imx: Add MSL support for i.mx6sx
It adds initial MSL support for i.mx6sx, including below features: 1. add cpu type check; 2. add system timer support; 3. add clock tree support; 4. add machine layer init support; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> Acked-by: Jason Liu
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/imx6sx-clock.txt10
-rw-r--r--arch/arm/mach-imx/Kconfig19
-rw-r--r--arch/arm/mach-imx/Makefile1
-rw-r--r--arch/arm/mach-imx/clk-imx6sx.c435
-rw-r--r--arch/arm/mach-imx/common.h3
-rw-r--r--arch/arm/mach-imx/cpu.c3
-rw-r--r--arch/arm/mach-imx/mach-imx6sx.c83
-rw-r--r--arch/arm/mach-imx/mxc.h8
-rw-r--r--arch/arm/mach-imx/src.c8
-rw-r--r--arch/arm/mach-imx/time.c7
-rw-r--r--include/dt-bindings/clock/imx6sx-clock.h243
11 files changed, 814 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx6sx-clock.txt b/Documentation/devicetree/bindings/clock/imx6sx-clock.txt
new file mode 100644
index 000000000000..ee97197b26c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6sx-clock.txt
@@ -0,0 +1,10 @@
1* Clock bindings for Freescale i.MX6 SoloX
2
3Required properties:
4- compatible: Should be "fsl,imx6sx-ccm"
5- reg: Address and length of the register set
6- #clock-cells: Should be <1>
7
8The clock consumer should specify the desired clock by having the clock
9ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sx-clock.h
10for the full list of i.MX6 SoloX clock IDs.
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index f4412742a966..94668debca5e 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -842,6 +842,25 @@ config SOC_IMX6SL
842 help 842 help
843 This enables support for Freescale i.MX6 SoloLite processor. 843 This enables support for Freescale i.MX6 SoloLite processor.
844 844
845config SOC_IMX6SX
846 bool "i.MX6 SoloX support"
847 select ARM_ERRATA_754322
848 select ARM_ERRATA_775420
849 select ARM_GIC
850 select CPU_V7
851 select HAVE_IMX_ANATOP
852 select HAVE_IMX_GPC
853 select HAVE_IMX_MMDC
854 select HAVE_IMX_SRC
855 select PINCTRL
856 select PINCTRL_IMX6SX
857 select PL310_ERRATA_588369 if CACHE_PL310
858 select PL310_ERRATA_727915 if CACHE_PL310
859 select PL310_ERRATA_769419 if CACHE_PL310
860
861 help
862 This enables support for Freescale i.MX6 SoloX processor.
863
845config SOC_VF610 864config SOC_VF610
846 bool "Vybrid Family VF610 support" 865 bool "Vybrid Family VF610 support"
847 select CPU_V7 866 select CPU_V7
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 87a323b0f0f8..d56ea8b34182 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_SMP) += headsmp.o platsmp.o
101obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 101obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
102obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o 102obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
103obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o 103obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
104obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o
104 105
105AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a 106AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
106obj-$(CONFIG_PM) += pm-imx6.o headsmp.o suspend-imx6.o 107obj-$(CONFIG_PM) += pm-imx6.o headsmp.o suspend-imx6.o
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
new file mode 100644
index 000000000000..757dbdbd4ec1
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -0,0 +1,435 @@
1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/clock/imx6sx-clock.h>
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21#include <linux/types.h>
22
23#include "clk.h"
24#include "common.h"
25#include "hardware.h"
26
27#define CCM_CCGR_OFFSET(index) (index * 2)
28
29static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
30static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
31static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
32static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", };
33static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
34static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
35static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
36static const char *ocram_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
37static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
38static const char *gpu_axi_sels[] = { "pll2_pfd2_396m", "pll3_pfd0_720m", "pll3_pfd1_540m", "pll2_bus", };
39static const char *gpu_core_sels[] = { "pll3_pfd1_540m", "pll3_pfd0_720m", "pll2_bus", "pll2_pfd2_396m", };
40static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
41static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
42static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", };
43static const char *ldb_di1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
44static const char *pcie_axi_sels[] = { "axi", "ahb", };
45static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll5_video_div", "pll4_audio_div", };
46static const char *qspi1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
47static const char *perclk_sels[] = { "ipg", "osc", };
48static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
49static const char *vid_sels[] = { "pll3_pfd1_540m", "pll3_usb_otg", "pll3_pfd3_454m", "pll4_audio_div", "pll5_video_div", };
50static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", "dummy", };
51static const char *uart_sels[] = { "pll3_80m", "osc", };
52static const char *qspi2_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", "dummy", "dummy", };
53static const char *enet_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
54static const char *enet_sels[] = { "enet_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
55static const char *m4_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "osc", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd3_454m", };
56static const char *m4_sels[] = { "m4_pre_sel", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
57static const char *eim_slow_sels[] = { "ocram", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
58static const char *ecspi_sels[] = { "pll3_60m", "osc", };
59static const char *lcdif1_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };
60static const char *lcdif1_sels[] = { "lcdif1_pre_sel", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
61static const char *lcdif2_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd3_594m", "pll3_pfd1_540m", };
62static const char *lcdif2_sels[] = { "lcdif2_pre_sel", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
63static const char *display_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll3_usb_otg", "pll3_pfd1_540m", };
64static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
65static const char *cko1_sels[] = {
66 "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
67 "dummy", "ocram", "dummy", "pxp_axi", "epdc_axi", "lcdif_pix",
68 "epdc_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
69};
70static const char *cko2_sels[] = {
71 "dummy", "mmdc_p0_fast", "usdhc4", "usdhc1", "dummy", "wrck",
72 "ecspi_root", "dummy", "usdhc3", "pcie", "arm", "csi_core",
73 "lcdif_axi", "dummy", "osc", "dummy", "gpu2d_ovg_core",
74 "usdhc2", "ssi1", "ssi2", "ssi3", "gpu2d_core", "dummy",
75 "dummy", "dummy", "dummy", "esai", "eim_slow", "uart_serial",
76 "spdif", "asrc", "dummy",
77};
78static const char *cko_sels[] = { "cko1", "cko2", };
79
80static struct clk *clks[IMX6SX_CLK_CLK_END];
81static struct clk_onecell_data clk_data;
82
83static int const clks_init_on[] __initconst = {
84 IMX6SX_CLK_AIPS_TZ1, IMX6SX_CLK_AIPS_TZ2, IMX6SX_CLK_AIPS_TZ3,
85 IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3,
86 IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG,
87 IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM,
88 IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK,
89};
90
91static struct clk_div_table clk_enet_ref_table[] = {
92 { .val = 0, .div = 20, },
93 { .val = 1, .div = 10, },
94 { .val = 2, .div = 5, },
95 { .val = 3, .div = 4, },
96};
97
98static struct clk_div_table post_div_table[] = {
99 { .val = 2, .div = 1, },
100 { .val = 1, .div = 2, },
101 { .val = 0, .div = 4, },
102 { }
103};
104
105static struct clk_div_table video_div_table[] = {
106 { .val = 0, .div = 1, },
107 { .val = 1, .div = 2, },
108 { .val = 2, .div = 1, },
109 { .val = 3, .div = 4, },
110 { }
111};
112
113static void __init imx6sx_clocks_init(struct device_node *ccm_node)
114{
115 struct device_node *np;
116 void __iomem *base;
117 int i, irq;
118
119 clks[IMX6SX_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
120 clks[IMX6SX_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
121 clks[IMX6SX_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
122 clks[IMX6SX_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
123 /* ipp_di clock is external input */
124 clks[IMX6SX_CLK_IPP_DI0] = imx_obtain_fixed_clock("ipp_di0", 0);
125 clks[IMX6SX_CLK_IPP_DI1] = imx_obtain_fixed_clock("ipp_di1", 0);
126
127 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
128 base = of_iomap(np, 0);
129 WARN_ON(!base);
130
131 /* type name parent_name base div_mask always_on */
132 clks[IMX6SX_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f, false);
133 clks[IMX6SX_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1, false);
134 clks[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3, false);
135 clks[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f, false);
136 clks[IMX6SX_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f, false);
137 clks[IMX6SX_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3, false);
138 clks[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3, false);
139
140 /*
141 * Bit 20 is the reserved and read-only bit, we do this only for:
142 * - Do nothing for usbphy clk_enable/disable
143 * - Keep refcount when do usbphy clk_enable/disable, in that case,
144 * the clk framework may need to enable/disable usbphy's parent
145 */
146 clks[IMX6SX_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
147 clks[IMX6SX_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
148
149 /*
150 * usbphy*_gate needs to be on after system boots up, and software
151 * never needs to control it anymore.
152 */
153 clks[IMX6SX_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
154 clks[IMX6SX_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
155
156 clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
157 clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
158
159 clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
160 base + 0xe0, 0, 2, 0, clk_enet_ref_table,
161 &imx_ccm_lock);
162
163 /* name parent_name reg idx */
164 clks[IMX6SX_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
165 clks[IMX6SX_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
166 clks[IMX6SX_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
167 clks[IMX6SX_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3);
168 clks[IMX6SX_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
169 clks[IMX6SX_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
170 clks[IMX6SX_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
171 clks[IMX6SX_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
172
173 /* name parent_name mult div */
174 clks[IMX6SX_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
175 clks[IMX6SX_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
176 clks[IMX6SX_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
177 clks[IMX6SX_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
178 clks[IMX6SX_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
179 clks[IMX6SX_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
180
181 clks[IMX6SX_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio",
182 CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
183 clks[IMX6SX_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
184 CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
185 clks[IMX6SX_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video",
186 CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
187 clks[IMX6SX_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
188 CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
189
190 np = ccm_node;
191 base = of_iomap(np, 0);
192 WARN_ON(!base);
193 imx6_pm_set_ccm_base(base);
194
195 /* name reg shift width parent_names num_parents */
196 clks[IMX6SX_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
197 clks[IMX6SX_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
198 clks[IMX6SX_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 2, ocram_sels, ARRAY_SIZE(ocram_sels));
199 clks[IMX6SX_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
200 clks[IMX6SX_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
201 clks[IMX6SX_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
202 clks[IMX6SX_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
203 clks[IMX6SX_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
204 clks[IMX6SX_CLK_GPU_AXI_SEL] = imx_clk_mux("gpu_axi_sel", base + 0x18, 8, 2, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
205 clks[IMX6SX_CLK_GPU_CORE_SEL] = imx_clk_mux("gpu_core_sel", base + 0x18, 4, 2, gpu_core_sels, ARRAY_SIZE(gpu_core_sels));
206 clks[IMX6SX_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels));
207 clks[IMX6SX_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
208 clks[IMX6SX_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
209 clks[IMX6SX_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
210 clks[IMX6SX_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
211 clks[IMX6SX_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
212 clks[IMX6SX_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
213 clks[IMX6SX_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
214 clks[IMX6SX_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels));
215 clks[IMX6SX_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels));
216 clks[IMX6SX_CLK_VID_SEL] = imx_clk_mux("vid_sel", base + 0x20, 21, 3, vid_sels, ARRAY_SIZE(vid_sels));
217 clks[IMX6SX_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
218 clks[IMX6SX_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels));
219 clks[IMX6SX_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
220 clks[IMX6SX_CLK_QSPI2_SEL] = imx_clk_mux("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels));
221 clks[IMX6SX_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
222 clks[IMX6SX_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
223 clks[IMX6SX_CLK_ENET_PRE_SEL] = imx_clk_mux("enet_pre_sel", base + 0x34, 15, 3, enet_pre_sels, ARRAY_SIZE(enet_pre_sels));
224 clks[IMX6SX_CLK_ENET_SEL] = imx_clk_mux("enet_sel", base + 0x34, 9, 3, enet_sels, ARRAY_SIZE(enet_sels));
225 clks[IMX6SX_CLK_M4_PRE_SEL] = imx_clk_mux("m4_pre_sel", base + 0x34, 6, 3, m4_pre_sels, ARRAY_SIZE(m4_pre_sels));
226 clks[IMX6SX_CLK_M4_SEL] = imx_clk_mux("m4_sel", base + 0x34, 0, 3, m4_sels, ARRAY_SIZE(m4_sels));
227 clks[IMX6SX_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
228 clks[IMX6SX_CLK_LCDIF1_PRE_SEL] = imx_clk_mux("lcdif1_pre_sel", base + 0x38, 15, 3, lcdif1_pre_sels, ARRAY_SIZE(lcdif1_pre_sels));
229 clks[IMX6SX_CLK_LCDIF1_SEL] = imx_clk_mux("lcdif1_sel", base + 0x38, 9, 3, lcdif1_sels, ARRAY_SIZE(lcdif1_sels));
230 clks[IMX6SX_CLK_LCDIF2_PRE_SEL] = imx_clk_mux("lcdif2_pre_sel", base + 0x38, 6, 3, lcdif2_pre_sels, ARRAY_SIZE(lcdif2_pre_sels));
231 clks[IMX6SX_CLK_LCDIF2_SEL] = imx_clk_mux("lcdif2_sel", base + 0x38, 0, 3, lcdif2_sels, ARRAY_SIZE(lcdif2_sels));
232 clks[IMX6SX_CLK_DISPLAY_SEL] = imx_clk_mux("display_sel", base + 0x3c, 14, 2, display_sels, ARRAY_SIZE(display_sels));
233 clks[IMX6SX_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels));
234 clks[IMX6SX_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
235 clks[IMX6SX_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
236 clks[IMX6SX_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
237
238 clks[IMX6SX_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT);
239 clks[IMX6SX_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT);
240 clks[IMX6SX_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di1_sels, ARRAY_SIZE(ldb_di1_sels), CLK_SET_RATE_PARENT);
241 clks[IMX6SX_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels), CLK_SET_RATE_PARENT);
242
243 /* name parent_name reg shift width */
244 clks[IMX6SX_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
245 clks[IMX6SX_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
246 clks[IMX6SX_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
247 clks[IMX6SX_CLK_GPU_CORE_PODF] = imx_clk_divider("gpu_core_podf", "gpu_core_sel", base + 0x18, 29, 3);
248 clks[IMX6SX_CLK_GPU_AXI_PODF] = imx_clk_divider("gpu_axi_podf", "gpu_axi_sel", base + 0x18, 26, 3);
249 clks[IMX6SX_CLK_LCDIF1_PODF] = imx_clk_divider("lcdif1_podf", "lcdif1_sel", base + 0x18, 23, 3);
250 clks[IMX6SX_CLK_QSPI1_PODF] = imx_clk_divider("qspi1_podf", "qspi1_sel", base + 0x1c, 26, 3);
251 clks[IMX6SX_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3);
252 clks[IMX6SX_CLK_LCDIF2_PODF] = imx_clk_divider("lcdif2_podf", "lcdif2_sel", base + 0x1c, 20, 3);
253 clks[IMX6SX_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6);
254 clks[IMX6SX_CLK_VID_PODF] = imx_clk_divider("vid_podf", "vid_sel", base + 0x20, 24, 2);
255 clks[IMX6SX_CLK_CAN_PODF] = imx_clk_divider("can_podf", "can_sel", base + 0x20, 2, 6);
256 clks[IMX6SX_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
257 clks[IMX6SX_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
258 clks[IMX6SX_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
259 clks[IMX6SX_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
260 clks[IMX6SX_CLK_UART_PODF] = imx_clk_divider("uart_podf", "uart_sel", base + 0x24, 0, 6);
261 clks[IMX6SX_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
262 clks[IMX6SX_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
263 clks[IMX6SX_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
264 clks[IMX6SX_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
265 clks[IMX6SX_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
266 clks[IMX6SX_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
267 clks[IMX6SX_CLK_QSPI2_PRED] = imx_clk_divider("qspi2_pred", "qspi2_sel", base + 0x2c, 18, 3);
268 clks[IMX6SX_CLK_QSPI2_PODF] = imx_clk_divider("qspi2_podf", "qspi2_pred", base + 0x2c, 21, 6);
269 clks[IMX6SX_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
270 clks[IMX6SX_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
271 clks[IMX6SX_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
272 clks[IMX6SX_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
273 clks[IMX6SX_CLK_ASRC_PRED] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
274 clks[IMX6SX_CLK_ASRC_PODF] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
275 clks[IMX6SX_CLK_ENET_PODF] = imx_clk_divider("enet_podf", "enet_pre_sel", base + 0x34, 12, 3);
276 clks[IMX6SX_CLK_M4_PODF] = imx_clk_divider("m4_podf", "m4_sel", base + 0x34, 3, 3);
277 clks[IMX6SX_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6);
278 clks[IMX6SX_CLK_LCDIF1_PRED] = imx_clk_divider("lcdif1_pred", "lcdif1_sel", base + 0x38, 12, 3);
279 clks[IMX6SX_CLK_LCDIF2_PRED] = imx_clk_divider("lcdif2_pred", "lcdif2_sel", base + 0x38, 3, 3);
280 clks[IMX6SX_CLK_DISPLAY_PODF] = imx_clk_divider("display_podf", "display_sel", base + 0x3c, 16, 3);
281 clks[IMX6SX_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
282 clks[IMX6SX_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
283 clks[IMX6SX_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
284
285 clks[IMX6SX_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
286 clks[IMX6SX_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
287 clks[IMX6SX_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
288 clks[IMX6SX_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7);
289
290 /* name reg shift width busy: reg, shift parent_names num_parents */
291 clks[IMX6SX_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
292 clks[IMX6SX_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
293 /* name parent_name reg shift width busy: reg, shift */
294 clks[IMX6SX_CLK_OCRAM_PODF] = imx_clk_busy_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3, base + 0x48, 0);
295 clks[IMX6SX_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
296 clks[IMX6SX_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
297 clks[IMX6SX_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
298
299 /* name parent_name reg shift */
300 /* CCGR0 */
301 clks[IMX6SX_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0);
302 clks[IMX6SX_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2);
303 clks[IMX6SX_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
304 clks[IMX6SX_CLK_ASRC] = imx_clk_gate2("asrc", "ahb", base + 0x68, 6);
305 clks[IMX6SX_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
306 clks[IMX6SX_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
307 clks[IMX6SX_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
308 clks[IMX6SX_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
309 clks[IMX6SX_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_podf", base + 0x68, 16);
310 clks[IMX6SX_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
311 clks[IMX6SX_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_podf", base + 0x68, 20);
312 clks[IMX6SX_CLK_DCIC1] = imx_clk_gate2("dcic1", "display_podf", base + 0x68, 24);
313 clks[IMX6SX_CLK_DCIC2] = imx_clk_gate2("dcic2", "display_podf", base + 0x68, 26);
314 clks[IMX6SX_CLK_AIPS_TZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30);
315
316 /* CCGR1 */
317 clks[IMX6SX_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
318 clks[IMX6SX_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2);
319 clks[IMX6SX_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4);
320 clks[IMX6SX_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6);
321 clks[IMX6SX_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_podf", base + 0x6c, 8);
322 clks[IMX6SX_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12);
323 clks[IMX6SX_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14);
324 clks[IMX6SX_CLK_ESAI] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16);
325 clks[IMX6SX_CLK_WAKEUP] = imx_clk_gate2("wakeup", "ipg", base + 0x6c, 18);
326 clks[IMX6SX_CLK_GPT_BUS] = imx_clk_gate2("gpt_bus", "perclk", base + 0x6c, 20);
327 clks[IMX6SX_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22);
328 clks[IMX6SX_CLK_GPU] = imx_clk_gate2("gpu", "gpu_core_podf", base + 0x6c, 26);
329 clks[IMX6SX_CLK_CANFD] = imx_clk_gate2("canfd", "can_podf", base + 0x6c, 30);
330
331 /* CCGR2 */
332 clks[IMX6SX_CLK_CSI] = imx_clk_gate2("csi", "display_podf", base + 0x70, 2);
333 clks[IMX6SX_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6);
334 clks[IMX6SX_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8);
335 clks[IMX6SX_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
336 clks[IMX6SX_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
337 clks[IMX6SX_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif1_podf", base + 0x70, 14);
338 clks[IMX6SX_CLK_IPMUX1] = imx_clk_gate2("ipmux1", "ahb", base + 0x70, 16);
339 clks[IMX6SX_CLK_IPMUX2] = imx_clk_gate2("ipmux2", "ahb", base + 0x70, 18);
340 clks[IMX6SX_CLK_IPMUX3] = imx_clk_gate2("ipmux3", "ahb", base + 0x70, 20);
341 clks[IMX6SX_CLK_TZASC1] = imx_clk_gate2("tzasc1", "mmdc_podf", base + 0x70, 22);
342 clks[IMX6SX_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "display_podf", base + 0x70, 28);
343 clks[IMX6SX_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "display_podf", base + 0x70, 30);
344
345 /* CCGR3 */
346 clks[IMX6SX_CLK_M4] = imx_clk_gate2("m4", "m4_podf", base + 0x74, 2);
347 clks[IMX6SX_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4);
348 clks[IMX6SX_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "enet_sel", base + 0x74, 4);
349 clks[IMX6SX_CLK_DISPLAY_AXI] = imx_clk_gate2("display_axi", "display_podf", base + 0x74, 6);
350 clks[IMX6SX_CLK_LCDIF2_PIX] = imx_clk_gate2("lcdif2_pix", "lcdif2_podf", base + 0x74, 8);
351 clks[IMX6SX_CLK_LCDIF1_PIX] = imx_clk_gate2("lcdif1_pix", "lcdif1_podf", base + 0x74, 10);
352 clks[IMX6SX_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12);
353 clks[IMX6SX_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14);
354 clks[IMX6SX_CLK_MLB] = imx_clk_gate2("mlb", "ahb", base + 0x74, 18);
355 clks[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_gate2("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20);
356 clks[IMX6SX_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24);
357 clks[IMX6SX_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28);
358
359 /* CCGR4 */
360 clks[IMX6SX_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "display_podf", base + 0x78, 0);
361 clks[IMX6SX_CLK_QSPI2] = imx_clk_gate2("qspi2", "qspi2_podf", base + 0x78, 10);
362 clks[IMX6SX_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
363 clks[IMX6SX_CLK_PER2_MAIN] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14);
364 clks[IMX6SX_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16);
365 clks[IMX6SX_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18);
366 clks[IMX6SX_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
367 clks[IMX6SX_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
368 clks[IMX6SX_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
369 clks[IMX6SX_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
370 clks[IMX6SX_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "qspi2_podf", base + 0x78, 28);
371 clks[IMX6SX_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
372
373 /* CCGR5 */
374 clks[IMX6SX_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
375 clks[IMX6SX_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
376 clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
377 clks[IMX6SX_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
378 clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
379 clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
380 clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
381 clks[IMX6SX_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18);
382 clks[IMX6SX_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20);
383 clks[IMX6SX_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22);
384 clks[IMX6SX_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
385 clks[IMX6SX_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_podf", base + 0x7c, 26);
386 clks[IMX6SX_CLK_SAI1] = imx_clk_gate2("sai1", "ssi1_podf", base + 0x7c, 28);
387 clks[IMX6SX_CLK_SAI2] = imx_clk_gate2("sai2", "ssi2_podf", base + 0x7c, 30);
388
389 /* CCGR6 */
390 clks[IMX6SX_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
391 clks[IMX6SX_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
392 clks[IMX6SX_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
393 clks[IMX6SX_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
394 clks[IMX6SX_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
395 clks[IMX6SX_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10);
396 clks[IMX6SX_CLK_PWM8] = imx_clk_gate2("pwm8", "perclk", base + 0x80, 16);
397 clks[IMX6SX_CLK_VADC] = imx_clk_gate2("vadc", "vid_podf", base + 0x80, 20);
398 clks[IMX6SX_CLK_GIS] = imx_clk_gate2("gis", "display_podf", base + 0x80, 22);
399 clks[IMX6SX_CLK_I2C4] = imx_clk_gate2("i2c4", "perclk", base + 0x80, 24);
400 clks[IMX6SX_CLK_PWM5] = imx_clk_gate2("pwm5", "perclk", base + 0x80, 26);
401 clks[IMX6SX_CLK_PWM6] = imx_clk_gate2("pwm6", "perclk", base + 0x80, 28);
402 clks[IMX6SX_CLK_PWM7] = imx_clk_gate2("pwm7", "perclk", base + 0x80, 30);
403
404 clks[IMX6SX_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
405 clks[IMX6SX_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
406
407 for (i = 0; i < ARRAY_SIZE(clks); i++)
408 if (IS_ERR(clks[i]))
409 pr_err("i.MX6sx clk %d: register failed with %ld\n", i, PTR_ERR(clks[i]));
410
411 clk_data.clks = clks;
412 clk_data.clk_num = ARRAY_SIZE(clks);
413 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
414
415 clk_register_clkdev(clks[IMX6SX_CLK_GPT_BUS], "ipg", "imx-gpt.0");
416 clk_register_clkdev(clks[IMX6SX_CLK_GPT_SERIAL], "per", "imx-gpt.0");
417 clk_register_clkdev(clks[IMX6SX_CLK_GPT_3M], "gpt_3m", "imx-gpt.0");
418 clk_register_clkdev(clks[IMX6SX_CLK_CKO1_SEL], "cko1_sel", NULL);
419 clk_register_clkdev(clks[IMX6SX_CLK_AHB], "ahb", NULL);
420 clk_register_clkdev(clks[IMX6SX_CLK_CKO1], "cko1", NULL);
421 clk_register_clkdev(clks[IMX6SX_CLK_ARM], NULL, "cpu0");
422
423 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
424 clk_prepare_enable(clks[clks_init_on[i]]);
425
426 /* Set initial power mode */
427 imx6_set_lpm(WAIT_CLOCKED);
428
429 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-gpt");
430 base = of_iomap(np, 0);
431 WARN_ON(!base);
432 irq = irq_of_parse_and_map(np, 0);
433 mxc_timer_init(base, irq);
434}
435CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index ccab418fa3fc..80a132961671 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
3 */ 3 */
4 4
5/* 5/*
@@ -117,6 +117,7 @@ void tzic_handle_irq(struct pt_regs *);
117extern void imx_enable_cpu(int cpu, bool enable); 117extern void imx_enable_cpu(int cpu, bool enable);
118extern void imx_set_cpu_jump(int cpu, void *jump_addr); 118extern void imx_set_cpu_jump(int cpu, void *jump_addr);
119extern u32 imx_get_cpu_arg(int cpu); 119extern u32 imx_get_cpu_arg(int cpu);
120extern u32 imx_get_smbr1(void);
120extern void imx_set_cpu_arg(int cpu, u32 arg); 121extern void imx_set_cpu_arg(int cpu, u32 arg);
121extern void v7_cpu_resume(void); 122extern void v7_cpu_resume(void);
122#ifdef CONFIG_SMP 123#ifdef CONFIG_SMP
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 8ebcc20662b0..a29831acbb5d 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -110,6 +110,9 @@ struct device * __init imx_soc_device_init(void)
110 case MXC_CPU_IMX6DL: 110 case MXC_CPU_IMX6DL:
111 soc_id = "i.MX6DL"; 111 soc_id = "i.MX6DL";
112 break; 112 break;
113 case MXC_CPU_IMX6SX:
114 soc_id = "i.MX6SX";
115 break;
113 case MXC_CPU_IMX6Q: 116 case MXC_CPU_IMX6Q:
114 soc_id = "i.MX6Q"; 117 soc_id = "i.MX6Q";
115 break; 118 break;
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
new file mode 100644
index 000000000000..8415e6d58b33
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -0,0 +1,83 @@
1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/delay.h>
12#include <linux/irqchip.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/of_platform.h>
16#include <linux/opp.h>
17#include <linux/regmap.h>
18#include <linux/mfd/syscon.h>
19#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20#include <asm/mach/arch.h>
21#include <asm/mach/map.h>
22#include <asm/system_misc.h>
23
24#include "common.h"
25#include "cpuidle.h"
26#include "hardware.h"
27
28static void __init imx6sx_init_machine(void)
29{
30 struct device *parent;
31
32 mxc_arch_reset_init_dt();
33
34 parent = imx_soc_device_init();
35 if (parent == NULL)
36 pr_warn("failed to initialize soc device\n");
37
38 of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
39
40 imx_anatop_init();
41 imx6_pm_init();
42}
43
44static void __init imx6sx_map_io(void)
45{
46 debug_ll_io_init();
47 imx6_pm_map_io();
48}
49
50#define MX6SX_SRC_SMBR_L2_AS_OCRAM_MASK 0x100
51
52static void __init imx6sx_init_irq(void)
53{
54 imx_init_revision_from_anatop();
55 imx_src_init();
56
57 if (!(imx_get_smbr1() & MX6SX_SRC_SMBR_L2_AS_OCRAM_MASK))
58 imx_init_l2cache();
59 else
60 pr_info("L2 cache as OCRAM, skipping init\n");
61
62 imx_gpc_init();
63 irqchip_init();
64}
65
66static void __init imx6sx_timer_init(void)
67{
68 of_clk_init(NULL);
69}
70
71static const char *imx6sx_dt_compat[] __initdata = {
72 "fsl,imx6sx",
73 NULL,
74};
75
76DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)")
77 .map_io = imx6sx_map_io,
78 .init_irq = imx6sx_init_irq,
79 .init_time = imx6sx_timer_init,
80 .init_machine = imx6sx_init_machine,
81 .dt_compat = imx6sx_dt_compat,
82 .restart = mxc_restart,
83MACHINE_END
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index c78174dca791..88c4bce0aa6d 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2004-2007, 2010, 2013 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2007, 2010, 2013-2014 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) 3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4 * 4 *
5 * This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
@@ -36,6 +36,7 @@
36#define MXC_CPU_MX53 53 36#define MXC_CPU_MX53 53
37#define MXC_CPU_IMX6SL 0x60 37#define MXC_CPU_IMX6SL 0x60
38#define MXC_CPU_IMX6DL 0x61 38#define MXC_CPU_IMX6DL 0x61
39#define MXC_CPU_IMX6SX 0x62
39#define MXC_CPU_IMX6Q 0x63 40#define MXC_CPU_IMX6Q 0x63
40 41
41#define IMX_CHIP_REVISION_1_0 0x10 42#define IMX_CHIP_REVISION_1_0 0x10
@@ -155,6 +156,11 @@ extern unsigned int __mxc_cpu_type;
155#endif 156#endif
156 157
157#ifndef __ASSEMBLY__ 158#ifndef __ASSEMBLY__
159static inline bool cpu_is_imx6sx(void)
160{
161 return __mxc_cpu_type == MXC_CPU_IMX6SX;
162}
163
158static inline bool cpu_is_imx6sl(void) 164static inline bool cpu_is_imx6sl(void)
159{ 165{
160 return __mxc_cpu_type == MXC_CPU_IMX6SL; 166 return __mxc_cpu_type == MXC_CPU_IMX6SL;
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index ade704eff2d0..bbb3a6d271c5 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2011, 2013 Freescale Semiconductor, Inc. 2 * Copyright 2011, 2013-2014 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd. 3 * Copyright 2011 Linaro Ltd.
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * The code contained herein is licensed under the GNU General Public
@@ -20,6 +20,7 @@
20#include "common.h" 20#include "common.h"
21 21
22#define SRC_SCR 0x000 22#define SRC_SCR 0x000
23#define SRC_SMBR1 0x004
23#define SRC_GPR1 0x020 24#define SRC_GPR1 0x020
24#define BP_SRC_SCR_WARM_RESET_ENABLE 0 25#define BP_SRC_SCR_WARM_RESET_ENABLE 0
25#define BP_SRC_SCR_SW_GPU_RST 1 26#define BP_SRC_SCR_SW_GPU_RST 1
@@ -109,6 +110,11 @@ u32 imx_get_cpu_arg(int cpu)
109 return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4); 110 return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4);
110} 111}
111 112
113u32 imx_get_smbr1(void)
114{
115 return readl_relaxed(src_base + SRC_SMBR1);
116}
117
112void imx_set_cpu_arg(int cpu, u32 arg) 118void imx_set_cpu_arg(int cpu, u32 arg)
113{ 119{
114 cpu = cpu_logical_map(cpu); 120 cpu = cpu_logical_map(cpu);
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index 4ffad1458bca..9f2e2c76f98e 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -5,6 +5,7 @@
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com) 5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) 6 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
7 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) 7 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
8 * Copyright (C) 2014 Freescale Semiconductor, Inc.
8 * 9 *
9 * This program is free software; you can redistribute it and/or 10 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License 11 * modify it under the terms of the GNU General Public License
@@ -290,7 +291,7 @@ void __init mxc_timer_init(void __iomem *base, int irq)
290 * imx6dl, others from per clk. 291 * imx6dl, others from per clk.
291 */ 292 */
292 if ((cpu_is_imx6q() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_0) 293 if ((cpu_is_imx6q() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_0)
293 || cpu_is_imx6dl()) 294 || cpu_is_imx6dl() || cpu_is_imx6sx())
294 timer_clk = clk_get_sys("imx-gpt.0", "gpt_3m"); 295 timer_clk = clk_get_sys("imx-gpt.0", "gpt_3m");
295 else 296 else
296 timer_clk = clk_get_sys("imx-gpt.0", "per"); 297 timer_clk = clk_get_sys("imx-gpt.0", "per");
@@ -317,10 +318,10 @@ void __init mxc_timer_init(void __iomem *base, int irq)
317 318
318 if (timer_is_v2()) { 319 if (timer_is_v2()) {
319 if ((cpu_is_imx6q() && imx_get_soc_revision() > 320 if ((cpu_is_imx6q() && imx_get_soc_revision() >
320 IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { 321 IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl() || cpu_is_imx6sx()) {
321 tctl_val = V2_TCTL_CLK_OSC_DIV8 | V2_TCTL_FRR | 322 tctl_val = V2_TCTL_CLK_OSC_DIV8 | V2_TCTL_FRR |
322 V2_TCTL_WAITEN | MXC_TCTL_TEN; 323 V2_TCTL_WAITEN | MXC_TCTL_TEN;
323 if (cpu_is_imx6dl()) { 324 if (cpu_is_imx6dl() || cpu_is_imx6sx()) {
324 /* 24 / 8 = 3 MHz */ 325 /* 24 / 8 = 3 MHz */
325 tprer_val = 7 << V2_TPRER_PRE24M; 326 tprer_val = 7 << V2_TPRER_PRE24M;
326 __raw_writel(tprer_val, timer_base + MXC_TPRER); 327 __raw_writel(tprer_val, timer_base + MXC_TPRER);
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
new file mode 100644
index 000000000000..10c81341d1ab
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -0,0 +1,243 @@
1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
11#define __DT_BINDINGS_CLOCK_IMX6SX_H
12
13#define IMX6SX_CLK_DUMMY 0
14#define IMX6SX_CLK_CKIL 1
15#define IMX6SX_CLK_CKIH 2
16#define IMX6SX_CLK_OSC 3
17#define IMX6SX_CLK_PLL1_SYS 4
18#define IMX6SX_CLK_PLL2_BUS 5
19#define IMX6SX_CLK_PLL3_USB_OTG 6
20#define IMX6SX_CLK_PLL4_AUDIO 7
21#define IMX6SX_CLK_PLL5_VIDEO 8
22#define IMX6SX_CLK_PLL6_ENET 9
23#define IMX6SX_CLK_PLL7_USB_HOST 10
24#define IMX6SX_CLK_USBPHY1 11
25#define IMX6SX_CLK_USBPHY2 12
26#define IMX6SX_CLK_USBPHY1_GATE 13
27#define IMX6SX_CLK_USBPHY2_GATE 14
28#define IMX6SX_CLK_PCIE_REF 15
29#define IMX6SX_CLK_PCIE_REF_125M 16
30#define IMX6SX_CLK_ENET_REF 17
31#define IMX6SX_CLK_PLL2_PFD0 18
32#define IMX6SX_CLK_PLL2_PFD1 19
33#define IMX6SX_CLK_PLL2_PFD2 20
34#define IMX6SX_CLK_PLL2_PFD3 21
35#define IMX6SX_CLK_PLL3_PFD0 22
36#define IMX6SX_CLK_PLL3_PFD1 23
37#define IMX6SX_CLK_PLL3_PFD2 24
38#define IMX6SX_CLK_PLL3_PFD3 25
39#define IMX6SX_CLK_PLL2_198M 26
40#define IMX6SX_CLK_PLL3_120M 27
41#define IMX6SX_CLK_PLL3_80M 28
42#define IMX6SX_CLK_PLL3_60M 29
43#define IMX6SX_CLK_TWD 30
44#define IMX6SX_CLK_PLL4_POST_DIV 31
45#define IMX6SX_CLK_PLL4_AUDIO_DIV 32
46#define IMX6SX_CLK_PLL5_POST_DIV 33
47#define IMX6SX_CLK_PLL5_VIDEO_DIV 34
48#define IMX6SX_CLK_STEP 35
49#define IMX6SX_CLK_PLL1_SW 36
50#define IMX6SX_CLK_OCRAM_SEL 37
51#define IMX6SX_CLK_PERIPH_PRE 38
52#define IMX6SX_CLK_PERIPH2_PRE 39
53#define IMX6SX_CLK_PERIPH_CLK2_SEL 40
54#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41
55#define IMX6SX_CLK_PCIE_AXI_SEL 42
56#define IMX6SX_CLK_GPU_AXI_SEL 43
57#define IMX6SX_CLK_GPU_CORE_SEL 44
58#define IMX6SX_CLK_EIM_SLOW_SEL 45
59#define IMX6SX_CLK_USDHC1_SEL 46
60#define IMX6SX_CLK_USDHC2_SEL 47
61#define IMX6SX_CLK_USDHC3_SEL 48
62#define IMX6SX_CLK_USDHC4_SEL 49
63#define IMX6SX_CLK_SSI1_SEL 50
64#define IMX6SX_CLK_SSI2_SEL 51
65#define IMX6SX_CLK_SSI3_SEL 52
66#define IMX6SX_CLK_QSPI1_SEL 53
67#define IMX6SX_CLK_PERCLK_SEL 54
68#define IMX6SX_CLK_VID_SEL 55
69#define IMX6SX_CLK_ESAI_SEL 56
70#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57
71#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58
72#define IMX6SX_CLK_CAN_SEL 59
73#define IMX6SX_CLK_UART_SEL 60
74#define IMX6SX_CLK_QSPI2_SEL 61
75#define IMX6SX_CLK_LDB_DI1_SEL 62
76#define IMX6SX_CLK_LDB_DI0_SEL 63
77#define IMX6SX_CLK_SPDIF_SEL 64
78#define IMX6SX_CLK_ASRC_SEL 65
79#define IMX6SX_CLK_ENET_PRE_SEL 66
80#define IMX6SX_CLK_ENET_SEL 67
81#define IMX6SX_CLK_M4_PRE_SEL 68
82#define IMX6SX_CLK_M4_SEL 69
83#define IMX6SX_CLK_ECSPI_SEL 70
84#define IMX6SX_CLK_LCDIF1_PRE_SEL 71
85#define IMX6SX_CLK_LCDIF2_PRE_SEL 72
86#define IMX6SX_CLK_LCDIF1_SEL 73
87#define IMX6SX_CLK_LCDIF2_SEL 74
88#define IMX6SX_CLK_DISPLAY_SEL 75
89#define IMX6SX_CLK_CSI_SEL 76
90#define IMX6SX_CLK_CKO1_SEL 77
91#define IMX6SX_CLK_CKO2_SEL 78
92#define IMX6SX_CLK_CKO 79
93#define IMX6SX_CLK_PERIPH_CLK2 80
94#define IMX6SX_CLK_PERIPH2_CLK2 81
95#define IMX6SX_CLK_IPG 82
96#define IMX6SX_CLK_GPU_CORE_PODF 83
97#define IMX6SX_CLK_GPU_AXI_PODF 84
98#define IMX6SX_CLK_LCDIF1_PODF 85
99#define IMX6SX_CLK_QSPI1_PODF 86
100#define IMX6SX_CLK_EIM_SLOW_PODF 87
101#define IMX6SX_CLK_LCDIF2_PODF 88
102#define IMX6SX_CLK_PERCLK 89
103#define IMX6SX_CLK_VID_PODF 90
104#define IMX6SX_CLK_CAN_PODF 91
105#define IMX6SX_CLK_USDHC1_PODF 92
106#define IMX6SX_CLK_USDHC2_PODF 93
107#define IMX6SX_CLK_USDHC3_PODF 94
108#define IMX6SX_CLK_USDHC4_PODF 95
109#define IMX6SX_CLK_UART_PODF 96
110#define IMX6SX_CLK_ESAI_PRED 97
111#define IMX6SX_CLK_ESAI_PODF 98
112#define IMX6SX_CLK_SSI3_PRED 99
113#define IMX6SX_CLK_SSI3_PODF 100
114#define IMX6SX_CLK_SSI1_PRED 101
115#define IMX6SX_CLK_SSI1_PODF 102
116#define IMX6SX_CLK_QSPI2_PRED 103
117#define IMX6SX_CLK_QSPI2_PODF 104
118#define IMX6SX_CLK_SSI2_PRED 105
119#define IMX6SX_CLK_SSI2_PODF 106
120#define IMX6SX_CLK_SPDIF_PRED 107
121#define IMX6SX_CLK_SPDIF_PODF 108
122#define IMX6SX_CLK_ASRC_PRED 109
123#define IMX6SX_CLK_ASRC_PODF 110
124#define IMX6SX_CLK_ENET_PODF 111
125#define IMX6SX_CLK_M4_PODF 112
126#define IMX6SX_CLK_ECSPI_PODF 113
127#define IMX6SX_CLK_LCDIF1_PRED 114
128#define IMX6SX_CLK_LCDIF2_PRED 115
129#define IMX6SX_CLK_DISPLAY_PODF 116
130#define IMX6SX_CLK_CSI_PODF 117
131#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118
132#define IMX6SX_CLK_LDB_DI0_DIV_7 119
133#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120
134#define IMX6SX_CLK_LDB_DI1_DIV_7 121
135#define IMX6SX_CLK_CKO1_PODF 122
136#define IMX6SX_CLK_CKO2_PODF 123
137#define IMX6SX_CLK_PERIPH 124
138#define IMX6SX_CLK_PERIPH2 125
139#define IMX6SX_CLK_OCRAM 126
140#define IMX6SX_CLK_AHB 127
141#define IMX6SX_CLK_MMDC_PODF 128
142#define IMX6SX_CLK_ARM 129
143#define IMX6SX_CLK_AIPS_TZ1 130
144#define IMX6SX_CLK_AIPS_TZ2 131
145#define IMX6SX_CLK_APBH_DMA 132
146#define IMX6SX_CLK_ASRC 133
147#define IMX6SX_CLK_CAAM_MEM 134
148#define IMX6SX_CLK_CAAM_ACLK 135
149#define IMX6SX_CLK_CAAM_IPG 136
150#define IMX6SX_CLK_CAN1_IPG 137
151#define IMX6SX_CLK_CAN1_SERIAL 138
152#define IMX6SX_CLK_CAN2_IPG 139
153#define IMX6SX_CLK_CAN2_SERIAL 140
154#define IMX6SX_CLK_CPU_DEBUG 141
155#define IMX6SX_CLK_DCIC1 142
156#define IMX6SX_CLK_DCIC2 143
157#define IMX6SX_CLK_AIPS_TZ3 144
158#define IMX6SX_CLK_ECSPI1 145
159#define IMX6SX_CLK_ECSPI2 146
160#define IMX6SX_CLK_ECSPI3 147
161#define IMX6SX_CLK_ECSPI4 148
162#define IMX6SX_CLK_ECSPI5 149
163#define IMX6SX_CLK_EPIT1 150
164#define IMX6SX_CLK_EPIT2 151
165#define IMX6SX_CLK_ESAI 152
166#define IMX6SX_CLK_WAKEUP 153
167#define IMX6SX_CLK_GPT_BUS 154
168#define IMX6SX_CLK_GPT_SERIAL 155
169#define IMX6SX_CLK_GPU 156
170#define IMX6SX_CLK_OCRAM_S 157
171#define IMX6SX_CLK_CANFD 158
172#define IMX6SX_CLK_CSI 159
173#define IMX6SX_CLK_I2C1 160
174#define IMX6SX_CLK_I2C2 161
175#define IMX6SX_CLK_I2C3 162
176#define IMX6SX_CLK_OCOTP 163
177#define IMX6SX_CLK_IOMUXC 164
178#define IMX6SX_CLK_IPMUX1 165
179#define IMX6SX_CLK_IPMUX2 166
180#define IMX6SX_CLK_IPMUX3 167
181#define IMX6SX_CLK_TZASC1 168
182#define IMX6SX_CLK_LCDIF_APB 169
183#define IMX6SX_CLK_PXP_AXI 170
184#define IMX6SX_CLK_M4 171
185#define IMX6SX_CLK_ENET 172
186#define IMX6SX_CLK_DISPLAY_AXI 173
187#define IMX6SX_CLK_LCDIF2_PIX 174
188#define IMX6SX_CLK_LCDIF1_PIX 175
189#define IMX6SX_CLK_LDB_DI0 176
190#define IMX6SX_CLK_QSPI1 177
191#define IMX6SX_CLK_MLB 178
192#define IMX6SX_CLK_MMDC_P0_FAST 179
193#define IMX6SX_CLK_MMDC_P0_IPG 180
194#define IMX6SX_CLK_AXI 181
195#define IMX6SX_CLK_PCIE_AXI 182
196#define IMX6SX_CLK_QSPI2 183
197#define IMX6SX_CLK_PER1_BCH 184
198#define IMX6SX_CLK_PER2_MAIN 185
199#define IMX6SX_CLK_PWM1 186
200#define IMX6SX_CLK_PWM2 187
201#define IMX6SX_CLK_PWM3 188
202#define IMX6SX_CLK_PWM4 189
203#define IMX6SX_CLK_GPMI_BCH_APB 190
204#define IMX6SX_CLK_GPMI_BCH 191
205#define IMX6SX_CLK_GPMI_IO 192
206#define IMX6SX_CLK_GPMI_APB 193
207#define IMX6SX_CLK_ROM 194
208#define IMX6SX_CLK_SDMA 195
209#define IMX6SX_CLK_SPBA 196
210#define IMX6SX_CLK_SPDIF 197
211#define IMX6SX_CLK_SSI1_IPG 198
212#define IMX6SX_CLK_SSI2_IPG 199
213#define IMX6SX_CLK_SSI3_IPG 200
214#define IMX6SX_CLK_SSI1 201
215#define IMX6SX_CLK_SSI2 202
216#define IMX6SX_CLK_SSI3 203
217#define IMX6SX_CLK_UART_IPG 204
218#define IMX6SX_CLK_UART_SERIAL 205
219#define IMX6SX_CLK_SAI1 206
220#define IMX6SX_CLK_SAI2 207
221#define IMX6SX_CLK_USBOH3 208
222#define IMX6SX_CLK_USDHC1 209
223#define IMX6SX_CLK_USDHC2 210
224#define IMX6SX_CLK_USDHC3 211
225#define IMX6SX_CLK_USDHC4 212
226#define IMX6SX_CLK_EIM_SLOW 213
227#define IMX6SX_CLK_PWM8 214
228#define IMX6SX_CLK_VADC 215
229#define IMX6SX_CLK_GIS 216
230#define IMX6SX_CLK_I2C4 217
231#define IMX6SX_CLK_PWM5 218
232#define IMX6SX_CLK_PWM6 219
233#define IMX6SX_CLK_PWM7 220
234#define IMX6SX_CLK_CKO1 221
235#define IMX6SX_CLK_CKO2 222
236#define IMX6SX_CLK_IPP_DI0 223
237#define IMX6SX_CLK_IPP_DI1 224
238#define IMX6SX_CLK_ENET_AHB 225
239#define IMX6SX_CLK_OCRAM_PODF 226
240#define IMX6SX_CLK_GPT_3M 227
241#define IMX6SX_CLK_CLK_END 228
242
243#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-21 10:25:39 -0400