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authorNicolin Chen <b42378@freescale.com>2013-09-12 02:56:36 -0400
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:05:39 -0400
commitba60ff7437cbd247c5b9f49f78d8c81315f5d538 (patch)
treee5ef61d464e6be60e063e9dbed5ca85299190b98
parentbc52deb92239a80724b0a236fb5a74e6485650a7 (diff)
ENGR00279368-3 mxc: asrc: Add missing clock control
* Add missing clock control * Set ASRC clock to 7.5MHz as 3.0.35 does * Use the same divisor for ideal ratio mode as 3.0.35 does Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c2
-rw-r--r--drivers/mxc/asrc/mxc_asrc.c9
-rw-r--r--include/linux/mxc_asrc.h2
3 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 51c6b9940323..8d5a4d57dac4 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -515,6 +515,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
515 clk_set_parent(clk[ssi2_sel], clk[pll4_audio_div]); 515 clk_set_parent(clk[ssi2_sel], clk[pll4_audio_div]);
516 clk_set_parent(clk[ssi3_sel], clk[pll4_audio_div]); 516 clk_set_parent(clk[ssi3_sel], clk[pll4_audio_div]);
517 clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]); 517 clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
518 clk_set_parent(clk[asrc_sel], clk[pll3_usb_otg]);
519 clk_set_rate(clk[asrc_sel], 7500000);
518 520
519 /* Set pll4_audio to a value that can derive 5K-88.2KHz and 8K-96KHz */ 521 /* Set pll4_audio to a value that can derive 5K-88.2KHz and 8K-96KHz */
520 clk_set_rate(clk[pll4_audio_div], 541900800); 522 clk_set_rate(clk[pll4_audio_div], 541900800);
diff --git a/drivers/mxc/asrc/mxc_asrc.c b/drivers/mxc/asrc/mxc_asrc.c
index 3bba8f46980a..5ae42217b77c 100644
--- a/drivers/mxc/asrc/mxc_asrc.c
+++ b/drivers/mxc/asrc/mxc_asrc.c
@@ -680,6 +680,8 @@ EXPORT_SYMBOL(asrc_get_per_addr);
680 680
681static int mxc_init_asrc(void) 681static int mxc_init_asrc(void)
682{ 682{
683 clk_enable(asrc->asrc_clk);
684
683 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */ 685 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
684 asrc_regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN); 686 asrc_regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
685 687
@@ -708,6 +710,8 @@ static int mxc_init_asrc(void)
708 /* Set the processing clock for 56KHz, 133M */ 710 /* Set the processing clock for 56KHz, 133M */
709 asrc_regmap_write(asrc->regmap, REG_ASR56K, 0x0947); 711 asrc_regmap_write(asrc->regmap, REG_ASR56K, 0x0947);
710 712
713 clk_disable(asrc->asrc_clk);
714
711 return 0; 715 return 0;
712} 716}
713 717
@@ -1927,7 +1931,7 @@ static int mxc_asrc_probe(struct platform_device *pdev)
1927 goto err_iomap; 1931 goto err_iomap;
1928 } 1932 }
1929#ifndef ASRC_USE_REGMAP 1933#ifndef ASRC_USE_REGMAP
1930 clk_prepare_enable(asrc->asrc_clk); 1934 clk_prepare(asrc->asrc_clk);
1931#endif 1935#endif
1932 1936
1933 ret = of_property_read_u32_array(pdev->dev.of_node, 1937 ret = of_property_read_u32_array(pdev->dev.of_node,
@@ -1984,6 +1988,9 @@ err_iomap:
1984 1988
1985static int mxc_asrc_remove(struct platform_device *pdev) 1989static int mxc_asrc_remove(struct platform_device *pdev)
1986{ 1990{
1991#ifndef ASRC_USE_REGMAP
1992 clk_unprepare(asrc->asrc_clk);
1993#endif
1987 asrc_proc_remove(); 1994 asrc_proc_remove();
1988 misc_deregister(&asrc_miscdev); 1995 misc_deregister(&asrc_miscdev);
1989 1996
diff --git a/include/linux/mxc_asrc.h b/include/linux/mxc_asrc.h
index 9f742a9da80e..ecee963193af 100644
--- a/include/linux/mxc_asrc.h
+++ b/include/linux/mxc_asrc.h
@@ -30,7 +30,7 @@
30 30
31 31
32/* Ideal Ratio mode doesn't care the outclk frequency, so be fixed */ 32/* Ideal Ratio mode doesn't care the outclk frequency, so be fixed */
33#define ASRC_PRESCALER_IDEAL_RATIO 7 33#define ASRC_PRESCALER_IDEAL_RATIO 5
34/* SPDIF rxclk pulse rate is 128 * samplerate, so 2 ^ 7 */ 34/* SPDIF rxclk pulse rate is 128 * samplerate, so 2 ^ 7 */
35#define ASRC_PRESCALER_SPDIF_RX 7 35#define ASRC_PRESCALER_SPDIF_RX 7
36/* SPDIF txclk pulse rate is 64 * samplerate, so 2 ^ 6 */ 36/* SPDIF txclk pulse rate is 64 * samplerate, so 2 ^ 6 */