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authorLars-Peter Clausen <lars@metafoo.de>2011-11-28 11:28:11 -0500
committerMark Brown <broonie@opensource.wolfsonmicro.com>2011-11-28 13:57:52 -0500
commitb82ca578fd8b28d9600a077f4e24e22a71383fe8 (patch)
tree9875d9f6039e7e2d6d61f806965aac577c7dca62
parent0718fd27775fcc335c728cfa4965ce78c0662b67 (diff)
ASoC: ad193x: Use snd_soc_update_bits where appropriate
We can reduce the code size here a bit by using snd_soc_update_bits instead of open-coding the read-modify-write cycle. The conversion done in this patch is not completely straightforward and some minor code restructuring has been incorporated to further reduce the code size. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
-rw-r--r--sound/soc/codecs/ad193x.c96
-rw-r--r--sound/soc/codecs/ad193x.h17
2 files changed, 45 insertions, 68 deletions
diff --git a/sound/soc/codecs/ad193x.c b/sound/soc/codecs/ad193x.c
index c19e2232f10d..7d64f2021b06 100644
--- a/sound/soc/codecs/ad193x.c
+++ b/sound/soc/codecs/ad193x.c
@@ -123,35 +123,29 @@ static int ad193x_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
123 unsigned int rx_mask, int slots, int width) 123 unsigned int rx_mask, int slots, int width)
124{ 124{
125 struct snd_soc_codec *codec = dai->codec; 125 struct snd_soc_codec *codec = dai->codec;
126 int dac_reg = snd_soc_read(codec, AD193X_DAC_CTRL1); 126 unsigned int channels;
127 int adc_reg = snd_soc_read(codec, AD193X_ADC_CTRL2);
128
129 dac_reg &= ~AD193X_DAC_CHAN_MASK;
130 adc_reg &= ~AD193X_ADC_CHAN_MASK;
131 127
132 switch (slots) { 128 switch (slots) {
133 case 2: 129 case 2:
134 dac_reg |= AD193X_DAC_2_CHANNELS << AD193X_DAC_CHAN_SHFT; 130 channels = AD193X_2_CHANNELS;
135 adc_reg |= AD193X_ADC_2_CHANNELS << AD193X_ADC_CHAN_SHFT;
136 break; 131 break;
137 case 4: 132 case 4:
138 dac_reg |= AD193X_DAC_4_CHANNELS << AD193X_DAC_CHAN_SHFT; 133 channels = AD193X_4_CHANNELS;
139 adc_reg |= AD193X_ADC_4_CHANNELS << AD193X_ADC_CHAN_SHFT;
140 break; 134 break;
141 case 8: 135 case 8:
142 dac_reg |= AD193X_DAC_8_CHANNELS << AD193X_DAC_CHAN_SHFT; 136 channels = AD193X_8_CHANNELS;
143 adc_reg |= AD193X_ADC_8_CHANNELS << AD193X_ADC_CHAN_SHFT;
144 break; 137 break;
145 case 16: 138 case 16:
146 dac_reg |= AD193X_DAC_16_CHANNELS << AD193X_DAC_CHAN_SHFT; 139 channels = AD193X_16_CHANNELS;
147 adc_reg |= AD193X_ADC_16_CHANNELS << AD193X_ADC_CHAN_SHFT;
148 break; 140 break;
149 default: 141 default:
150 return -EINVAL; 142 return -EINVAL;
151 } 143 }
152 144
153 snd_soc_write(codec, AD193X_DAC_CTRL1, dac_reg); 145 snd_soc_update_bits(codec, AD193X_DAC_CTRL1, AD193X_DAC_CHAN_MASK,
154 snd_soc_write(codec, AD193X_ADC_CTRL2, adc_reg); 146 channels << AD193X_DAC_CHAN_SHFT);
147 snd_soc_update_bits(codec, AD193X_ADC_CTRL2, AD193X_ADC_CHAN_MASK,
148 channels << AD193X_ADC_CHAN_SHFT);
155 149
156 return 0; 150 return 0;
157} 151}
@@ -160,23 +154,19 @@ static int ad193x_set_dai_fmt(struct snd_soc_dai *codec_dai,
160 unsigned int fmt) 154 unsigned int fmt)
161{ 155{
162 struct snd_soc_codec *codec = codec_dai->codec; 156 struct snd_soc_codec *codec = codec_dai->codec;
163 int adc_reg1, adc_reg2, dac_reg; 157 unsigned int adc_serfmt = 0;
164 158 unsigned int adc_fmt = 0;
165 adc_reg1 = snd_soc_read(codec, AD193X_ADC_CTRL1); 159 unsigned int dac_fmt = 0;
166 adc_reg2 = snd_soc_read(codec, AD193X_ADC_CTRL2);
167 dac_reg = snd_soc_read(codec, AD193X_DAC_CTRL1);
168 160
169 /* At present, the driver only support AUX ADC mode(SND_SOC_DAIFMT_I2S 161 /* At present, the driver only support AUX ADC mode(SND_SOC_DAIFMT_I2S
170 * with TDM) and ADC&DAC TDM mode(SND_SOC_DAIFMT_DSP_A) 162 * with TDM) and ADC&DAC TDM mode(SND_SOC_DAIFMT_DSP_A)
171 */ 163 */
172 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 164 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
173 case SND_SOC_DAIFMT_I2S: 165 case SND_SOC_DAIFMT_I2S:
174 adc_reg1 &= ~AD193X_ADC_SERFMT_MASK; 166 adc_serfmt |= AD193X_ADC_SERFMT_TDM;
175 adc_reg1 |= AD193X_ADC_SERFMT_TDM;
176 break; 167 break;
177 case SND_SOC_DAIFMT_DSP_A: 168 case SND_SOC_DAIFMT_DSP_A:
178 adc_reg1 &= ~AD193X_ADC_SERFMT_MASK; 169 adc_serfmt |= AD193X_ADC_SERFMT_AUX;
179 adc_reg1 |= AD193X_ADC_SERFMT_AUX;
180 break; 170 break;
181 default: 171 default:
182 return -EINVAL; 172 return -EINVAL;
@@ -184,29 +174,20 @@ static int ad193x_set_dai_fmt(struct snd_soc_dai *codec_dai,
184 174
185 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 175 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
186 case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */ 176 case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */
187 adc_reg2 &= ~AD193X_ADC_LEFT_HIGH;
188 adc_reg2 &= ~AD193X_ADC_BCLK_INV;
189 dac_reg &= ~AD193X_DAC_LEFT_HIGH;
190 dac_reg &= ~AD193X_DAC_BCLK_INV;
191 break; 177 break;
192 case SND_SOC_DAIFMT_NB_IF: /* normal bclk + invert frm */ 178 case SND_SOC_DAIFMT_NB_IF: /* normal bclk + invert frm */
193 adc_reg2 |= AD193X_ADC_LEFT_HIGH; 179 adc_fmt |= AD193X_ADC_LEFT_HIGH;
194 adc_reg2 &= ~AD193X_ADC_BCLK_INV; 180 dac_fmt |= AD193X_DAC_LEFT_HIGH;
195 dac_reg |= AD193X_DAC_LEFT_HIGH;
196 dac_reg &= ~AD193X_DAC_BCLK_INV;
197 break; 181 break;
198 case SND_SOC_DAIFMT_IB_NF: /* invert bclk + normal frm */ 182 case SND_SOC_DAIFMT_IB_NF: /* invert bclk + normal frm */
199 adc_reg2 &= ~AD193X_ADC_LEFT_HIGH; 183 adc_fmt |= AD193X_ADC_BCLK_INV;
200 adc_reg2 |= AD193X_ADC_BCLK_INV; 184 dac_fmt |= AD193X_DAC_BCLK_INV;
201 dac_reg &= ~AD193X_DAC_LEFT_HIGH;
202 dac_reg |= AD193X_DAC_BCLK_INV;
203 break; 185 break;
204
205 case SND_SOC_DAIFMT_IB_IF: /* invert bclk + frm */ 186 case SND_SOC_DAIFMT_IB_IF: /* invert bclk + frm */
206 adc_reg2 |= AD193X_ADC_LEFT_HIGH; 187 adc_fmt |= AD193X_ADC_LEFT_HIGH;
207 adc_reg2 |= AD193X_ADC_BCLK_INV; 188 adc_fmt |= AD193X_ADC_BCLK_INV;
208 dac_reg |= AD193X_DAC_LEFT_HIGH; 189 dac_fmt |= AD193X_DAC_LEFT_HIGH;
209 dac_reg |= AD193X_DAC_BCLK_INV; 190 dac_fmt |= AD193X_DAC_BCLK_INV;
210 break; 191 break;
211 default: 192 default:
212 return -EINVAL; 193 return -EINVAL;
@@ -214,36 +195,31 @@ static int ad193x_set_dai_fmt(struct snd_soc_dai *codec_dai,
214 195
215 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 196 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
216 case SND_SOC_DAIFMT_CBM_CFM: /* codec clk & frm master */ 197 case SND_SOC_DAIFMT_CBM_CFM: /* codec clk & frm master */
217 adc_reg2 |= AD193X_ADC_LCR_MASTER; 198 adc_fmt |= AD193X_ADC_LCR_MASTER;
218 adc_reg2 |= AD193X_ADC_BCLK_MASTER; 199 adc_fmt |= AD193X_ADC_BCLK_MASTER;
219 dac_reg |= AD193X_DAC_LCR_MASTER; 200 dac_fmt |= AD193X_DAC_LCR_MASTER;
220 dac_reg |= AD193X_DAC_BCLK_MASTER; 201 dac_fmt |= AD193X_DAC_BCLK_MASTER;
221 break; 202 break;
222 case SND_SOC_DAIFMT_CBS_CFM: /* codec clk slave & frm master */ 203 case SND_SOC_DAIFMT_CBS_CFM: /* codec clk slave & frm master */
223 adc_reg2 |= AD193X_ADC_LCR_MASTER; 204 adc_fmt |= AD193X_ADC_LCR_MASTER;
224 adc_reg2 &= ~AD193X_ADC_BCLK_MASTER; 205 dac_fmt |= AD193X_DAC_LCR_MASTER;
225 dac_reg |= AD193X_DAC_LCR_MASTER;
226 dac_reg &= ~AD193X_DAC_BCLK_MASTER;
227 break; 206 break;
228 case SND_SOC_DAIFMT_CBM_CFS: /* codec clk master & frame slave */ 207 case SND_SOC_DAIFMT_CBM_CFS: /* codec clk master & frame slave */
229 adc_reg2 &= ~AD193X_ADC_LCR_MASTER; 208 adc_fmt |= AD193X_ADC_BCLK_MASTER;
230 adc_reg2 |= AD193X_ADC_BCLK_MASTER; 209 dac_fmt |= AD193X_DAC_BCLK_MASTER;
231 dac_reg &= ~AD193X_DAC_LCR_MASTER;
232 dac_reg |= AD193X_DAC_BCLK_MASTER;
233 break; 210 break;
234 case SND_SOC_DAIFMT_CBS_CFS: /* codec clk & frm slave */ 211 case SND_SOC_DAIFMT_CBS_CFS: /* codec clk & frm slave */
235 adc_reg2 &= ~AD193X_ADC_LCR_MASTER;
236 adc_reg2 &= ~AD193X_ADC_BCLK_MASTER;
237 dac_reg &= ~AD193X_DAC_LCR_MASTER;
238 dac_reg &= ~AD193X_DAC_BCLK_MASTER;
239 break; 212 break;
240 default: 213 default:
241 return -EINVAL; 214 return -EINVAL;
242 } 215 }
243 216
244 snd_soc_write(codec, AD193X_ADC_CTRL1, adc_reg1); 217 snd_soc_update_bits(codec, AD193X_ADC_CTRL1, AD193X_ADC_SERFMT_MASK,
245 snd_soc_write(codec, AD193X_ADC_CTRL2, adc_reg2); 218 adc_serfmt);
246 snd_soc_write(codec, AD193X_DAC_CTRL1, dac_reg); 219 snd_soc_update_bits(codec, AD193X_ADC_CTRL2, AD193X_ADC_FMT_MASK,
220 adc_fmt);
221 snd_soc_update_bits(codec, AD193X_DAC_CTRL1, AD193X_DAC_FMT_MASK,
222 dac_fmt);
247 223
248 return 0; 224 return 0;
249} 225}
diff --git a/sound/soc/codecs/ad193x.h b/sound/soc/codecs/ad193x.h
index 1507eaa425a3..473388049992 100644
--- a/sound/soc/codecs/ad193x.h
+++ b/sound/soc/codecs/ad193x.h
@@ -23,16 +23,14 @@
23#define AD193X_DAC_SERFMT_STEREO (0 << 6) 23#define AD193X_DAC_SERFMT_STEREO (0 << 6)
24#define AD193X_DAC_SERFMT_TDM (1 << 6) 24#define AD193X_DAC_SERFMT_TDM (1 << 6)
25#define AD193X_DAC_CTRL1 0x03 25#define AD193X_DAC_CTRL1 0x03
26#define AD193X_DAC_2_CHANNELS 0
27#define AD193X_DAC_4_CHANNELS 1
28#define AD193X_DAC_8_CHANNELS 2
29#define AD193X_DAC_16_CHANNELS 3
30#define AD193X_DAC_CHAN_SHFT 1 26#define AD193X_DAC_CHAN_SHFT 1
31#define AD193X_DAC_CHAN_MASK (3 << AD193X_DAC_CHAN_SHFT) 27#define AD193X_DAC_CHAN_MASK (3 << AD193X_DAC_CHAN_SHFT)
32#define AD193X_DAC_LCR_MASTER (1 << 4) 28#define AD193X_DAC_LCR_MASTER (1 << 4)
33#define AD193X_DAC_BCLK_MASTER (1 << 5) 29#define AD193X_DAC_BCLK_MASTER (1 << 5)
34#define AD193X_DAC_LEFT_HIGH (1 << 3) 30#define AD193X_DAC_LEFT_HIGH (1 << 3)
35#define AD193X_DAC_BCLK_INV (1 << 7) 31#define AD193X_DAC_BCLK_INV (1 << 7)
32#define AD193X_DAC_FMT_MASK (AD193X_DAC_LCR_MASTER | \
33 AD193X_DAC_BCLK_MASTER | AD193X_DAC_LEFT_HIGH | AD193X_DAC_BCLK_INV)
36#define AD193X_DAC_CTRL2 0x04 34#define AD193X_DAC_CTRL2 0x04
37#define AD193X_DAC_WORD_LEN_SHFT 3 35#define AD193X_DAC_WORD_LEN_SHFT 3
38#define AD193X_DAC_WORD_LEN_MASK 0x18 36#define AD193X_DAC_WORD_LEN_MASK 0x18
@@ -68,16 +66,19 @@
68#define AD193X_ADC_SERFMT_AUX (2 << 5) 66#define AD193X_ADC_SERFMT_AUX (2 << 5)
69#define AD193X_ADC_WORD_LEN_MASK 0x3 67#define AD193X_ADC_WORD_LEN_MASK 0x3
70#define AD193X_ADC_CTRL2 0x10 68#define AD193X_ADC_CTRL2 0x10
71#define AD193X_ADC_2_CHANNELS 0
72#define AD193X_ADC_4_CHANNELS 1
73#define AD193X_ADC_8_CHANNELS 2
74#define AD193X_ADC_16_CHANNELS 3
75#define AD193X_ADC_CHAN_SHFT 4 69#define AD193X_ADC_CHAN_SHFT 4
76#define AD193X_ADC_CHAN_MASK (3 << AD193X_ADC_CHAN_SHFT) 70#define AD193X_ADC_CHAN_MASK (3 << AD193X_ADC_CHAN_SHFT)
77#define AD193X_ADC_LCR_MASTER (1 << 3) 71#define AD193X_ADC_LCR_MASTER (1 << 3)
78#define AD193X_ADC_BCLK_MASTER (1 << 6) 72#define AD193X_ADC_BCLK_MASTER (1 << 6)
79#define AD193X_ADC_LEFT_HIGH (1 << 2) 73#define AD193X_ADC_LEFT_HIGH (1 << 2)
80#define AD193X_ADC_BCLK_INV (1 << 1) 74#define AD193X_ADC_BCLK_INV (1 << 1)
75#define AD193X_ADC_FMT_MASK (AD193X_ADC_LCR_MASTER | \
76 AD193X_ADC_BCLK_MASTER | AD193X_ADC_LEFT_HIGH | AD193X_ADC_BCLK_INV)
77
78#define AD193X_2_CHANNELS 0
79#define AD193X_4_CHANNELS 1
80#define AD193X_8_CHANNELS 2
81#define AD193X_16_CHANNELS 3
81 82
82#define AD193X_NUM_REGS 17 83#define AD193X_NUM_REGS 17
83 84