diff options
| author | John W. Linville <linville@tuxdriver.com> | 2011-09-19 15:00:16 -0400 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2011-09-19 15:00:16 -0400 |
| commit | b53d63ecce17c4ddf8636def9f6e8b865c3927f9 (patch) | |
| tree | 683ef774fcfb423fa35f61e4326d0ce3f6a7c283 | |
| parent | 765cf9976e937f1cfe9159bf4534967c8bf8eb6d (diff) | |
| parent | 12e62d6f7ec475e546b40bece2045da15d6c21ef (diff) | |
Merge branch 'master' of ssh://infradead/~/public_git/wireless-next into for-davem
137 files changed, 9860 insertions, 4594 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 579713ef7cfb..3891a12eb6a7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS | |||
| @@ -1246,6 +1246,14 @@ W: http://wireless.kernel.org/en/users/Drivers/ath5k | |||
| 1246 | S: Maintained | 1246 | S: Maintained |
| 1247 | F: drivers/net/wireless/ath/ath5k/ | 1247 | F: drivers/net/wireless/ath/ath5k/ |
| 1248 | 1248 | ||
| 1249 | ATHEROS ATH6KL WIRELESS DRIVER | ||
| 1250 | M: Kalle Valo <kvalo@qca.qualcomm.com> | ||
| 1251 | L: linux-wireless@vger.kernel.org | ||
| 1252 | W: http://wireless.kernel.org/en/users/Drivers/ath6kl | ||
| 1253 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath6kl.git | ||
| 1254 | S: Supported | ||
| 1255 | F: drivers/net/wireless/ath/ath6kl/ | ||
| 1256 | |||
| 1249 | ATHEROS ATH9K WIRELESS DRIVER | 1257 | ATHEROS ATH9K WIRELESS DRIVER |
| 1250 | M: "Luis R. Rodriguez" <mcgrof@qca.qualcomm.com> | 1258 | M: "Luis R. Rodriguez" <mcgrof@qca.qualcomm.com> |
| 1251 | M: Jouni Malinen <jouni@qca.qualcomm.com> | 1259 | M: Jouni Malinen <jouni@qca.qualcomm.com> |
| @@ -6145,12 +6153,6 @@ M: Jakub Schmidtke <sjakub@gmail.com> | |||
| 6145 | S: Odd Fixes | 6153 | S: Odd Fixes |
| 6146 | F: drivers/staging/asus_oled/ | 6154 | F: drivers/staging/asus_oled/ |
| 6147 | 6155 | ||
| 6148 | STAGING - ATHEROS ATH6KL WIRELESS DRIVER | ||
| 6149 | M: Luis R. Rodriguez <mcgrof@gmail.com> | ||
| 6150 | M: Naveen Singh <nsingh@atheros.com> | ||
| 6151 | S: Odd Fixes | ||
| 6152 | F: drivers/staging/ath6kl/ | ||
| 6153 | |||
| 6154 | STAGING - COMEDI | 6156 | STAGING - COMEDI |
| 6155 | M: Ian Abbott <abbotti@mev.co.uk> | 6157 | M: Ian Abbott <abbotti@mev.co.uk> |
| 6156 | M: Mori Hess <fmhess@users.sourceforge.net> | 6158 | M: Mori Hess <fmhess@users.sourceforge.net> |
diff --git a/drivers/bcma/sprom.c b/drivers/bcma/sprom.c index 166ed13ec066..d7292390d236 100644 --- a/drivers/bcma/sprom.c +++ b/drivers/bcma/sprom.c | |||
| @@ -133,6 +133,15 @@ static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom) | |||
| 133 | v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i]; | 133 | v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i]; |
| 134 | *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v); | 134 | *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v); |
| 135 | } | 135 | } |
| 136 | |||
| 137 | bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)]; | ||
| 138 | |||
| 139 | bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)]; | ||
| 140 | bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)]; | ||
| 141 | bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)]; | ||
| 142 | bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)]; | ||
| 143 | |||
| 144 | bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)]; | ||
| 136 | } | 145 | } |
| 137 | 146 | ||
| 138 | int bcma_sprom_get(struct bcma_bus *bus) | 147 | int bcma_sprom_get(struct bcma_bus *bus) |
diff --git a/drivers/net/wireless/ath/ath.h b/drivers/net/wireless/ath/ath.h index 9891fb605a01..4ed7f248a577 100644 --- a/drivers/net/wireless/ath/ath.h +++ b/drivers/net/wireless/ath/ath.h | |||
| @@ -140,9 +140,6 @@ struct ath_common { | |||
| 140 | u8 curbssid[ETH_ALEN]; | 140 | u8 curbssid[ETH_ALEN]; |
| 141 | u8 bssidmask[ETH_ALEN]; | 141 | u8 bssidmask[ETH_ALEN]; |
| 142 | 142 | ||
| 143 | u8 tx_chainmask; | ||
| 144 | u8 rx_chainmask; | ||
| 145 | |||
| 146 | u32 rx_bufsize; | 143 | u32 rx_bufsize; |
| 147 | 144 | ||
| 148 | u32 keymax; | 145 | u32 keymax; |
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_initvals.h b/drivers/net/wireless/ath/ath9k/ar5008_initvals.h index 234617c948a1..f81e7fc60a36 100644 --- a/drivers/net/wireless/ath/ath9k/ar5008_initvals.h +++ b/drivers/net/wireless/ath/ath9k/ar5008_initvals.h | |||
| @@ -14,70 +14,71 @@ | |||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | static const u32 ar5416Modes[][6] = { | 17 | static const u32 ar5416Modes[][5] = { |
| 18 | {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0}, | 18 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 19 | {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0}, | 19 | {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, |
| 20 | {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180}, | 20 | {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, |
| 21 | {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008}, | 21 | {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38}, |
| 22 | {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0}, | 22 | {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000}, |
| 23 | {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf}, | 23 | {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00}, |
| 24 | {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810}, | 24 | {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab}, |
| 25 | {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a}, | 25 | {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810}, |
| 26 | {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303}, | 26 | {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a}, |
| 27 | {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200}, | 27 | {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300}, |
| 28 | {0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, | 28 | {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200}, |
| 29 | {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001}, | 29 | {0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, |
| 30 | {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, | 30 | {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001}, |
| 31 | {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007}, | 31 | {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, |
| 32 | {0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0}, | 32 | {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007}, |
| 33 | {0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68}, | 33 | {0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0}, |
| 34 | {0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68}, | 34 | {0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68}, |
| 35 | {0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68}, | 35 | {0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68}, |
| 36 | {0x00009850, 0x6c48b4e0, 0x6d48b4e0, 0x6d48b0de, 0x6c48b0de, 0x6c48b0de}, | 36 | {0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68}, |
| 37 | {0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e}, | 37 | {0x00009850, 0x6c48b4e0, 0x6d48b4e0, 0x6d48b0de, 0x6c48b0de}, |
| 38 | {0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e}, | 38 | {0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e}, |
| 39 | {0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18}, | 39 | {0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e}, |
| 40 | {0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00}, | 40 | {0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18}, |
| 41 | {0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190}, | 41 | {0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00}, |
| 42 | {0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081}, | 42 | {0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190}, |
| 43 | {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0}, | 43 | {0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081}, |
| 44 | {0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134, 0x00000134}, | 44 | {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, |
| 45 | {0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b}, | 45 | {0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134}, |
| 46 | {0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020}, | 46 | {0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b}, |
| 47 | {0x00009960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80}, | 47 | {0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020}, |
| 48 | {0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80}, | 48 | {0x00009960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80}, |
| 49 | {0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80}, | 49 | {0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80}, |
| 50 | {0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120}, | 50 | {0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80}, |
| 51 | {0x000099bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00}, | 51 | {0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120}, |
| 52 | {0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be}, | 52 | {0x000099bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00}, |
| 53 | {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77}, | 53 | {0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be}, |
| 54 | {0x000099c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c}, | 54 | {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77}, |
| 55 | {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8}, | 55 | {0x000099c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c}, |
| 56 | {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384}, | 56 | {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8}, |
| 57 | {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 57 | {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384}, |
| 58 | {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 58 | {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 59 | {0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880}, | 59 | {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 60 | {0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788}, | 60 | {0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880}, |
| 61 | {0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120}, | 61 | {0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788}, |
| 62 | {0x0000b20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120}, | 62 | {0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120}, |
| 63 | {0x0000c20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120}, | 63 | {0x0000b20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120}, |
| 64 | {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a}, | 64 | {0x0000c20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120}, |
| 65 | {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000}, | 65 | {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a}, |
| 66 | {0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa}, | 66 | {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, |
| 67 | {0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000}, | 67 | {0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa}, |
| 68 | {0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402}, | 68 | {0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000}, |
| 69 | {0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06}, | 69 | {0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402}, |
| 70 | {0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b}, | 70 | {0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06}, |
| 71 | {0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b}, | 71 | {0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b}, |
| 72 | {0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a}, | 72 | {0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b}, |
| 73 | {0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf}, | 73 | {0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a}, |
| 74 | {0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f}, | 74 | {0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf}, |
| 75 | {0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f}, | 75 | {0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f}, |
| 76 | {0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f}, | 76 | {0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f}, |
| 77 | {0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000}, | 77 | {0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f}, |
| 78 | {0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 78 | {0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000}, |
| 79 | {0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 79 | {0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 80 | {0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 80 | {0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 81 | {0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 81 | }; | 82 | }; |
| 82 | 83 | ||
| 83 | static const u32 ar5416Common[][2] = { | 84 | static const u32 ar5416Common[][2] = { |
| @@ -668,6 +669,6 @@ static const u32 ar5416Addac[][2] = { | |||
| 668 | {0x0000989c, 0x00000000}, | 669 | {0x0000989c, 0x00000000}, |
| 669 | {0x0000989c, 0x00000000}, | 670 | {0x0000989c, 0x00000000}, |
| 670 | {0x0000989c, 0x00000000}, | 671 | {0x0000989c, 0x00000000}, |
| 671 | {0x000098cc, 0x00000000}, | 672 | {0x000098c4, 0x00000000}, |
| 672 | }; | 673 | }; |
| 673 | 674 | ||
diff --git a/drivers/net/wireless/ath/ath9k/ar9001_initvals.h b/drivers/net/wireless/ath/ath9k/ar9001_initvals.h index 6d2e2f3303f9..e8bdc75405f1 100644 --- a/drivers/net/wireless/ath/ath9k/ar9001_initvals.h +++ b/drivers/net/wireless/ath/ath9k/ar9001_initvals.h | |||
| @@ -14,73 +14,74 @@ | |||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | static const u32 ar5416Modes_9100[][6] = { | 17 | static const u32 ar5416Modes_9100[][5] = { |
| 18 | {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0}, | 18 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 19 | {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0}, | 19 | {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, |
| 20 | {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180}, | 20 | {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, |
| 21 | {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008}, | 21 | {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38}, |
| 22 | {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0}, | 22 | {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000}, |
| 23 | {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf}, | 23 | {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00}, |
| 24 | {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810}, | 24 | {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab}, |
| 25 | {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a}, | 25 | {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810}, |
| 26 | {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303}, | 26 | {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a}, |
| 27 | {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200}, | 27 | {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300}, |
| 28 | {0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, | 28 | {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200}, |
| 29 | {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001}, | 29 | {0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, |
| 30 | {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, | 30 | {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001}, |
| 31 | {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007}, | 31 | {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, |
| 32 | {0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0}, | 32 | {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007}, |
| 33 | {0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68}, | 33 | {0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0}, |
| 34 | {0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68}, | 34 | {0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68}, |
| 35 | {0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68}, | 35 | {0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68}, |
| 36 | {0x00009850, 0x6c48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6c48b0e2, 0x6c48b0e2}, | 36 | {0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68}, |
| 37 | {0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e}, | 37 | {0x00009850, 0x6c48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6c48b0e2}, |
| 38 | {0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e}, | 38 | {0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e}, |
| 39 | {0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18}, | 39 | {0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e}, |
| 40 | {0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00}, | 40 | {0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20}, |
| 41 | {0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0}, | 41 | {0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00}, |
| 42 | {0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081}, | 42 | {0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0}, |
| 43 | {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0}, | 43 | {0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081}, |
| 44 | {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016}, | 44 | {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, |
| 45 | {0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d}, | 45 | {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b}, |
| 46 | {0x00009940, 0x00750604, 0x00754604, 0xfff81204, 0xfff81204, 0xfff81204}, | 46 | {0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d}, |
| 47 | {0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020}, | 47 | {0x00009940, 0x00750604, 0x00754604, 0xfff81204, 0xfff81204}, |
| 48 | {0x00009954, 0x5f3ca3de, 0x5f3ca3de, 0xe250a51e, 0xe250a51e, 0xe250a51e}, | 48 | {0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020}, |
| 49 | {0x00009958, 0x2108ecff, 0x2108ecff, 0x3388ffff, 0x3388ffff, 0x3388ffff}, | 49 | {0x00009954, 0x5f3ca3de, 0x5f3ca3de, 0xe250a51e, 0xe250a51e}, |
| 50 | {0x00009960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0}, | 50 | {0x00009958, 0x2108ecff, 0x2108ecff, 0x3388ffff, 0x3388ffff}, |
| 51 | {0x0000a960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0}, | 51 | {0x00009960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0}, |
| 52 | {0x0000b960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0}, | 52 | {0x0000a960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0}, |
| 53 | {0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120}, | 53 | {0x0000b960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0}, |
| 54 | {0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a1000, 0x001a0c00, 0x001a0c00}, | 54 | {0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120}, |
| 55 | {0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be}, | 55 | {0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a1000, 0x001a0c00}, |
| 56 | {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77}, | 56 | {0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be}, |
| 57 | {0x000099c8, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329}, | 57 | {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77}, |
| 58 | {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8}, | 58 | {0x000099c8, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329}, |
| 59 | {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384}, | 59 | {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8}, |
| 60 | {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 60 | {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384}, |
| 61 | {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 61 | {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 62 | {0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880}, | 62 | {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 63 | {0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788}, | 63 | {0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880}, |
| 64 | {0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120}, | 64 | {0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788}, |
| 65 | {0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120}, | 65 | {0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120}, |
| 66 | {0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120}, | 66 | {0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120}, |
| 67 | {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a}, | 67 | {0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120}, |
| 68 | {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000}, | 68 | {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a}, |
| 69 | {0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa}, | 69 | {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, |
| 70 | {0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000}, | 70 | {0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa}, |
| 71 | {0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402}, | 71 | {0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000}, |
| 72 | {0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06}, | 72 | {0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402}, |
| 73 | {0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b}, | 73 | {0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06}, |
| 74 | {0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b}, | 74 | {0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b}, |
| 75 | {0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a}, | 75 | {0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b}, |
| 76 | {0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf}, | 76 | {0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a}, |
| 77 | {0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f}, | 77 | {0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf}, |
| 78 | {0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f}, | 78 | {0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f}, |
| 79 | {0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f}, | 79 | {0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f}, |
| 80 | {0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000}, | 80 | {0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f}, |
| 81 | {0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 81 | {0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000}, |
| 82 | {0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 82 | {0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 83 | {0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 83 | {0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 84 | {0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 84 | }; | 85 | }; |
| 85 | 86 | ||
| 86 | static const u32 ar5416Common_9100[][2] = { | 87 | static const u32 ar5416Common_9100[][2] = { |
| @@ -666,71 +667,72 @@ static const u32 ar5416Addac_9100[][2] = { | |||
| 666 | {0x000098cc, 0x00000000}, | 667 | {0x000098cc, 0x00000000}, |
| 667 | }; | 668 | }; |
| 668 | 669 | ||
| 669 | static const u32 ar5416Modes_9160[][6] = { | 670 | static const u32 ar5416Modes_9160[][5] = { |
| 670 | {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0}, | 671 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 671 | {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0}, | 672 | {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, |
| 672 | {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180}, | 673 | {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, |
| 673 | {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008}, | 674 | {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38}, |
| 674 | {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0}, | 675 | {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000}, |
| 675 | {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf}, | 676 | {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00}, |
| 676 | {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810}, | 677 | {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab}, |
| 677 | {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a}, | 678 | {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810}, |
| 678 | {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303}, | 679 | {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a}, |
| 679 | {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200}, | 680 | {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300}, |
| 680 | {0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, | 681 | {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200}, |
| 681 | {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001}, | 682 | {0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, |
| 682 | {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, | 683 | {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001}, |
| 683 | {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007}, | 684 | {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, |
| 684 | {0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0}, | 685 | {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007}, |
| 685 | {0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68}, | 686 | {0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0}, |
| 686 | {0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68}, | 687 | {0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68}, |
| 687 | {0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68}, | 688 | {0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68}, |
| 688 | {0x00009850, 0x6c48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6c48b0e2, 0x6c48b0e2}, | 689 | {0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68}, |
| 689 | {0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e}, | 690 | {0x00009850, 0x6c48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6c48b0e2}, |
| 690 | {0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e}, | 691 | {0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e}, |
| 691 | {0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18}, | 692 | {0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e}, |
| 692 | {0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00}, | 693 | {0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20}, |
| 693 | {0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0}, | 694 | {0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00}, |
| 694 | {0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081}, | 695 | {0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0}, |
| 695 | {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0}, | 696 | {0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081}, |
| 696 | {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016}, | 697 | {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, |
| 697 | {0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d}, | 698 | {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b}, |
| 698 | {0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020}, | 699 | {0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d}, |
| 699 | {0x00009960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40}, | 700 | {0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020}, |
| 700 | {0x0000a960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40}, | 701 | {0x00009960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40}, |
| 701 | {0x0000b960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40}, | 702 | {0x0000a960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40}, |
| 702 | {0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120}, | 703 | {0x0000b960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40}, |
| 703 | {0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce}, | 704 | {0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120}, |
| 704 | {0x000099bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00, 0x001a0c00}, | 705 | {0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce}, |
| 705 | {0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be}, | 706 | {0x000099bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00}, |
| 706 | {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77}, | 707 | {0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be}, |
| 707 | {0x000099c8, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329}, | 708 | {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77}, |
| 708 | {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8}, | 709 | {0x000099c8, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329}, |
| 709 | {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384}, | 710 | {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8}, |
| 710 | {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 711 | {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384}, |
| 711 | {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 712 | {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 712 | {0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880}, | 713 | {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 713 | {0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788}, | 714 | {0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880}, |
| 714 | {0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120}, | 715 | {0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788}, |
| 715 | {0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120}, | 716 | {0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120}, |
| 716 | {0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120}, | 717 | {0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120}, |
| 717 | {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a}, | 718 | {0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120}, |
| 718 | {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000}, | 719 | {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a}, |
| 719 | {0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa}, | 720 | {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, |
| 720 | {0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000}, | 721 | {0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa}, |
| 721 | {0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402}, | 722 | {0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000}, |
| 722 | {0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06}, | 723 | {0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402}, |
| 723 | {0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b}, | 724 | {0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06}, |
| 724 | {0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b}, | 725 | {0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b}, |
| 725 | {0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a}, | 726 | {0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b}, |
| 726 | {0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf}, | 727 | {0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a}, |
| 727 | {0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f}, | 728 | {0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf}, |
| 728 | {0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f}, | 729 | {0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f}, |
| 729 | {0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f}, | 730 | {0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f}, |
| 730 | {0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000}, | 731 | {0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f}, |
| 731 | {0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 732 | {0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000}, |
| 732 | {0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 733 | {0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 733 | {0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 734 | {0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 735 | {0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 734 | }; | 736 | }; |
| 735 | 737 | ||
| 736 | static const u32 ar5416Common_9160[][2] = { | 738 | static const u32 ar5416Common_9160[][2] = { |
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c index b54ab78fb092..626d547d2f06 100644 --- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c | |||
| @@ -30,7 +30,7 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah) | |||
| 30 | { | 30 | { |
| 31 | if (AR_SREV_9271(ah)) { | 31 | if (AR_SREV_9271(ah)) { |
| 32 | INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271, | 32 | INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271, |
| 33 | ARRAY_SIZE(ar9271Modes_9271), 6); | 33 | ARRAY_SIZE(ar9271Modes_9271), 5); |
| 34 | INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, | 34 | INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, |
| 35 | ARRAY_SIZE(ar9271Common_9271), 2); | 35 | ARRAY_SIZE(ar9271Common_9271), 2); |
| 36 | INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271, | 36 | INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271, |
| @@ -41,21 +41,21 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah) | |||
| 41 | ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2); | 41 | ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2); |
| 42 | INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only, | 42 | INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only, |
| 43 | ar9271Modes_9271_1_0_only, | 43 | ar9271Modes_9271_1_0_only, |
| 44 | ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6); | 44 | ARRAY_SIZE(ar9271Modes_9271_1_0_only), 5); |
| 45 | INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg, | 45 | INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg, |
| 46 | ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6); | 46 | ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 5); |
| 47 | INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271, | 47 | INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271, |
| 48 | ar9271Modes_high_power_tx_gain_9271, | 48 | ar9271Modes_high_power_tx_gain_9271, |
| 49 | ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6); | 49 | ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 5); |
| 50 | INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271, | 50 | INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271, |
| 51 | ar9271Modes_normal_power_tx_gain_9271, | 51 | ar9271Modes_normal_power_tx_gain_9271, |
| 52 | ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6); | 52 | ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 5); |
| 53 | return; | 53 | return; |
| 54 | } | 54 | } |
| 55 | 55 | ||
| 56 | if (AR_SREV_9287_11_OR_LATER(ah)) { | 56 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
| 57 | INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1, | 57 | INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1, |
| 58 | ARRAY_SIZE(ar9287Modes_9287_1_1), 6); | 58 | ARRAY_SIZE(ar9287Modes_9287_1_1), 5); |
| 59 | INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1, | 59 | INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1, |
| 60 | ARRAY_SIZE(ar9287Common_9287_1_1), 2); | 60 | ARRAY_SIZE(ar9287Common_9287_1_1), 2); |
| 61 | if (ah->config.pcie_clock_req) | 61 | if (ah->config.pcie_clock_req) |
| @@ -71,7 +71,7 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah) | |||
| 71 | 71 | ||
| 72 | 72 | ||
| 73 | INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, | 73 | INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, |
| 74 | ARRAY_SIZE(ar9285Modes_9285_1_2), 6); | 74 | ARRAY_SIZE(ar9285Modes_9285_1_2), 5); |
| 75 | INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, | 75 | INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, |
| 76 | ARRAY_SIZE(ar9285Common_9285_1_2), 2); | 76 | ARRAY_SIZE(ar9285Common_9285_1_2), 2); |
| 77 | 77 | ||
| @@ -87,7 +87,7 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah) | |||
| 87 | } | 87 | } |
| 88 | } else if (AR_SREV_9280_20_OR_LATER(ah)) { | 88 | } else if (AR_SREV_9280_20_OR_LATER(ah)) { |
| 89 | INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, | 89 | INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, |
| 90 | ARRAY_SIZE(ar9280Modes_9280_2), 6); | 90 | ARRAY_SIZE(ar9280Modes_9280_2), 5); |
| 91 | INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, | 91 | INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, |
| 92 | ARRAY_SIZE(ar9280Common_9280_2), 2); | 92 | ARRAY_SIZE(ar9280Common_9280_2), 2); |
| 93 | 93 | ||
| @@ -105,7 +105,7 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah) | |||
| 105 | ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); | 105 | ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); |
| 106 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { | 106 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { |
| 107 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, | 107 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, |
| 108 | ARRAY_SIZE(ar5416Modes_9160), 6); | 108 | ARRAY_SIZE(ar5416Modes_9160), 5); |
| 109 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, | 109 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, |
| 110 | ARRAY_SIZE(ar5416Common_9160), 2); | 110 | ARRAY_SIZE(ar5416Common_9160), 2); |
| 111 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160, | 111 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160, |
| @@ -134,7 +134,7 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah) | |||
| 134 | } | 134 | } |
| 135 | } else if (AR_SREV_9100_OR_LATER(ah)) { | 135 | } else if (AR_SREV_9100_OR_LATER(ah)) { |
| 136 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, | 136 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, |
| 137 | ARRAY_SIZE(ar5416Modes_9100), 6); | 137 | ARRAY_SIZE(ar5416Modes_9100), 5); |
| 138 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, | 138 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, |
| 139 | ARRAY_SIZE(ar5416Common_9100), 2); | 139 | ARRAY_SIZE(ar5416Common_9100), 2); |
| 140 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100, | 140 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100, |
| @@ -157,7 +157,7 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah) | |||
| 157 | ARRAY_SIZE(ar5416Addac_9100), 2); | 157 | ARRAY_SIZE(ar5416Addac_9100), 2); |
| 158 | } else { | 158 | } else { |
| 159 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, | 159 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, |
| 160 | ARRAY_SIZE(ar5416Modes), 6); | 160 | ARRAY_SIZE(ar5416Modes), 5); |
| 161 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, | 161 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, |
| 162 | ARRAY_SIZE(ar5416Common), 2); | 162 | ARRAY_SIZE(ar5416Common), 2); |
| 163 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, | 163 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, |
| @@ -207,19 +207,19 @@ static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah) | |||
| 207 | if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) | 207 | if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) |
| 208 | INIT_INI_ARRAY(&ah->iniModesRxGain, | 208 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 209 | ar9280Modes_backoff_13db_rxgain_9280_2, | 209 | ar9280Modes_backoff_13db_rxgain_9280_2, |
| 210 | ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); | 210 | ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 5); |
| 211 | else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) | 211 | else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) |
| 212 | INIT_INI_ARRAY(&ah->iniModesRxGain, | 212 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 213 | ar9280Modes_backoff_23db_rxgain_9280_2, | 213 | ar9280Modes_backoff_23db_rxgain_9280_2, |
| 214 | ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); | 214 | ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 5); |
| 215 | else | 215 | else |
| 216 | INIT_INI_ARRAY(&ah->iniModesRxGain, | 216 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 217 | ar9280Modes_original_rxgain_9280_2, | 217 | ar9280Modes_original_rxgain_9280_2, |
| 218 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); | 218 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5); |
| 219 | } else { | 219 | } else { |
| 220 | INIT_INI_ARRAY(&ah->iniModesRxGain, | 220 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 221 | ar9280Modes_original_rxgain_9280_2, | 221 | ar9280Modes_original_rxgain_9280_2, |
| 222 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); | 222 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5); |
| 223 | } | 223 | } |
| 224 | } | 224 | } |
| 225 | 225 | ||
| @@ -234,15 +234,15 @@ static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah) | |||
| 234 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) | 234 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) |
| 235 | INIT_INI_ARRAY(&ah->iniModesTxGain, | 235 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 236 | ar9280Modes_high_power_tx_gain_9280_2, | 236 | ar9280Modes_high_power_tx_gain_9280_2, |
| 237 | ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); | 237 | ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 5); |
| 238 | else | 238 | else |
| 239 | INIT_INI_ARRAY(&ah->iniModesTxGain, | 239 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 240 | ar9280Modes_original_tx_gain_9280_2, | 240 | ar9280Modes_original_tx_gain_9280_2, |
| 241 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); | 241 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5); |
| 242 | } else { | 242 | } else { |
| 243 | INIT_INI_ARRAY(&ah->iniModesTxGain, | 243 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 244 | ar9280Modes_original_tx_gain_9280_2, | 244 | ar9280Modes_original_tx_gain_9280_2, |
| 245 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); | 245 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5); |
| 246 | } | 246 | } |
| 247 | } | 247 | } |
| 248 | 248 | ||
| @@ -251,14 +251,14 @@ static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah) | |||
| 251 | if (AR_SREV_9287_11_OR_LATER(ah)) | 251 | if (AR_SREV_9287_11_OR_LATER(ah)) |
| 252 | INIT_INI_ARRAY(&ah->iniModesRxGain, | 252 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 253 | ar9287Modes_rx_gain_9287_1_1, | 253 | ar9287Modes_rx_gain_9287_1_1, |
| 254 | ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6); | 254 | ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 5); |
| 255 | else if (AR_SREV_9280_20(ah)) | 255 | else if (AR_SREV_9280_20(ah)) |
| 256 | ar9280_20_hw_init_rxgain_ini(ah); | 256 | ar9280_20_hw_init_rxgain_ini(ah); |
| 257 | 257 | ||
| 258 | if (AR_SREV_9287_11_OR_LATER(ah)) { | 258 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
| 259 | INIT_INI_ARRAY(&ah->iniModesTxGain, | 259 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 260 | ar9287Modes_tx_gain_9287_1_1, | 260 | ar9287Modes_tx_gain_9287_1_1, |
| 261 | ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6); | 261 | ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 5); |
| 262 | } else if (AR_SREV_9280_20(ah)) { | 262 | } else if (AR_SREV_9280_20(ah)) { |
| 263 | ar9280_20_hw_init_txgain_ini(ah); | 263 | ar9280_20_hw_init_txgain_ini(ah); |
| 264 | } else if (AR_SREV_9285_12_OR_LATER(ah)) { | 264 | } else if (AR_SREV_9285_12_OR_LATER(ah)) { |
| @@ -270,24 +270,24 @@ static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah) | |||
| 270 | INIT_INI_ARRAY(&ah->iniModesTxGain, | 270 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 271 | ar9285Modes_XE2_0_high_power, | 271 | ar9285Modes_XE2_0_high_power, |
| 272 | ARRAY_SIZE( | 272 | ARRAY_SIZE( |
| 273 | ar9285Modes_XE2_0_high_power), 6); | 273 | ar9285Modes_XE2_0_high_power), 5); |
| 274 | } else { | 274 | } else { |
| 275 | INIT_INI_ARRAY(&ah->iniModesTxGain, | 275 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 276 | ar9285Modes_high_power_tx_gain_9285_1_2, | 276 | ar9285Modes_high_power_tx_gain_9285_1_2, |
| 277 | ARRAY_SIZE( | 277 | ARRAY_SIZE( |
| 278 | ar9285Modes_high_power_tx_gain_9285_1_2), 6); | 278 | ar9285Modes_high_power_tx_gain_9285_1_2), 5); |
| 279 | } | 279 | } |
| 280 | } else { | 280 | } else { |
| 281 | if (AR_SREV_9285E_20(ah)) { | 281 | if (AR_SREV_9285E_20(ah)) { |
| 282 | INIT_INI_ARRAY(&ah->iniModesTxGain, | 282 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 283 | ar9285Modes_XE2_0_normal_power, | 283 | ar9285Modes_XE2_0_normal_power, |
| 284 | ARRAY_SIZE( | 284 | ARRAY_SIZE( |
| 285 | ar9285Modes_XE2_0_normal_power), 6); | 285 | ar9285Modes_XE2_0_normal_power), 5); |
| 286 | } else { | 286 | } else { |
| 287 | INIT_INI_ARRAY(&ah->iniModesTxGain, | 287 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 288 | ar9285Modes_original_tx_gain_9285_1_2, | 288 | ar9285Modes_original_tx_gain_9285_1_2, |
| 289 | ARRAY_SIZE( | 289 | ARRAY_SIZE( |
| 290 | ar9285Modes_original_tx_gain_9285_1_2), 6); | 290 | ar9285Modes_original_tx_gain_9285_1_2), 5); |
| 291 | } | 291 | } |
| 292 | } | 292 | } |
| 293 | } | 293 | } |
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_initvals.h b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h index 7573257731b6..863db321070d 100644 --- a/drivers/net/wireless/ath/ath9k/ar9002_initvals.h +++ b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h | |||
| @@ -14,53 +14,54 @@ | |||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | static const u32 ar9280Modes_9280_2[][6] = { | 17 | static const u32 ar9280Modes_9280_2[][5] = { |
| 18 | {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0}, | 18 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 19 | {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0}, | 19 | {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, |
| 20 | {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180}, | 20 | {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, |
| 21 | {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008}, | 21 | {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38}, |
| 22 | {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0}, | 22 | {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 23 | {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f}, | 23 | {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00}, |
| 24 | {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810}, | 24 | {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b}, |
| 25 | {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a}, | 25 | {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810}, |
| 26 | {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880}, | 26 | {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a}, |
| 27 | {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303}, | 27 | {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, |
| 28 | {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200}, | 28 | {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300}, |
| 29 | {0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e}, | 29 | {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200}, |
| 30 | {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001}, | 30 | {0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e}, |
| 31 | {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, | 31 | {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001}, |
| 32 | {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007}, | 32 | {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, |
| 33 | {0x00009840, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e, 0x206a012e}, | 33 | {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007}, |
| 34 | {0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0}, | 34 | {0x00009840, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e}, |
| 35 | {0x00009850, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2}, | 35 | {0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0}, |
| 36 | {0x00009858, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e}, | 36 | {0x00009850, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2}, |
| 37 | {0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e}, | 37 | {0x00009858, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e}, |
| 38 | {0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18}, | 38 | {0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e}, |
| 39 | {0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00}, | 39 | {0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20}, |
| 40 | {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, | 40 | {0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00}, |
| 41 | {0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881}, | 41 | {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, |
| 42 | {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0}, | 42 | {0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881}, |
| 43 | {0x00009918, 0x0000000a, 0x00000014, 0x00000268, 0x0000000b, 0x00000016}, | 43 | {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, |
| 44 | {0x00009924, 0xd00a8a0b, 0xd00a8a0b, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d}, | 44 | {0x00009918, 0x0000000a, 0x00000014, 0x00000268, 0x0000000b}, |
| 45 | {0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010}, | 45 | {0x00009924, 0xd00a8a0b, 0xd00a8a0b, 0xd00a8a0d, 0xd00a8a0d}, |
| 46 | {0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010}, | 46 | {0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010}, |
| 47 | {0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010}, | 47 | {0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010}, |
| 48 | {0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210}, | 48 | {0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010}, |
| 49 | {0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce}, | 49 | {0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210}, |
| 50 | {0x000099b8, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c}, | 50 | {0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce}, |
| 51 | {0x000099bc, 0x00000a00, 0x00000a00, 0x00000c00, 0x00000c00, 0x00000c00}, | 51 | {0x000099b8, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c}, |
| 52 | {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, | 52 | {0x000099bc, 0x00000a00, 0x00000a00, 0x00000c00, 0x00000c00}, |
| 53 | {0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444}, | 53 | {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, |
| 54 | {0x0000a20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019}, | 54 | {0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444}, |
| 55 | {0x0000b20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019}, | 55 | {0x0000a20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019}, |
| 56 | {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a}, | 56 | {0x0000b20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019}, |
| 57 | {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000}, | 57 | {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a}, |
| 58 | {0x0000a23c, 0x13c88000, 0x13c88000, 0x13c88001, 0x13c88000, 0x13c88000}, | 58 | {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, |
| 59 | {0x0000a250, 0x001ff000, 0x001ff000, 0x0004a000, 0x0004a000, 0x0004a000}, | 59 | {0x0000a23c, 0x13c88000, 0x13c88000, 0x13c88001, 0x13c88000}, |
| 60 | {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e}, | 60 | {0x0000a250, 0x001ff000, 0x001ff000, 0x0004a000, 0x0004a000}, |
| 61 | {0x0000a388, 0x0c000000, 0x0c000000, 0x08000000, 0x0c000000, 0x0c000000}, | 61 | {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e}, |
| 62 | {0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 62 | {0x0000a388, 0x0c000000, 0x0c000000, 0x08000000, 0x0c000000}, |
| 63 | {0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000}, | 63 | {0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 64 | {0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000}, | ||
| 64 | }; | 65 | }; |
| 65 | 66 | ||
| 66 | static const u32 ar9280Common_9280_2[][2] = { | 67 | static const u32 ar9280Common_9280_2[][2] = { |
| @@ -424,471 +425,476 @@ static const u32 ar9280Modes_fast_clock_9280_2[][3] = { | |||
| 424 | {0x00009918, 0x0000000b, 0x00000016}, | 425 | {0x00009918, 0x0000000b, 0x00000016}, |
| 425 | }; | 426 | }; |
| 426 | 427 | ||
| 427 | static const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][6] = { | 428 | static const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][5] = { |
| 428 | {0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290}, | 429 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 429 | {0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300}, | 430 | {0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290}, |
| 430 | {0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304}, | 431 | {0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300}, |
| 431 | {0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308}, | 432 | {0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304}, |
| 432 | {0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c}, | 433 | {0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308}, |
| 433 | {0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000}, | 434 | {0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c}, |
| 434 | {0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004}, | 435 | {0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000}, |
| 435 | {0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008}, | 436 | {0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004}, |
| 436 | {0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c}, | 437 | {0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008}, |
| 437 | {0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080}, | 438 | {0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c}, |
| 438 | {0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084}, | 439 | {0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080}, |
| 439 | {0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088}, | 440 | {0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084}, |
| 440 | {0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c}, | 441 | {0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088}, |
| 441 | {0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100}, | 442 | {0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c}, |
| 442 | {0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104}, | 443 | {0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100}, |
| 443 | {0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108}, | 444 | {0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104}, |
| 444 | {0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c}, | 445 | {0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108}, |
| 445 | {0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110}, | 446 | {0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c}, |
| 446 | {0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114}, | 447 | {0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110}, |
| 447 | {0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180}, | 448 | {0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114}, |
| 448 | {0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184}, | 449 | {0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180}, |
| 449 | {0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188}, | 450 | {0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184}, |
| 450 | {0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c}, | 451 | {0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188}, |
| 451 | {0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190}, | 452 | {0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c}, |
| 452 | {0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194}, | 453 | {0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190}, |
| 453 | {0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0}, | 454 | {0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194}, |
| 454 | {0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c}, | 455 | {0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0}, |
| 455 | {0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8}, | 456 | {0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c}, |
| 456 | {0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284}, | 457 | {0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8}, |
| 457 | {0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288}, | 458 | {0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284}, |
| 458 | {0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224}, | 459 | {0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288}, |
| 459 | {0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290}, | 460 | {0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224}, |
| 460 | {0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300}, | 461 | {0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290}, |
| 461 | {0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304}, | 462 | {0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300}, |
| 462 | {0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308}, | 463 | {0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304}, |
| 463 | {0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c}, | 464 | {0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308}, |
| 464 | {0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380}, | 465 | {0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c}, |
| 465 | {0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384}, | 466 | {0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380}, |
| 466 | {0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700}, | 467 | {0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384}, |
| 467 | {0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704}, | 468 | {0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700}, |
| 468 | {0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708}, | 469 | {0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704}, |
| 469 | {0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c}, | 470 | {0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708}, |
| 470 | {0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780}, | 471 | {0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c}, |
| 471 | {0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784}, | 472 | {0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780}, |
| 472 | {0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00}, | 473 | {0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784}, |
| 473 | {0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04}, | 474 | {0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00}, |
| 474 | {0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08}, | 475 | {0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04}, |
| 475 | {0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c}, | 476 | {0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08}, |
| 476 | {0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b10, 0x00008b10, 0x00008b10}, | 477 | {0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c}, |
| 477 | {0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b80, 0x00008b80, 0x00008b80}, | 478 | {0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b10, 0x00008b10}, |
| 478 | {0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b84, 0x00008b84, 0x00008b84}, | 479 | {0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b80, 0x00008b80}, |
| 479 | {0x00009acc, 0x0000b380, 0x0000b380, 0x00008b88, 0x00008b88, 0x00008b88}, | 480 | {0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b84, 0x00008b84}, |
| 480 | {0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b8c, 0x00008b8c, 0x00008b8c}, | 481 | {0x00009acc, 0x0000b380, 0x0000b380, 0x00008b88, 0x00008b88}, |
| 481 | {0x00009ad4, 0x0000b388, 0x0000b388, 0x00008b90, 0x00008b90, 0x00008b90}, | 482 | {0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b8c, 0x00008b8c}, |
| 482 | {0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008b94, 0x00008b94, 0x00008b94}, | 483 | {0x00009ad4, 0x0000b388, 0x0000b388, 0x00008b90, 0x00008b90}, |
| 483 | {0x00009adc, 0x0000b390, 0x0000b390, 0x00008b98, 0x00008b98, 0x00008b98}, | 484 | {0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008b94, 0x00008b94}, |
| 484 | {0x00009ae0, 0x0000b394, 0x0000b394, 0x00008ba4, 0x00008ba4, 0x00008ba4}, | 485 | {0x00009adc, 0x0000b390, 0x0000b390, 0x00008b98, 0x00008b98}, |
| 485 | {0x00009ae4, 0x0000b398, 0x0000b398, 0x00008ba8, 0x00008ba8, 0x00008ba8}, | 486 | {0x00009ae0, 0x0000b394, 0x0000b394, 0x00008ba4, 0x00008ba4}, |
| 486 | {0x00009ae8, 0x0000b780, 0x0000b780, 0x00008bac, 0x00008bac, 0x00008bac}, | 487 | {0x00009ae4, 0x0000b398, 0x0000b398, 0x00008ba8, 0x00008ba8}, |
| 487 | {0x00009aec, 0x0000b784, 0x0000b784, 0x00008bb0, 0x00008bb0, 0x00008bb0}, | 488 | {0x00009ae8, 0x0000b780, 0x0000b780, 0x00008bac, 0x00008bac}, |
| 488 | {0x00009af0, 0x0000b788, 0x0000b788, 0x00008bb4, 0x00008bb4, 0x00008bb4}, | 489 | {0x00009aec, 0x0000b784, 0x0000b784, 0x00008bb0, 0x00008bb0}, |
| 489 | {0x00009af4, 0x0000b78c, 0x0000b78c, 0x00008ba1, 0x00008ba1, 0x00008ba1}, | 490 | {0x00009af0, 0x0000b788, 0x0000b788, 0x00008bb4, 0x00008bb4}, |
| 490 | {0x00009af8, 0x0000b790, 0x0000b790, 0x00008ba5, 0x00008ba5, 0x00008ba5}, | 491 | {0x00009af4, 0x0000b78c, 0x0000b78c, 0x00008ba1, 0x00008ba1}, |
| 491 | {0x00009afc, 0x0000b794, 0x0000b794, 0x00008ba9, 0x00008ba9, 0x00008ba9}, | 492 | {0x00009af8, 0x0000b790, 0x0000b790, 0x00008ba5, 0x00008ba5}, |
| 492 | {0x00009b00, 0x0000b798, 0x0000b798, 0x00008bad, 0x00008bad, 0x00008bad}, | 493 | {0x00009afc, 0x0000b794, 0x0000b794, 0x00008ba9, 0x00008ba9}, |
| 493 | {0x00009b04, 0x0000d784, 0x0000d784, 0x00008bb1, 0x00008bb1, 0x00008bb1}, | 494 | {0x00009b00, 0x0000b798, 0x0000b798, 0x00008bad, 0x00008bad}, |
| 494 | {0x00009b08, 0x0000d788, 0x0000d788, 0x00008bb5, 0x00008bb5, 0x00008bb5}, | 495 | {0x00009b04, 0x0000d784, 0x0000d784, 0x00008bb1, 0x00008bb1}, |
| 495 | {0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00008ba2, 0x00008ba2, 0x00008ba2}, | 496 | {0x00009b08, 0x0000d788, 0x0000d788, 0x00008bb5, 0x00008bb5}, |
| 496 | {0x00009b10, 0x0000d790, 0x0000d790, 0x00008ba6, 0x00008ba6, 0x00008ba6}, | 497 | {0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00008ba2, 0x00008ba2}, |
| 497 | {0x00009b14, 0x0000f780, 0x0000f780, 0x00008baa, 0x00008baa, 0x00008baa}, | 498 | {0x00009b10, 0x0000d790, 0x0000d790, 0x00008ba6, 0x00008ba6}, |
| 498 | {0x00009b18, 0x0000f784, 0x0000f784, 0x00008bae, 0x00008bae, 0x00008bae}, | 499 | {0x00009b14, 0x0000f780, 0x0000f780, 0x00008baa, 0x00008baa}, |
| 499 | {0x00009b1c, 0x0000f788, 0x0000f788, 0x00008bb2, 0x00008bb2, 0x00008bb2}, | 500 | {0x00009b18, 0x0000f784, 0x0000f784, 0x00008bae, 0x00008bae}, |
| 500 | {0x00009b20, 0x0000f78c, 0x0000f78c, 0x00008bb6, 0x00008bb6, 0x00008bb6}, | 501 | {0x00009b1c, 0x0000f788, 0x0000f788, 0x00008bb2, 0x00008bb2}, |
| 501 | {0x00009b24, 0x0000f790, 0x0000f790, 0x00008ba3, 0x00008ba3, 0x00008ba3}, | 502 | {0x00009b20, 0x0000f78c, 0x0000f78c, 0x00008bb6, 0x00008bb6}, |
| 502 | {0x00009b28, 0x0000f794, 0x0000f794, 0x00008ba7, 0x00008ba7, 0x00008ba7}, | 503 | {0x00009b24, 0x0000f790, 0x0000f790, 0x00008ba3, 0x00008ba3}, |
| 503 | {0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x00008bab, 0x00008bab, 0x00008bab}, | 504 | {0x00009b28, 0x0000f794, 0x0000f794, 0x00008ba7, 0x00008ba7}, |
| 504 | {0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00008baf, 0x00008baf, 0x00008baf}, | 505 | {0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x00008bab, 0x00008bab}, |
| 505 | {0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00008bb3, 0x00008bb3, 0x00008bb3}, | 506 | {0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00008baf, 0x00008baf}, |
| 506 | {0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00008bb7, 0x00008bb7, 0x00008bb7}, | 507 | {0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00008bb3, 0x00008bb3}, |
| 507 | {0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00008bc3, 0x00008bc3, 0x00008bc3}, | 508 | {0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00008bb7, 0x00008bb7}, |
| 508 | {0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x00008bc7, 0x00008bc7, 0x00008bc7}, | 509 | {0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00008bc3, 0x00008bc3}, |
| 509 | {0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x00008bcb, 0x00008bcb, 0x00008bcb}, | 510 | {0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x00008bc7, 0x00008bc7}, |
| 510 | {0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00008bcf, 0x00008bcf, 0x00008bcf}, | 511 | {0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x00008bcb, 0x00008bcb}, |
| 511 | {0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00008bd3, 0x00008bd3, 0x00008bd3}, | 512 | {0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00008bcf, 0x00008bcf}, |
| 512 | {0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00008bd7, 0x00008bd7, 0x00008bd7}, | 513 | {0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00008bd3, 0x00008bd3}, |
| 513 | {0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 514 | {0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00008bd7, 0x00008bd7}, |
| 514 | {0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 515 | {0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00008bdb, 0x00008bdb}, |
| 515 | {0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 516 | {0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x00008bdb, 0x00008bdb}, |
| 516 | {0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 517 | {0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x00008bdb, 0x00008bdb}, |
| 517 | {0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 518 | {0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00008bdb, 0x00008bdb}, |
| 518 | {0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 519 | {0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00008bdb, 0x00008bdb}, |
| 519 | {0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 520 | {0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x00008bdb, 0x00008bdb}, |
| 520 | {0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 521 | {0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x00008bdb, 0x00008bdb}, |
| 521 | {0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 522 | {0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x00008bdb, 0x00008bdb}, |
| 522 | {0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 523 | {0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x00008bdb, 0x00008bdb}, |
| 523 | {0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 524 | {0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x00008bdb, 0x00008bdb}, |
| 524 | {0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 525 | {0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x00008bdb, 0x00008bdb}, |
| 525 | {0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 526 | {0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x00008bdb, 0x00008bdb}, |
| 526 | {0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 527 | {0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x00008bdb, 0x00008bdb}, |
| 527 | {0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 528 | {0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x00008bdb, 0x00008bdb}, |
| 528 | {0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 529 | {0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x00008bdb, 0x00008bdb}, |
| 529 | {0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 530 | {0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x00008bdb, 0x00008bdb}, |
| 530 | {0x00009b98, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 531 | {0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x00008bdb, 0x00008bdb}, |
| 531 | {0x00009b9c, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 532 | {0x00009b98, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 532 | {0x00009ba0, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 533 | {0x00009b9c, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 533 | {0x00009ba4, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 534 | {0x00009ba0, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 534 | {0x00009ba8, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 535 | {0x00009ba4, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 535 | {0x00009bac, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 536 | {0x00009ba8, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 536 | {0x00009bb0, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 537 | {0x00009bac, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 537 | {0x00009bb4, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 538 | {0x00009bb0, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 538 | {0x00009bb8, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 539 | {0x00009bb4, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 539 | {0x00009bbc, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 540 | {0x00009bb8, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 540 | {0x00009bc0, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 541 | {0x00009bbc, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 541 | {0x00009bc4, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 542 | {0x00009bc0, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 542 | {0x00009bc8, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 543 | {0x00009bc4, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 543 | {0x00009bcc, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 544 | {0x00009bc8, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 544 | {0x00009bd0, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 545 | {0x00009bcc, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 545 | {0x00009bd4, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 546 | {0x00009bd0, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 546 | {0x00009bd8, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 547 | {0x00009bd4, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 547 | {0x00009bdc, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 548 | {0x00009bd8, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 548 | {0x00009be0, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 549 | {0x00009bdc, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 549 | {0x00009be4, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 550 | {0x00009be0, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 550 | {0x00009be8, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 551 | {0x00009be4, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 551 | {0x00009bec, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 552 | {0x00009be8, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 552 | {0x00009bf0, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 553 | {0x00009bec, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 553 | {0x00009bf4, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 554 | {0x00009bf0, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 554 | {0x00009bf8, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 555 | {0x00009bf4, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 555 | {0x00009bfc, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb, 0x00008bdb}, | 556 | {0x00009bf8, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 556 | {0x00009848, 0x00001066, 0x00001066, 0x00001055, 0x00001055, 0x00001055}, | 557 | {0x00009bfc, 0x0000f7db, 0x0000f7db, 0x00008bdb, 0x00008bdb}, |
| 557 | {0x0000a848, 0x00001066, 0x00001066, 0x00001055, 0x00001055, 0x00001055}, | 558 | {0x00009848, 0x00001066, 0x00001066, 0x00001055, 0x00001055}, |
| 559 | {0x0000a848, 0x00001066, 0x00001066, 0x00001055, 0x00001055}, | ||
| 558 | }; | 560 | }; |
| 559 | 561 | ||
| 560 | static const u32 ar9280Modes_original_rxgain_9280_2[][6] = { | 562 | static const u32 ar9280Modes_original_rxgain_9280_2[][5] = { |
| 561 | {0x00009a00, 0x00008184, 0x00008184, 0x00008000, 0x00008000, 0x00008000}, | 563 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 562 | {0x00009a04, 0x00008188, 0x00008188, 0x00008000, 0x00008000, 0x00008000}, | 564 | {0x00009a00, 0x00008184, 0x00008184, 0x00008000, 0x00008000}, |
| 563 | {0x00009a08, 0x0000818c, 0x0000818c, 0x00008000, 0x00008000, 0x00008000}, | 565 | {0x00009a04, 0x00008188, 0x00008188, 0x00008000, 0x00008000}, |
| 564 | {0x00009a0c, 0x00008190, 0x00008190, 0x00008000, 0x00008000, 0x00008000}, | 566 | {0x00009a08, 0x0000818c, 0x0000818c, 0x00008000, 0x00008000}, |
| 565 | {0x00009a10, 0x00008194, 0x00008194, 0x00008000, 0x00008000, 0x00008000}, | 567 | {0x00009a0c, 0x00008190, 0x00008190, 0x00008000, 0x00008000}, |
| 566 | {0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000}, | 568 | {0x00009a10, 0x00008194, 0x00008194, 0x00008000, 0x00008000}, |
| 567 | {0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004}, | 569 | {0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000}, |
| 568 | {0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008}, | 570 | {0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004}, |
| 569 | {0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c}, | 571 | {0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008}, |
| 570 | {0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080}, | 572 | {0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c}, |
| 571 | {0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084}, | 573 | {0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080}, |
| 572 | {0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088}, | 574 | {0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084}, |
| 573 | {0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c}, | 575 | {0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088}, |
| 574 | {0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100}, | 576 | {0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c}, |
| 575 | {0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104}, | 577 | {0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100}, |
| 576 | {0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108}, | 578 | {0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104}, |
| 577 | {0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c}, | 579 | {0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108}, |
| 578 | {0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110}, | 580 | {0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c}, |
| 579 | {0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114}, | 581 | {0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110}, |
| 580 | {0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180}, | 582 | {0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114}, |
| 581 | {0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184}, | 583 | {0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180}, |
| 582 | {0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188}, | 584 | {0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184}, |
| 583 | {0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c}, | 585 | {0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188}, |
| 584 | {0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190}, | 586 | {0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c}, |
| 585 | {0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194}, | 587 | {0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190}, |
| 586 | {0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0}, | 588 | {0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194}, |
| 587 | {0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c}, | 589 | {0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0}, |
| 588 | {0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8}, | 590 | {0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c}, |
| 589 | {0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284}, | 591 | {0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8}, |
| 590 | {0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288}, | 592 | {0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284}, |
| 591 | {0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224}, | 593 | {0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288}, |
| 592 | {0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290}, | 594 | {0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224}, |
| 593 | {0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300}, | 595 | {0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290}, |
| 594 | {0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304}, | 596 | {0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300}, |
| 595 | {0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308}, | 597 | {0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304}, |
| 596 | {0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c}, | 598 | {0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308}, |
| 597 | {0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380}, | 599 | {0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c}, |
| 598 | {0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384}, | 600 | {0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380}, |
| 599 | {0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700}, | 601 | {0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384}, |
| 600 | {0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704}, | 602 | {0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700}, |
| 601 | {0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708}, | 603 | {0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704}, |
| 602 | {0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c}, | 604 | {0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708}, |
| 603 | {0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780}, | 605 | {0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c}, |
| 604 | {0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784}, | 606 | {0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780}, |
| 605 | {0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00}, | 607 | {0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784}, |
| 606 | {0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04}, | 608 | {0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00}, |
| 607 | {0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08}, | 609 | {0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04}, |
| 608 | {0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c}, | 610 | {0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08}, |
| 609 | {0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80}, | 611 | {0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c}, |
| 610 | {0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84}, | 612 | {0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80}, |
| 611 | {0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88}, | 613 | {0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84}, |
| 612 | {0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c}, | 614 | {0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88}, |
| 613 | {0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90}, | 615 | {0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c}, |
| 614 | {0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80}, | 616 | {0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90}, |
| 615 | {0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84}, | 617 | {0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80}, |
| 616 | {0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88}, | 618 | {0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84}, |
| 617 | {0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c}, | 619 | {0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88}, |
| 618 | {0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90}, | 620 | {0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c}, |
| 619 | {0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c}, | 621 | {0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90}, |
| 620 | {0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310}, | 622 | {0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c}, |
| 621 | {0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384}, | 623 | {0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310}, |
| 622 | {0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388}, | 624 | {0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384}, |
| 623 | {0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324}, | 625 | {0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388}, |
| 624 | {0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704}, | 626 | {0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324}, |
| 625 | {0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4}, | 627 | {0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704}, |
| 626 | {0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8}, | 628 | {0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4}, |
| 627 | {0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710}, | 629 | {0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8}, |
| 628 | {0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714}, | 630 | {0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710}, |
| 629 | {0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720}, | 631 | {0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714}, |
| 630 | {0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724}, | 632 | {0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720}, |
| 631 | {0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728}, | 633 | {0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724}, |
| 632 | {0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c}, | 634 | {0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728}, |
| 633 | {0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0}, | 635 | {0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c}, |
| 634 | {0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4}, | 636 | {0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0}, |
| 635 | {0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8}, | 637 | {0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4}, |
| 636 | {0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0}, | 638 | {0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8}, |
| 637 | {0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4}, | 639 | {0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0}, |
| 638 | {0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8}, | 640 | {0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4}, |
| 639 | {0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5}, | 641 | {0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8}, |
| 640 | {0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9}, | 642 | {0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5}, |
| 641 | {0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad}, | 643 | {0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9}, |
| 642 | {0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1}, | 644 | {0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad}, |
| 643 | {0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5}, | 645 | {0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1}, |
| 644 | {0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9}, | 646 | {0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5}, |
| 645 | {0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5}, | 647 | {0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9}, |
| 646 | {0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9}, | 648 | {0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5}, |
| 647 | {0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1}, | 649 | {0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9}, |
| 648 | {0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5}, | 650 | {0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1}, |
| 649 | {0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9}, | 651 | {0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5}, |
| 650 | {0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6}, | 652 | {0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9}, |
| 651 | {0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca}, | 653 | {0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6}, |
| 652 | {0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce}, | 654 | {0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca}, |
| 653 | {0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2}, | 655 | {0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce}, |
| 654 | {0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6}, | 656 | {0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2}, |
| 655 | {0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3}, | 657 | {0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6}, |
| 656 | {0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7}, | 658 | {0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3}, |
| 657 | {0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb}, | 659 | {0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7}, |
| 658 | {0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf}, | 660 | {0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb}, |
| 659 | {0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7}, | 661 | {0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf}, |
| 660 | {0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db}, | 662 | {0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7}, |
| 661 | {0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db}, | 663 | {0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db}, |
| 662 | {0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db}, | 664 | {0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db}, |
| 663 | {0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 665 | {0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db}, |
| 664 | {0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 666 | {0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 665 | {0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 667 | {0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 666 | {0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 668 | {0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 667 | {0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 669 | {0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 668 | {0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 670 | {0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 669 | {0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 671 | {0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 670 | {0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 672 | {0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 671 | {0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 673 | {0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 672 | {0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 674 | {0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 673 | {0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 675 | {0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 674 | {0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 676 | {0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 675 | {0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 677 | {0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 676 | {0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 678 | {0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 677 | {0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 679 | {0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 678 | {0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 680 | {0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 679 | {0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 681 | {0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 680 | {0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 682 | {0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 681 | {0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 683 | {0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 682 | {0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 684 | {0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 683 | {0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 685 | {0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 684 | {0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 686 | {0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 685 | {0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 687 | {0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 686 | {0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 688 | {0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 687 | {0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 689 | {0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 688 | {0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db}, | 690 | {0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 689 | {0x00009848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063}, | 691 | {0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db}, |
| 690 | {0x0000a848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063}, | 692 | {0x00009848, 0x00001066, 0x00001066, 0x00001063, 0x00001063}, |
| 693 | {0x0000a848, 0x00001066, 0x00001066, 0x00001063, 0x00001063}, | ||
| 691 | }; | 694 | }; |
| 692 | 695 | ||
| 693 | static const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = { | 696 | static const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][5] = { |
| 694 | {0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290}, | 697 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 695 | {0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300}, | 698 | {0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290}, |
| 696 | {0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304}, | 699 | {0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300}, |
| 697 | {0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308}, | 700 | {0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304}, |
| 698 | {0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c}, | 701 | {0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308}, |
| 699 | {0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000}, | 702 | {0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c}, |
| 700 | {0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004}, | 703 | {0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000}, |
| 701 | {0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008}, | 704 | {0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004}, |
| 702 | {0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c}, | 705 | {0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008}, |
| 703 | {0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080}, | 706 | {0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c}, |
| 704 | {0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084}, | 707 | {0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080}, |
| 705 | {0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088}, | 708 | {0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084}, |
| 706 | {0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c}, | 709 | {0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088}, |
| 707 | {0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100}, | 710 | {0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c}, |
| 708 | {0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104}, | 711 | {0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100}, |
| 709 | {0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108}, | 712 | {0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104}, |
| 710 | {0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c}, | 713 | {0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108}, |
| 711 | {0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110}, | 714 | {0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c}, |
| 712 | {0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114}, | 715 | {0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110}, |
| 713 | {0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180}, | 716 | {0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114}, |
| 714 | {0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184}, | 717 | {0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180}, |
| 715 | {0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188}, | 718 | {0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184}, |
| 716 | {0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c}, | 719 | {0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188}, |
| 717 | {0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190}, | 720 | {0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c}, |
| 718 | {0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194}, | 721 | {0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190}, |
| 719 | {0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0}, | 722 | {0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194}, |
| 720 | {0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c}, | 723 | {0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0}, |
| 721 | {0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8}, | 724 | {0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c}, |
| 722 | {0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284}, | 725 | {0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8}, |
| 723 | {0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288}, | 726 | {0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284}, |
| 724 | {0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224}, | 727 | {0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288}, |
| 725 | {0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290}, | 728 | {0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224}, |
| 726 | {0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300}, | 729 | {0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290}, |
| 727 | {0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304}, | 730 | {0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300}, |
| 728 | {0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308}, | 731 | {0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304}, |
| 729 | {0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c}, | 732 | {0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308}, |
| 730 | {0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380}, | 733 | {0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c}, |
| 731 | {0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384}, | 734 | {0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380}, |
| 732 | {0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700}, | 735 | {0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384}, |
| 733 | {0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704}, | 736 | {0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700}, |
| 734 | {0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708}, | 737 | {0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704}, |
| 735 | {0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c}, | 738 | {0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708}, |
| 736 | {0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780}, | 739 | {0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c}, |
| 737 | {0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784}, | 740 | {0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780}, |
| 738 | {0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00}, | 741 | {0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784}, |
| 739 | {0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04}, | 742 | {0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00}, |
| 740 | {0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08}, | 743 | {0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04}, |
| 741 | {0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c}, | 744 | {0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08}, |
| 742 | {0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80}, | 745 | {0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c}, |
| 743 | {0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84}, | 746 | {0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80}, |
| 744 | {0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88}, | 747 | {0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84}, |
| 745 | {0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c}, | 748 | {0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88}, |
| 746 | {0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90}, | 749 | {0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c}, |
| 747 | {0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80}, | 750 | {0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90}, |
| 748 | {0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84}, | 751 | {0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80}, |
| 749 | {0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88}, | 752 | {0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84}, |
| 750 | {0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c}, | 753 | {0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88}, |
| 751 | {0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90}, | 754 | {0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c}, |
| 752 | {0x00009ae8, 0x0000b780, 0x0000b780, 0x00009310, 0x00009310, 0x00009310}, | 755 | {0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90}, |
| 753 | {0x00009aec, 0x0000b784, 0x0000b784, 0x00009314, 0x00009314, 0x00009314}, | 756 | {0x00009ae8, 0x0000b780, 0x0000b780, 0x00009310, 0x00009310}, |
| 754 | {0x00009af0, 0x0000b788, 0x0000b788, 0x00009320, 0x00009320, 0x00009320}, | 757 | {0x00009aec, 0x0000b784, 0x0000b784, 0x00009314, 0x00009314}, |
| 755 | {0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009324, 0x00009324, 0x00009324}, | 758 | {0x00009af0, 0x0000b788, 0x0000b788, 0x00009320, 0x00009320}, |
| 756 | {0x00009af8, 0x0000b790, 0x0000b790, 0x00009328, 0x00009328, 0x00009328}, | 759 | {0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009324, 0x00009324}, |
| 757 | {0x00009afc, 0x0000b794, 0x0000b794, 0x0000932c, 0x0000932c, 0x0000932c}, | 760 | {0x00009af8, 0x0000b790, 0x0000b790, 0x00009328, 0x00009328}, |
| 758 | {0x00009b00, 0x0000b798, 0x0000b798, 0x00009330, 0x00009330, 0x00009330}, | 761 | {0x00009afc, 0x0000b794, 0x0000b794, 0x0000932c, 0x0000932c}, |
| 759 | {0x00009b04, 0x0000d784, 0x0000d784, 0x00009334, 0x00009334, 0x00009334}, | 762 | {0x00009b00, 0x0000b798, 0x0000b798, 0x00009330, 0x00009330}, |
| 760 | {0x00009b08, 0x0000d788, 0x0000d788, 0x00009321, 0x00009321, 0x00009321}, | 763 | {0x00009b04, 0x0000d784, 0x0000d784, 0x00009334, 0x00009334}, |
| 761 | {0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009325, 0x00009325, 0x00009325}, | 764 | {0x00009b08, 0x0000d788, 0x0000d788, 0x00009321, 0x00009321}, |
| 762 | {0x00009b10, 0x0000d790, 0x0000d790, 0x00009329, 0x00009329, 0x00009329}, | 765 | {0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009325, 0x00009325}, |
| 763 | {0x00009b14, 0x0000f780, 0x0000f780, 0x0000932d, 0x0000932d, 0x0000932d}, | 766 | {0x00009b10, 0x0000d790, 0x0000d790, 0x00009329, 0x00009329}, |
| 764 | {0x00009b18, 0x0000f784, 0x0000f784, 0x00009331, 0x00009331, 0x00009331}, | 767 | {0x00009b14, 0x0000f780, 0x0000f780, 0x0000932d, 0x0000932d}, |
| 765 | {0x00009b1c, 0x0000f788, 0x0000f788, 0x00009335, 0x00009335, 0x00009335}, | 768 | {0x00009b18, 0x0000f784, 0x0000f784, 0x00009331, 0x00009331}, |
| 766 | {0x00009b20, 0x0000f78c, 0x0000f78c, 0x00009322, 0x00009322, 0x00009322}, | 769 | {0x00009b1c, 0x0000f788, 0x0000f788, 0x00009335, 0x00009335}, |
| 767 | {0x00009b24, 0x0000f790, 0x0000f790, 0x00009326, 0x00009326, 0x00009326}, | 770 | {0x00009b20, 0x0000f78c, 0x0000f78c, 0x00009322, 0x00009322}, |
| 768 | {0x00009b28, 0x0000f794, 0x0000f794, 0x0000932a, 0x0000932a, 0x0000932a}, | 771 | {0x00009b24, 0x0000f790, 0x0000f790, 0x00009326, 0x00009326}, |
| 769 | {0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x0000932e, 0x0000932e, 0x0000932e}, | 772 | {0x00009b28, 0x0000f794, 0x0000f794, 0x0000932a, 0x0000932a}, |
| 770 | {0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00009332, 0x00009332, 0x00009332}, | 773 | {0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x0000932e, 0x0000932e}, |
| 771 | {0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00009336, 0x00009336, 0x00009336}, | 774 | {0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00009332, 0x00009332}, |
| 772 | {0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00009323, 0x00009323, 0x00009323}, | 775 | {0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00009336, 0x00009336}, |
| 773 | {0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00009327, 0x00009327, 0x00009327}, | 776 | {0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00009323, 0x00009323}, |
| 774 | {0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x0000932b, 0x0000932b, 0x0000932b}, | 777 | {0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00009327, 0x00009327}, |
| 775 | {0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x0000932f, 0x0000932f, 0x0000932f}, | 778 | {0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x0000932b, 0x0000932b}, |
| 776 | {0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00009333, 0x00009333, 0x00009333}, | 779 | {0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x0000932f, 0x0000932f}, |
| 777 | {0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00009337, 0x00009337, 0x00009337}, | 780 | {0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00009333, 0x00009333}, |
| 778 | {0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00009343, 0x00009343, 0x00009343}, | 781 | {0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00009337, 0x00009337}, |
| 779 | {0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00009347, 0x00009347, 0x00009347}, | 782 | {0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00009343, 0x00009343}, |
| 780 | {0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x0000934b, 0x0000934b, 0x0000934b}, | 783 | {0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00009347, 0x00009347}, |
| 781 | {0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x0000934f, 0x0000934f, 0x0000934f}, | 784 | {0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x0000934b, 0x0000934b}, |
| 782 | {0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00009353, 0x00009353, 0x00009353}, | 785 | {0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x0000934f, 0x0000934f}, |
| 783 | {0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00009357, 0x00009357, 0x00009357}, | 786 | {0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00009353, 0x00009353}, |
| 784 | {0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x0000935b, 0x0000935b, 0x0000935b}, | 787 | {0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00009357, 0x00009357}, |
| 785 | {0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x0000935b, 0x0000935b, 0x0000935b}, | 788 | {0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x0000935b, 0x0000935b}, |
| 786 | {0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x0000935b, 0x0000935b, 0x0000935b}, | 789 | {0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x0000935b, 0x0000935b}, |
| 787 | {0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x0000935b, 0x0000935b, 0x0000935b}, | 790 | {0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x0000935b, 0x0000935b}, |
| 788 | {0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x0000935b, 0x0000935b, 0x0000935b}, | 791 | {0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x0000935b, 0x0000935b}, |
| 789 | {0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x0000935b, 0x0000935b, 0x0000935b}, | 792 | {0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x0000935b, 0x0000935b}, |
| 790 | {0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x0000935b, 0x0000935b, 0x0000935b}, | 793 | {0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x0000935b, 0x0000935b}, |
| 791 | {0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x0000935b, 0x0000935b, 0x0000935b}, | 794 | {0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x0000935b, 0x0000935b}, |
| 792 | {0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x0000935b, 0x0000935b, 0x0000935b}, | 795 | {0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x0000935b, 0x0000935b}, |
| 793 | {0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x0000935b, 0x0000935b, 0x0000935b}, | 796 | {0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x0000935b, 0x0000935b}, |
| 794 | {0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x0000935b, 0x0000935b, 0x0000935b}, | 797 | {0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x0000935b, 0x0000935b}, |
| 795 | {0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x0000935b, 0x0000935b, 0x0000935b}, | 798 | {0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x0000935b, 0x0000935b}, |
| 796 | {0x00009b98, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 799 | {0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x0000935b, 0x0000935b}, |
| 797 | {0x00009b9c, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 800 | {0x00009b98, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 798 | {0x00009ba0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 801 | {0x00009b9c, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 799 | {0x00009ba4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 802 | {0x00009ba0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 800 | {0x00009ba8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 803 | {0x00009ba4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 801 | {0x00009bac, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 804 | {0x00009ba8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 802 | {0x00009bb0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 805 | {0x00009bac, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 803 | {0x00009bb4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 806 | {0x00009bb0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 804 | {0x00009bb8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 807 | {0x00009bb4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 805 | {0x00009bbc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 808 | {0x00009bb8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 806 | {0x00009bc0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 809 | {0x00009bbc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 807 | {0x00009bc4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 810 | {0x00009bc0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 808 | {0x00009bc8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 811 | {0x00009bc4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 809 | {0x00009bcc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 812 | {0x00009bc8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 810 | {0x00009bd0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 813 | {0x00009bcc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 811 | {0x00009bd4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 814 | {0x00009bd0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 812 | {0x00009bd8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 815 | {0x00009bd4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 813 | {0x00009bdc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 816 | {0x00009bd8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 814 | {0x00009be0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 817 | {0x00009bdc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 815 | {0x00009be4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 818 | {0x00009be0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 816 | {0x00009be8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 819 | {0x00009be4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 817 | {0x00009bec, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 820 | {0x00009be8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 818 | {0x00009bf0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 821 | {0x00009bec, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 819 | {0x00009bf4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 822 | {0x00009bf0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 820 | {0x00009bf8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 823 | {0x00009bf4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 821 | {0x00009bfc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b}, | 824 | {0x00009bf8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 822 | {0x00009848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a}, | 825 | {0x00009bfc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b}, |
| 823 | {0x0000a848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a}, | 826 | {0x00009848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a}, |
| 827 | {0x0000a848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a}, | ||
| 824 | }; | 828 | }; |
| 825 | 829 | ||
| 826 | static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = { | 830 | static const u32 ar9280Modes_high_power_tx_gain_9280_2[][5] = { |
| 827 | {0x0000a274, 0x0a19e652, 0x0a19e652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652}, | 831 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 828 | {0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce}, | 832 | {0x0000a274, 0x0a19e652, 0x0a19e652, 0x0a1aa652, 0x0a1aa652}, |
| 829 | {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 833 | {0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce}, |
| 830 | {0x0000a304, 0x00003002, 0x00003002, 0x00004002, 0x00004002, 0x00004002}, | 834 | {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 831 | {0x0000a308, 0x00006004, 0x00006004, 0x00007008, 0x00007008, 0x00007008}, | 835 | {0x0000a304, 0x00003002, 0x00003002, 0x00004002, 0x00004002}, |
| 832 | {0x0000a30c, 0x0000a006, 0x0000a006, 0x0000c010, 0x0000c010, 0x0000c010}, | 836 | {0x0000a308, 0x00006004, 0x00006004, 0x00007008, 0x00007008}, |
| 833 | {0x0000a310, 0x0000e012, 0x0000e012, 0x00010012, 0x00010012, 0x00010012}, | 837 | {0x0000a30c, 0x0000a006, 0x0000a006, 0x0000c010, 0x0000c010}, |
| 834 | {0x0000a314, 0x00011014, 0x00011014, 0x00013014, 0x00013014, 0x00013014}, | 838 | {0x0000a310, 0x0000e012, 0x0000e012, 0x00010012, 0x00010012}, |
| 835 | {0x0000a318, 0x0001504a, 0x0001504a, 0x0001820a, 0x0001820a, 0x0001820a}, | 839 | {0x0000a314, 0x00011014, 0x00011014, 0x00013014, 0x00013014}, |
| 836 | {0x0000a31c, 0x0001904c, 0x0001904c, 0x0001b211, 0x0001b211, 0x0001b211}, | 840 | {0x0000a318, 0x0001504a, 0x0001504a, 0x0001820a, 0x0001820a}, |
| 837 | {0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213}, | 841 | {0x0000a31c, 0x0001904c, 0x0001904c, 0x0001b211, 0x0001b211}, |
| 838 | {0x0000a324, 0x00021092, 0x00021092, 0x00022411, 0x00022411, 0x00022411}, | 842 | {0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213}, |
| 839 | {0x0000a328, 0x0002510a, 0x0002510a, 0x00025413, 0x00025413, 0x00025413}, | 843 | {0x0000a324, 0x00021092, 0x00021092, 0x00022411, 0x00022411}, |
| 840 | {0x0000a32c, 0x0002910c, 0x0002910c, 0x00029811, 0x00029811, 0x00029811}, | 844 | {0x0000a328, 0x0002510a, 0x0002510a, 0x00025413, 0x00025413}, |
| 841 | {0x0000a330, 0x0002c18b, 0x0002c18b, 0x0002c813, 0x0002c813, 0x0002c813}, | 845 | {0x0000a32c, 0x0002910c, 0x0002910c, 0x00029811, 0x00029811}, |
| 842 | {0x0000a334, 0x0002f1cc, 0x0002f1cc, 0x00030a14, 0x00030a14, 0x00030a14}, | 846 | {0x0000a330, 0x0002c18b, 0x0002c18b, 0x0002c813, 0x0002c813}, |
| 843 | {0x0000a338, 0x000321eb, 0x000321eb, 0x00035a50, 0x00035a50, 0x00035a50}, | 847 | {0x0000a334, 0x0002f1cc, 0x0002f1cc, 0x00030a14, 0x00030a14}, |
| 844 | {0x0000a33c, 0x000341ec, 0x000341ec, 0x00039c4c, 0x00039c4c, 0x00039c4c}, | 848 | {0x0000a338, 0x000321eb, 0x000321eb, 0x00035a50, 0x00035a50}, |
| 845 | {0x0000a340, 0x000341ec, 0x000341ec, 0x0003de8a, 0x0003de8a, 0x0003de8a}, | 849 | {0x0000a33c, 0x000341ec, 0x000341ec, 0x00039c4c, 0x00039c4c}, |
| 846 | {0x0000a344, 0x000341ec, 0x000341ec, 0x00042e92, 0x00042e92, 0x00042e92}, | 850 | {0x0000a340, 0x000341ec, 0x000341ec, 0x0003de8a, 0x0003de8a}, |
| 847 | {0x0000a348, 0x000341ec, 0x000341ec, 0x00046ed2, 0x00046ed2, 0x00046ed2}, | 851 | {0x0000a344, 0x000341ec, 0x000341ec, 0x00042e92, 0x00042e92}, |
| 848 | {0x0000a34c, 0x000341ec, 0x000341ec, 0x0004bed5, 0x0004bed5, 0x0004bed5}, | 852 | {0x0000a348, 0x000341ec, 0x000341ec, 0x00046ed2, 0x00046ed2}, |
| 849 | {0x0000a350, 0x000341ec, 0x000341ec, 0x0004ff54, 0x0004ff54, 0x0004ff54}, | 853 | {0x0000a34c, 0x000341ec, 0x000341ec, 0x0004bed5, 0x0004bed5}, |
| 850 | {0x0000a354, 0x000341ec, 0x000341ec, 0x00055fd5, 0x00055fd5, 0x00055fd5}, | 854 | {0x0000a350, 0x000341ec, 0x000341ec, 0x0004ff54, 0x0004ff54}, |
| 851 | {0x0000a3ec, 0x00f70081, 0x00f70081, 0x00f70081, 0x00f70081, 0x00f70081}, | 855 | {0x0000a354, 0x000341ec, 0x000341ec, 0x00055fd5, 0x00055fd5}, |
| 852 | {0x00007814, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff}, | 856 | {0x0000a3ec, 0x00f70081, 0x00f70081, 0x00f70081, 0x00f70081}, |
| 853 | {0x00007838, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff}, | 857 | {0x00007814, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff}, |
| 854 | {0x0000781c, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000}, | 858 | {0x00007838, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff}, |
| 855 | {0x00007840, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000}, | 859 | {0x0000781c, 0x00172000, 0x00172000, 0x00172000, 0x00172000}, |
| 856 | {0x00007820, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480}, | 860 | {0x00007840, 0x00172000, 0x00172000, 0x00172000, 0x00172000}, |
| 857 | {0x00007844, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480}, | 861 | {0x00007820, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480}, |
| 862 | {0x00007844, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480}, | ||
| 858 | }; | 863 | }; |
| 859 | 864 | ||
| 860 | static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = { | 865 | static const u32 ar9280Modes_original_tx_gain_9280_2[][5] = { |
| 861 | {0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652}, | 866 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 862 | {0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce}, | 867 | {0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652}, |
| 863 | {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 868 | {0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce}, |
| 864 | {0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002}, | 869 | {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 865 | {0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009}, | 870 | {0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002}, |
| 866 | {0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b}, | 871 | {0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009}, |
| 867 | {0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012}, | 872 | {0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b}, |
| 868 | {0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048}, | 873 | {0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012}, |
| 869 | {0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a}, | 874 | {0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048}, |
| 870 | {0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211}, | 875 | {0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a}, |
| 871 | {0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213}, | 876 | {0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211}, |
| 872 | {0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b}, | 877 | {0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213}, |
| 873 | {0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412}, | 878 | {0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b}, |
| 874 | {0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414}, | 879 | {0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412}, |
| 875 | {0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a}, | 880 | {0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414}, |
| 876 | {0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649}, | 881 | {0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a}, |
| 877 | {0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b}, | 882 | {0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649}, |
| 878 | {0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49}, | 883 | {0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b}, |
| 879 | {0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48}, | 884 | {0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49}, |
| 880 | {0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a}, | 885 | {0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48}, |
| 881 | {0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88}, | 886 | {0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a}, |
| 882 | {0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a}, | 887 | {0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88}, |
| 883 | {0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9}, | 888 | {0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a}, |
| 884 | {0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42}, | 889 | {0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9}, |
| 885 | {0x0000a3ec, 0x00f70081, 0x00f70081, 0x00f70081, 0x00f70081, 0x00f70081}, | 890 | {0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42}, |
| 886 | {0x00007814, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff}, | 891 | {0x0000a3ec, 0x00f70081, 0x00f70081, 0x00f70081, 0x00f70081}, |
| 887 | {0x00007838, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff}, | 892 | {0x00007814, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff}, |
| 888 | {0x0000781c, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000}, | 893 | {0x00007838, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff}, |
| 889 | {0x00007840, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000}, | 894 | {0x0000781c, 0x00392000, 0x00392000, 0x00392000, 0x00392000}, |
| 890 | {0x00007820, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480}, | 895 | {0x00007840, 0x00392000, 0x00392000, 0x00392000, 0x00392000}, |
| 891 | {0x00007844, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480}, | 896 | {0x00007820, 0x92592480, 0x92592480, 0x92592480, 0x92592480}, |
| 897 | {0x00007844, 0x92592480, 0x92592480, 0x92592480, 0x92592480}, | ||
| 892 | }; | 898 | }; |
| 893 | 899 | ||
| 894 | static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = { | 900 | static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = { |
| @@ -947,309 +953,310 @@ static const u32 ar9285PciePhy_clkreq_off_L1_9285[][2] = { | |||
| 947 | {0x00004044, 0x00000000}, | 953 | {0x00004044, 0x00000000}, |
| 948 | }; | 954 | }; |
| 949 | 955 | ||
| 950 | static const u32 ar9285Modes_9285_1_2[][6] = { | 956 | static const u32 ar9285Modes_9285_1_2[][5] = { |
| 951 | {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0}, | 957 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 952 | {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0}, | 958 | {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, |
| 953 | {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180}, | 959 | {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, |
| 954 | {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008}, | 960 | {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38}, |
| 955 | {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0}, | 961 | {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 956 | {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f}, | 962 | {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00}, |
| 957 | {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880}, | 963 | {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b}, |
| 958 | {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303}, | 964 | {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, |
| 959 | {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200}, | 965 | {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300}, |
| 960 | {0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e}, | 966 | {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200}, |
| 961 | {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001}, | 967 | {0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e}, |
| 962 | {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, | 968 | {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001}, |
| 963 | {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007}, | 969 | {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, |
| 964 | {0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e}, | 970 | {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007}, |
| 965 | {0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0}, | 971 | {0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e}, |
| 966 | {0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059}, | 972 | {0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620}, |
| 967 | {0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059}, | 973 | {0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053}, |
| 968 | {0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2}, | 974 | {0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053}, |
| 969 | {0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e}, | 975 | {0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2}, |
| 970 | {0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e}, | 976 | {0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e}, |
| 971 | {0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18}, | 977 | {0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e}, |
| 972 | {0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00}, | 978 | {0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20}, |
| 973 | {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, | 979 | {0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00}, |
| 974 | {0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881}, | 980 | {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, |
| 975 | {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0}, | 981 | {0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881}, |
| 976 | {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016}, | 982 | {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, |
| 977 | {0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d}, | 983 | {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b}, |
| 978 | {0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010}, | 984 | {0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d}, |
| 979 | {0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 985 | {0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020}, |
| 980 | {0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 986 | {0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 981 | {0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c}, | 987 | {0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 982 | {0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00}, | 988 | {0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c}, |
| 983 | {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, | 989 | {0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00}, |
| 984 | {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77}, | 990 | {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, |
| 985 | {0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f}, | 991 | {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77}, |
| 986 | {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8}, | 992 | {0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f}, |
| 987 | {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384}, | 993 | {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8}, |
| 988 | {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 994 | {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384}, |
| 989 | {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 995 | {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 990 | {0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000}, | 996 | {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 991 | {0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000}, | 997 | {0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084}, |
| 992 | {0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000}, | 998 | {0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088}, |
| 993 | {0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000}, | 999 | {0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c}, |
| 994 | {0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000}, | 1000 | {0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100}, |
| 995 | {0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000}, | 1001 | {0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104}, |
| 996 | {0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000}, | 1002 | {0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108}, |
| 997 | {0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000}, | 1003 | {0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c}, |
| 998 | {0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000}, | 1004 | {0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110}, |
| 999 | {0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000}, | 1005 | {0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114}, |
| 1000 | {0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000}, | 1006 | {0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180}, |
| 1001 | {0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000}, | 1007 | {0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184}, |
| 1002 | {0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000}, | 1008 | {0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188}, |
| 1003 | {0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000}, | 1009 | {0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c}, |
| 1004 | {0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000}, | 1010 | {0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190}, |
| 1005 | {0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000}, | 1011 | {0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194}, |
| 1006 | {0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000}, | 1012 | {0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0}, |
| 1007 | {0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000}, | 1013 | {0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c}, |
| 1008 | {0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000}, | 1014 | {0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8}, |
| 1009 | {0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000}, | 1015 | {0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284}, |
| 1010 | {0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000}, | 1016 | {0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288}, |
| 1011 | {0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000}, | 1017 | {0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224}, |
| 1012 | {0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000}, | 1018 | {0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290}, |
| 1013 | {0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000}, | 1019 | {0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300}, |
| 1014 | {0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000}, | 1020 | {0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304}, |
| 1015 | {0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000}, | 1021 | {0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308}, |
| 1016 | {0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000}, | 1022 | {0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c}, |
| 1017 | {0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000}, | 1023 | {0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380}, |
| 1018 | {0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000}, | 1024 | {0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384}, |
| 1019 | {0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000}, | 1025 | {0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700}, |
| 1020 | {0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000}, | 1026 | {0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704}, |
| 1021 | {0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000}, | 1027 | {0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708}, |
| 1022 | {0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000}, | 1028 | {0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c}, |
| 1023 | {0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000}, | 1029 | {0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780}, |
| 1024 | {0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000}, | 1030 | {0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784}, |
| 1025 | {0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000}, | 1031 | {0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00}, |
| 1026 | {0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000}, | 1032 | {0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04}, |
| 1027 | {0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000}, | 1033 | {0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08}, |
| 1028 | {0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000}, | 1034 | {0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c}, |
| 1029 | {0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000}, | 1035 | {0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80}, |
| 1030 | {0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000}, | 1036 | {0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84}, |
| 1031 | {0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000}, | 1037 | {0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88}, |
| 1032 | {0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000}, | 1038 | {0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c}, |
| 1033 | {0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000}, | 1039 | {0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90}, |
| 1034 | {0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000}, | 1040 | {0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80}, |
| 1035 | {0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000}, | 1041 | {0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84}, |
| 1036 | {0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000}, | 1042 | {0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88}, |
| 1037 | {0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000}, | 1043 | {0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c}, |
| 1038 | {0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000}, | 1044 | {0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90}, |
| 1039 | {0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000}, | 1045 | {0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c}, |
| 1040 | {0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000}, | 1046 | {0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310}, |
| 1041 | {0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000}, | 1047 | {0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384}, |
| 1042 | {0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000}, | 1048 | {0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388}, |
| 1043 | {0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000}, | 1049 | {0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324}, |
| 1044 | {0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000}, | 1050 | {0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704}, |
| 1045 | {0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000}, | 1051 | {0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4}, |
| 1046 | {0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000}, | 1052 | {0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8}, |
| 1047 | {0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000}, | 1053 | {0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710}, |
| 1048 | {0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000}, | 1054 | {0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714}, |
| 1049 | {0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000}, | 1055 | {0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720}, |
| 1050 | {0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000}, | 1056 | {0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724}, |
| 1051 | {0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000}, | 1057 | {0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728}, |
| 1052 | {0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000}, | 1058 | {0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c}, |
| 1053 | {0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000}, | 1059 | {0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0}, |
| 1054 | {0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000}, | 1060 | {0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4}, |
| 1055 | {0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000}, | 1061 | {0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8}, |
| 1056 | {0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000}, | 1062 | {0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0}, |
| 1057 | {0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000}, | 1063 | {0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4}, |
| 1058 | {0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000}, | 1064 | {0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8}, |
| 1059 | {0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000}, | 1065 | {0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5}, |
| 1060 | {0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000}, | 1066 | {0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9}, |
| 1061 | {0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000}, | 1067 | {0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad}, |
| 1062 | {0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000}, | 1068 | {0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1}, |
| 1063 | {0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000}, | 1069 | {0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5}, |
| 1064 | {0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000}, | 1070 | {0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9}, |
| 1065 | {0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000}, | 1071 | {0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5}, |
| 1066 | {0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000}, | 1072 | {0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9}, |
| 1067 | {0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000}, | 1073 | {0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1}, |
| 1068 | {0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000}, | 1074 | {0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5}, |
| 1069 | {0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000}, | 1075 | {0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9}, |
| 1070 | {0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000}, | 1076 | {0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6}, |
| 1071 | {0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000}, | 1077 | {0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca}, |
| 1072 | {0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000}, | 1078 | {0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce}, |
| 1073 | {0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000}, | 1079 | {0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2}, |
| 1074 | {0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000}, | 1080 | {0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6}, |
| 1075 | {0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000}, | 1081 | {0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3}, |
| 1076 | {0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000}, | 1082 | {0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7}, |
| 1077 | {0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000}, | 1083 | {0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb}, |
| 1078 | {0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000}, | 1084 | {0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf}, |
| 1079 | {0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1085 | {0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7}, |
| 1080 | {0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1086 | {0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1081 | {0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1087 | {0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1082 | {0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1088 | {0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1083 | {0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1089 | {0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1084 | {0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1090 | {0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1085 | {0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1091 | {0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1086 | {0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1092 | {0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1087 | {0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1093 | {0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1088 | {0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1094 | {0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1089 | {0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1095 | {0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1090 | {0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1096 | {0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1091 | {0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1097 | {0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1092 | {0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1098 | {0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1093 | {0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1099 | {0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1094 | {0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1100 | {0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1095 | {0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1101 | {0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1096 | {0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1102 | {0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1097 | {0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1103 | {0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1098 | {0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1104 | {0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1099 | {0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1105 | {0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1100 | {0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1106 | {0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1101 | {0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1107 | {0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1102 | {0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1108 | {0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1103 | {0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1109 | {0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1104 | {0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1110 | {0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1105 | {0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1111 | {0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1106 | {0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1112 | {0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1107 | {0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1113 | {0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1108 | {0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1114 | {0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1109 | {0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1115 | {0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1110 | {0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1116 | {0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1111 | {0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1117 | {0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1112 | {0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1118 | {0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1113 | {0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1119 | {0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1114 | {0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1120 | {0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1115 | {0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1121 | {0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1116 | {0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1122 | {0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1117 | {0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1123 | {0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1118 | {0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000}, | 1124 | {0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1119 | {0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000}, | 1125 | {0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084}, |
| 1120 | {0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000}, | 1126 | {0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088}, |
| 1121 | {0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000}, | 1127 | {0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c}, |
| 1122 | {0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000}, | 1128 | {0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100}, |
| 1123 | {0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000}, | 1129 | {0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104}, |
| 1124 | {0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000}, | 1130 | {0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108}, |
| 1125 | {0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000}, | 1131 | {0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c}, |
| 1126 | {0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000}, | 1132 | {0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110}, |
| 1127 | {0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000}, | 1133 | {0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114}, |
| 1128 | {0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000}, | 1134 | {0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180}, |
| 1129 | {0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000}, | 1135 | {0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184}, |
| 1130 | {0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000}, | 1136 | {0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188}, |
| 1131 | {0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000}, | 1137 | {0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c}, |
| 1132 | {0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000}, | 1138 | {0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190}, |
| 1133 | {0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000}, | 1139 | {0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194}, |
| 1134 | {0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000}, | 1140 | {0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0}, |
| 1135 | {0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000}, | 1141 | {0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c}, |
| 1136 | {0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000}, | 1142 | {0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8}, |
| 1137 | {0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000}, | 1143 | {0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284}, |
| 1138 | {0x0000aa50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000}, | 1144 | {0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288}, |
| 1139 | {0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000}, | 1145 | {0x0000aa50, 0x00000000, 0x00000000, 0x00058224, 0x00058224}, |
| 1140 | {0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000}, | 1146 | {0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290}, |
| 1141 | {0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000}, | 1147 | {0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300}, |
| 1142 | {0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000}, | 1148 | {0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304}, |
| 1143 | {0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000}, | 1149 | {0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308}, |
| 1144 | {0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000}, | 1150 | {0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c}, |
| 1145 | {0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000}, | 1151 | {0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380}, |
| 1146 | {0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000}, | 1152 | {0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384}, |
| 1147 | {0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000}, | 1153 | {0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700}, |
| 1148 | {0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000}, | 1154 | {0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704}, |
| 1149 | {0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000}, | 1155 | {0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708}, |
| 1150 | {0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000}, | 1156 | {0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c}, |
| 1151 | {0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000}, | 1157 | {0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780}, |
| 1152 | {0x0000aa88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000}, | 1158 | {0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784}, |
| 1153 | {0x0000aa8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000}, | 1159 | {0x0000aa88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00}, |
| 1154 | {0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000}, | 1160 | {0x0000aa8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04}, |
| 1155 | {0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000}, | 1161 | {0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08}, |
| 1156 | {0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000}, | 1162 | {0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c}, |
| 1157 | {0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000}, | 1163 | {0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80}, |
| 1158 | {0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000}, | 1164 | {0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84}, |
| 1159 | {0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000}, | 1165 | {0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88}, |
| 1160 | {0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000}, | 1166 | {0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c}, |
| 1161 | {0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000}, | 1167 | {0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90}, |
| 1162 | {0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000}, | 1168 | {0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80}, |
| 1163 | {0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000}, | 1169 | {0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84}, |
| 1164 | {0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000}, | 1170 | {0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88}, |
| 1165 | {0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000}, | 1171 | {0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c}, |
| 1166 | {0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000}, | 1172 | {0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90}, |
| 1167 | {0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000}, | 1173 | {0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c}, |
| 1168 | {0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000}, | 1174 | {0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310}, |
| 1169 | {0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000}, | 1175 | {0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384}, |
| 1170 | {0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000}, | 1176 | {0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388}, |
| 1171 | {0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000}, | 1177 | {0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324}, |
| 1172 | {0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000}, | 1178 | {0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704}, |
| 1173 | {0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000}, | 1179 | {0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4}, |
| 1174 | {0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000}, | 1180 | {0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8}, |
| 1175 | {0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000}, | 1181 | {0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710}, |
| 1176 | {0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000}, | 1182 | {0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714}, |
| 1177 | {0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000}, | 1183 | {0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720}, |
| 1178 | {0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000}, | 1184 | {0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724}, |
| 1179 | {0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000}, | 1185 | {0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728}, |
| 1180 | {0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000}, | 1186 | {0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c}, |
| 1181 | {0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000}, | 1187 | {0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0}, |
| 1182 | {0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000}, | 1188 | {0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4}, |
| 1183 | {0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000}, | 1189 | {0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8}, |
| 1184 | {0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000}, | 1190 | {0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0}, |
| 1185 | {0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000}, | 1191 | {0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4}, |
| 1186 | {0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000}, | 1192 | {0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8}, |
| 1187 | {0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000}, | 1193 | {0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5}, |
| 1188 | {0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000}, | 1194 | {0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9}, |
| 1189 | {0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000}, | 1195 | {0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad}, |
| 1190 | {0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000}, | 1196 | {0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1}, |
| 1191 | {0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000}, | 1197 | {0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5}, |
| 1192 | {0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000}, | 1198 | {0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9}, |
| 1193 | {0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000}, | 1199 | {0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5}, |
| 1194 | {0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000}, | 1200 | {0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9}, |
| 1195 | {0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000}, | 1201 | {0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1}, |
| 1196 | {0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000}, | 1202 | {0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5}, |
| 1197 | {0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000}, | 1203 | {0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9}, |
| 1198 | {0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000}, | 1204 | {0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6}, |
| 1199 | {0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000}, | 1205 | {0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca}, |
| 1200 | {0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000}, | 1206 | {0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce}, |
| 1201 | {0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000}, | 1207 | {0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2}, |
| 1202 | {0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000}, | 1208 | {0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6}, |
| 1203 | {0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000}, | 1209 | {0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3}, |
| 1204 | {0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000}, | 1210 | {0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7}, |
| 1205 | {0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000}, | 1211 | {0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb}, |
| 1206 | {0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000}, | 1212 | {0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf}, |
| 1207 | {0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1213 | {0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7}, |
| 1208 | {0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1214 | {0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1209 | {0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1215 | {0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1210 | {0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1216 | {0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1211 | {0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1217 | {0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1212 | {0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1218 | {0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1213 | {0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1219 | {0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1214 | {0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1220 | {0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1215 | {0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1221 | {0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1216 | {0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1222 | {0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1217 | {0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1223 | {0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1218 | {0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1224 | {0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1219 | {0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1225 | {0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1220 | {0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1226 | {0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1221 | {0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1227 | {0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1222 | {0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1228 | {0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1223 | {0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1229 | {0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1224 | {0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1230 | {0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1225 | {0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1231 | {0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1226 | {0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1232 | {0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1227 | {0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1233 | {0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1228 | {0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1234 | {0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1229 | {0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1235 | {0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1230 | {0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1236 | {0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1231 | {0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1237 | {0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1232 | {0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1238 | {0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1233 | {0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1239 | {0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1234 | {0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1240 | {0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1235 | {0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1241 | {0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1236 | {0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1242 | {0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1237 | {0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1243 | {0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1238 | {0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1244 | {0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1239 | {0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1245 | {0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1240 | {0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1246 | {0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1241 | {0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1247 | {0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1242 | {0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1248 | {0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1243 | {0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1249 | {0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1244 | {0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1250 | {0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1245 | {0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 1251 | {0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1246 | {0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004}, | 1252 | {0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 1247 | {0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000}, | 1253 | {0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004}, |
| 1248 | {0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000}, | 1254 | {0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000}, |
| 1249 | {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a}, | 1255 | {0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000}, |
| 1250 | {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000}, | 1256 | {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a}, |
| 1251 | {0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000}, | 1257 | {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, |
| 1252 | {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e}, | 1258 | {0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000}, |
| 1259 | {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e}, | ||
| 1253 | }; | 1260 | }; |
| 1254 | 1261 | ||
| 1255 | static const u32 ar9285Common_9285_1_2[][2] = { | 1262 | static const u32 ar9285Common_9285_1_2[][2] = { |
| @@ -1572,164 +1579,168 @@ static const u32 ar9285Common_9285_1_2[][2] = { | |||
| 1572 | {0x00007870, 0x10142c00}, | 1579 | {0x00007870, 0x10142c00}, |
| 1573 | }; | 1580 | }; |
| 1574 | 1581 | ||
| 1575 | static const u32 ar9285Modes_high_power_tx_gain_9285_1_2[][6] = { | 1582 | static const u32 ar9285Modes_high_power_tx_gain_9285_1_2[][5] = { |
| 1576 | {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 1583 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 1577 | {0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000}, | 1584 | {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 1578 | {0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000}, | 1585 | {0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200}, |
| 1579 | {0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000}, | 1586 | {0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201}, |
| 1580 | {0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000}, | 1587 | {0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240}, |
| 1581 | {0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000}, | 1588 | {0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241}, |
| 1582 | {0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000}, | 1589 | {0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600}, |
| 1583 | {0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000}, | 1590 | {0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800}, |
| 1584 | {0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000}, | 1591 | {0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802}, |
| 1585 | {0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000}, | 1592 | {0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805}, |
| 1586 | {0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000}, | 1593 | {0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80}, |
| 1587 | {0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000}, | 1594 | {0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00}, |
| 1588 | {0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000}, | 1595 | {0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40}, |
| 1589 | {0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000}, | 1596 | {0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80}, |
| 1590 | {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000}, | 1597 | {0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82}, |
| 1591 | {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000}, | 1598 | {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e}, |
| 1592 | {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1599 | {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e}, |
| 1593 | {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1600 | {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1594 | {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1601 | {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1595 | {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1602 | {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1596 | {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1603 | {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1597 | {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1604 | {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1598 | {0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8}, | 1605 | {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1599 | {0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b}, | 1606 | {0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8}, |
| 1600 | {0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e}, | 1607 | {0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b}, |
| 1601 | {0x00007838, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803}, | 1608 | {0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e}, |
| 1602 | {0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe}, | 1609 | {0x00007838, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803}, |
| 1603 | {0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20}, | 1610 | {0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe}, |
| 1604 | {0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe}, | 1611 | {0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20}, |
| 1605 | {0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00}, | 1612 | {0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe}, |
| 1606 | {0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652}, | 1613 | {0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00}, |
| 1607 | {0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7}, | 1614 | {0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652}, |
| 1608 | {0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7}, | 1615 | {0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7}, |
| 1609 | {0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7}, | 1616 | {0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7}, |
| 1610 | {0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7}, | 1617 | {0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7}, |
| 1611 | {0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7}, | 1618 | {0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7}, |
| 1612 | {0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7}, | 1619 | {0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7}, |
| 1620 | {0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7}, | ||
| 1613 | }; | 1621 | }; |
| 1614 | 1622 | ||
| 1615 | static const u32 ar9285Modes_original_tx_gain_9285_1_2[][6] = { | 1623 | static const u32 ar9285Modes_original_tx_gain_9285_1_2[][5] = { |
| 1616 | {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 1624 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 1617 | {0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000}, | 1625 | {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 1618 | {0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000}, | 1626 | {0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200}, |
| 1619 | {0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000}, | 1627 | {0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208}, |
| 1620 | {0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000}, | 1628 | {0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608}, |
| 1621 | {0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000}, | 1629 | {0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618}, |
| 1622 | {0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000}, | 1630 | {0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9}, |
| 1623 | {0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000}, | 1631 | {0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710}, |
| 1624 | {0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000}, | 1632 | {0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718}, |
| 1625 | {0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000}, | 1633 | {0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758}, |
| 1626 | {0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000}, | 1634 | {0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a}, |
| 1627 | {0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000}, | 1635 | {0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c}, |
| 1628 | {0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000}, | 1636 | {0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e}, |
| 1629 | {0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000}, | 1637 | {0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f}, |
| 1630 | {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000}, | 1638 | {0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df}, |
| 1631 | {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000}, | 1639 | {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e}, |
| 1632 | {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1640 | {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e}, |
| 1633 | {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1641 | {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1634 | {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1642 | {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1635 | {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1643 | {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1636 | {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1644 | {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1637 | {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1645 | {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1638 | {0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8}, | 1646 | {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1639 | {0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b}, | 1647 | {0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8}, |
| 1640 | {0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e}, | 1648 | {0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b}, |
| 1641 | {0x00007838, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801}, | 1649 | {0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e}, |
| 1642 | {0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe}, | 1650 | {0x00007838, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801}, |
| 1643 | {0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20}, | 1651 | {0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe}, |
| 1644 | {0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4}, | 1652 | {0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20}, |
| 1645 | {0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04}, | 1653 | {0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4}, |
| 1646 | {0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652}, | 1654 | {0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04}, |
| 1647 | {0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c}, | 1655 | {0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652}, |
| 1648 | {0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c}, | 1656 | {0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c}, |
| 1649 | {0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c}, | 1657 | {0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c}, |
| 1650 | {0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c}, | 1658 | {0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c}, |
| 1651 | {0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c}, | 1659 | {0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c}, |
| 1652 | {0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c}, | 1660 | {0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c}, |
| 1661 | {0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c}, | ||
| 1653 | }; | 1662 | }; |
| 1654 | 1663 | ||
| 1655 | static const u32 ar9285Modes_XE2_0_normal_power[][6] = { | 1664 | static const u32 ar9285Modes_XE2_0_normal_power[][5] = { |
| 1656 | {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 1665 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 1657 | {0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000}, | 1666 | {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 1658 | {0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000}, | 1667 | {0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200}, |
| 1659 | {0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000}, | 1668 | {0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208}, |
| 1660 | {0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000}, | 1669 | {0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608}, |
| 1661 | {0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000}, | 1670 | {0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618}, |
| 1662 | {0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000}, | 1671 | {0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9}, |
| 1663 | {0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000}, | 1672 | {0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710}, |
| 1664 | {0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000}, | 1673 | {0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718}, |
| 1665 | {0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000}, | 1674 | {0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758}, |
| 1666 | {0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000}, | 1675 | {0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a}, |
| 1667 | {0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000}, | 1676 | {0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c}, |
| 1668 | {0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000}, | 1677 | {0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e}, |
| 1669 | {0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000}, | 1678 | {0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f}, |
| 1670 | {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000}, | 1679 | {0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df}, |
| 1671 | {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000}, | 1680 | {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e}, |
| 1672 | {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1681 | {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e}, |
| 1673 | {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1682 | {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1674 | {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1683 | {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1675 | {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1684 | {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1676 | {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1685 | {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1677 | {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1686 | {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1678 | {0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8}, | 1687 | {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1679 | {0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b, 0x4ad2491b}, | 1688 | {0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8}, |
| 1680 | {0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6dbae}, | 1689 | {0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b}, |
| 1681 | {0x00007838, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441}, | 1690 | {0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e}, |
| 1682 | {0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe}, | 1691 | {0x00007838, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441}, |
| 1683 | {0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c}, | 1692 | {0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe}, |
| 1684 | {0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4}, | 1693 | {0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c}, |
| 1685 | {0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04}, | 1694 | {0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4}, |
| 1686 | {0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652}, | 1695 | {0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04}, |
| 1687 | {0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c}, | 1696 | {0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652}, |
| 1688 | {0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c}, | 1697 | {0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c}, |
| 1689 | {0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c}, | 1698 | {0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c}, |
| 1690 | {0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c}, | 1699 | {0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c}, |
| 1691 | {0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c}, | 1700 | {0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c}, |
| 1692 | {0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c}, | 1701 | {0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c}, |
| 1702 | {0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c}, | ||
| 1693 | }; | 1703 | }; |
| 1694 | 1704 | ||
| 1695 | static const u32 ar9285Modes_XE2_0_high_power[][6] = { | 1705 | static const u32 ar9285Modes_XE2_0_high_power[][5] = { |
| 1696 | {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 1706 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 1697 | {0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000}, | 1707 | {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 1698 | {0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000}, | 1708 | {0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200}, |
| 1699 | {0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000}, | 1709 | {0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201}, |
| 1700 | {0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000}, | 1710 | {0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240}, |
| 1701 | {0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000}, | 1711 | {0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241}, |
| 1702 | {0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000}, | 1712 | {0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600}, |
| 1703 | {0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000}, | 1713 | {0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800}, |
| 1704 | {0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000}, | 1714 | {0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802}, |
| 1705 | {0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000}, | 1715 | {0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805}, |
| 1706 | {0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000}, | 1716 | {0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80}, |
| 1707 | {0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000}, | 1717 | {0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00}, |
| 1708 | {0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000}, | 1718 | {0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40}, |
| 1709 | {0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000}, | 1719 | {0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80}, |
| 1710 | {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000}, | 1720 | {0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82}, |
| 1711 | {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000}, | 1721 | {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e}, |
| 1712 | {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1722 | {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e}, |
| 1713 | {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1723 | {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1714 | {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1724 | {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1715 | {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1725 | {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1716 | {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1726 | {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1717 | {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 1727 | {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1718 | {0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8}, | 1728 | {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 1719 | {0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b, 0x4ad2491b}, | 1729 | {0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8}, |
| 1720 | {0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e}, | 1730 | {0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b}, |
| 1721 | {0x00007838, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443}, | 1731 | {0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e}, |
| 1722 | {0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe}, | 1732 | {0x00007838, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443}, |
| 1723 | {0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c}, | 1733 | {0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe}, |
| 1724 | {0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe}, | 1734 | {0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c}, |
| 1725 | {0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00}, | 1735 | {0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe}, |
| 1726 | {0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652}, | 1736 | {0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00}, |
| 1727 | {0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7}, | 1737 | {0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652}, |
| 1728 | {0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7}, | 1738 | {0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7}, |
| 1729 | {0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7}, | 1739 | {0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7}, |
| 1730 | {0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7}, | 1740 | {0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7}, |
| 1731 | {0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7}, | 1741 | {0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7}, |
| 1732 | {0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7}, | 1742 | {0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7}, |
| 1743 | {0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7}, | ||
| 1733 | }; | 1744 | }; |
| 1734 | 1745 | ||
| 1735 | static const u32 ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = { | 1746 | static const u32 ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = { |
| @@ -1760,50 +1771,51 @@ static const u32 ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = { | |||
| 1760 | {0x00004044, 0x00000000}, | 1771 | {0x00004044, 0x00000000}, |
| 1761 | }; | 1772 | }; |
| 1762 | 1773 | ||
| 1763 | static const u32 ar9287Modes_9287_1_1[][6] = { | 1774 | static const u32 ar9287Modes_9287_1_1[][5] = { |
| 1764 | {0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0}, | 1775 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 1765 | {0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0}, | 1776 | {0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160}, |
| 1766 | {0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38, 0x00001180}, | 1777 | {0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c}, |
| 1767 | {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008}, | 1778 | {0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38}, |
| 1768 | {0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00, 0x06e006e0}, | 1779 | {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 1769 | {0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b, 0x0988004f}, | 1780 | {0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00}, |
| 1770 | {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810}, | 1781 | {0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b}, |
| 1771 | {0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a, 0x0000320a}, | 1782 | {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810}, |
| 1772 | {0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440, 0x00006880}, | 1783 | {0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a}, |
| 1773 | {0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300, 0x00000303}, | 1784 | {0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440}, |
| 1774 | {0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200, 0x02020200}, | 1785 | {0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300}, |
| 1775 | {0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e, 0x01000e0e}, | 1786 | {0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200}, |
| 1776 | {0x00009828, 0x00000000, 0x00000000, 0x3a020001, 0x3a020001, 0x3a020001}, | 1787 | {0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e}, |
| 1777 | {0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e, 0x00000e0e}, | 1788 | {0x00009828, 0x00000000, 0x00000000, 0x3a020001, 0x3a020001}, |
| 1778 | {0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007, 0x00000007}, | 1789 | {0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e}, |
| 1779 | {0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e, 0x206a012e}, | 1790 | {0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007}, |
| 1780 | {0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0, 0x037216a0}, | 1791 | {0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e}, |
| 1781 | {0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2}, | 1792 | {0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0}, |
| 1782 | {0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e}, | 1793 | {0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2}, |
| 1783 | {0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e, 0x31395d5e}, | 1794 | {0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e}, |
| 1784 | {0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20, 0x00058d18}, | 1795 | {0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e}, |
| 1785 | {0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00, 0x0001ce00}, | 1796 | {0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20}, |
| 1786 | {0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, | 1797 | {0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00}, |
| 1787 | {0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881, 0x06903881}, | 1798 | {0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0}, |
| 1788 | {0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898, 0x000007d0}, | 1799 | {0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881}, |
| 1789 | {0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b, 0x00000016}, | 1800 | {0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898}, |
| 1790 | {0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d}, | 1801 | {0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b}, |
| 1791 | {0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010, 0xefbc1010}, | 1802 | {0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d}, |
| 1792 | {0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010}, | 1803 | {0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010}, |
| 1793 | {0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010}, | 1804 | {0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010}, |
| 1794 | {0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210, 0x00000210}, | 1805 | {0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010}, |
| 1795 | {0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce, 0x000003ce}, | 1806 | {0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210}, |
| 1796 | {0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c, 0x0000001c}, | 1807 | {0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce}, |
| 1797 | {0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00, 0x00000c00}, | 1808 | {0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c}, |
| 1798 | {0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, | 1809 | {0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00}, |
| 1799 | {0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444, 0x00000444}, | 1810 | {0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4}, |
| 1800 | {0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 1811 | {0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444}, |
| 1801 | {0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 1812 | {0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 1802 | {0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a, 0x1883800a}, | 1813 | {0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 1803 | {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000}, | 1814 | {0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a}, |
| 1804 | {0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000, 0x0004a000}, | 1815 | {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, |
| 1805 | {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e}, | 1816 | {0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000}, |
| 1806 | {0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 1817 | {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e}, |
| 1818 | {0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1807 | }; | 1819 | }; |
| 1808 | 1820 | ||
| 1809 | static const u32 ar9287Common_9287_1_1[][2] = { | 1821 | static const u32 ar9287Common_9287_1_1[][2] = { |
| @@ -2189,313 +2201,315 @@ static const u32 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1[][2] = { | |||
| 2189 | {0x0000a1fc, 0xca9228ee}, | 2201 | {0x0000a1fc, 0xca9228ee}, |
| 2190 | }; | 2202 | }; |
| 2191 | 2203 | ||
| 2192 | static const u32 ar9287Modes_tx_gain_9287_1_1[][6] = { | 2204 | static const u32 ar9287Modes_tx_gain_9287_1_1[][5] = { |
| 2193 | {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 2205 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 2194 | {0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002}, | 2206 | {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 2195 | {0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004, 0x00008004}, | 2207 | {0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002}, |
| 2196 | {0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a, 0x0000c00a}, | 2208 | {0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004}, |
| 2197 | {0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c, 0x0001000c}, | 2209 | {0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a}, |
| 2198 | {0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b, 0x0001420b}, | 2210 | {0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c}, |
| 2199 | {0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a, 0x0001824a}, | 2211 | {0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b}, |
| 2200 | {0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a, 0x0001c44a}, | 2212 | {0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a}, |
| 2201 | {0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a, 0x0002064a}, | 2213 | {0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a}, |
| 2202 | {0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a, 0x0002484a}, | 2214 | {0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a}, |
| 2203 | {0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a, 0x00028a4a}, | 2215 | {0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a}, |
| 2204 | {0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a}, | 2216 | {0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a}, |
| 2205 | {0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a, 0x00030e4a}, | 2217 | {0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a}, |
| 2206 | {0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a, 0x00034e8a}, | 2218 | {0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a}, |
| 2207 | {0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c, 0x00038e8c}, | 2219 | {0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a}, |
| 2208 | {0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc, 0x0003cecc}, | 2220 | {0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c}, |
| 2209 | {0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4, 0x00040ed4}, | 2221 | {0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc}, |
| 2210 | {0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc, 0x00044edc}, | 2222 | {0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4}, |
| 2211 | {0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede, 0x00048ede}, | 2223 | {0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc}, |
| 2212 | {0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e}, | 2224 | {0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede}, |
| 2213 | {0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e, 0x00050f5e}, | 2225 | {0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e}, |
| 2214 | {0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e, 0x00054f9e}, | 2226 | {0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e}, |
| 2215 | {0x0000a780, 0x00000000, 0x00000000, 0x00000062, 0x00000062, 0x00000062}, | 2227 | {0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e}, |
| 2216 | {0x0000a784, 0x00000000, 0x00000000, 0x00004064, 0x00004064, 0x00004064}, | 2228 | {0x0000a780, 0x00000000, 0x00000000, 0x00000062, 0x00000062}, |
| 2217 | {0x0000a788, 0x00000000, 0x00000000, 0x000080a4, 0x000080a4, 0x000080a4}, | 2229 | {0x0000a784, 0x00000000, 0x00000000, 0x00004064, 0x00004064}, |
| 2218 | {0x0000a78c, 0x00000000, 0x00000000, 0x0000c0aa, 0x0000c0aa, 0x0000c0aa}, | 2230 | {0x0000a788, 0x00000000, 0x00000000, 0x000080a4, 0x000080a4}, |
| 2219 | {0x0000a790, 0x00000000, 0x00000000, 0x000100ac, 0x000100ac, 0x000100ac}, | 2231 | {0x0000a78c, 0x00000000, 0x00000000, 0x0000c0aa, 0x0000c0aa}, |
| 2220 | {0x0000a794, 0x00000000, 0x00000000, 0x000140b4, 0x000140b4, 0x000140b4}, | 2232 | {0x0000a790, 0x00000000, 0x00000000, 0x000100ac, 0x000100ac}, |
| 2221 | {0x0000a798, 0x00000000, 0x00000000, 0x000180f4, 0x000180f4, 0x000180f4}, | 2233 | {0x0000a794, 0x00000000, 0x00000000, 0x000140b4, 0x000140b4}, |
| 2222 | {0x0000a79c, 0x00000000, 0x00000000, 0x0001c134, 0x0001c134, 0x0001c134}, | 2234 | {0x0000a798, 0x00000000, 0x00000000, 0x000180f4, 0x000180f4}, |
| 2223 | {0x0000a7a0, 0x00000000, 0x00000000, 0x00020174, 0x00020174, 0x00020174}, | 2235 | {0x0000a79c, 0x00000000, 0x00000000, 0x0001c134, 0x0001c134}, |
| 2224 | {0x0000a7a4, 0x00000000, 0x00000000, 0x0002417c, 0x0002417c, 0x0002417c}, | 2236 | {0x0000a7a0, 0x00000000, 0x00000000, 0x00020174, 0x00020174}, |
| 2225 | {0x0000a7a8, 0x00000000, 0x00000000, 0x0002817e, 0x0002817e, 0x0002817e}, | 2237 | {0x0000a7a4, 0x00000000, 0x00000000, 0x0002417c, 0x0002417c}, |
| 2226 | {0x0000a7ac, 0x00000000, 0x00000000, 0x0002c1be, 0x0002c1be, 0x0002c1be}, | 2238 | {0x0000a7a8, 0x00000000, 0x00000000, 0x0002817e, 0x0002817e}, |
| 2227 | {0x0000a7b0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe}, | 2239 | {0x0000a7ac, 0x00000000, 0x00000000, 0x0002c1be, 0x0002c1be}, |
| 2228 | {0x0000a7b4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe}, | 2240 | {0x0000a7b0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe}, |
| 2229 | {0x0000a7b8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe}, | 2241 | {0x0000a7b4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe}, |
| 2230 | {0x0000a7bc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe}, | 2242 | {0x0000a7b8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe}, |
| 2231 | {0x0000a7c0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe}, | 2243 | {0x0000a7bc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe}, |
| 2232 | {0x0000a7c4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe}, | 2244 | {0x0000a7c0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe}, |
| 2233 | {0x0000a7c8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe}, | 2245 | {0x0000a7c4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe}, |
| 2234 | {0x0000a7cc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe}, | 2246 | {0x0000a7c8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe}, |
| 2235 | {0x0000a7d0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe}, | 2247 | {0x0000a7cc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe}, |
| 2236 | {0x0000a7d4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe}, | 2248 | {0x0000a7d0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe}, |
| 2237 | {0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000}, | 2249 | {0x0000a7d4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe}, |
| 2250 | {0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000}, | ||
| 2238 | }; | 2251 | }; |
| 2239 | 2252 | ||
| 2240 | static const u32 ar9287Modes_rx_gain_9287_1_1[][6] = { | 2253 | static const u32 ar9287Modes_rx_gain_9287_1_1[][5] = { |
| 2241 | {0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120}, | 2254 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 2242 | {0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124}, | 2255 | {0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120}, |
| 2243 | {0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128}, | 2256 | {0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124}, |
| 2244 | {0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c}, | 2257 | {0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128}, |
| 2245 | {0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130}, | 2258 | {0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c}, |
| 2246 | {0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194}, | 2259 | {0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130}, |
| 2247 | {0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198}, | 2260 | {0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194}, |
| 2248 | {0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c}, | 2261 | {0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198}, |
| 2249 | {0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210}, | 2262 | {0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c}, |
| 2250 | {0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284}, | 2263 | {0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210}, |
| 2251 | {0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288}, | 2264 | {0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284}, |
| 2252 | {0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c}, | 2265 | {0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288}, |
| 2253 | {0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290}, | 2266 | {0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c}, |
| 2254 | {0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294}, | 2267 | {0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290}, |
| 2255 | {0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0}, | 2268 | {0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294}, |
| 2256 | {0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4}, | 2269 | {0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0}, |
| 2257 | {0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8}, | 2270 | {0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4}, |
| 2258 | {0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac}, | 2271 | {0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8}, |
| 2259 | {0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0}, | 2272 | {0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac}, |
| 2260 | {0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4}, | 2273 | {0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0}, |
| 2261 | {0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8}, | 2274 | {0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4}, |
| 2262 | {0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4}, | 2275 | {0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8}, |
| 2263 | {0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708}, | 2276 | {0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4}, |
| 2264 | {0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c}, | 2277 | {0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708}, |
| 2265 | {0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710}, | 2278 | {0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c}, |
| 2266 | {0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04}, | 2279 | {0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710}, |
| 2267 | {0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08}, | 2280 | {0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04}, |
| 2268 | {0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c}, | 2281 | {0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08}, |
| 2269 | {0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10}, | 2282 | {0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c}, |
| 2270 | {0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14}, | 2283 | {0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10}, |
| 2271 | {0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18}, | 2284 | {0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14}, |
| 2272 | {0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c}, | 2285 | {0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18}, |
| 2273 | {0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90}, | 2286 | {0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c}, |
| 2274 | {0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94}, | 2287 | {0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90}, |
| 2275 | {0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98}, | 2288 | {0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94}, |
| 2276 | {0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4}, | 2289 | {0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98}, |
| 2277 | {0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8}, | 2290 | {0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4}, |
| 2278 | {0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04}, | 2291 | {0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8}, |
| 2279 | {0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08}, | 2292 | {0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04}, |
| 2280 | {0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c}, | 2293 | {0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08}, |
| 2281 | {0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10}, | 2294 | {0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c}, |
| 2282 | {0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14}, | 2295 | {0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10}, |
| 2283 | {0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18}, | 2296 | {0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14}, |
| 2284 | {0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c}, | 2297 | {0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18}, |
| 2285 | {0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90}, | 2298 | {0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c}, |
| 2286 | {0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18}, | 2299 | {0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90}, |
| 2287 | {0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24}, | 2300 | {0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18}, |
| 2288 | {0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28}, | 2301 | {0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24}, |
| 2289 | {0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314}, | 2302 | {0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28}, |
| 2290 | {0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318}, | 2303 | {0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314}, |
| 2291 | {0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c}, | 2304 | {0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318}, |
| 2292 | {0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390}, | 2305 | {0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c}, |
| 2293 | {0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394}, | 2306 | {0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390}, |
| 2294 | {0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398}, | 2307 | {0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394}, |
| 2295 | {0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4}, | 2308 | {0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398}, |
| 2296 | {0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8}, | 2309 | {0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4}, |
| 2297 | {0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac}, | 2310 | {0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8}, |
| 2298 | {0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0}, | 2311 | {0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac}, |
| 2299 | {0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380}, | 2312 | {0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0}, |
| 2300 | {0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384}, | 2313 | {0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380}, |
| 2301 | {0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388}, | 2314 | {0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384}, |
| 2302 | {0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710}, | 2315 | {0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388}, |
| 2303 | {0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714}, | 2316 | {0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710}, |
| 2304 | {0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718}, | 2317 | {0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714}, |
| 2305 | {0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10}, | 2318 | {0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718}, |
| 2306 | {0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14}, | 2319 | {0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10}, |
| 2307 | {0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18}, | 2320 | {0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14}, |
| 2308 | {0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c}, | 2321 | {0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18}, |
| 2309 | {0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90}, | 2322 | {0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c}, |
| 2310 | {0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94}, | 2323 | {0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90}, |
| 2311 | {0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c}, | 2324 | {0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94}, |
| 2312 | {0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90}, | 2325 | {0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c}, |
| 2313 | {0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94}, | 2326 | {0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90}, |
| 2314 | {0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0}, | 2327 | {0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94}, |
| 2315 | {0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4}, | 2328 | {0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0}, |
| 2316 | {0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8}, | 2329 | {0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4}, |
| 2317 | {0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac}, | 2330 | {0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8}, |
| 2318 | {0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0}, | 2331 | {0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac}, |
| 2319 | {0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4}, | 2332 | {0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0}, |
| 2320 | {0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1}, | 2333 | {0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4}, |
| 2321 | {0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5}, | 2334 | {0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1}, |
| 2322 | {0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9}, | 2335 | {0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5}, |
| 2323 | {0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad}, | 2336 | {0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9}, |
| 2324 | {0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1}, | 2337 | {0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad}, |
| 2325 | {0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5}, | 2338 | {0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1}, |
| 2326 | {0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9}, | 2339 | {0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5}, |
| 2327 | {0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5}, | 2340 | {0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9}, |
| 2328 | {0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9}, | 2341 | {0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5}, |
| 2329 | {0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd}, | 2342 | {0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9}, |
| 2330 | {0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1}, | 2343 | {0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd}, |
| 2331 | {0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5}, | 2344 | {0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1}, |
| 2332 | {0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2}, | 2345 | {0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5}, |
| 2333 | {0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6}, | 2346 | {0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2}, |
| 2334 | {0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca}, | 2347 | {0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6}, |
| 2335 | {0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce}, | 2348 | {0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca}, |
| 2336 | {0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2}, | 2349 | {0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce}, |
| 2337 | {0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6}, | 2350 | {0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2}, |
| 2338 | {0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda}, | 2351 | {0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6}, |
| 2339 | {0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7}, | 2352 | {0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda}, |
| 2340 | {0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb}, | 2353 | {0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7}, |
| 2341 | {0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf}, | 2354 | {0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb}, |
| 2342 | {0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3}, | 2355 | {0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf}, |
| 2343 | {0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7}, | 2356 | {0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3}, |
| 2344 | {0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2357 | {0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7}, |
| 2345 | {0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2358 | {0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2346 | {0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2359 | {0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2347 | {0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2360 | {0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2348 | {0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2361 | {0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2349 | {0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2362 | {0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2350 | {0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2363 | {0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2351 | {0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2364 | {0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2352 | {0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2365 | {0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2353 | {0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2366 | {0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2354 | {0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2367 | {0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2355 | {0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2368 | {0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2356 | {0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2369 | {0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2357 | {0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2370 | {0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2358 | {0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2371 | {0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2359 | {0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2372 | {0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2360 | {0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2373 | {0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2361 | {0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2374 | {0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2362 | {0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2375 | {0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2363 | {0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2376 | {0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2364 | {0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2377 | {0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2365 | {0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2378 | {0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2366 | {0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2379 | {0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2367 | {0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2380 | {0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2368 | {0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2381 | {0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2369 | {0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120}, | 2382 | {0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2370 | {0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124}, | 2383 | {0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120}, |
| 2371 | {0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128}, | 2384 | {0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124}, |
| 2372 | {0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c}, | 2385 | {0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128}, |
| 2373 | {0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130}, | 2386 | {0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c}, |
| 2374 | {0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194}, | 2387 | {0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130}, |
| 2375 | {0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198}, | 2388 | {0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194}, |
| 2376 | {0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c}, | 2389 | {0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198}, |
| 2377 | {0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210}, | 2390 | {0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c}, |
| 2378 | {0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284}, | 2391 | {0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210}, |
| 2379 | {0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288}, | 2392 | {0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284}, |
| 2380 | {0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c}, | 2393 | {0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288}, |
| 2381 | {0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290}, | 2394 | {0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c}, |
| 2382 | {0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294}, | 2395 | {0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290}, |
| 2383 | {0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0}, | 2396 | {0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294}, |
| 2384 | {0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4}, | 2397 | {0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0}, |
| 2385 | {0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8}, | 2398 | {0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4}, |
| 2386 | {0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac}, | 2399 | {0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8}, |
| 2387 | {0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0}, | 2400 | {0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac}, |
| 2388 | {0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4}, | 2401 | {0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0}, |
| 2389 | {0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8}, | 2402 | {0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4}, |
| 2390 | {0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4}, | 2403 | {0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8}, |
| 2391 | {0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708}, | 2404 | {0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4}, |
| 2392 | {0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c}, | 2405 | {0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708}, |
| 2393 | {0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710}, | 2406 | {0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c}, |
| 2394 | {0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04}, | 2407 | {0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710}, |
| 2395 | {0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08}, | 2408 | {0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04}, |
| 2396 | {0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c}, | 2409 | {0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08}, |
| 2397 | {0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10}, | 2410 | {0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c}, |
| 2398 | {0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14}, | 2411 | {0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10}, |
| 2399 | {0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18}, | 2412 | {0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14}, |
| 2400 | {0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c}, | 2413 | {0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18}, |
| 2401 | {0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90}, | 2414 | {0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c}, |
| 2402 | {0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94}, | 2415 | {0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90}, |
| 2403 | {0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98}, | 2416 | {0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94}, |
| 2404 | {0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4}, | 2417 | {0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98}, |
| 2405 | {0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8}, | 2418 | {0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4}, |
| 2406 | {0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04}, | 2419 | {0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8}, |
| 2407 | {0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08}, | 2420 | {0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04}, |
| 2408 | {0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c}, | 2421 | {0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08}, |
| 2409 | {0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10}, | 2422 | {0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c}, |
| 2410 | {0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14}, | 2423 | {0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10}, |
| 2411 | {0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18}, | 2424 | {0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14}, |
| 2412 | {0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c}, | 2425 | {0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18}, |
| 2413 | {0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90}, | 2426 | {0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c}, |
| 2414 | {0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18}, | 2427 | {0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90}, |
| 2415 | {0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24}, | 2428 | {0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18}, |
| 2416 | {0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28}, | 2429 | {0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24}, |
| 2417 | {0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314}, | 2430 | {0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28}, |
| 2418 | {0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318}, | 2431 | {0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314}, |
| 2419 | {0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c}, | 2432 | {0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318}, |
| 2420 | {0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390}, | 2433 | {0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c}, |
| 2421 | {0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394}, | 2434 | {0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390}, |
| 2422 | {0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398}, | 2435 | {0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394}, |
| 2423 | {0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4}, | 2436 | {0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398}, |
| 2424 | {0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8}, | 2437 | {0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4}, |
| 2425 | {0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac}, | 2438 | {0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8}, |
| 2426 | {0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0}, | 2439 | {0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac}, |
| 2427 | {0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380}, | 2440 | {0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0}, |
| 2428 | {0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384}, | 2441 | {0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380}, |
| 2429 | {0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388}, | 2442 | {0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384}, |
| 2430 | {0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710}, | 2443 | {0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388}, |
| 2431 | {0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714}, | 2444 | {0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710}, |
| 2432 | {0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718}, | 2445 | {0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714}, |
| 2433 | {0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10}, | 2446 | {0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718}, |
| 2434 | {0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14}, | 2447 | {0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10}, |
| 2435 | {0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18}, | 2448 | {0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14}, |
| 2436 | {0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c}, | 2449 | {0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18}, |
| 2437 | {0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90}, | 2450 | {0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c}, |
| 2438 | {0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94}, | 2451 | {0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90}, |
| 2439 | {0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c}, | 2452 | {0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94}, |
| 2440 | {0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90}, | 2453 | {0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c}, |
| 2441 | {0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94}, | 2454 | {0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90}, |
| 2442 | {0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0}, | 2455 | {0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94}, |
| 2443 | {0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4}, | 2456 | {0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0}, |
| 2444 | {0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8}, | 2457 | {0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4}, |
| 2445 | {0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac}, | 2458 | {0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8}, |
| 2446 | {0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0}, | 2459 | {0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac}, |
| 2447 | {0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4}, | 2460 | {0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0}, |
| 2448 | {0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1}, | 2461 | {0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4}, |
| 2449 | {0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5}, | 2462 | {0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1}, |
| 2450 | {0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9}, | 2463 | {0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5}, |
| 2451 | {0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad}, | 2464 | {0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9}, |
| 2452 | {0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1}, | 2465 | {0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad}, |
| 2453 | {0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5}, | 2466 | {0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1}, |
| 2454 | {0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9}, | 2467 | {0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5}, |
| 2455 | {0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5}, | 2468 | {0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9}, |
| 2456 | {0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9}, | 2469 | {0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5}, |
| 2457 | {0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd}, | 2470 | {0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9}, |
| 2458 | {0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1}, | 2471 | {0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd}, |
| 2459 | {0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5}, | 2472 | {0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1}, |
| 2460 | {0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2}, | 2473 | {0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5}, |
| 2461 | {0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6}, | 2474 | {0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2}, |
| 2462 | {0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca}, | 2475 | {0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6}, |
| 2463 | {0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce}, | 2476 | {0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca}, |
| 2464 | {0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2}, | 2477 | {0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce}, |
| 2465 | {0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6}, | 2478 | {0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2}, |
| 2466 | {0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda}, | 2479 | {0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6}, |
| 2467 | {0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7}, | 2480 | {0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda}, |
| 2468 | {0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb}, | 2481 | {0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7}, |
| 2469 | {0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf}, | 2482 | {0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb}, |
| 2470 | {0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3}, | 2483 | {0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf}, |
| 2471 | {0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7}, | 2484 | {0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3}, |
| 2472 | {0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2485 | {0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7}, |
| 2473 | {0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2486 | {0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2474 | {0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2487 | {0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2475 | {0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2488 | {0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2476 | {0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2489 | {0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2477 | {0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2490 | {0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2478 | {0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2491 | {0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2479 | {0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2492 | {0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2480 | {0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2493 | {0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2481 | {0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2494 | {0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2482 | {0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2495 | {0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2483 | {0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2496 | {0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2484 | {0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2497 | {0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2485 | {0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2498 | {0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2486 | {0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2499 | {0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2487 | {0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2500 | {0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2488 | {0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2501 | {0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2489 | {0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2502 | {0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2490 | {0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2503 | {0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2491 | {0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2504 | {0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2492 | {0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2505 | {0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2493 | {0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2506 | {0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2494 | {0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2507 | {0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2495 | {0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2508 | {0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2496 | {0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb}, | 2509 | {0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2497 | {0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067}, | 2510 | {0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb}, |
| 2498 | {0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067}, | 2511 | {0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067}, |
| 2512 | {0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067}, | ||
| 2499 | }; | 2513 | }; |
| 2500 | 2514 | ||
| 2501 | static const u32 ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = { | 2515 | static const u32 ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = { |
| @@ -2526,310 +2540,311 @@ static const u32 ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = { | |||
| 2526 | {0x00004044, 0x00000000}, | 2540 | {0x00004044, 0x00000000}, |
| 2527 | }; | 2541 | }; |
| 2528 | 2542 | ||
| 2529 | static const u32 ar9271Modes_9271[][6] = { | 2543 | static const u32 ar9271Modes_9271[][5] = { |
| 2530 | {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0}, | 2544 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 2531 | {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0}, | 2545 | {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, |
| 2532 | {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180}, | 2546 | {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, |
| 2533 | {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008}, | 2547 | {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38}, |
| 2534 | {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0}, | 2548 | {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 2535 | {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f}, | 2549 | {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00}, |
| 2536 | {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880}, | 2550 | {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b}, |
| 2537 | {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303}, | 2551 | {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, |
| 2538 | {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200}, | 2552 | {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300}, |
| 2539 | {0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e}, | 2553 | {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200}, |
| 2540 | {0x00009828, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001}, | 2554 | {0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e}, |
| 2541 | {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, | 2555 | {0x00009828, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001}, |
| 2542 | {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007}, | 2556 | {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, |
| 2543 | {0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e}, | 2557 | {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007}, |
| 2544 | {0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0}, | 2558 | {0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e}, |
| 2545 | {0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059}, | 2559 | {0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620}, |
| 2546 | {0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059}, | 2560 | {0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053}, |
| 2547 | {0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2}, | 2561 | {0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053}, |
| 2548 | {0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e}, | 2562 | {0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2}, |
| 2549 | {0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e}, | 2563 | {0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e}, |
| 2550 | {0x00009860, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18}, | 2564 | {0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e}, |
| 2551 | {0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00}, | 2565 | {0x00009860, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18}, |
| 2552 | {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, | 2566 | {0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00}, |
| 2553 | {0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881}, | 2567 | {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, |
| 2554 | {0x00009910, 0x30002310, 0x30002310, 0x30002310, 0x30002310, 0x30002310}, | 2568 | {0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881}, |
| 2555 | {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0}, | 2569 | {0x00009910, 0x30002310, 0x30002310, 0x30002310, 0x30002310}, |
| 2556 | {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016}, | 2570 | {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, |
| 2557 | {0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d}, | 2571 | {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b}, |
| 2558 | {0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010}, | 2572 | {0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d}, |
| 2559 | {0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 2573 | {0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020}, |
| 2560 | {0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 2574 | {0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 2561 | {0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c}, | 2575 | {0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 2562 | {0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00}, | 2576 | {0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c}, |
| 2563 | {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, | 2577 | {0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00}, |
| 2564 | {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77}, | 2578 | {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, |
| 2565 | {0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f}, | 2579 | {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77}, |
| 2566 | {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8}, | 2580 | {0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f}, |
| 2567 | {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384}, | 2581 | {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8}, |
| 2568 | {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 2582 | {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384}, |
| 2569 | {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 2583 | {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 2570 | {0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000}, | 2584 | {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 2571 | {0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000}, | 2585 | {0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084}, |
| 2572 | {0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000}, | 2586 | {0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088}, |
| 2573 | {0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000}, | 2587 | {0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c}, |
| 2574 | {0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000}, | 2588 | {0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100}, |
| 2575 | {0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000}, | 2589 | {0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104}, |
| 2576 | {0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000}, | 2590 | {0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108}, |
| 2577 | {0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000}, | 2591 | {0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c}, |
| 2578 | {0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000}, | 2592 | {0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110}, |
| 2579 | {0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000}, | 2593 | {0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114}, |
| 2580 | {0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000}, | 2594 | {0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180}, |
| 2581 | {0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000}, | 2595 | {0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184}, |
| 2582 | {0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000}, | 2596 | {0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188}, |
| 2583 | {0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000}, | 2597 | {0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c}, |
| 2584 | {0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000}, | 2598 | {0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190}, |
| 2585 | {0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000}, | 2599 | {0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194}, |
| 2586 | {0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000}, | 2600 | {0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0}, |
| 2587 | {0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000}, | 2601 | {0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c}, |
| 2588 | {0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000}, | 2602 | {0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8}, |
| 2589 | {0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000}, | 2603 | {0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284}, |
| 2590 | {0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000}, | 2604 | {0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288}, |
| 2591 | {0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000}, | 2605 | {0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224}, |
| 2592 | {0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000}, | 2606 | {0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290}, |
| 2593 | {0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000}, | 2607 | {0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300}, |
| 2594 | {0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000}, | 2608 | {0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304}, |
| 2595 | {0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000}, | 2609 | {0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308}, |
| 2596 | {0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000}, | 2610 | {0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c}, |
| 2597 | {0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000}, | 2611 | {0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380}, |
| 2598 | {0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000}, | 2612 | {0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384}, |
| 2599 | {0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000}, | 2613 | {0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700}, |
| 2600 | {0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000}, | 2614 | {0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704}, |
| 2601 | {0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000}, | 2615 | {0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708}, |
| 2602 | {0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000}, | 2616 | {0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c}, |
| 2603 | {0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000}, | 2617 | {0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780}, |
| 2604 | {0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000}, | 2618 | {0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784}, |
| 2605 | {0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000}, | 2619 | {0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00}, |
| 2606 | {0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000}, | 2620 | {0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04}, |
| 2607 | {0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000}, | 2621 | {0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08}, |
| 2608 | {0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000}, | 2622 | {0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c}, |
| 2609 | {0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000}, | 2623 | {0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80}, |
| 2610 | {0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000}, | 2624 | {0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84}, |
| 2611 | {0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000}, | 2625 | {0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88}, |
| 2612 | {0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000}, | 2626 | {0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c}, |
| 2613 | {0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000}, | 2627 | {0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90}, |
| 2614 | {0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000}, | 2628 | {0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80}, |
| 2615 | {0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000}, | 2629 | {0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84}, |
| 2616 | {0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000}, | 2630 | {0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88}, |
| 2617 | {0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000}, | 2631 | {0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c}, |
| 2618 | {0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000}, | 2632 | {0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90}, |
| 2619 | {0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000}, | 2633 | {0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c}, |
| 2620 | {0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000}, | 2634 | {0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310}, |
| 2621 | {0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000}, | 2635 | {0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384}, |
| 2622 | {0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000}, | 2636 | {0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388}, |
| 2623 | {0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000}, | 2637 | {0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324}, |
| 2624 | {0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000}, | 2638 | {0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704}, |
| 2625 | {0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000}, | 2639 | {0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4}, |
| 2626 | {0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000}, | 2640 | {0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8}, |
| 2627 | {0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000}, | 2641 | {0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710}, |
| 2628 | {0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000}, | 2642 | {0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714}, |
| 2629 | {0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000}, | 2643 | {0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720}, |
| 2630 | {0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000}, | 2644 | {0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724}, |
| 2631 | {0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000}, | 2645 | {0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728}, |
| 2632 | {0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000}, | 2646 | {0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c}, |
| 2633 | {0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000}, | 2647 | {0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0}, |
| 2634 | {0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000}, | 2648 | {0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4}, |
| 2635 | {0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000}, | 2649 | {0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8}, |
| 2636 | {0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000}, | 2650 | {0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0}, |
| 2637 | {0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000}, | 2651 | {0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4}, |
| 2638 | {0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000}, | 2652 | {0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8}, |
| 2639 | {0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000}, | 2653 | {0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5}, |
| 2640 | {0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000}, | 2654 | {0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9}, |
| 2641 | {0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000}, | 2655 | {0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad}, |
| 2642 | {0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000}, | 2656 | {0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1}, |
| 2643 | {0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000}, | 2657 | {0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5}, |
| 2644 | {0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000}, | 2658 | {0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9}, |
| 2645 | {0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000}, | 2659 | {0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5}, |
| 2646 | {0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000}, | 2660 | {0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9}, |
| 2647 | {0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000}, | 2661 | {0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1}, |
| 2648 | {0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000}, | 2662 | {0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5}, |
| 2649 | {0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000}, | 2663 | {0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9}, |
| 2650 | {0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000}, | 2664 | {0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6}, |
| 2651 | {0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000}, | 2665 | {0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca}, |
| 2652 | {0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000}, | 2666 | {0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce}, |
| 2653 | {0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000}, | 2667 | {0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2}, |
| 2654 | {0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000}, | 2668 | {0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6}, |
| 2655 | {0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000}, | 2669 | {0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3}, |
| 2656 | {0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000}, | 2670 | {0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7}, |
| 2657 | {0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000}, | 2671 | {0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb}, |
| 2658 | {0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000}, | 2672 | {0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf}, |
| 2659 | {0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2673 | {0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7}, |
| 2660 | {0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2674 | {0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2661 | {0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2675 | {0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2662 | {0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2676 | {0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2663 | {0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2677 | {0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2664 | {0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2678 | {0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2665 | {0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2679 | {0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2666 | {0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2680 | {0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2667 | {0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2681 | {0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2668 | {0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2682 | {0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2669 | {0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2683 | {0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2670 | {0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2684 | {0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2671 | {0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2685 | {0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2672 | {0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2686 | {0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2673 | {0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2687 | {0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2674 | {0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2688 | {0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2675 | {0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2689 | {0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2676 | {0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2690 | {0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2677 | {0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2691 | {0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2678 | {0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2692 | {0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2679 | {0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2693 | {0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2680 | {0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2694 | {0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2681 | {0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2695 | {0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2682 | {0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2696 | {0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2683 | {0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2697 | {0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2684 | {0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2698 | {0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2685 | {0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2699 | {0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2686 | {0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2700 | {0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2687 | {0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2701 | {0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2688 | {0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2702 | {0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2689 | {0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2703 | {0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2690 | {0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2704 | {0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2691 | {0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2705 | {0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2692 | {0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2706 | {0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2693 | {0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2707 | {0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2694 | {0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2708 | {0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2695 | {0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2709 | {0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2696 | {0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2710 | {0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2697 | {0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2711 | {0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2698 | {0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000}, | 2712 | {0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2699 | {0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000}, | 2713 | {0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084}, |
| 2700 | {0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000}, | 2714 | {0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088}, |
| 2701 | {0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000}, | 2715 | {0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c}, |
| 2702 | {0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000}, | 2716 | {0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100}, |
| 2703 | {0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000}, | 2717 | {0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104}, |
| 2704 | {0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000}, | 2718 | {0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108}, |
| 2705 | {0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000}, | 2719 | {0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c}, |
| 2706 | {0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000}, | 2720 | {0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110}, |
| 2707 | {0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000}, | 2721 | {0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114}, |
| 2708 | {0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000}, | 2722 | {0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180}, |
| 2709 | {0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000}, | 2723 | {0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184}, |
| 2710 | {0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000}, | 2724 | {0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188}, |
| 2711 | {0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000}, | 2725 | {0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c}, |
| 2712 | {0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000}, | 2726 | {0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190}, |
| 2713 | {0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000}, | 2727 | {0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194}, |
| 2714 | {0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000}, | 2728 | {0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0}, |
| 2715 | {0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000}, | 2729 | {0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c}, |
| 2716 | {0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000}, | 2730 | {0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8}, |
| 2717 | {0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000}, | 2731 | {0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284}, |
| 2718 | {0x0000aa50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000}, | 2732 | {0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288}, |
| 2719 | {0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000}, | 2733 | {0x0000aa50, 0x00000000, 0x00000000, 0x00058224, 0x00058224}, |
| 2720 | {0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000}, | 2734 | {0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290}, |
| 2721 | {0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000}, | 2735 | {0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300}, |
| 2722 | {0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000}, | 2736 | {0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304}, |
| 2723 | {0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000}, | 2737 | {0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308}, |
| 2724 | {0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000}, | 2738 | {0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c}, |
| 2725 | {0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000}, | 2739 | {0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380}, |
| 2726 | {0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000}, | 2740 | {0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384}, |
| 2727 | {0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000}, | 2741 | {0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700}, |
| 2728 | {0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000}, | 2742 | {0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704}, |
| 2729 | {0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000}, | 2743 | {0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708}, |
| 2730 | {0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000}, | 2744 | {0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c}, |
| 2731 | {0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000}, | 2745 | {0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780}, |
| 2732 | {0x0000aa88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000}, | 2746 | {0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784}, |
| 2733 | {0x0000aa8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000}, | 2747 | {0x0000aa88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00}, |
| 2734 | {0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000}, | 2748 | {0x0000aa8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04}, |
| 2735 | {0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000}, | 2749 | {0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08}, |
| 2736 | {0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000}, | 2750 | {0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c}, |
| 2737 | {0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000}, | 2751 | {0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80}, |
| 2738 | {0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000}, | 2752 | {0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84}, |
| 2739 | {0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000}, | 2753 | {0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88}, |
| 2740 | {0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000}, | 2754 | {0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c}, |
| 2741 | {0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000}, | 2755 | {0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90}, |
| 2742 | {0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000}, | 2756 | {0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80}, |
| 2743 | {0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000}, | 2757 | {0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84}, |
| 2744 | {0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000}, | 2758 | {0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88}, |
| 2745 | {0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000}, | 2759 | {0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c}, |
| 2746 | {0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000}, | 2760 | {0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90}, |
| 2747 | {0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000}, | 2761 | {0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c}, |
| 2748 | {0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000}, | 2762 | {0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310}, |
| 2749 | {0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000}, | 2763 | {0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384}, |
| 2750 | {0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000}, | 2764 | {0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388}, |
| 2751 | {0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000}, | 2765 | {0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324}, |
| 2752 | {0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000}, | 2766 | {0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704}, |
| 2753 | {0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000}, | 2767 | {0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4}, |
| 2754 | {0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000}, | 2768 | {0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8}, |
| 2755 | {0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000}, | 2769 | {0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710}, |
| 2756 | {0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000}, | 2770 | {0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714}, |
| 2757 | {0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000}, | 2771 | {0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720}, |
| 2758 | {0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000}, | 2772 | {0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724}, |
| 2759 | {0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000}, | 2773 | {0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728}, |
| 2760 | {0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000}, | 2774 | {0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c}, |
| 2761 | {0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000}, | 2775 | {0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0}, |
| 2762 | {0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000}, | 2776 | {0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4}, |
| 2763 | {0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000}, | 2777 | {0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8}, |
| 2764 | {0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000}, | 2778 | {0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0}, |
| 2765 | {0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000}, | 2779 | {0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4}, |
| 2766 | {0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000}, | 2780 | {0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8}, |
| 2767 | {0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000}, | 2781 | {0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5}, |
| 2768 | {0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000}, | 2782 | {0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9}, |
| 2769 | {0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000}, | 2783 | {0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad}, |
| 2770 | {0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000}, | 2784 | {0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1}, |
| 2771 | {0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000}, | 2785 | {0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5}, |
| 2772 | {0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000}, | 2786 | {0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9}, |
| 2773 | {0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000}, | 2787 | {0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5}, |
| 2774 | {0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000}, | 2788 | {0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9}, |
| 2775 | {0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000}, | 2789 | {0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1}, |
| 2776 | {0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000}, | 2790 | {0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5}, |
| 2777 | {0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000}, | 2791 | {0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9}, |
| 2778 | {0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000}, | 2792 | {0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6}, |
| 2779 | {0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000}, | 2793 | {0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca}, |
| 2780 | {0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000}, | 2794 | {0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce}, |
| 2781 | {0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000}, | 2795 | {0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2}, |
| 2782 | {0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000}, | 2796 | {0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6}, |
| 2783 | {0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000}, | 2797 | {0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3}, |
| 2784 | {0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000}, | 2798 | {0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7}, |
| 2785 | {0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000}, | 2799 | {0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb}, |
| 2786 | {0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000}, | 2800 | {0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf}, |
| 2787 | {0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2801 | {0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7}, |
| 2788 | {0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2802 | {0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2789 | {0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2803 | {0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2790 | {0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2804 | {0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2791 | {0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2805 | {0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2792 | {0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2806 | {0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2793 | {0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2807 | {0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2794 | {0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2808 | {0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2795 | {0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2809 | {0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2796 | {0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2810 | {0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2797 | {0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2811 | {0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2798 | {0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2812 | {0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2799 | {0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2813 | {0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2800 | {0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2814 | {0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2801 | {0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2815 | {0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2802 | {0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2816 | {0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2803 | {0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2817 | {0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2804 | {0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2818 | {0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2805 | {0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2819 | {0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2806 | {0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2820 | {0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2807 | {0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2821 | {0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2808 | {0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2822 | {0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2809 | {0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2823 | {0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2810 | {0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2824 | {0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2811 | {0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2825 | {0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2812 | {0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2826 | {0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2813 | {0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2827 | {0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2814 | {0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2828 | {0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2815 | {0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2829 | {0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2816 | {0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2830 | {0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2817 | {0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2831 | {0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2818 | {0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2832 | {0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2819 | {0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2833 | {0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2820 | {0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2834 | {0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2821 | {0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2835 | {0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2822 | {0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2836 | {0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2823 | {0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2837 | {0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2824 | {0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2838 | {0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2825 | {0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000}, | 2839 | {0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2826 | {0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004}, | 2840 | {0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db}, |
| 2827 | {0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000}, | 2841 | {0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004}, |
| 2828 | {0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000}, | 2842 | {0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000}, |
| 2829 | {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a}, | 2843 | {0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000}, |
| 2830 | {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000}, | 2844 | {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a}, |
| 2831 | {0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000}, | 2845 | {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, |
| 2832 | {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e}, | 2846 | {0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000}, |
| 2847 | {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e}, | ||
| 2833 | }; | 2848 | }; |
| 2834 | 2849 | ||
| 2835 | static const u32 ar9271Common_9271[][2] = { | 2850 | static const u32 ar9271Common_9271[][2] = { |
| @@ -3175,91 +3190,95 @@ static const u32 ar9271Common_japan_2484_cck_fir_coeff_9271[][2] = { | |||
| 3175 | {0x0000a1fc, 0xca9228ee}, | 3190 | {0x0000a1fc, 0xca9228ee}, |
| 3176 | }; | 3191 | }; |
| 3177 | 3192 | ||
| 3178 | static const u32 ar9271Modes_9271_1_0_only[][6] = { | 3193 | static const u32 ar9271Modes_9271_1_0_only[][5] = { |
| 3179 | {0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311, 0x30002311}, | 3194 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 3180 | {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001}, | 3195 | {0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311}, |
| 3196 | {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001}, | ||
| 3181 | }; | 3197 | }; |
| 3182 | 3198 | ||
| 3183 | static const u32 ar9271Modes_9271_ANI_reg[][6] = { | 3199 | static const u32 ar9271Modes_9271_ANI_reg[][5] = { |
| 3184 | {0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2}, | 3200 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 3185 | {0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e}, | 3201 | {0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2}, |
| 3186 | {0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e}, | 3202 | {0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e}, |
| 3187 | {0x0000986c, 0x06903881, 0x06903881, 0x06903881, 0x06903881, 0x06903881}, | 3203 | {0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e}, |
| 3188 | {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, | 3204 | {0x0000986c, 0x06903881, 0x06903881, 0x06903881, 0x06903881}, |
| 3189 | {0x0000a208, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8}, | 3205 | {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, |
| 3190 | {0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d}, | 3206 | {0x0000a208, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8}, |
| 3191 | {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, | 3207 | {0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d}, |
| 3208 | {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, | ||
| 3192 | }; | 3209 | }; |
| 3193 | 3210 | ||
| 3194 | static const u32 ar9271Modes_normal_power_tx_gain_9271[][6] = { | 3211 | static const u32 ar9271Modes_normal_power_tx_gain_9271[][5] = { |
| 3195 | {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | 3212 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 3196 | {0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000}, | 3213 | {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, |
| 3197 | {0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000}, | 3214 | {0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200}, |
| 3198 | {0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000}, | 3215 | {0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208}, |
| 3199 | {0x0000a310, 0x00000000, 0x00000000, 0x0001e610, 0x0001e610, 0x00000000}, | 3216 | {0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608}, |
| 3200 | {0x0000a314, 0x00000000, 0x00000000, 0x0002d6d0, 0x0002d6d0, 0x00000000}, | 3217 | {0x0000a310, 0x00000000, 0x00000000, 0x0001e610, 0x0001e610}, |
| 3201 | {0x0000a318, 0x00000000, 0x00000000, 0x00039758, 0x00039758, 0x00000000}, | 3218 | {0x0000a314, 0x00000000, 0x00000000, 0x00024650, 0x00024650}, |
| 3202 | {0x0000a31c, 0x00000000, 0x00000000, 0x0003b759, 0x0003b759, 0x00000000}, | 3219 | {0x0000a318, 0x00000000, 0x00000000, 0x0002d6d0, 0x0002d6d0}, |
| 3203 | {0x0000a320, 0x00000000, 0x00000000, 0x0003d75a, 0x0003d75a, 0x00000000}, | 3220 | {0x0000a31c, 0x00000000, 0x00000000, 0x000316d2, 0x000316d2}, |
| 3204 | {0x0000a324, 0x00000000, 0x00000000, 0x0004175c, 0x0004175c, 0x00000000}, | 3221 | {0x0000a320, 0x00000000, 0x00000000, 0x00039758, 0x00039758}, |
| 3205 | {0x0000a328, 0x00000000, 0x00000000, 0x0004575e, 0x0004575e, 0x00000000}, | 3222 | {0x0000a324, 0x00000000, 0x00000000, 0x0003b759, 0x0003b759}, |
| 3206 | {0x0000a32c, 0x00000000, 0x00000000, 0x0004979f, 0x0004979f, 0x00000000}, | 3223 | {0x0000a328, 0x00000000, 0x00000000, 0x0003d75a, 0x0003d75a}, |
| 3207 | {0x0000a330, 0x00000000, 0x00000000, 0x0004d7df, 0x0004d7df, 0x00000000}, | 3224 | {0x0000a32c, 0x00000000, 0x00000000, 0x0004175c, 0x0004175c}, |
| 3208 | {0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de, 0x00000000}, | 3225 | {0x0000a330, 0x00000000, 0x00000000, 0x0004575e, 0x0004575e}, |
| 3209 | {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000}, | 3226 | {0x0000a334, 0x000368de, 0x000368de, 0x0004979f, 0x0004979f}, |
| 3210 | {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000}, | 3227 | {0x0000a338, 0x0003891e, 0x0003891e, 0x0004d7df, 0x0004d7df}, |
| 3211 | {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 3228 | {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e}, |
| 3212 | {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 3229 | {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 3213 | {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 3230 | {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 3214 | {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 3231 | {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 3215 | {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 3232 | {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 3216 | {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 3233 | {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 3217 | {0x00007838, 0x00000029, 0x00000029, 0x00000029, 0x00000029, 0x00000029}, | 3234 | {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 3218 | {0x00007824, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff}, | 3235 | {0x00007838, 0x00000029, 0x00000029, 0x00000029, 0x00000029}, |
| 3219 | {0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4}, | 3236 | {0x00007824, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff}, |
| 3220 | {0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04}, | 3237 | {0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4}, |
| 3221 | {0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a218652, 0x0a218652, 0x0a22a652}, | 3238 | {0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04}, |
| 3222 | {0x0000a278, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd}, | 3239 | {0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21c652, 0x0a21c652}, |
| 3223 | {0x0000a27c, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd}, | 3240 | {0x0000a278, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd}, |
| 3224 | {0x0000a394, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd}, | 3241 | {0x0000a27c, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd}, |
| 3225 | {0x0000a398, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd}, | 3242 | {0x0000a394, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd}, |
| 3226 | {0x0000a3dc, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd}, | 3243 | {0x0000a398, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd}, |
| 3227 | {0x0000a3e0, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd}, | 3244 | {0x0000a3dc, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd}, |
| 3245 | {0x0000a3e0, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd}, | ||
| 3228 | }; | 3246 | }; |
| 3229 | 3247 | ||
| 3230 | static const u32 ar9271Modes_high_power_tx_gain_9271[][6] = { | 3248 | static const u32 ar9271Modes_high_power_tx_gain_9271[][5] = { |
| 3231 | {0x0000a300, 0x00000000, 0x00000000, 0x00010000, 0x00010000, 0x00000000}, | 3249 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
| 3232 | {0x0000a304, 0x00000000, 0x00000000, 0x00016200, 0x00016200, 0x00000000}, | 3250 | {0x0000a300, 0x00000000, 0x00000000, 0x00010000, 0x00010000}, |
| 3233 | {0x0000a308, 0x00000000, 0x00000000, 0x00018201, 0x00018201, 0x00000000}, | 3251 | {0x0000a304, 0x00000000, 0x00000000, 0x00016200, 0x00016200}, |
| 3234 | {0x0000a30c, 0x00000000, 0x00000000, 0x0001b240, 0x0001b240, 0x00000000}, | 3252 | {0x0000a308, 0x00000000, 0x00000000, 0x00018201, 0x00018201}, |
| 3235 | {0x0000a310, 0x00000000, 0x00000000, 0x0001d241, 0x0001d241, 0x00000000}, | 3253 | {0x0000a30c, 0x00000000, 0x00000000, 0x0001b240, 0x0001b240}, |
| 3236 | {0x0000a314, 0x00000000, 0x00000000, 0x0001f600, 0x0001f600, 0x00000000}, | 3254 | {0x0000a310, 0x00000000, 0x00000000, 0x0001d241, 0x0001d241}, |
| 3237 | {0x0000a318, 0x00000000, 0x00000000, 0x00022800, 0x00022800, 0x00000000}, | 3255 | {0x0000a314, 0x00000000, 0x00000000, 0x0001f600, 0x0001f600}, |
| 3238 | {0x0000a31c, 0x00000000, 0x00000000, 0x00026802, 0x00026802, 0x00000000}, | 3256 | {0x0000a318, 0x00000000, 0x00000000, 0x00022800, 0x00022800}, |
| 3239 | {0x0000a320, 0x00000000, 0x00000000, 0x0002b805, 0x0002b805, 0x00000000}, | 3257 | {0x0000a31c, 0x00000000, 0x00000000, 0x00026802, 0x00026802}, |
| 3240 | {0x0000a324, 0x00000000, 0x00000000, 0x0002ea41, 0x0002ea41, 0x00000000}, | 3258 | {0x0000a320, 0x00000000, 0x00000000, 0x0002b805, 0x0002b805}, |
| 3241 | {0x0000a328, 0x00000000, 0x00000000, 0x00038b00, 0x00038b00, 0x00000000}, | 3259 | {0x0000a324, 0x00000000, 0x00000000, 0x0002ea41, 0x0002ea41}, |
| 3242 | {0x0000a32c, 0x00000000, 0x00000000, 0x0003ab40, 0x0003ab40, 0x00000000}, | 3260 | {0x0000a328, 0x00000000, 0x00000000, 0x00038b00, 0x00038b00}, |
| 3243 | {0x0000a330, 0x00000000, 0x00000000, 0x0003cd80, 0x0003cd80, 0x00000000}, | 3261 | {0x0000a32c, 0x00000000, 0x00000000, 0x0003ab40, 0x0003ab40}, |
| 3244 | {0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de, 0x00000000}, | 3262 | {0x0000a330, 0x00000000, 0x00000000, 0x0003cd80, 0x0003cd80}, |
| 3245 | {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000}, | 3263 | {0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de}, |
| 3246 | {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000}, | 3264 | {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e}, |
| 3247 | {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 3265 | {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e}, |
| 3248 | {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 3266 | {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 3249 | {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 3267 | {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 3250 | {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 3268 | {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 3251 | {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 3269 | {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 3252 | {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000}, | 3270 | {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 3253 | {0x00007838, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b}, | 3271 | {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df}, |
| 3254 | {0x00007824, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff}, | 3272 | {0x00007838, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b}, |
| 3255 | {0x0000786c, 0x08609eb6, 0x08609eb6, 0x08609eba, 0x08609eba, 0x08609eb6}, | 3273 | {0x00007824, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff}, |
| 3256 | {0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00}, | 3274 | {0x0000786c, 0x08609eb6, 0x08609eb6, 0x08609eba, 0x08609eba}, |
| 3257 | {0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a214652, 0x0a214652, 0x0a22a652}, | 3275 | {0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00}, |
| 3258 | {0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7}, | 3276 | {0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a214652, 0x0a214652}, |
| 3259 | {0x0000a27c, 0x05018063, 0x05038063, 0x05018063, 0x05018063, 0x05018063}, | 3277 | {0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7}, |
| 3260 | {0x0000a394, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63}, | 3278 | {0x0000a27c, 0x05018063, 0x05038063, 0x05018063, 0x05018063}, |
| 3261 | {0x0000a398, 0x00000063, 0x00000063, 0x00000063, 0x00000063, 0x00000063}, | 3279 | {0x0000a394, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63}, |
| 3262 | {0x0000a3dc, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63}, | 3280 | {0x0000a398, 0x00000063, 0x00000063, 0x00000063, 0x00000063}, |
| 3263 | {0x0000a3e0, 0x00000063, 0x00000063, 0x00000063, 0x00000063, 0x00000063}, | 3281 | {0x0000a3dc, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63}, |
| 3282 | {0x0000a3e0, 0x00000063, 0x00000063, 0x00000063, 0x00000063}, | ||
| 3264 | }; | 3283 | }; |
| 3265 | 3284 | ||
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_mac.c b/drivers/net/wireless/ath/ath9k/ar9002_mac.c index 33deb0d574b0..f7d8e516a2a9 100644 --- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c +++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c | |||
| @@ -170,33 +170,104 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) | |||
| 170 | return true; | 170 | return true; |
| 171 | } | 171 | } |
| 172 | 172 | ||
| 173 | static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen, | 173 | static void |
| 174 | bool is_firstseg, bool is_lastseg, | 174 | ar9002_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i) |
| 175 | const void *ds0, dma_addr_t buf_addr, | ||
| 176 | unsigned int qcu) | ||
| 177 | { | 175 | { |
| 178 | struct ar5416_desc *ads = AR5416DESC(ds); | 176 | struct ar5416_desc *ads = AR5416DESC(ds); |
| 177 | u32 ctl1, ctl6; | ||
| 179 | 178 | ||
| 180 | ads->ds_data = buf_addr; | ||
| 181 | |||
| 182 | if (is_firstseg) { | ||
| 183 | ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore); | ||
| 184 | } else if (is_lastseg) { | ||
| 185 | ads->ds_ctl0 = 0; | ||
| 186 | ads->ds_ctl1 = seglen; | ||
| 187 | ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2; | ||
| 188 | ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3; | ||
| 189 | } else { | ||
| 190 | ads->ds_ctl0 = 0; | ||
| 191 | ads->ds_ctl1 = seglen | AR_TxMore; | ||
| 192 | ads->ds_ctl2 = 0; | ||
| 193 | ads->ds_ctl3 = 0; | ||
| 194 | } | ||
| 195 | ads->ds_txstatus0 = ads->ds_txstatus1 = 0; | 179 | ads->ds_txstatus0 = ads->ds_txstatus1 = 0; |
| 196 | ads->ds_txstatus2 = ads->ds_txstatus3 = 0; | 180 | ads->ds_txstatus2 = ads->ds_txstatus3 = 0; |
| 197 | ads->ds_txstatus4 = ads->ds_txstatus5 = 0; | 181 | ads->ds_txstatus4 = ads->ds_txstatus5 = 0; |
| 198 | ads->ds_txstatus6 = ads->ds_txstatus7 = 0; | 182 | ads->ds_txstatus6 = ads->ds_txstatus7 = 0; |
| 199 | ads->ds_txstatus8 = ads->ds_txstatus9 = 0; | 183 | ads->ds_txstatus8 = ads->ds_txstatus9 = 0; |
| 184 | |||
| 185 | ACCESS_ONCE(ads->ds_link) = i->link; | ||
| 186 | ACCESS_ONCE(ads->ds_data) = i->buf_addr[0]; | ||
| 187 | |||
| 188 | ctl1 = i->buf_len[0] | (i->is_last ? 0 : AR_TxMore); | ||
| 189 | ctl6 = SM(i->keytype, AR_EncrType); | ||
| 190 | |||
| 191 | if (AR_SREV_9285(ah)) { | ||
| 192 | ads->ds_ctl8 = 0; | ||
| 193 | ads->ds_ctl9 = 0; | ||
| 194 | ads->ds_ctl10 = 0; | ||
| 195 | ads->ds_ctl11 = 0; | ||
| 196 | } | ||
| 197 | |||
| 198 | if ((i->is_first || i->is_last) && | ||
| 199 | i->aggr != AGGR_BUF_MIDDLE && i->aggr != AGGR_BUF_LAST) { | ||
| 200 | ACCESS_ONCE(ads->ds_ctl2) = set11nTries(i->rates, 0) | ||
| 201 | | set11nTries(i->rates, 1) | ||
| 202 | | set11nTries(i->rates, 2) | ||
| 203 | | set11nTries(i->rates, 3) | ||
| 204 | | (i->dur_update ? AR_DurUpdateEna : 0) | ||
| 205 | | SM(0, AR_BurstDur); | ||
| 206 | |||
| 207 | ACCESS_ONCE(ads->ds_ctl3) = set11nRate(i->rates, 0) | ||
| 208 | | set11nRate(i->rates, 1) | ||
| 209 | | set11nRate(i->rates, 2) | ||
| 210 | | set11nRate(i->rates, 3); | ||
| 211 | } else { | ||
| 212 | ACCESS_ONCE(ads->ds_ctl2) = 0; | ||
| 213 | ACCESS_ONCE(ads->ds_ctl3) = 0; | ||
| 214 | } | ||
| 215 | |||
| 216 | if (!i->is_first) { | ||
| 217 | ACCESS_ONCE(ads->ds_ctl0) = 0; | ||
| 218 | ACCESS_ONCE(ads->ds_ctl1) = ctl1; | ||
| 219 | ACCESS_ONCE(ads->ds_ctl6) = ctl6; | ||
| 220 | return; | ||
| 221 | } | ||
| 222 | |||
| 223 | ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0) | ||
| 224 | | SM(i->type, AR_FrameType) | ||
| 225 | | (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) | ||
| 226 | | (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) | ||
| 227 | | (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); | ||
| 228 | |||
| 229 | switch (i->aggr) { | ||
| 230 | case AGGR_BUF_FIRST: | ||
| 231 | ctl6 |= SM(i->aggr_len, AR_AggrLen); | ||
| 232 | /* fall through */ | ||
| 233 | case AGGR_BUF_MIDDLE: | ||
| 234 | ctl1 |= AR_IsAggr | AR_MoreAggr; | ||
| 235 | ctl6 |= SM(i->ndelim, AR_PadDelim); | ||
| 236 | break; | ||
| 237 | case AGGR_BUF_LAST: | ||
| 238 | ctl1 |= AR_IsAggr; | ||
| 239 | break; | ||
| 240 | case AGGR_BUF_NONE: | ||
| 241 | break; | ||
| 242 | } | ||
| 243 | |||
| 244 | ACCESS_ONCE(ads->ds_ctl0) = (i->pkt_len & AR_FrameLen) | ||
| 245 | | (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) | ||
| 246 | | SM(i->txpower, AR_XmitPower) | ||
| 247 | | (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) | ||
| 248 | | (i->flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0) | ||
| 249 | | (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0) | ||
| 250 | | (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) | ||
| 251 | | (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable : | ||
| 252 | (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0)); | ||
| 253 | |||
| 254 | ACCESS_ONCE(ads->ds_ctl1) = ctl1; | ||
| 255 | ACCESS_ONCE(ads->ds_ctl6) = ctl6; | ||
| 256 | |||
| 257 | if (i->aggr == AGGR_BUF_MIDDLE || i->aggr == AGGR_BUF_LAST) | ||
| 258 | return; | ||
| 259 | |||
| 260 | ACCESS_ONCE(ads->ds_ctl4) = set11nPktDurRTSCTS(i->rates, 0) | ||
| 261 | | set11nPktDurRTSCTS(i->rates, 1); | ||
| 262 | |||
| 263 | ACCESS_ONCE(ads->ds_ctl5) = set11nPktDurRTSCTS(i->rates, 2) | ||
| 264 | | set11nPktDurRTSCTS(i->rates, 3); | ||
| 265 | |||
| 266 | ACCESS_ONCE(ads->ds_ctl7) = set11nRateFlags(i->rates, 0) | ||
| 267 | | set11nRateFlags(i->rates, 1) | ||
| 268 | | set11nRateFlags(i->rates, 2) | ||
| 269 | | set11nRateFlags(i->rates, 3) | ||
| 270 | | SM(i->rtscts_rate, AR_RTSCTSRate); | ||
| 200 | } | 271 | } |
| 201 | 272 | ||
| 202 | static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds, | 273 | static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds, |
| @@ -271,145 +342,6 @@ static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds, | |||
| 271 | return 0; | 342 | return 0; |
| 272 | } | 343 | } |
| 273 | 344 | ||
| 274 | static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds, | ||
| 275 | u32 pktLen, enum ath9k_pkt_type type, | ||
| 276 | u32 txPower, u8 keyIx, | ||
| 277 | enum ath9k_key_type keyType, u32 flags) | ||
| 278 | { | ||
| 279 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 280 | |||
| 281 | if (txPower > 63) | ||
| 282 | txPower = 63; | ||
| 283 | |||
| 284 | ads->ds_ctl0 = (pktLen & AR_FrameLen) | ||
| 285 | | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) | ||
| 286 | | SM(txPower, AR_XmitPower) | ||
| 287 | | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) | ||
| 288 | | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0) | ||
| 289 | | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0); | ||
| 290 | |||
| 291 | ads->ds_ctl1 = | ||
| 292 | (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0) | ||
| 293 | | SM(type, AR_FrameType) | ||
| 294 | | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) | ||
| 295 | | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) | ||
| 296 | | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); | ||
| 297 | |||
| 298 | ads->ds_ctl6 = SM(keyType, AR_EncrType); | ||
| 299 | |||
| 300 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) { | ||
| 301 | ads->ds_ctl8 = 0; | ||
| 302 | ads->ds_ctl9 = 0; | ||
| 303 | ads->ds_ctl10 = 0; | ||
| 304 | ads->ds_ctl11 = 0; | ||
| 305 | } | ||
| 306 | } | ||
| 307 | |||
| 308 | static void ar9002_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val) | ||
| 309 | { | ||
| 310 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 311 | |||
| 312 | if (val) | ||
| 313 | ads->ds_ctl0 |= AR_ClrDestMask; | ||
| 314 | else | ||
| 315 | ads->ds_ctl0 &= ~AR_ClrDestMask; | ||
| 316 | } | ||
| 317 | |||
| 318 | static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds, | ||
| 319 | void *lastds, | ||
| 320 | u32 durUpdateEn, u32 rtsctsRate, | ||
| 321 | u32 rtsctsDuration, | ||
| 322 | struct ath9k_11n_rate_series series[], | ||
| 323 | u32 nseries, u32 flags) | ||
| 324 | { | ||
| 325 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 326 | struct ar5416_desc *last_ads = AR5416DESC(lastds); | ||
| 327 | u32 ds_ctl0; | ||
| 328 | |||
| 329 | if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) { | ||
| 330 | ds_ctl0 = ads->ds_ctl0; | ||
| 331 | |||
| 332 | if (flags & ATH9K_TXDESC_RTSENA) { | ||
| 333 | ds_ctl0 &= ~AR_CTSEnable; | ||
| 334 | ds_ctl0 |= AR_RTSEnable; | ||
| 335 | } else { | ||
| 336 | ds_ctl0 &= ~AR_RTSEnable; | ||
| 337 | ds_ctl0 |= AR_CTSEnable; | ||
| 338 | } | ||
| 339 | |||
| 340 | ads->ds_ctl0 = ds_ctl0; | ||
| 341 | } else { | ||
| 342 | ads->ds_ctl0 = | ||
| 343 | (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable)); | ||
| 344 | } | ||
| 345 | |||
| 346 | ads->ds_ctl2 = set11nTries(series, 0) | ||
| 347 | | set11nTries(series, 1) | ||
| 348 | | set11nTries(series, 2) | ||
| 349 | | set11nTries(series, 3) | ||
| 350 | | (durUpdateEn ? AR_DurUpdateEna : 0) | ||
| 351 | | SM(0, AR_BurstDur); | ||
| 352 | |||
| 353 | ads->ds_ctl3 = set11nRate(series, 0) | ||
| 354 | | set11nRate(series, 1) | ||
| 355 | | set11nRate(series, 2) | ||
| 356 | | set11nRate(series, 3); | ||
| 357 | |||
| 358 | ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0) | ||
| 359 | | set11nPktDurRTSCTS(series, 1); | ||
| 360 | |||
| 361 | ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2) | ||
| 362 | | set11nPktDurRTSCTS(series, 3); | ||
| 363 | |||
| 364 | ads->ds_ctl7 = set11nRateFlags(series, 0) | ||
| 365 | | set11nRateFlags(series, 1) | ||
| 366 | | set11nRateFlags(series, 2) | ||
| 367 | | set11nRateFlags(series, 3) | ||
| 368 | | SM(rtsctsRate, AR_RTSCTSRate); | ||
| 369 | last_ads->ds_ctl2 = ads->ds_ctl2; | ||
| 370 | last_ads->ds_ctl3 = ads->ds_ctl3; | ||
| 371 | } | ||
| 372 | |||
| 373 | static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds, | ||
| 374 | u32 aggrLen) | ||
| 375 | { | ||
| 376 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 377 | |||
| 378 | ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); | ||
| 379 | ads->ds_ctl6 &= ~AR_AggrLen; | ||
| 380 | ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen); | ||
| 381 | } | ||
| 382 | |||
| 383 | static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds, | ||
| 384 | u32 numDelims) | ||
| 385 | { | ||
| 386 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 387 | unsigned int ctl6; | ||
| 388 | |||
| 389 | ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); | ||
| 390 | |||
| 391 | ctl6 = ads->ds_ctl6; | ||
| 392 | ctl6 &= ~AR_PadDelim; | ||
| 393 | ctl6 |= SM(numDelims, AR_PadDelim); | ||
| 394 | ads->ds_ctl6 = ctl6; | ||
| 395 | } | ||
| 396 | |||
| 397 | static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds) | ||
| 398 | { | ||
| 399 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 400 | |||
| 401 | ads->ds_ctl1 |= AR_IsAggr; | ||
| 402 | ads->ds_ctl1 &= ~AR_MoreAggr; | ||
| 403 | ads->ds_ctl6 &= ~AR_PadDelim; | ||
| 404 | } | ||
| 405 | |||
| 406 | static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds) | ||
| 407 | { | ||
| 408 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 409 | |||
| 410 | ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr); | ||
| 411 | } | ||
| 412 | |||
| 413 | void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, | 345 | void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, |
| 414 | u32 size, u32 flags) | 346 | u32 size, u32 flags) |
| 415 | { | 347 | { |
| @@ -433,13 +365,6 @@ void ar9002_hw_attach_mac_ops(struct ath_hw *ah) | |||
| 433 | ops->rx_enable = ar9002_hw_rx_enable; | 365 | ops->rx_enable = ar9002_hw_rx_enable; |
| 434 | ops->set_desc_link = ar9002_hw_set_desc_link; | 366 | ops->set_desc_link = ar9002_hw_set_desc_link; |
| 435 | ops->get_isr = ar9002_hw_get_isr; | 367 | ops->get_isr = ar9002_hw_get_isr; |
| 436 | ops->fill_txdesc = ar9002_hw_fill_txdesc; | 368 | ops->set_txdesc = ar9002_set_txdesc; |
| 437 | ops->proc_txdesc = ar9002_hw_proc_txdesc; | 369 | ops->proc_txdesc = ar9002_hw_proc_txdesc; |
| 438 | ops->set11n_txdesc = ar9002_hw_set11n_txdesc; | ||
| 439 | ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario; | ||
| 440 | ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first; | ||
| 441 | ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle; | ||
| 442 | ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last; | ||
| 443 | ops->clr11n_aggr = ar9002_hw_clr11n_aggr; | ||
| 444 | ops->set_clrdmask = ar9002_hw_set_clrdmask; | ||
| 445 | } | 370 | } |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c index fa35a0235f44..3319a676c0fb 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c | |||
| @@ -615,11 +615,10 @@ static void ar9003_hw_detect_outlier(int *mp_coeff, int nmeasurement, | |||
| 615 | { | 615 | { |
| 616 | int mp_max = -64, max_idx = 0; | 616 | int mp_max = -64, max_idx = 0; |
| 617 | int mp_min = 63, min_idx = 0; | 617 | int mp_min = 63, min_idx = 0; |
| 618 | int mp_avg = 0, i, outlier_idx = 0; | 618 | int mp_avg = 0, i, outlier_idx = 0, mp_count = 0; |
| 619 | 619 | ||
| 620 | /* find min/max mismatch across all calibrated gains */ | 620 | /* find min/max mismatch across all calibrated gains */ |
| 621 | for (i = 0; i < nmeasurement; i++) { | 621 | for (i = 0; i < nmeasurement; i++) { |
| 622 | mp_avg += mp_coeff[i]; | ||
| 623 | if (mp_coeff[i] > mp_max) { | 622 | if (mp_coeff[i] > mp_max) { |
| 624 | mp_max = mp_coeff[i]; | 623 | mp_max = mp_coeff[i]; |
| 625 | max_idx = i; | 624 | max_idx = i; |
| @@ -632,10 +631,20 @@ static void ar9003_hw_detect_outlier(int *mp_coeff, int nmeasurement, | |||
| 632 | /* find average (exclude max abs value) */ | 631 | /* find average (exclude max abs value) */ |
| 633 | for (i = 0; i < nmeasurement; i++) { | 632 | for (i = 0; i < nmeasurement; i++) { |
| 634 | if ((abs(mp_coeff[i]) < abs(mp_max)) || | 633 | if ((abs(mp_coeff[i]) < abs(mp_max)) || |
| 635 | (abs(mp_coeff[i]) < abs(mp_min))) | 634 | (abs(mp_coeff[i]) < abs(mp_min))) { |
| 636 | mp_avg += mp_coeff[i]; | 635 | mp_avg += mp_coeff[i]; |
| 636 | mp_count++; | ||
| 637 | } | ||
| 637 | } | 638 | } |
| 638 | mp_avg /= (nmeasurement - 1); | 639 | |
| 640 | /* | ||
| 641 | * finding mean magnitude/phase if possible, otherwise | ||
| 642 | * just use the last value as the mean | ||
| 643 | */ | ||
| 644 | if (mp_count) | ||
| 645 | mp_avg /= mp_count; | ||
| 646 | else | ||
| 647 | mp_avg = mp_coeff[nmeasurement - 1]; | ||
| 639 | 648 | ||
| 640 | /* detect outlier */ | 649 | /* detect outlier */ |
| 641 | if (abs(mp_max - mp_min) > max_delta) { | 650 | if (abs(mp_max - mp_min) > max_delta) { |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c index 5f3ac251b486..a73e50d80cbb 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | |||
| @@ -22,25 +22,6 @@ | |||
| 22 | #define COMP_HDR_LEN 4 | 22 | #define COMP_HDR_LEN 4 |
| 23 | #define COMP_CKSUM_LEN 2 | 23 | #define COMP_CKSUM_LEN 2 |
| 24 | 24 | ||
| 25 | #define AR_CH0_TOP (0x00016288) | ||
| 26 | #define AR_CH0_TOP_XPABIASLVL (0x300) | ||
| 27 | #define AR_CH0_TOP_XPABIASLVL_S (8) | ||
| 28 | |||
| 29 | #define AR_CH0_THERM (0x00016290) | ||
| 30 | #define AR_CH0_THERM_XPABIASLVL_MSB 0x3 | ||
| 31 | #define AR_CH0_THERM_XPABIASLVL_MSB_S 0 | ||
| 32 | #define AR_CH0_THERM_XPASHORT2GND 0x4 | ||
| 33 | #define AR_CH0_THERM_XPASHORT2GND_S 2 | ||
| 34 | |||
| 35 | #define AR_SWITCH_TABLE_COM_ALL (0xffff) | ||
| 36 | #define AR_SWITCH_TABLE_COM_ALL_S (0) | ||
| 37 | |||
| 38 | #define AR_SWITCH_TABLE_COM2_ALL (0xffffff) | ||
| 39 | #define AR_SWITCH_TABLE_COM2_ALL_S (0) | ||
| 40 | |||
| 41 | #define AR_SWITCH_TABLE_ALL (0xfff) | ||
| 42 | #define AR_SWITCH_TABLE_ALL_S (0) | ||
| 43 | |||
| 44 | #define LE16(x) __constant_cpu_to_le16(x) | 25 | #define LE16(x) __constant_cpu_to_le16(x) |
| 45 | #define LE32(x) __constant_cpu_to_le32(x) | 26 | #define LE32(x) __constant_cpu_to_le32(x) |
| 46 | 27 | ||
| @@ -158,7 +139,7 @@ static const struct ar9300_eeprom ar9300_default = { | |||
| 158 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), | 139 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), |
| 159 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), | 140 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), |
| 160 | .futureModal = { | 141 | .futureModal = { |
| 161 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 142 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 162 | }, | 143 | }, |
| 163 | }, | 144 | }, |
| 164 | .base_ext1 = { | 145 | .base_ext1 = { |
| @@ -360,7 +341,7 @@ static const struct ar9300_eeprom ar9300_default = { | |||
| 360 | .papdRateMaskHt20 = LE32(0x0c80c080), | 341 | .papdRateMaskHt20 = LE32(0x0c80c080), |
| 361 | .papdRateMaskHt40 = LE32(0x0080c080), | 342 | .papdRateMaskHt40 = LE32(0x0080c080), |
| 362 | .futureModal = { | 343 | .futureModal = { |
| 363 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 344 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 364 | }, | 345 | }, |
| 365 | }, | 346 | }, |
| 366 | .base_ext2 = { | 347 | .base_ext2 = { |
| @@ -735,7 +716,7 @@ static const struct ar9300_eeprom ar9300_x113 = { | |||
| 735 | .papdRateMaskHt20 = LE32(0x0c80c080), | 716 | .papdRateMaskHt20 = LE32(0x0c80c080), |
| 736 | .papdRateMaskHt40 = LE32(0x0080c080), | 717 | .papdRateMaskHt40 = LE32(0x0080c080), |
| 737 | .futureModal = { | 718 | .futureModal = { |
| 738 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 719 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 739 | }, | 720 | }, |
| 740 | }, | 721 | }, |
| 741 | .base_ext1 = { | 722 | .base_ext1 = { |
| @@ -937,7 +918,7 @@ static const struct ar9300_eeprom ar9300_x113 = { | |||
| 937 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), | 918 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), |
| 938 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), | 919 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), |
| 939 | .futureModal = { | 920 | .futureModal = { |
| 940 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 921 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 941 | }, | 922 | }, |
| 942 | }, | 923 | }, |
| 943 | .base_ext2 = { | 924 | .base_ext2 = { |
| @@ -1313,7 +1294,7 @@ static const struct ar9300_eeprom ar9300_h112 = { | |||
| 1313 | .papdRateMaskHt20 = LE32(0x80c080), | 1294 | .papdRateMaskHt20 = LE32(0x80c080), |
| 1314 | .papdRateMaskHt40 = LE32(0x80c080), | 1295 | .papdRateMaskHt40 = LE32(0x80c080), |
| 1315 | .futureModal = { | 1296 | .futureModal = { |
| 1316 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 1297 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 1317 | }, | 1298 | }, |
| 1318 | }, | 1299 | }, |
| 1319 | .base_ext1 = { | 1300 | .base_ext1 = { |
| @@ -1515,7 +1496,7 @@ static const struct ar9300_eeprom ar9300_h112 = { | |||
| 1515 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), | 1496 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), |
| 1516 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), | 1497 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), |
| 1517 | .futureModal = { | 1498 | .futureModal = { |
| 1518 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 1499 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 1519 | }, | 1500 | }, |
| 1520 | }, | 1501 | }, |
| 1521 | .base_ext2 = { | 1502 | .base_ext2 = { |
| @@ -1891,7 +1872,7 @@ static const struct ar9300_eeprom ar9300_x112 = { | |||
| 1891 | .papdRateMaskHt20 = LE32(0x0c80c080), | 1872 | .papdRateMaskHt20 = LE32(0x0c80c080), |
| 1892 | .papdRateMaskHt40 = LE32(0x0080c080), | 1873 | .papdRateMaskHt40 = LE32(0x0080c080), |
| 1893 | .futureModal = { | 1874 | .futureModal = { |
| 1894 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 1875 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 1895 | }, | 1876 | }, |
| 1896 | }, | 1877 | }, |
| 1897 | .base_ext1 = { | 1878 | .base_ext1 = { |
| @@ -2093,7 +2074,7 @@ static const struct ar9300_eeprom ar9300_x112 = { | |||
| 2093 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), | 2074 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), |
| 2094 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), | 2075 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), |
| 2095 | .futureModal = { | 2076 | .futureModal = { |
| 2096 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 2077 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 2097 | }, | 2078 | }, |
| 2098 | }, | 2079 | }, |
| 2099 | .base_ext2 = { | 2080 | .base_ext2 = { |
| @@ -2468,7 +2449,7 @@ static const struct ar9300_eeprom ar9300_h116 = { | |||
| 2468 | .papdRateMaskHt20 = LE32(0x0c80C080), | 2449 | .papdRateMaskHt20 = LE32(0x0c80C080), |
| 2469 | .papdRateMaskHt40 = LE32(0x0080C080), | 2450 | .papdRateMaskHt40 = LE32(0x0080C080), |
| 2470 | .futureModal = { | 2451 | .futureModal = { |
| 2471 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 2452 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 2472 | }, | 2453 | }, |
| 2473 | }, | 2454 | }, |
| 2474 | .base_ext1 = { | 2455 | .base_ext1 = { |
| @@ -2670,7 +2651,7 @@ static const struct ar9300_eeprom ar9300_h116 = { | |||
| 2670 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), | 2651 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), |
| 2671 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), | 2652 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), |
| 2672 | .futureModal = { | 2653 | .futureModal = { |
| 2673 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 2654 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 2674 | }, | 2655 | }, |
| 2675 | }, | 2656 | }, |
| 2676 | .base_ext2 = { | 2657 | .base_ext2 = { |
| @@ -3573,6 +3554,8 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) | |||
| 3573 | 3554 | ||
| 3574 | if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) | 3555 | if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) |
| 3575 | REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias); | 3556 | REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias); |
| 3557 | else if (AR_SREV_9480(ah)) | ||
| 3558 | REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); | ||
| 3576 | else { | 3559 | else { |
| 3577 | REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); | 3560 | REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); |
| 3578 | REG_RMW_FIELD(ah, AR_CH0_THERM, | 3561 | REG_RMW_FIELD(ah, AR_CH0_THERM, |
| @@ -3583,6 +3566,19 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) | |||
| 3583 | } | 3566 | } |
| 3584 | } | 3567 | } |
| 3585 | 3568 | ||
| 3569 | static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is_2ghz) | ||
| 3570 | { | ||
| 3571 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | ||
| 3572 | __le32 val; | ||
| 3573 | |||
| 3574 | if (is_2ghz) | ||
| 3575 | val = eep->modalHeader2G.switchcomspdt; | ||
| 3576 | else | ||
| 3577 | val = eep->modalHeader5G.switchcomspdt; | ||
| 3578 | return le32_to_cpu(val); | ||
| 3579 | } | ||
| 3580 | |||
| 3581 | |||
| 3586 | static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz) | 3582 | static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz) |
| 3587 | { | 3583 | { |
| 3588 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | 3584 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
| @@ -3637,7 +3633,36 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) | |||
| 3637 | 3633 | ||
| 3638 | u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz); | 3634 | u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz); |
| 3639 | 3635 | ||
| 3640 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value); | 3636 | if (AR_SREV_9480(ah)) { |
| 3637 | if (AR_SREV_9480_10(ah)) { | ||
| 3638 | value &= ~AR_SWITCH_TABLE_COM_SPDT; | ||
| 3639 | value |= 0x00100000; | ||
| 3640 | } | ||
| 3641 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, | ||
| 3642 | AR_SWITCH_TABLE_COM_AR9480_ALL, value); | ||
| 3643 | } else | ||
| 3644 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, | ||
| 3645 | AR_SWITCH_TABLE_COM_ALL, value); | ||
| 3646 | |||
| 3647 | |||
| 3648 | /* | ||
| 3649 | * AR9480 defines new switch table for BT/WLAN, | ||
| 3650 | * here's new field name in XXX.ref for both 2G and 5G. | ||
| 3651 | * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044) | ||
| 3652 | * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX | ||
| 3653 | * SWITCH_TABLE_COM_SPDT_WLAN_RX | ||
| 3654 | * | ||
| 3655 | * 11:8 R/W SWITCH_TABLE_COM_SPDT_WLAN_TX | ||
| 3656 | * SWITCH_TABLE_COM_SPDT_WLAN_TX | ||
| 3657 | * | ||
| 3658 | * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE | ||
| 3659 | * SWITCH_TABLE_COM_SPDT_WLAN_IDLE | ||
| 3660 | */ | ||
| 3661 | if (AR_SREV_9480_20_OR_LATER(ah)) { | ||
| 3662 | value = ar9003_switch_com_spdt_get(ah, is2ghz); | ||
| 3663 | REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, | ||
| 3664 | AR_SWITCH_TABLE_COM_SPDT_ALL, value); | ||
| 3665 | } | ||
| 3641 | 3666 | ||
| 3642 | value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz); | 3667 | value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz); |
| 3643 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value); | 3668 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value); |
| @@ -3837,6 +3862,7 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) | |||
| 3837 | { | 3862 | { |
| 3838 | int internal_regulator = | 3863 | int internal_regulator = |
| 3839 | ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR); | 3864 | ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR); |
| 3865 | u32 reg_val; | ||
| 3840 | 3866 | ||
| 3841 | if (internal_regulator) { | 3867 | if (internal_regulator) { |
| 3842 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { | 3868 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { |
| @@ -3881,13 +3907,16 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) | |||
| 3881 | REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); | 3907 | REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); |
| 3882 | if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) | 3908 | if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) |
| 3883 | return; | 3909 | return; |
| 3910 | } else if (AR_SREV_9480(ah)) { | ||
| 3911 | reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG); | ||
| 3912 | REG_WRITE(ah, AR_PHY_PMU1, reg_val); | ||
| 3884 | } else { | 3913 | } else { |
| 3885 | /* Internal regulator is ON. Write swreg register. */ | 3914 | /* Internal regulator is ON. Write swreg register. */ |
| 3886 | int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG); | 3915 | reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG); |
| 3887 | REG_WRITE(ah, AR_RTC_REG_CONTROL1, | 3916 | REG_WRITE(ah, AR_RTC_REG_CONTROL1, |
| 3888 | REG_READ(ah, AR_RTC_REG_CONTROL1) & | 3917 | REG_READ(ah, AR_RTC_REG_CONTROL1) & |
| 3889 | (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM)); | 3918 | (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM)); |
| 3890 | REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg); | 3919 | REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val); |
| 3891 | /* Set REG_CONTROL1.SWREG_PROGRAM */ | 3920 | /* Set REG_CONTROL1.SWREG_PROGRAM */ |
| 3892 | REG_WRITE(ah, AR_RTC_REG_CONTROL1, | 3921 | REG_WRITE(ah, AR_RTC_REG_CONTROL1, |
| 3893 | REG_READ(ah, | 3922 | REG_READ(ah, |
| @@ -3898,22 +3927,24 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) | |||
| 3898 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { | 3927 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { |
| 3899 | REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0); | 3928 | REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0); |
| 3900 | while (REG_READ_FIELD(ah, AR_PHY_PMU2, | 3929 | while (REG_READ_FIELD(ah, AR_PHY_PMU2, |
| 3901 | AR_PHY_PMU2_PGM)) | 3930 | AR_PHY_PMU2_PGM)) |
| 3902 | udelay(10); | 3931 | udelay(10); |
| 3903 | 3932 | ||
| 3904 | REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); | 3933 | REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); |
| 3905 | while (!REG_READ_FIELD(ah, AR_PHY_PMU1, | 3934 | while (!REG_READ_FIELD(ah, AR_PHY_PMU1, |
| 3906 | AR_PHY_PMU1_PWD)) | 3935 | AR_PHY_PMU1_PWD)) |
| 3907 | udelay(10); | 3936 | udelay(10); |
| 3908 | REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1); | 3937 | REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1); |
| 3909 | while (!REG_READ_FIELD(ah, AR_PHY_PMU2, | 3938 | while (!REG_READ_FIELD(ah, AR_PHY_PMU2, |
| 3910 | AR_PHY_PMU2_PGM)) | 3939 | AR_PHY_PMU2_PGM)) |
| 3911 | udelay(10); | 3940 | udelay(10); |
| 3912 | } else | 3941 | } else if (AR_SREV_9480(ah)) |
| 3913 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, | 3942 | REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); |
| 3914 | (REG_READ(ah, | 3943 | else { |
| 3915 | AR_RTC_SLEEP_CLK) | | 3944 | reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) | |
| 3916 | AR_RTC_FORCE_SWREG_PRD)); | 3945 | AR_RTC_FORCE_SWREG_PRD; |
| 3946 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val); | ||
| 3947 | } | ||
| 3917 | } | 3948 | } |
| 3918 | 3949 | ||
| 3919 | } | 3950 | } |
| @@ -4493,6 +4524,12 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah, | |||
| 4493 | tempSlope = eep->modalHeader5G.tempSlope; | 4524 | tempSlope = eep->modalHeader5G.tempSlope; |
| 4494 | 4525 | ||
| 4495 | REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope); | 4526 | REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope); |
| 4527 | |||
| 4528 | if (AR_SREV_9480_20(ah)) | ||
| 4529 | REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, | ||
| 4530 | AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope); | ||
| 4531 | |||
| 4532 | |||
| 4496 | REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE, | 4533 | REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE, |
| 4497 | temperature[0]); | 4534 | temperature[0]); |
| 4498 | 4535 | ||
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h index ab21a4915981..6335a867527e 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h | |||
| @@ -233,7 +233,8 @@ struct ar9300_modal_eep_header { | |||
| 233 | u8 thresh62; | 233 | u8 thresh62; |
| 234 | __le32 papdRateMaskHt20; | 234 | __le32 papdRateMaskHt20; |
| 235 | __le32 papdRateMaskHt40; | 235 | __le32 papdRateMaskHt40; |
| 236 | u8 futureModal[10]; | 236 | __le16 switchcomspdt; |
| 237 | u8 futureModal[8]; | ||
| 237 | } __packed; | 238 | } __packed; |
| 238 | 239 | ||
| 239 | struct ar9300_cal_data_per_freq_op_loop { | 240 | struct ar9300_cal_data_per_freq_op_loop { |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c index b6839e695270..901f417bb036 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c | |||
| @@ -22,6 +22,8 @@ | |||
| 22 | #include "ar9330_1p1_initvals.h" | 22 | #include "ar9330_1p1_initvals.h" |
| 23 | #include "ar9330_1p2_initvals.h" | 23 | #include "ar9330_1p2_initvals.h" |
| 24 | #include "ar9580_1p0_initvals.h" | 24 | #include "ar9580_1p0_initvals.h" |
| 25 | #include "ar9480_1p0_initvals.h" | ||
| 26 | #include "ar9480_2p0_initvals.h" | ||
| 25 | 27 | ||
| 26 | /* General hardware code for the AR9003 hadware family */ | 28 | /* General hardware code for the AR9003 hadware family */ |
| 27 | 29 | ||
| @@ -32,6 +34,14 @@ | |||
| 32 | */ | 34 | */ |
| 33 | static void ar9003_hw_init_mode_regs(struct ath_hw *ah) | 35 | static void ar9003_hw_init_mode_regs(struct ath_hw *ah) |
| 34 | { | 36 | { |
| 37 | #define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \ | ||
| 38 | ar9480_pciephy_pll_on_clkreq_disable_L1_2p0 | ||
| 39 | |||
| 40 | #define AR9480_BB_CTX_COEFJ(x) \ | ||
| 41 | ar9480_##x##_baseband_core_txfir_coeff_japan_2484 | ||
| 42 | |||
| 43 | #define AR9480_BBC_TXIFR_COEFFJ \ | ||
| 44 | ar9480_2p0_baseband_core_txfir_coeff_japan_2484 | ||
| 35 | if (AR_SREV_9330_11(ah)) { | 45 | if (AR_SREV_9330_11(ah)) { |
| 36 | /* mac */ | 46 | /* mac */ |
| 37 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); | 47 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); |
| @@ -254,6 +264,132 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) | |||
| 254 | ar9485_1_1_pcie_phy_clkreq_disable_L1, | 264 | ar9485_1_1_pcie_phy_clkreq_disable_L1, |
| 255 | ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1), | 265 | ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1), |
| 256 | 2); | 266 | 2); |
| 267 | } else if (AR_SREV_9480_10(ah)) { | ||
| 268 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); | ||
| 269 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9480_1p0_mac_core, | ||
| 270 | ARRAY_SIZE(ar9480_1p0_mac_core), 2); | ||
| 271 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], | ||
| 272 | ar9480_1p0_mac_postamble, | ||
| 273 | ARRAY_SIZE(ar9480_1p0_mac_postamble), | ||
| 274 | 5); | ||
| 275 | |||
| 276 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); | ||
| 277 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], | ||
| 278 | ar9480_1p0_baseband_core, | ||
| 279 | ARRAY_SIZE(ar9480_1p0_baseband_core), | ||
| 280 | 2); | ||
| 281 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], | ||
| 282 | ar9480_1p0_baseband_postamble, | ||
| 283 | ARRAY_SIZE(ar9480_1p0_baseband_postamble), 5); | ||
| 284 | |||
| 285 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); | ||
| 286 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], | ||
| 287 | ar9480_1p0_radio_core, | ||
| 288 | ARRAY_SIZE(ar9480_1p0_radio_core), 2); | ||
| 289 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], | ||
| 290 | ar9480_1p0_radio_postamble, | ||
| 291 | ARRAY_SIZE(ar9480_1p0_radio_postamble), 5); | ||
| 292 | |||
| 293 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], | ||
| 294 | ar9480_1p0_soc_preamble, | ||
| 295 | ARRAY_SIZE(ar9480_1p0_soc_preamble), 2); | ||
| 296 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); | ||
| 297 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], | ||
| 298 | ar9480_1p0_soc_postamble, | ||
| 299 | ARRAY_SIZE(ar9480_1p0_soc_postamble), 5); | ||
| 300 | |||
| 301 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 302 | ar9480_common_rx_gain_table_1p0, | ||
| 303 | ARRAY_SIZE(ar9480_common_rx_gain_table_1p0), 2); | ||
| 304 | |||
| 305 | /* Awake -> Sleep Setting */ | ||
| 306 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | ||
| 307 | ar9480_pcie_phy_clkreq_disable_L1_1p0, | ||
| 308 | ARRAY_SIZE(ar9480_pcie_phy_clkreq_disable_L1_1p0), | ||
| 309 | 2); | ||
| 310 | |||
| 311 | /* Sleep -> Awake Setting */ | ||
| 312 | INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, | ||
| 313 | ar9480_pcie_phy_clkreq_disable_L1_1p0, | ||
| 314 | ARRAY_SIZE(ar9480_pcie_phy_clkreq_disable_L1_1p0), | ||
| 315 | 2); | ||
| 316 | |||
| 317 | INIT_INI_ARRAY(&ah->iniModesAdditional, | ||
| 318 | ar9480_modes_fast_clock_1p0, | ||
| 319 | ARRAY_SIZE(ar9480_modes_fast_clock_1p0), 3); | ||
| 320 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, | ||
| 321 | AR9480_BB_CTX_COEFJ(1p0), | ||
| 322 | ARRAY_SIZE(AR9480_BB_CTX_COEFJ(1p0)), 2); | ||
| 323 | |||
| 324 | } else if (AR_SREV_9480_20(ah)) { | ||
| 325 | |||
| 326 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); | ||
| 327 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9480_2p0_mac_core, | ||
| 328 | ARRAY_SIZE(ar9480_2p0_mac_core), 2); | ||
| 329 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], | ||
| 330 | ar9480_2p0_mac_postamble, | ||
| 331 | ARRAY_SIZE(ar9480_2p0_mac_postamble), 5); | ||
| 332 | |||
| 333 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); | ||
| 334 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], | ||
| 335 | ar9480_2p0_baseband_core, | ||
| 336 | ARRAY_SIZE(ar9480_2p0_baseband_core), 2); | ||
| 337 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], | ||
| 338 | ar9480_2p0_baseband_postamble, | ||
| 339 | ARRAY_SIZE(ar9480_2p0_baseband_postamble), 5); | ||
| 340 | |||
| 341 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); | ||
| 342 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], | ||
| 343 | ar9480_2p0_radio_core, | ||
| 344 | ARRAY_SIZE(ar9480_2p0_radio_core), 2); | ||
| 345 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], | ||
| 346 | ar9480_2p0_radio_postamble, | ||
| 347 | ARRAY_SIZE(ar9480_2p0_radio_postamble), 5); | ||
| 348 | INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant, | ||
| 349 | ar9480_2p0_radio_postamble_sys2ant, | ||
| 350 | ARRAY_SIZE(ar9480_2p0_radio_postamble_sys2ant), | ||
| 351 | 5); | ||
| 352 | |||
| 353 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], | ||
| 354 | ar9480_2p0_soc_preamble, | ||
| 355 | ARRAY_SIZE(ar9480_2p0_soc_preamble), 2); | ||
| 356 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); | ||
| 357 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], | ||
| 358 | ar9480_2p0_soc_postamble, | ||
| 359 | ARRAY_SIZE(ar9480_2p0_soc_postamble), 5); | ||
| 360 | |||
| 361 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 362 | ar9480_common_rx_gain_table_2p0, | ||
| 363 | ARRAY_SIZE(ar9480_common_rx_gain_table_2p0), 2); | ||
| 364 | |||
| 365 | INIT_INI_ARRAY(&ah->ini_BTCOEX_MAX_TXPWR, | ||
| 366 | ar9480_2p0_BTCOEX_MAX_TXPWR_table, | ||
| 367 | ARRAY_SIZE(ar9480_2p0_BTCOEX_MAX_TXPWR_table), | ||
| 368 | 2); | ||
| 369 | |||
| 370 | /* Awake -> Sleep Setting */ | ||
| 371 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | ||
| 372 | PCIE_PLL_ON_CREQ_DIS_L1_2P0, | ||
| 373 | ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0), | ||
| 374 | 2); | ||
| 375 | /* Sleep -> Awake Setting */ | ||
| 376 | INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, | ||
| 377 | PCIE_PLL_ON_CREQ_DIS_L1_2P0, | ||
| 378 | ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0), | ||
| 379 | 2); | ||
| 380 | |||
| 381 | /* Fast clock modal settings */ | ||
| 382 | INIT_INI_ARRAY(&ah->iniModesAdditional, | ||
| 383 | ar9480_modes_fast_clock_2p0, | ||
| 384 | ARRAY_SIZE(ar9480_modes_fast_clock_2p0), 3); | ||
| 385 | |||
| 386 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, | ||
| 387 | AR9480_BB_CTX_COEFJ(2p0), | ||
| 388 | ARRAY_SIZE(AR9480_BB_CTX_COEFJ(2p0)), 2); | ||
| 389 | |||
| 390 | INIT_INI_ARRAY(&ah->ini_japan2484, AR9480_BBC_TXIFR_COEFFJ, | ||
| 391 | ARRAY_SIZE(AR9480_BBC_TXIFR_COEFFJ), 2); | ||
| 392 | |||
| 257 | } else if (AR_SREV_9580(ah)) { | 393 | } else if (AR_SREV_9580(ah)) { |
| 258 | /* mac */ | 394 | /* mac */ |
| 259 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); | 395 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); |
| @@ -374,208 +510,293 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) | |||
| 374 | } | 510 | } |
| 375 | } | 511 | } |
| 376 | 512 | ||
| 513 | static void ar9003_tx_gain_table_mode0(struct ath_hw *ah) | ||
| 514 | { | ||
| 515 | if (AR_SREV_9330_12(ah)) | ||
| 516 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 517 | ar9331_modes_lowest_ob_db_tx_gain_1p2, | ||
| 518 | ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2), | ||
| 519 | 5); | ||
| 520 | else if (AR_SREV_9330_11(ah)) | ||
| 521 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 522 | ar9331_modes_lowest_ob_db_tx_gain_1p1, | ||
| 523 | ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1), | ||
| 524 | 5); | ||
| 525 | else if (AR_SREV_9340(ah)) | ||
| 526 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 527 | ar9340Modes_lowest_ob_db_tx_gain_table_1p0, | ||
| 528 | ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), | ||
| 529 | 5); | ||
| 530 | else if (AR_SREV_9485_11(ah)) | ||
| 531 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 532 | ar9485_modes_lowest_ob_db_tx_gain_1_1, | ||
| 533 | ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1), | ||
| 534 | 5); | ||
| 535 | else if (AR_SREV_9580(ah)) | ||
| 536 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 537 | ar9580_1p0_lowest_ob_db_tx_gain_table, | ||
| 538 | ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table), | ||
| 539 | 5); | ||
| 540 | else if (AR_SREV_9480_10(ah)) | ||
| 541 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 542 | ar9480_modes_low_ob_db_tx_gain_table_1p0, | ||
| 543 | ARRAY_SIZE(ar9480_modes_low_ob_db_tx_gain_table_1p0), | ||
| 544 | 5); | ||
| 545 | else if (AR_SREV_9480_20(ah)) | ||
| 546 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 547 | ar9480_modes_low_ob_db_tx_gain_table_2p0, | ||
| 548 | ARRAY_SIZE(ar9480_modes_low_ob_db_tx_gain_table_2p0), | ||
| 549 | 5); | ||
| 550 | else | ||
| 551 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 552 | ar9300Modes_lowest_ob_db_tx_gain_table_2p2, | ||
| 553 | ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2), | ||
| 554 | 5); | ||
| 555 | } | ||
| 556 | |||
| 557 | static void ar9003_tx_gain_table_mode1(struct ath_hw *ah) | ||
| 558 | { | ||
| 559 | if (AR_SREV_9330_12(ah)) | ||
| 560 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 561 | ar9331_modes_high_ob_db_tx_gain_1p2, | ||
| 562 | ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2), | ||
| 563 | 5); | ||
| 564 | else if (AR_SREV_9330_11(ah)) | ||
| 565 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 566 | ar9331_modes_high_ob_db_tx_gain_1p1, | ||
| 567 | ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1), | ||
| 568 | 5); | ||
| 569 | else if (AR_SREV_9340(ah)) | ||
| 570 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 571 | ar9340Modes_lowest_ob_db_tx_gain_table_1p0, | ||
| 572 | ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), | ||
| 573 | 5); | ||
| 574 | else if (AR_SREV_9485_11(ah)) | ||
| 575 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 576 | ar9485Modes_high_ob_db_tx_gain_1_1, | ||
| 577 | ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1), | ||
| 578 | 5); | ||
| 579 | else if (AR_SREV_9580(ah)) | ||
| 580 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 581 | ar9580_1p0_high_ob_db_tx_gain_table, | ||
| 582 | ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table), | ||
| 583 | 5); | ||
| 584 | else if (AR_SREV_9480_10(ah)) | ||
| 585 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 586 | ar9480_modes_high_ob_db_tx_gain_table_1p0, | ||
| 587 | ARRAY_SIZE(ar9480_modes_high_ob_db_tx_gain_table_1p0), | ||
| 588 | 5); | ||
| 589 | else if (AR_SREV_9480_20(ah)) | ||
| 590 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 591 | ar9480_modes_high_ob_db_tx_gain_table_2p0, | ||
| 592 | ARRAY_SIZE(ar9480_modes_high_ob_db_tx_gain_table_2p0), | ||
| 593 | 5); | ||
| 594 | else | ||
| 595 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 596 | ar9300Modes_high_ob_db_tx_gain_table_2p2, | ||
| 597 | ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2), | ||
| 598 | 5); | ||
| 599 | } | ||
| 600 | |||
| 601 | static void ar9003_tx_gain_table_mode2(struct ath_hw *ah) | ||
| 602 | { | ||
| 603 | if (AR_SREV_9330_12(ah)) | ||
| 604 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 605 | ar9331_modes_low_ob_db_tx_gain_1p2, | ||
| 606 | ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2), | ||
| 607 | 5); | ||
| 608 | else if (AR_SREV_9330_11(ah)) | ||
| 609 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 610 | ar9331_modes_low_ob_db_tx_gain_1p1, | ||
| 611 | ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1), | ||
| 612 | 5); | ||
| 613 | else if (AR_SREV_9340(ah)) | ||
| 614 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 615 | ar9340Modes_lowest_ob_db_tx_gain_table_1p0, | ||
| 616 | ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), | ||
| 617 | 5); | ||
| 618 | else if (AR_SREV_9485_11(ah)) | ||
| 619 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 620 | ar9485Modes_low_ob_db_tx_gain_1_1, | ||
| 621 | ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1), | ||
| 622 | 5); | ||
| 623 | else if (AR_SREV_9580(ah)) | ||
| 624 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 625 | ar9580_1p0_low_ob_db_tx_gain_table, | ||
| 626 | ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table), | ||
| 627 | 5); | ||
| 628 | else | ||
| 629 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 630 | ar9300Modes_low_ob_db_tx_gain_table_2p2, | ||
| 631 | ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2), | ||
| 632 | 5); | ||
| 633 | } | ||
| 634 | |||
| 635 | static void ar9003_tx_gain_table_mode3(struct ath_hw *ah) | ||
| 636 | { | ||
| 637 | if (AR_SREV_9330_12(ah)) | ||
| 638 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 639 | ar9331_modes_high_power_tx_gain_1p2, | ||
| 640 | ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2), | ||
| 641 | 5); | ||
| 642 | else if (AR_SREV_9330_11(ah)) | ||
| 643 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 644 | ar9331_modes_high_power_tx_gain_1p1, | ||
| 645 | ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1), | ||
| 646 | 5); | ||
| 647 | else if (AR_SREV_9340(ah)) | ||
| 648 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 649 | ar9340Modes_lowest_ob_db_tx_gain_table_1p0, | ||
| 650 | ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), | ||
| 651 | 5); | ||
| 652 | else if (AR_SREV_9485_11(ah)) | ||
| 653 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 654 | ar9485Modes_high_power_tx_gain_1_1, | ||
| 655 | ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1), | ||
| 656 | 5); | ||
| 657 | else if (AR_SREV_9580(ah)) | ||
| 658 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 659 | ar9580_1p0_high_power_tx_gain_table, | ||
| 660 | ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table), | ||
| 661 | 5); | ||
| 662 | else | ||
| 663 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 664 | ar9300Modes_high_power_tx_gain_table_2p2, | ||
| 665 | ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2), | ||
| 666 | 5); | ||
| 667 | } | ||
| 668 | |||
| 377 | static void ar9003_tx_gain_table_apply(struct ath_hw *ah) | 669 | static void ar9003_tx_gain_table_apply(struct ath_hw *ah) |
| 378 | { | 670 | { |
| 379 | switch (ar9003_hw_get_tx_gain_idx(ah)) { | 671 | switch (ar9003_hw_get_tx_gain_idx(ah)) { |
| 380 | case 0: | 672 | case 0: |
| 381 | default: | 673 | default: |
| 382 | if (AR_SREV_9330_12(ah)) | 674 | ar9003_tx_gain_table_mode0(ah); |
| 383 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 384 | ar9331_modes_lowest_ob_db_tx_gain_1p2, | ||
| 385 | ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2), | ||
| 386 | 5); | ||
| 387 | else if (AR_SREV_9330_11(ah)) | ||
| 388 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 389 | ar9331_modes_lowest_ob_db_tx_gain_1p1, | ||
| 390 | ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1), | ||
| 391 | 5); | ||
| 392 | else if (AR_SREV_9340(ah)) | ||
| 393 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 394 | ar9340Modes_lowest_ob_db_tx_gain_table_1p0, | ||
| 395 | ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), | ||
| 396 | 5); | ||
| 397 | else if (AR_SREV_9485_11(ah)) | ||
| 398 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 399 | ar9485_modes_lowest_ob_db_tx_gain_1_1, | ||
| 400 | ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1), | ||
| 401 | 5); | ||
| 402 | else if (AR_SREV_9580(ah)) | ||
| 403 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 404 | ar9580_1p0_lowest_ob_db_tx_gain_table, | ||
| 405 | ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table), | ||
| 406 | 5); | ||
| 407 | else | ||
| 408 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 409 | ar9300Modes_lowest_ob_db_tx_gain_table_2p2, | ||
| 410 | ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2), | ||
| 411 | 5); | ||
| 412 | break; | 675 | break; |
| 413 | case 1: | 676 | case 1: |
| 414 | if (AR_SREV_9330_12(ah)) | 677 | ar9003_tx_gain_table_mode1(ah); |
| 415 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 416 | ar9331_modes_high_ob_db_tx_gain_1p2, | ||
| 417 | ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2), | ||
| 418 | 5); | ||
| 419 | else if (AR_SREV_9330_11(ah)) | ||
| 420 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 421 | ar9331_modes_high_ob_db_tx_gain_1p1, | ||
| 422 | ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1), | ||
| 423 | 5); | ||
| 424 | else if (AR_SREV_9340(ah)) | ||
| 425 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 426 | ar9340Modes_lowest_ob_db_tx_gain_table_1p0, | ||
| 427 | ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), | ||
| 428 | 5); | ||
| 429 | else if (AR_SREV_9485_11(ah)) | ||
| 430 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 431 | ar9485Modes_high_ob_db_tx_gain_1_1, | ||
| 432 | ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1), | ||
| 433 | 5); | ||
| 434 | else if (AR_SREV_9580(ah)) | ||
| 435 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 436 | ar9580_1p0_high_ob_db_tx_gain_table, | ||
| 437 | ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table), | ||
| 438 | 5); | ||
| 439 | else | ||
| 440 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 441 | ar9300Modes_high_ob_db_tx_gain_table_2p2, | ||
| 442 | ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2), | ||
| 443 | 5); | ||
| 444 | break; | 678 | break; |
| 445 | case 2: | 679 | case 2: |
| 446 | if (AR_SREV_9330_12(ah)) | 680 | ar9003_tx_gain_table_mode2(ah); |
| 447 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 448 | ar9331_modes_low_ob_db_tx_gain_1p2, | ||
| 449 | ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2), | ||
| 450 | 5); | ||
| 451 | else if (AR_SREV_9330_11(ah)) | ||
| 452 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 453 | ar9331_modes_low_ob_db_tx_gain_1p1, | ||
| 454 | ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1), | ||
| 455 | 5); | ||
| 456 | else if (AR_SREV_9340(ah)) | ||
| 457 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 458 | ar9340Modes_lowest_ob_db_tx_gain_table_1p0, | ||
| 459 | ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), | ||
| 460 | 5); | ||
| 461 | else if (AR_SREV_9485_11(ah)) | ||
| 462 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 463 | ar9485Modes_low_ob_db_tx_gain_1_1, | ||
| 464 | ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1), | ||
| 465 | 5); | ||
| 466 | else if (AR_SREV_9580(ah)) | ||
| 467 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 468 | ar9580_1p0_low_ob_db_tx_gain_table, | ||
| 469 | ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table), | ||
| 470 | 5); | ||
| 471 | else | ||
| 472 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 473 | ar9300Modes_low_ob_db_tx_gain_table_2p2, | ||
| 474 | ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2), | ||
| 475 | 5); | ||
| 476 | break; | 681 | break; |
| 477 | case 3: | 682 | case 3: |
| 478 | if (AR_SREV_9330_12(ah)) | 683 | ar9003_tx_gain_table_mode3(ah); |
| 479 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 480 | ar9331_modes_high_power_tx_gain_1p2, | ||
| 481 | ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2), | ||
| 482 | 5); | ||
| 483 | else if (AR_SREV_9330_11(ah)) | ||
| 484 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 485 | ar9331_modes_high_power_tx_gain_1p1, | ||
| 486 | ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1), | ||
| 487 | 5); | ||
| 488 | else if (AR_SREV_9340(ah)) | ||
| 489 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 490 | ar9340Modes_lowest_ob_db_tx_gain_table_1p0, | ||
| 491 | ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), | ||
| 492 | 5); | ||
| 493 | else if (AR_SREV_9485_11(ah)) | ||
| 494 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 495 | ar9485Modes_high_power_tx_gain_1_1, | ||
| 496 | ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1), | ||
| 497 | 5); | ||
| 498 | else if (AR_SREV_9580(ah)) | ||
| 499 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 500 | ar9580_1p0_high_power_tx_gain_table, | ||
| 501 | ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table), | ||
| 502 | 5); | ||
| 503 | else | ||
| 504 | INIT_INI_ARRAY(&ah->iniModesTxGain, | ||
| 505 | ar9300Modes_high_power_tx_gain_table_2p2, | ||
| 506 | ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2), | ||
| 507 | 5); | ||
| 508 | break; | 684 | break; |
| 509 | } | 685 | } |
| 510 | } | 686 | } |
| 511 | 687 | ||
| 688 | static void ar9003_rx_gain_table_mode0(struct ath_hw *ah) | ||
| 689 | { | ||
| 690 | if (AR_SREV_9330_12(ah)) | ||
| 691 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 692 | ar9331_common_rx_gain_1p2, | ||
| 693 | ARRAY_SIZE(ar9331_common_rx_gain_1p2), | ||
| 694 | 2); | ||
| 695 | else if (AR_SREV_9330_11(ah)) | ||
| 696 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 697 | ar9331_common_rx_gain_1p1, | ||
| 698 | ARRAY_SIZE(ar9331_common_rx_gain_1p1), | ||
| 699 | 2); | ||
| 700 | else if (AR_SREV_9340(ah)) | ||
| 701 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 702 | ar9340Common_rx_gain_table_1p0, | ||
| 703 | ARRAY_SIZE(ar9340Common_rx_gain_table_1p0), | ||
| 704 | 2); | ||
| 705 | else if (AR_SREV_9485_11(ah)) | ||
| 706 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 707 | ar9485Common_wo_xlna_rx_gain_1_1, | ||
| 708 | ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), | ||
| 709 | 2); | ||
| 710 | else if (AR_SREV_9580(ah)) | ||
| 711 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 712 | ar9580_1p0_rx_gain_table, | ||
| 713 | ARRAY_SIZE(ar9580_1p0_rx_gain_table), | ||
| 714 | 2); | ||
| 715 | else if (AR_SREV_9480_10(ah)) | ||
| 716 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 717 | ar9480_common_rx_gain_table_1p0, | ||
| 718 | ARRAY_SIZE(ar9480_common_rx_gain_table_1p0), | ||
| 719 | 2); | ||
| 720 | else if (AR_SREV_9480_20(ah)) | ||
| 721 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 722 | ar9480_common_rx_gain_table_2p0, | ||
| 723 | ARRAY_SIZE(ar9480_common_rx_gain_table_2p0), | ||
| 724 | 2); | ||
| 725 | else | ||
| 726 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 727 | ar9300Common_rx_gain_table_2p2, | ||
| 728 | ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), | ||
| 729 | 2); | ||
| 730 | } | ||
| 731 | |||
| 732 | static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) | ||
| 733 | { | ||
| 734 | if (AR_SREV_9330_12(ah)) | ||
| 735 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 736 | ar9331_common_wo_xlna_rx_gain_1p2, | ||
| 737 | ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2), | ||
| 738 | 2); | ||
| 739 | else if (AR_SREV_9330_11(ah)) | ||
| 740 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 741 | ar9331_common_wo_xlna_rx_gain_1p1, | ||
| 742 | ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1), | ||
| 743 | 2); | ||
| 744 | else if (AR_SREV_9340(ah)) | ||
| 745 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 746 | ar9340Common_wo_xlna_rx_gain_table_1p0, | ||
| 747 | ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0), | ||
| 748 | 2); | ||
| 749 | else if (AR_SREV_9485_11(ah)) | ||
| 750 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 751 | ar9485Common_wo_xlna_rx_gain_1_1, | ||
| 752 | ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), | ||
| 753 | 2); | ||
| 754 | else if (AR_SREV_9480_10(ah)) | ||
| 755 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 756 | ar9480_common_wo_xlna_rx_gain_table_1p0, | ||
| 757 | ARRAY_SIZE(ar9480_common_wo_xlna_rx_gain_table_1p0), | ||
| 758 | 2); | ||
| 759 | else if (AR_SREV_9480_20(ah)) | ||
| 760 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 761 | ar9480_common_wo_xlna_rx_gain_table_2p0, | ||
| 762 | ARRAY_SIZE(ar9480_common_wo_xlna_rx_gain_table_2p0), | ||
| 763 | 2); | ||
| 764 | else if (AR_SREV_9580(ah)) | ||
| 765 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 766 | ar9580_1p0_wo_xlna_rx_gain_table, | ||
| 767 | ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table), | ||
| 768 | 2); | ||
| 769 | else | ||
| 770 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 771 | ar9300Common_wo_xlna_rx_gain_table_2p2, | ||
| 772 | ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2), | ||
| 773 | 2); | ||
| 774 | } | ||
| 775 | |||
| 776 | static void ar9003_rx_gain_table_mode2(struct ath_hw *ah) | ||
| 777 | { | ||
| 778 | if (AR_SREV_9480_10(ah)) | ||
| 779 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 780 | ar9480_common_mixed_rx_gain_table_1p0, | ||
| 781 | ARRAY_SIZE(ar9480_common_mixed_rx_gain_table_1p0), 2); | ||
| 782 | else if (AR_SREV_9480_20(ah)) | ||
| 783 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 784 | ar9480_common_mixed_rx_gain_table_2p0, | ||
| 785 | ARRAY_SIZE(ar9480_common_mixed_rx_gain_table_2p0), 2); | ||
| 786 | } | ||
| 787 | |||
| 512 | static void ar9003_rx_gain_table_apply(struct ath_hw *ah) | 788 | static void ar9003_rx_gain_table_apply(struct ath_hw *ah) |
| 513 | { | 789 | { |
| 514 | switch (ar9003_hw_get_rx_gain_idx(ah)) { | 790 | switch (ar9003_hw_get_rx_gain_idx(ah)) { |
| 515 | case 0: | 791 | case 0: |
| 516 | default: | 792 | default: |
| 517 | if (AR_SREV_9330_12(ah)) | 793 | ar9003_rx_gain_table_mode0(ah); |
| 518 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 519 | ar9331_common_rx_gain_1p2, | ||
| 520 | ARRAY_SIZE(ar9331_common_rx_gain_1p2), | ||
| 521 | 2); | ||
| 522 | else if (AR_SREV_9330_11(ah)) | ||
| 523 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 524 | ar9331_common_rx_gain_1p1, | ||
| 525 | ARRAY_SIZE(ar9331_common_rx_gain_1p1), | ||
| 526 | 2); | ||
| 527 | else if (AR_SREV_9340(ah)) | ||
| 528 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 529 | ar9340Common_rx_gain_table_1p0, | ||
| 530 | ARRAY_SIZE(ar9340Common_rx_gain_table_1p0), | ||
| 531 | 2); | ||
| 532 | else if (AR_SREV_9485_11(ah)) | ||
| 533 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 534 | ar9485Common_wo_xlna_rx_gain_1_1, | ||
| 535 | ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), | ||
| 536 | 2); | ||
| 537 | else if (AR_SREV_9580(ah)) | ||
| 538 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 539 | ar9580_1p0_rx_gain_table, | ||
| 540 | ARRAY_SIZE(ar9580_1p0_rx_gain_table), | ||
| 541 | 2); | ||
| 542 | else | ||
| 543 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 544 | ar9300Common_rx_gain_table_2p2, | ||
| 545 | ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), | ||
| 546 | 2); | ||
| 547 | break; | 794 | break; |
| 548 | case 1: | 795 | case 1: |
| 549 | if (AR_SREV_9330_12(ah)) | 796 | ar9003_rx_gain_table_mode1(ah); |
| 550 | INIT_INI_ARRAY(&ah->iniModesRxGain, | 797 | break; |
| 551 | ar9331_common_wo_xlna_rx_gain_1p2, | 798 | case 2: |
| 552 | ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2), | 799 | ar9003_rx_gain_table_mode2(ah); |
| 553 | 2); | ||
| 554 | else if (AR_SREV_9330_11(ah)) | ||
| 555 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 556 | ar9331_common_wo_xlna_rx_gain_1p1, | ||
| 557 | ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1), | ||
| 558 | 2); | ||
| 559 | else if (AR_SREV_9340(ah)) | ||
| 560 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 561 | ar9340Common_wo_xlna_rx_gain_table_1p0, | ||
| 562 | ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0), | ||
| 563 | 2); | ||
| 564 | else if (AR_SREV_9485_11(ah)) | ||
| 565 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 566 | ar9485Common_wo_xlna_rx_gain_1_1, | ||
| 567 | ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), | ||
| 568 | 2); | ||
| 569 | else if (AR_SREV_9580(ah)) | ||
| 570 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 571 | ar9580_1p0_wo_xlna_rx_gain_table, | ||
| 572 | ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table), | ||
| 573 | 2); | ||
| 574 | else | ||
| 575 | INIT_INI_ARRAY(&ah->iniModesRxGain, | ||
| 576 | ar9300Common_wo_xlna_rx_gain_table_2p2, | ||
| 577 | ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2), | ||
| 578 | 2); | ||
| 579 | break; | 800 | break; |
| 580 | } | 801 | } |
| 581 | } | 802 | } |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c index d08ab930e430..6cabc85bf61b 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c | |||
| @@ -21,6 +21,132 @@ static void ar9003_hw_rx_enable(struct ath_hw *hw) | |||
| 21 | REG_WRITE(hw, AR_CR, 0); | 21 | REG_WRITE(hw, AR_CR, 0); |
| 22 | } | 22 | } |
| 23 | 23 | ||
| 24 | static void | ||
| 25 | ar9003_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i) | ||
| 26 | { | ||
| 27 | struct ar9003_txc *ads = ds; | ||
| 28 | int checksum = 0; | ||
| 29 | u32 val, ctl12, ctl17; | ||
| 30 | |||
| 31 | val = (ATHEROS_VENDOR_ID << AR_DescId_S) | | ||
| 32 | (1 << AR_TxRxDesc_S) | | ||
| 33 | (1 << AR_CtrlStat_S) | | ||
| 34 | (i->qcu << AR_TxQcuNum_S) | 0x17; | ||
| 35 | |||
| 36 | checksum += val; | ||
| 37 | ACCESS_ONCE(ads->info) = val; | ||
| 38 | |||
| 39 | checksum += i->link; | ||
| 40 | ACCESS_ONCE(ads->link) = i->link; | ||
| 41 | |||
| 42 | checksum += i->buf_addr[0]; | ||
| 43 | ACCESS_ONCE(ads->data0) = i->buf_addr[0]; | ||
| 44 | checksum += i->buf_addr[1]; | ||
| 45 | ACCESS_ONCE(ads->data1) = i->buf_addr[1]; | ||
| 46 | checksum += i->buf_addr[2]; | ||
| 47 | ACCESS_ONCE(ads->data2) = i->buf_addr[2]; | ||
| 48 | checksum += i->buf_addr[3]; | ||
| 49 | ACCESS_ONCE(ads->data3) = i->buf_addr[3]; | ||
| 50 | |||
| 51 | checksum += (val = (i->buf_len[0] << AR_BufLen_S) & AR_BufLen); | ||
| 52 | ACCESS_ONCE(ads->ctl3) = val; | ||
| 53 | checksum += (val = (i->buf_len[1] << AR_BufLen_S) & AR_BufLen); | ||
| 54 | ACCESS_ONCE(ads->ctl5) = val; | ||
| 55 | checksum += (val = (i->buf_len[2] << AR_BufLen_S) & AR_BufLen); | ||
| 56 | ACCESS_ONCE(ads->ctl7) = val; | ||
| 57 | checksum += (val = (i->buf_len[3] << AR_BufLen_S) & AR_BufLen); | ||
| 58 | ACCESS_ONCE(ads->ctl9) = val; | ||
| 59 | |||
| 60 | checksum = (u16) (((checksum & 0xffff) + (checksum >> 16)) & 0xffff); | ||
| 61 | ACCESS_ONCE(ads->ctl10) = checksum; | ||
| 62 | |||
| 63 | if (i->is_first || i->is_last) { | ||
| 64 | ACCESS_ONCE(ads->ctl13) = set11nTries(i->rates, 0) | ||
| 65 | | set11nTries(i->rates, 1) | ||
| 66 | | set11nTries(i->rates, 2) | ||
| 67 | | set11nTries(i->rates, 3) | ||
| 68 | | (i->dur_update ? AR_DurUpdateEna : 0) | ||
| 69 | | SM(0, AR_BurstDur); | ||
| 70 | |||
| 71 | ACCESS_ONCE(ads->ctl14) = set11nRate(i->rates, 0) | ||
| 72 | | set11nRate(i->rates, 1) | ||
| 73 | | set11nRate(i->rates, 2) | ||
| 74 | | set11nRate(i->rates, 3); | ||
| 75 | } else { | ||
| 76 | ACCESS_ONCE(ads->ctl13) = 0; | ||
| 77 | ACCESS_ONCE(ads->ctl14) = 0; | ||
| 78 | } | ||
| 79 | |||
| 80 | ads->ctl20 = 0; | ||
| 81 | ads->ctl21 = 0; | ||
| 82 | ads->ctl22 = 0; | ||
| 83 | |||
| 84 | ctl17 = SM(i->keytype, AR_EncrType); | ||
| 85 | if (!i->is_first) { | ||
| 86 | ACCESS_ONCE(ads->ctl11) = 0; | ||
| 87 | ACCESS_ONCE(ads->ctl12) = i->is_last ? 0 : AR_TxMore; | ||
| 88 | ACCESS_ONCE(ads->ctl15) = 0; | ||
| 89 | ACCESS_ONCE(ads->ctl16) = 0; | ||
| 90 | ACCESS_ONCE(ads->ctl17) = ctl17; | ||
| 91 | ACCESS_ONCE(ads->ctl18) = 0; | ||
| 92 | ACCESS_ONCE(ads->ctl19) = 0; | ||
| 93 | return; | ||
| 94 | } | ||
| 95 | |||
| 96 | ACCESS_ONCE(ads->ctl11) = (i->pkt_len & AR_FrameLen) | ||
| 97 | | (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) | ||
| 98 | | SM(i->txpower, AR_XmitPower) | ||
| 99 | | (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) | ||
| 100 | | (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0) | ||
| 101 | | (i->flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0) | ||
| 102 | | (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) | ||
| 103 | | (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable : | ||
| 104 | (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0)); | ||
| 105 | |||
| 106 | ctl12 = (i->keyix != ATH9K_TXKEYIX_INVALID ? | ||
| 107 | SM(i->keyix, AR_DestIdx) : 0) | ||
| 108 | | SM(i->type, AR_FrameType) | ||
| 109 | | (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) | ||
| 110 | | (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) | ||
| 111 | | (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); | ||
| 112 | |||
| 113 | ctl17 |= (i->flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0); | ||
| 114 | switch (i->aggr) { | ||
| 115 | case AGGR_BUF_FIRST: | ||
| 116 | ctl17 |= SM(i->aggr_len, AR_AggrLen); | ||
| 117 | /* fall through */ | ||
| 118 | case AGGR_BUF_MIDDLE: | ||
| 119 | ctl12 |= AR_IsAggr | AR_MoreAggr; | ||
| 120 | ctl17 |= SM(i->ndelim, AR_PadDelim); | ||
| 121 | break; | ||
| 122 | case AGGR_BUF_LAST: | ||
| 123 | ctl12 |= AR_IsAggr; | ||
| 124 | break; | ||
| 125 | case AGGR_BUF_NONE: | ||
| 126 | break; | ||
| 127 | } | ||
| 128 | |||
| 129 | val = (i->flags & ATH9K_TXDESC_PAPRD) >> ATH9K_TXDESC_PAPRD_S; | ||
| 130 | ctl12 |= SM(val, AR_PAPRDChainMask); | ||
| 131 | |||
| 132 | ACCESS_ONCE(ads->ctl12) = ctl12; | ||
| 133 | ACCESS_ONCE(ads->ctl17) = ctl17; | ||
| 134 | |||
| 135 | ACCESS_ONCE(ads->ctl15) = set11nPktDurRTSCTS(i->rates, 0) | ||
| 136 | | set11nPktDurRTSCTS(i->rates, 1); | ||
| 137 | |||
| 138 | ACCESS_ONCE(ads->ctl16) = set11nPktDurRTSCTS(i->rates, 2) | ||
| 139 | | set11nPktDurRTSCTS(i->rates, 3); | ||
| 140 | |||
| 141 | ACCESS_ONCE(ads->ctl18) = set11nRateFlags(i->rates, 0) | ||
| 142 | | set11nRateFlags(i->rates, 1) | ||
| 143 | | set11nRateFlags(i->rates, 2) | ||
| 144 | | set11nRateFlags(i->rates, 3) | ||
| 145 | | SM(i->rtscts_rate, AR_RTSCTSRate); | ||
| 146 | |||
| 147 | ACCESS_ONCE(ads->ctl19) = AR_Not_Sounding; | ||
| 148 | } | ||
| 149 | |||
| 24 | static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads) | 150 | static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads) |
| 25 | { | 151 | { |
| 26 | int checksum; | 152 | int checksum; |
| @@ -185,47 +311,6 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) | |||
| 185 | return true; | 311 | return true; |
| 186 | } | 312 | } |
| 187 | 313 | ||
| 188 | static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen, | ||
| 189 | bool is_firstseg, bool is_lastseg, | ||
| 190 | const void *ds0, dma_addr_t buf_addr, | ||
| 191 | unsigned int qcu) | ||
| 192 | { | ||
| 193 | struct ar9003_txc *ads = (struct ar9003_txc *) ds; | ||
| 194 | unsigned int descid = 0; | ||
| 195 | |||
| 196 | ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) | | ||
| 197 | (1 << AR_TxRxDesc_S) | | ||
| 198 | (1 << AR_CtrlStat_S) | | ||
| 199 | (qcu << AR_TxQcuNum_S) | 0x17; | ||
| 200 | |||
| 201 | ads->data0 = buf_addr; | ||
| 202 | ads->data1 = 0; | ||
| 203 | ads->data2 = 0; | ||
| 204 | ads->data3 = 0; | ||
| 205 | |||
| 206 | ads->ctl3 = (seglen << AR_BufLen_S); | ||
| 207 | ads->ctl3 &= AR_BufLen; | ||
| 208 | |||
| 209 | /* Fill in pointer checksum and descriptor id */ | ||
| 210 | ads->ctl10 = ar9003_calc_ptr_chksum(ads); | ||
| 211 | ads->ctl10 |= (descid << AR_TxDescId_S); | ||
| 212 | |||
| 213 | if (is_firstseg) { | ||
| 214 | ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore); | ||
| 215 | } else if (is_lastseg) { | ||
| 216 | ads->ctl11 = 0; | ||
| 217 | ads->ctl12 = 0; | ||
| 218 | ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13; | ||
| 219 | ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14; | ||
| 220 | } else { | ||
| 221 | /* XXX Intermediate descriptor in a multi-descriptor frame.*/ | ||
| 222 | ads->ctl11 = 0; | ||
| 223 | ads->ctl12 = AR_TxMore; | ||
| 224 | ads->ctl13 = 0; | ||
| 225 | ads->ctl14 = 0; | ||
| 226 | } | ||
| 227 | } | ||
| 228 | |||
| 229 | static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, | 314 | static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, |
| 230 | struct ath_tx_status *ts) | 315 | struct ath_tx_status *ts) |
| 231 | { | 316 | { |
| @@ -310,161 +395,6 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, | |||
| 310 | return 0; | 395 | return 0; |
| 311 | } | 396 | } |
| 312 | 397 | ||
| 313 | static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds, | ||
| 314 | u32 pktlen, enum ath9k_pkt_type type, u32 txpower, | ||
| 315 | u8 keyIx, enum ath9k_key_type keyType, u32 flags) | ||
| 316 | { | ||
| 317 | struct ar9003_txc *ads = (struct ar9003_txc *) ds; | ||
| 318 | |||
| 319 | if (txpower > ah->txpower_limit) | ||
| 320 | txpower = ah->txpower_limit; | ||
| 321 | |||
| 322 | if (txpower > 63) | ||
| 323 | txpower = 63; | ||
| 324 | |||
| 325 | ads->ctl11 = (pktlen & AR_FrameLen) | ||
| 326 | | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) | ||
| 327 | | SM(txpower, AR_XmitPower) | ||
| 328 | | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) | ||
| 329 | | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0) | ||
| 330 | | (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0); | ||
| 331 | |||
| 332 | ads->ctl12 = | ||
| 333 | (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0) | ||
| 334 | | SM(type, AR_FrameType) | ||
| 335 | | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) | ||
| 336 | | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) | ||
| 337 | | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); | ||
| 338 | |||
| 339 | ads->ctl17 = SM(keyType, AR_EncrType) | | ||
| 340 | (flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0); | ||
| 341 | ads->ctl18 = 0; | ||
| 342 | ads->ctl19 = AR_Not_Sounding; | ||
| 343 | |||
| 344 | ads->ctl20 = 0; | ||
| 345 | ads->ctl21 = 0; | ||
| 346 | ads->ctl22 = 0; | ||
| 347 | } | ||
| 348 | |||
| 349 | static void ar9003_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val) | ||
| 350 | { | ||
| 351 | struct ar9003_txc *ads = (struct ar9003_txc *) ds; | ||
| 352 | |||
| 353 | if (val) | ||
| 354 | ads->ctl11 |= AR_ClrDestMask; | ||
| 355 | else | ||
| 356 | ads->ctl11 &= ~AR_ClrDestMask; | ||
| 357 | } | ||
| 358 | |||
| 359 | static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds, | ||
| 360 | void *lastds, | ||
| 361 | u32 durUpdateEn, u32 rtsctsRate, | ||
| 362 | u32 rtsctsDuration, | ||
| 363 | struct ath9k_11n_rate_series series[], | ||
| 364 | u32 nseries, u32 flags) | ||
| 365 | { | ||
| 366 | struct ar9003_txc *ads = (struct ar9003_txc *) ds; | ||
| 367 | struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds; | ||
| 368 | u_int32_t ctl11; | ||
| 369 | |||
| 370 | if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) { | ||
| 371 | ctl11 = ads->ctl11; | ||
| 372 | |||
| 373 | if (flags & ATH9K_TXDESC_RTSENA) { | ||
| 374 | ctl11 &= ~AR_CTSEnable; | ||
| 375 | ctl11 |= AR_RTSEnable; | ||
| 376 | } else { | ||
| 377 | ctl11 &= ~AR_RTSEnable; | ||
| 378 | ctl11 |= AR_CTSEnable; | ||
| 379 | } | ||
| 380 | |||
| 381 | ads->ctl11 = ctl11; | ||
| 382 | } else { | ||
| 383 | ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable)); | ||
| 384 | } | ||
| 385 | |||
| 386 | ads->ctl13 = set11nTries(series, 0) | ||
| 387 | | set11nTries(series, 1) | ||
| 388 | | set11nTries(series, 2) | ||
| 389 | | set11nTries(series, 3) | ||
| 390 | | (durUpdateEn ? AR_DurUpdateEna : 0) | ||
| 391 | | SM(0, AR_BurstDur); | ||
| 392 | |||
| 393 | ads->ctl14 = set11nRate(series, 0) | ||
| 394 | | set11nRate(series, 1) | ||
| 395 | | set11nRate(series, 2) | ||
| 396 | | set11nRate(series, 3); | ||
| 397 | |||
| 398 | ads->ctl15 = set11nPktDurRTSCTS(series, 0) | ||
| 399 | | set11nPktDurRTSCTS(series, 1); | ||
| 400 | |||
| 401 | ads->ctl16 = set11nPktDurRTSCTS(series, 2) | ||
| 402 | | set11nPktDurRTSCTS(series, 3); | ||
| 403 | |||
| 404 | ads->ctl18 = set11nRateFlags(series, 0) | ||
| 405 | | set11nRateFlags(series, 1) | ||
| 406 | | set11nRateFlags(series, 2) | ||
| 407 | | set11nRateFlags(series, 3) | ||
| 408 | | SM(rtsctsRate, AR_RTSCTSRate); | ||
| 409 | ads->ctl19 = AR_Not_Sounding; | ||
| 410 | |||
| 411 | last_ads->ctl13 = ads->ctl13; | ||
| 412 | last_ads->ctl14 = ads->ctl14; | ||
| 413 | } | ||
| 414 | |||
| 415 | static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds, | ||
| 416 | u32 aggrLen) | ||
| 417 | { | ||
| 418 | struct ar9003_txc *ads = (struct ar9003_txc *) ds; | ||
| 419 | |||
| 420 | ads->ctl12 |= (AR_IsAggr | AR_MoreAggr); | ||
| 421 | |||
| 422 | ads->ctl17 &= ~AR_AggrLen; | ||
| 423 | ads->ctl17 |= SM(aggrLen, AR_AggrLen); | ||
| 424 | } | ||
| 425 | |||
| 426 | static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds, | ||
| 427 | u32 numDelims) | ||
| 428 | { | ||
| 429 | struct ar9003_txc *ads = (struct ar9003_txc *) ds; | ||
| 430 | unsigned int ctl17; | ||
| 431 | |||
| 432 | ads->ctl12 |= (AR_IsAggr | AR_MoreAggr); | ||
| 433 | |||
| 434 | /* | ||
| 435 | * We use a stack variable to manipulate ctl6 to reduce uncached | ||
| 436 | * read modify, modfiy, write. | ||
| 437 | */ | ||
| 438 | ctl17 = ads->ctl17; | ||
| 439 | ctl17 &= ~AR_PadDelim; | ||
| 440 | ctl17 |= SM(numDelims, AR_PadDelim); | ||
| 441 | ads->ctl17 = ctl17; | ||
| 442 | } | ||
| 443 | |||
| 444 | static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds) | ||
| 445 | { | ||
| 446 | struct ar9003_txc *ads = (struct ar9003_txc *) ds; | ||
| 447 | |||
| 448 | ads->ctl12 |= AR_IsAggr; | ||
| 449 | ads->ctl12 &= ~AR_MoreAggr; | ||
| 450 | ads->ctl17 &= ~AR_PadDelim; | ||
| 451 | } | ||
| 452 | |||
| 453 | static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds) | ||
| 454 | { | ||
| 455 | struct ar9003_txc *ads = (struct ar9003_txc *) ds; | ||
| 456 | |||
| 457 | ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr); | ||
| 458 | } | ||
| 459 | |||
| 460 | void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains) | ||
| 461 | { | ||
| 462 | struct ar9003_txc *ads = ds; | ||
| 463 | |||
| 464 | ads->ctl12 |= SM(chains, AR_PAPRDChainMask); | ||
| 465 | } | ||
| 466 | EXPORT_SYMBOL(ar9003_hw_set_paprd_txdesc); | ||
| 467 | |||
| 468 | void ar9003_hw_attach_mac_ops(struct ath_hw *hw) | 398 | void ar9003_hw_attach_mac_ops(struct ath_hw *hw) |
| 469 | { | 399 | { |
| 470 | struct ath_hw_ops *ops = ath9k_hw_ops(hw); | 400 | struct ath_hw_ops *ops = ath9k_hw_ops(hw); |
| @@ -472,15 +402,8 @@ void ar9003_hw_attach_mac_ops(struct ath_hw *hw) | |||
| 472 | ops->rx_enable = ar9003_hw_rx_enable; | 402 | ops->rx_enable = ar9003_hw_rx_enable; |
| 473 | ops->set_desc_link = ar9003_hw_set_desc_link; | 403 | ops->set_desc_link = ar9003_hw_set_desc_link; |
| 474 | ops->get_isr = ar9003_hw_get_isr; | 404 | ops->get_isr = ar9003_hw_get_isr; |
| 475 | ops->fill_txdesc = ar9003_hw_fill_txdesc; | 405 | ops->set_txdesc = ar9003_set_txdesc; |
| 476 | ops->proc_txdesc = ar9003_hw_proc_txdesc; | 406 | ops->proc_txdesc = ar9003_hw_proc_txdesc; |
| 477 | ops->set11n_txdesc = ar9003_hw_set11n_txdesc; | ||
| 478 | ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario; | ||
| 479 | ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first; | ||
| 480 | ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle; | ||
| 481 | ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last; | ||
| 482 | ops->clr11n_aggr = ar9003_hw_clr11n_aggr; | ||
| 483 | ops->set_clrdmask = ar9003_hw_set_clrdmask; | ||
| 484 | } | 407 | } |
| 485 | 408 | ||
| 486 | void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size) | 409 | void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size) |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c index f80d1d633980..609acb2b504f 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c | |||
| @@ -113,7 +113,7 @@ static int ar9003_get_training_power_5g(struct ath_hw *ah) | |||
| 113 | if (delta > scale) | 113 | if (delta > scale) |
| 114 | return -1; | 114 | return -1; |
| 115 | 115 | ||
| 116 | switch (get_streams(common->tx_chainmask)) { | 116 | switch (get_streams(ah->txchainmask)) { |
| 117 | case 1: | 117 | case 1: |
| 118 | delta = 6; | 118 | delta = 6; |
| 119 | break; | 119 | break; |
| @@ -126,7 +126,7 @@ static int ar9003_get_training_power_5g(struct ath_hw *ah) | |||
| 126 | default: | 126 | default: |
| 127 | delta = 0; | 127 | delta = 0; |
| 128 | ath_dbg(common, ATH_DBG_CALIBRATE, | 128 | ath_dbg(common, ATH_DBG_CALIBRATE, |
| 129 | "Invalid tx-chainmask: %u\n", common->tx_chainmask); | 129 | "Invalid tx-chainmask: %u\n", ah->txchainmask); |
| 130 | } | 130 | } |
| 131 | 131 | ||
| 132 | power += delta; | 132 | power += delta; |
| @@ -147,7 +147,7 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah) | |||
| 147 | AR_PHY_PAPRD_CTRL1_B2 | 147 | AR_PHY_PAPRD_CTRL1_B2 |
| 148 | }; | 148 | }; |
| 149 | int training_power; | 149 | int training_power; |
| 150 | int i; | 150 | int i, val; |
| 151 | 151 | ||
| 152 | if (IS_CHAN_2GHZ(ah->curchan)) | 152 | if (IS_CHAN_2GHZ(ah->curchan)) |
| 153 | training_power = ar9003_get_training_power_2g(ah); | 153 | training_power = ar9003_get_training_power_2g(ah); |
| @@ -207,8 +207,9 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah) | |||
| 207 | AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING, 28); | 207 | AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING, 28); |
| 208 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1, | 208 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1, |
| 209 | AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE, 1); | 209 | AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE, 1); |
| 210 | val = AR_SREV_9480(ah) ? 0x91 : 147; | ||
| 210 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL2, | 211 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL2, |
| 211 | AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN, 147); | 212 | AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN, val); |
| 212 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, | 213 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, |
| 213 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN, 4); | 214 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN, 4); |
| 214 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, | 215 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, |
| @@ -217,7 +218,7 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah) | |||
| 217 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7); | 218 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7); |
| 218 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, | 219 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, |
| 219 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1); | 220 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1); |
| 220 | if (AR_SREV_9485(ah)) | 221 | if (AR_SREV_9485(ah) || AR_SREV_9480(ah)) |
| 221 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, | 222 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, |
| 222 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, | 223 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, |
| 223 | -3); | 224 | -3); |
| @@ -225,9 +226,10 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah) | |||
| 225 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, | 226 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, |
| 226 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, | 227 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, |
| 227 | -6); | 228 | -6); |
| 229 | val = AR_SREV_9480(ah) ? -10 : -15; | ||
| 228 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, | 230 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, |
| 229 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE, | 231 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE, |
| 230 | -15); | 232 | val); |
| 231 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, | 233 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, |
| 232 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE, 1); | 234 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE, 1); |
| 233 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL4, | 235 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL4, |
| @@ -757,6 +759,7 @@ void ar9003_paprd_populate_single_table(struct ath_hw *ah, | |||
| 757 | training_power); | 759 | training_power); |
| 758 | 760 | ||
| 759 | if (ah->caps.tx_chainmask & BIT(2)) | 761 | if (ah->caps.tx_chainmask & BIT(2)) |
| 762 | /* val AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL correct? */ | ||
| 760 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B2, | 763 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B2, |
| 761 | AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL, | 764 | AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL, |
| 762 | training_power); | 765 | training_power); |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c index 33edb5653ca6..95147948794d 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c | |||
| @@ -559,6 +559,9 @@ static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) | |||
| 559 | 559 | ||
| 560 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) | 560 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) |
| 561 | REG_WRITE(ah, AR_SELFGEN_MASK, 0x3); | 561 | REG_WRITE(ah, AR_SELFGEN_MASK, 0x3); |
| 562 | else if (AR_SREV_9480(ah)) | ||
| 563 | /* xxx only when MCI support is enabled */ | ||
| 564 | REG_WRITE(ah, AR_SELFGEN_MASK, 0x3); | ||
| 562 | else | 565 | else |
| 563 | REG_WRITE(ah, AR_SELFGEN_MASK, tx); | 566 | REG_WRITE(ah, AR_SELFGEN_MASK, tx); |
| 564 | 567 | ||
| @@ -658,6 +661,10 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, | |||
| 658 | ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); | 661 | ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); |
| 659 | ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); | 662 | ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); |
| 660 | ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); | 663 | ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); |
| 664 | if (i == ATH_INI_POST && AR_SREV_9480_20(ah)) | ||
| 665 | ar9003_hw_prog_ini(ah, | ||
| 666 | &ah->ini_radio_post_sys2ant, | ||
| 667 | modesIndex); | ||
| 661 | } | 668 | } |
| 662 | 669 | ||
| 663 | REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); | 670 | REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); |
| @@ -677,6 +684,9 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, | |||
| 677 | if (AR_SREV_9340(ah) && !ah->is_clk_25mhz) | 684 | if (AR_SREV_9340(ah) && !ah->is_clk_25mhz) |
| 678 | REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites); | 685 | REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites); |
| 679 | 686 | ||
| 687 | if (AR_SREV_9480(ah)) | ||
| 688 | ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1); | ||
| 689 | |||
| 680 | ar9003_hw_override_ini(ah); | 690 | ar9003_hw_override_ini(ah); |
| 681 | ar9003_hw_set_channel_regs(ah, chan); | 691 | ar9003_hw_set_channel_regs(ah, chan); |
| 682 | ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); | 692 | ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h index 80397de11e0d..6cea546a1507 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h | |||
| @@ -581,6 +581,9 @@ | |||
| 581 | #define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i) (AR_SM_BASE + \ | 581 | #define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i) (AR_SM_BASE + \ |
| 582 | (AR_SREV_9485(ah) ? \ | 582 | (AR_SREV_9485(ah) ? \ |
| 583 | 0x3d0 : 0x450) + ((_i) << 2)) | 583 | 0x3d0 : 0x450) + ((_i) << 2)) |
| 584 | #define AR_PHY_RTT_CTRL (AR_SM_BASE + 0x380) | ||
| 585 | #define AR_PHY_RTT_TABLE_SW_INTF_B (AR_SM_BASE + 0x384) | ||
| 586 | #define AR_PHY_RTT_TABLE_SW_INTF_1_B0 (AR_SM_BASE + 0x388) | ||
| 584 | 587 | ||
| 585 | #define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0) | 588 | #define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0) |
| 586 | #define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4) | 589 | #define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4) |
| @@ -600,6 +603,17 @@ | |||
| 600 | #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE 0x0000ff00 | 603 | #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE 0x0000ff00 |
| 601 | #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_S 8 | 604 | #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_S 8 |
| 602 | 605 | ||
| 606 | /* AIC Registers */ | ||
| 607 | #define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0) | ||
| 608 | #define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4) | ||
| 609 | #define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8) | ||
| 610 | #define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc) | ||
| 611 | #define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + (AR_SREV_9480_10(ah) ? \ | ||
| 612 | 0x4c0 : 0x4c4)) | ||
| 613 | #define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + (AR_SREV_9480_10(ah) ? \ | ||
| 614 | 0x4c4 : 0x4c8)) | ||
| 615 | #define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0) | ||
| 616 | #define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc) | ||
| 603 | 617 | ||
| 604 | #define AR_PHY_65NM_CH0_SYNTH4 0x1608c | 618 | #define AR_PHY_65NM_CH0_SYNTH4 0x1608c |
| 605 | #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002 | 619 | #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002 |
| @@ -609,7 +623,35 @@ | |||
| 609 | #define AR_PHY_65NM_CH0_BIAS2 0x160c4 | 623 | #define AR_PHY_65NM_CH0_BIAS2 0x160c4 |
| 610 | #define AR_PHY_65NM_CH0_BIAS4 0x160cc | 624 | #define AR_PHY_65NM_CH0_BIAS4 0x160cc |
| 611 | #define AR_PHY_65NM_CH0_RXTX4 0x1610c | 625 | #define AR_PHY_65NM_CH0_RXTX4 0x1610c |
| 612 | #define AR_PHY_65NM_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 : 0x1628c) | 626 | |
| 627 | #define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \ | ||
| 628 | ((AR_SREV_9480(ah) ? 0x1628c : 0x16280))) | ||
| 629 | #define AR_CH0_TOP_XPABIASLVL (0x300) | ||
| 630 | #define AR_CH0_TOP_XPABIASLVL_S (8) | ||
| 631 | |||
| 632 | #define AR_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 : \ | ||
| 633 | ((AR_SREV_9485(ah) ? 0x1628c : 0x16294))) | ||
| 634 | #define AR_CH0_THERM_XPABIASLVL_MSB 0x3 | ||
| 635 | #define AR_CH0_THERM_XPABIASLVL_MSB_S 0 | ||
| 636 | #define AR_CH0_THERM_XPASHORT2GND 0x4 | ||
| 637 | #define AR_CH0_THERM_XPASHORT2GND_S 2 | ||
| 638 | |||
| 639 | #define AR_SWITCH_TABLE_COM_ALL (0xffff) | ||
| 640 | #define AR_SWITCH_TABLE_COM_ALL_S (0) | ||
| 641 | #define AR_SWITCH_TABLE_COM_AR9480_ALL (0xffffff) | ||
| 642 | #define AR_SWITCH_TABLE_COM_AR9480_ALL_S (0) | ||
| 643 | #define AR_SWITCH_TABLE_COM_SPDT (0x00f00000) | ||
| 644 | #define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0) | ||
| 645 | #define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4) | ||
| 646 | |||
| 647 | #define AR_SWITCH_TABLE_COM2_ALL (0xffffff) | ||
| 648 | #define AR_SWITCH_TABLE_COM2_ALL_S (0) | ||
| 649 | |||
| 650 | #define AR_SWITCH_TABLE_ALL (0xfff) | ||
| 651 | #define AR_SWITCH_TABLE_ALL_S (0) | ||
| 652 | |||
| 653 | #define AR_PHY_65NM_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 :\ | ||
| 654 | (AR_SREV_9485(ah) ? 0x1628c : 0x16294)) | ||
| 613 | 655 | ||
| 614 | #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 | 656 | #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 |
| 615 | #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31 | 657 | #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31 |
| @@ -625,21 +667,23 @@ | |||
| 625 | #define AR_PHY_65NM_CH2_RXTX1 0x16900 | 667 | #define AR_PHY_65NM_CH2_RXTX1 0x16900 |
| 626 | #define AR_PHY_65NM_CH2_RXTX2 0x16904 | 668 | #define AR_PHY_65NM_CH2_RXTX2 0x16904 |
| 627 | 669 | ||
| 628 | #define AR_CH0_TOP2 (AR_SREV_9300(ah) ? 0x1628c : 0x16284) | 670 | #define AR_CH0_TOP2 (AR_SREV_9300(ah) ? 0x1628c : \ |
| 671 | (AR_SREV_9485(ah) ? 0x16284 : 0x16290)) | ||
| 629 | #define AR_CH0_TOP2_XPABIASLVL 0xf000 | 672 | #define AR_CH0_TOP2_XPABIASLVL 0xf000 |
| 630 | #define AR_CH0_TOP2_XPABIASLVL_S 12 | 673 | #define AR_CH0_TOP2_XPABIASLVL_S 12 |
| 631 | 674 | ||
| 632 | #define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : 0x16290) | 675 | #define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : \ |
| 676 | (AR_SREV_9485(ah) ? 0x16290 : 0x16298)) | ||
| 633 | #define AR_CH0_XTAL_CAPINDAC 0x7f000000 | 677 | #define AR_CH0_XTAL_CAPINDAC 0x7f000000 |
| 634 | #define AR_CH0_XTAL_CAPINDAC_S 24 | 678 | #define AR_CH0_XTAL_CAPINDAC_S 24 |
| 635 | #define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000 | 679 | #define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000 |
| 636 | #define AR_CH0_XTAL_CAPOUTDAC_S 17 | 680 | #define AR_CH0_XTAL_CAPOUTDAC_S 17 |
| 637 | 681 | ||
| 638 | #define AR_PHY_PMU1 0x16c40 | 682 | #define AR_PHY_PMU1 (AR_SREV_9480(ah) ? 0x16340 : 0x16c40) |
| 639 | #define AR_PHY_PMU1_PWD 0x1 | 683 | #define AR_PHY_PMU1_PWD 0x1 |
| 640 | #define AR_PHY_PMU1_PWD_S 0 | 684 | #define AR_PHY_PMU1_PWD_S 0 |
| 641 | 685 | ||
| 642 | #define AR_PHY_PMU2 0x16c44 | 686 | #define AR_PHY_PMU2 (AR_SREV_9480(ah) ? 0x16344 : 0x16c44) |
| 643 | #define AR_PHY_PMU2_PGM 0x00200000 | 687 | #define AR_PHY_PMU2_PGM 0x00200000 |
| 644 | #define AR_PHY_PMU2_PGM_S 21 | 688 | #define AR_PHY_PMU2_PGM_S 21 |
| 645 | 689 | ||
| @@ -839,19 +883,38 @@ | |||
| 839 | */ | 883 | */ |
| 840 | #define AR_SM1_BASE 0xb200 | 884 | #define AR_SM1_BASE 0xb200 |
| 841 | 885 | ||
| 842 | #define AR_PHY_SWITCH_CHAIN_1 (AR_SM1_BASE + 0x84) | 886 | #define AR_PHY_SWITCH_CHAIN_1 (AR_SM1_BASE + 0x84) |
| 843 | #define AR_PHY_FCAL_2_1 (AR_SM1_BASE + 0xd0) | 887 | #define AR_PHY_FCAL_2_1 (AR_SM1_BASE + 0xd0) |
| 844 | #define AR_PHY_DFT_TONE_CTL_1 (AR_SM1_BASE + 0xd4) | 888 | #define AR_PHY_DFT_TONE_CTL_1 (AR_SM1_BASE + 0xd4) |
| 845 | #define AR_PHY_CL_TAB_1 (AR_SM1_BASE + 0x100) | 889 | #define AR_PHY_CL_TAB_1 (AR_SM1_BASE + 0x100) |
| 846 | #define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180) | 890 | #define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180) |
| 847 | #define AR_PHY_TPC_4_B1 (AR_SM1_BASE + 0x204) | 891 | #define AR_PHY_TPC_4_B1 (AR_SM1_BASE + 0x204) |
| 848 | #define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208) | 892 | #define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208) |
| 849 | #define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c) | 893 | #define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c) |
| 850 | #define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220) | 894 | #define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220) |
| 851 | #define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + 0x240) | 895 | #define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + (AR_SREV_AR9300(ah) ? \ |
| 896 | 0x240 : 0x280)) | ||
| 897 | #define AR_PHY_TPC_19_B1 (AR_SM1_BASE + 0x240) | ||
| 898 | #define AR_PHY_TPC_19_B1_ALPHA_THERM 0xff | ||
| 899 | #define AR_PHY_TPC_19_B1_ALPHA_THERM_S 0 | ||
| 852 | #define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c) | 900 | #define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c) |
| 853 | #define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i) (AR_SM1_BASE + 0x450 + ((_i) << 2)) | 901 | #define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i) (AR_SM1_BASE + 0x450 + ((_i) << 2)) |
| 854 | 902 | ||
| 903 | /* SM 1 AIC Registers */ | ||
| 904 | |||
| 905 | #define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0) | ||
| 906 | #define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4) | ||
| 907 | #define AR_PHY_AIC_CTRL_2_B1 (AR_SM1_BASE + 0x4b8) | ||
| 908 | #define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \ | ||
| 909 | 0x4c0 : 0x4c4)) | ||
| 910 | #define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \ | ||
| 911 | 0x4c4 : 0x4c8)) | ||
| 912 | #define AR_PHY_AIC_CTRL_4_B1 (AR_SM1_BASE + 0x4c0) | ||
| 913 | #define AR_PHY_AIC_STAT_2_B1 (AR_SM1_BASE + 0x4cc) | ||
| 914 | |||
| 915 | #define AR_PHY_AIC_SRAM_ADDR_B1 (AR_SM1_BASE + 0x5f0) | ||
| 916 | #define AR_PHY_AIC_SRAM_DATA_B1 (AR_SM1_BASE + 0x5f4) | ||
| 917 | |||
| 855 | /* | 918 | /* |
| 856 | * Channel 2 Register Map | 919 | * Channel 2 Register Map |
| 857 | */ | 920 | */ |
| @@ -914,6 +977,13 @@ | |||
| 914 | 977 | ||
| 915 | #define AR_PHY_RSSI_3 (AR_AGC3_BASE + 0x180) | 978 | #define AR_PHY_RSSI_3 (AR_AGC3_BASE + 0x180) |
| 916 | 979 | ||
| 980 | /* GLB Registers */ | ||
| 981 | #define AR_GLB_BASE 0x20000 | ||
| 982 | #define AR_PHY_GLB_CONTROL (AR_GLB_BASE + 0x44) | ||
| 983 | #define AR_GLB_SCRATCH(_ah) (AR_GLB_BASE + \ | ||
| 984 | (AR_SREV_9480_20(_ah) ? 0x4c : 0x50)) | ||
| 985 | #define AR_GLB_STATUS (AR_GLB_BASE + 0x48) | ||
| 986 | |||
| 917 | /* | 987 | /* |
| 918 | * Misc helper defines | 988 | * Misc helper defines |
| 919 | */ | 989 | */ |
diff --git a/drivers/net/wireless/ath/ath9k/ar9480_1p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9480_1p0_initvals.h new file mode 100644 index 000000000000..4071bd2bd03f --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/ar9480_1p0_initvals.h | |||
| @@ -0,0 +1,1833 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2010 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef INITVALS_9480_1P0_H | ||
| 18 | #define INITVALS_9480_1P0_H | ||
| 19 | |||
| 20 | /* AR9480 1.0 */ | ||
| 21 | |||
| 22 | static const u32 ar9480_1p0_mac_core[][2] = { | ||
| 23 | /* Addr allmodes */ | ||
| 24 | {0x00000008, 0x00000000}, | ||
| 25 | {0x00000030, 0x00060085}, | ||
| 26 | {0x00000034, 0x00000005}, | ||
| 27 | {0x00000040, 0x00000000}, | ||
| 28 | {0x00000044, 0x00000000}, | ||
| 29 | {0x00000048, 0x00000008}, | ||
| 30 | {0x0000004c, 0x00000010}, | ||
| 31 | {0x00000050, 0x00000000}, | ||
| 32 | {0x00001040, 0x002ffc0f}, | ||
| 33 | {0x00001044, 0x002ffc0f}, | ||
| 34 | {0x00001048, 0x002ffc0f}, | ||
| 35 | {0x0000104c, 0x002ffc0f}, | ||
| 36 | {0x00001050, 0x002ffc0f}, | ||
| 37 | {0x00001054, 0x002ffc0f}, | ||
| 38 | {0x00001058, 0x002ffc0f}, | ||
| 39 | {0x0000105c, 0x002ffc0f}, | ||
| 40 | {0x00001060, 0x002ffc0f}, | ||
| 41 | {0x00001064, 0x002ffc0f}, | ||
| 42 | {0x000010f0, 0x00000100}, | ||
| 43 | {0x00001270, 0x00000000}, | ||
| 44 | {0x000012b0, 0x00000000}, | ||
| 45 | {0x000012f0, 0x00000000}, | ||
| 46 | {0x0000143c, 0x00000000}, | ||
| 47 | {0x0000147c, 0x00000000}, | ||
| 48 | {0x00001810, 0x0f000003}, | ||
| 49 | {0x00008000, 0x00000000}, | ||
| 50 | {0x00008004, 0x00000000}, | ||
| 51 | {0x00008008, 0x00000000}, | ||
| 52 | {0x0000800c, 0x00000000}, | ||
| 53 | {0x00008018, 0x00000000}, | ||
| 54 | {0x00008020, 0x00000000}, | ||
| 55 | {0x00008038, 0x00000000}, | ||
| 56 | {0x0000803c, 0x00080000}, | ||
| 57 | {0x00008040, 0x00000000}, | ||
| 58 | {0x00008044, 0x00000000}, | ||
| 59 | {0x00008048, 0x00000000}, | ||
| 60 | {0x0000804c, 0xffffffff}, | ||
| 61 | {0x00008050, 0xffffffff}, | ||
| 62 | {0x00008054, 0x00000000}, | ||
| 63 | {0x00008058, 0x00000000}, | ||
| 64 | {0x0000805c, 0x000fc78f}, | ||
| 65 | {0x00008060, 0x0000000f}, | ||
| 66 | {0x00008064, 0x00000000}, | ||
| 67 | {0x00008070, 0x00000310}, | ||
| 68 | {0x00008074, 0x00000020}, | ||
| 69 | {0x00008078, 0x00000000}, | ||
| 70 | {0x0000809c, 0x0000000f}, | ||
| 71 | {0x000080a0, 0x00000000}, | ||
| 72 | {0x000080a4, 0x02ff0000}, | ||
| 73 | {0x000080a8, 0x0e070605}, | ||
| 74 | {0x000080ac, 0x0000000d}, | ||
| 75 | {0x000080b0, 0x00000000}, | ||
| 76 | {0x000080b4, 0x00000000}, | ||
| 77 | {0x000080b8, 0x00000000}, | ||
| 78 | {0x000080bc, 0x00000000}, | ||
| 79 | {0x000080c0, 0x2a800000}, | ||
| 80 | {0x000080c4, 0x06900168}, | ||
| 81 | {0x000080c8, 0x13881c20}, | ||
| 82 | {0x000080cc, 0x01f40000}, | ||
| 83 | {0x000080d0, 0x00252500}, | ||
| 84 | {0x000080d4, 0x00a00005}, | ||
| 85 | {0x000080d8, 0x00400002}, | ||
| 86 | {0x000080dc, 0x00000000}, | ||
| 87 | {0x000080e0, 0xffffffff}, | ||
| 88 | {0x000080e4, 0x0000ffff}, | ||
| 89 | {0x000080e8, 0x3f3f3f3f}, | ||
| 90 | {0x000080ec, 0x00000000}, | ||
| 91 | {0x000080f0, 0x00000000}, | ||
| 92 | {0x000080f4, 0x00000000}, | ||
| 93 | {0x000080fc, 0x00020000}, | ||
| 94 | {0x00008100, 0x00000000}, | ||
| 95 | {0x00008108, 0x00000052}, | ||
| 96 | {0x0000810c, 0x00000000}, | ||
| 97 | {0x00008110, 0x00000000}, | ||
| 98 | {0x00008114, 0x000007ff}, | ||
| 99 | {0x00008118, 0x000000aa}, | ||
| 100 | {0x0000811c, 0x00003210}, | ||
| 101 | {0x00008124, 0x00000000}, | ||
| 102 | {0x00008128, 0x00000000}, | ||
| 103 | {0x0000812c, 0x00000000}, | ||
| 104 | {0x00008130, 0x00000000}, | ||
| 105 | {0x00008134, 0x00000000}, | ||
| 106 | {0x00008138, 0x00000000}, | ||
| 107 | {0x0000813c, 0x0000ffff}, | ||
| 108 | {0x00008144, 0xffffffff}, | ||
| 109 | {0x00008168, 0x00000000}, | ||
| 110 | {0x0000816c, 0x00000000}, | ||
| 111 | {0x00008170, 0x18486e00}, | ||
| 112 | {0x00008174, 0x33332210}, | ||
| 113 | {0x00008178, 0x00000000}, | ||
| 114 | {0x0000817c, 0x00020000}, | ||
| 115 | {0x000081c4, 0x33332210}, | ||
| 116 | {0x000081c8, 0x00000000}, | ||
| 117 | {0x000081cc, 0x00000000}, | ||
| 118 | {0x000081d4, 0x00000000}, | ||
| 119 | {0x000081ec, 0x00000000}, | ||
| 120 | {0x000081f0, 0x00000000}, | ||
| 121 | {0x000081f4, 0x00000000}, | ||
| 122 | {0x000081f8, 0x00000000}, | ||
| 123 | {0x000081fc, 0x00000000}, | ||
| 124 | {0x00008240, 0x00100000}, | ||
| 125 | {0x00008244, 0x0010f400}, | ||
| 126 | {0x00008248, 0x00000800}, | ||
| 127 | {0x0000824c, 0x0001e800}, | ||
| 128 | {0x00008250, 0x00000000}, | ||
| 129 | {0x00008254, 0x00000000}, | ||
| 130 | {0x00008258, 0x00000000}, | ||
| 131 | {0x0000825c, 0x40000000}, | ||
| 132 | {0x00008260, 0x00080922}, | ||
| 133 | {0x00008264, 0x99c00010}, | ||
| 134 | {0x00008268, 0xffffffff}, | ||
| 135 | {0x0000826c, 0x0000ffff}, | ||
| 136 | {0x00008270, 0x00000000}, | ||
| 137 | {0x00008274, 0x40000000}, | ||
| 138 | {0x00008278, 0x003e4180}, | ||
| 139 | {0x0000827c, 0x00000004}, | ||
| 140 | {0x00008284, 0x0000002c}, | ||
| 141 | {0x00008288, 0x0000002c}, | ||
| 142 | {0x0000828c, 0x000000ff}, | ||
| 143 | {0x00008294, 0x00000000}, | ||
| 144 | {0x00008298, 0x00000000}, | ||
| 145 | {0x0000829c, 0x00000000}, | ||
| 146 | {0x00008300, 0x00000140}, | ||
| 147 | {0x00008314, 0x00000000}, | ||
| 148 | {0x0000831c, 0x0000010d}, | ||
| 149 | {0x00008328, 0x00000000}, | ||
| 150 | {0x0000832c, 0x0000001f}, | ||
| 151 | {0x00008330, 0x00000302}, | ||
| 152 | {0x00008334, 0x00000700}, | ||
| 153 | {0x00008338, 0xffff0000}, | ||
| 154 | {0x0000833c, 0x02400000}, | ||
| 155 | {0x00008340, 0x000107ff}, | ||
| 156 | {0x00008344, 0xaa48105b}, | ||
| 157 | {0x00008348, 0x008f0000}, | ||
| 158 | {0x0000835c, 0x00000000}, | ||
| 159 | {0x00008360, 0xffffffff}, | ||
| 160 | {0x00008364, 0xffffffff}, | ||
| 161 | {0x00008368, 0x00000000}, | ||
| 162 | {0x00008370, 0x00000000}, | ||
| 163 | {0x00008374, 0x000000ff}, | ||
| 164 | {0x00008378, 0x00000000}, | ||
| 165 | {0x0000837c, 0x00000000}, | ||
| 166 | {0x00008380, 0xffffffff}, | ||
| 167 | {0x00008384, 0xffffffff}, | ||
| 168 | {0x00008390, 0xffffffff}, | ||
| 169 | {0x00008394, 0xffffffff}, | ||
| 170 | {0x00008398, 0x00000000}, | ||
| 171 | {0x0000839c, 0x00000000}, | ||
| 172 | {0x000083a4, 0x0000fa14}, | ||
| 173 | {0x000083a8, 0x000f0c00}, | ||
| 174 | {0x000083ac, 0x33332210}, | ||
| 175 | {0x000083b0, 0x33332210}, | ||
| 176 | {0x000083b4, 0x33332210}, | ||
| 177 | {0x000083b8, 0x33332210}, | ||
| 178 | {0x000083bc, 0x00000000}, | ||
| 179 | {0x000083c0, 0x00000000}, | ||
| 180 | {0x000083c4, 0x00000000}, | ||
| 181 | {0x000083c8, 0x00000000}, | ||
| 182 | {0x000083cc, 0x00000200}, | ||
| 183 | {0x000083d0, 0x000301ff}, | ||
| 184 | }; | ||
| 185 | |||
| 186 | static const u32 ar9480_1p0_baseband_core_txfir_coeff_japan_2484[][2] = { | ||
| 187 | /* Addr allmodes */ | ||
| 188 | {0x0000a398, 0x00000000}, | ||
| 189 | {0x0000a39c, 0x6f7f0301}, | ||
| 190 | {0x0000a3a0, 0xca9228ee}, | ||
| 191 | }; | ||
| 192 | |||
| 193 | static const u32 ar9480_1p0_sys3ant[][2] = { | ||
| 194 | /* Addr allmodes */ | ||
| 195 | {0x00063280, 0x00040807}, | ||
| 196 | {0x00063284, 0x104ccccc}, | ||
| 197 | }; | ||
| 198 | |||
| 199 | static const u32 ar9480_pcie_phy_clkreq_enable_L1_1p0[][2] = { | ||
| 200 | /* Addr allmodes */ | ||
| 201 | {0x00018c00, 0x10053e5e}, | ||
| 202 | {0x00018c04, 0x000801d8}, | ||
| 203 | {0x00018c08, 0x0000580c}, | ||
| 204 | }; | ||
| 205 | |||
| 206 | static const u32 ar9480_1p0_mac_core_emulation[][2] = { | ||
| 207 | /* Addr allmodes */ | ||
| 208 | {0x00000030, 0x00060085}, | ||
| 209 | {0x00000044, 0x00000008}, | ||
| 210 | {0x0000805c, 0xffffc7ff}, | ||
| 211 | {0x00008344, 0xaa4a105b}, | ||
| 212 | }; | ||
| 213 | |||
| 214 | static const u32 ar9480_common_rx_gain_table_ar9280_2p0_1p0[][2] = { | ||
| 215 | /* Addr allmodes */ | ||
| 216 | {0x0000a000, 0x02000101}, | ||
| 217 | {0x0000a004, 0x02000102}, | ||
| 218 | {0x0000a008, 0x02000103}, | ||
| 219 | {0x0000a00c, 0x02000104}, | ||
| 220 | {0x0000a010, 0x02000200}, | ||
| 221 | {0x0000a014, 0x02000201}, | ||
| 222 | {0x0000a018, 0x02000202}, | ||
| 223 | {0x0000a01c, 0x02000203}, | ||
| 224 | {0x0000a020, 0x02000204}, | ||
| 225 | {0x0000a024, 0x02000205}, | ||
| 226 | {0x0000a028, 0x02000208}, | ||
| 227 | {0x0000a02c, 0x02000302}, | ||
| 228 | {0x0000a030, 0x02000303}, | ||
| 229 | {0x0000a034, 0x02000304}, | ||
| 230 | {0x0000a038, 0x02000400}, | ||
| 231 | {0x0000a03c, 0x02010300}, | ||
| 232 | {0x0000a040, 0x02010301}, | ||
| 233 | {0x0000a044, 0x02010302}, | ||
| 234 | {0x0000a048, 0x02000500}, | ||
| 235 | {0x0000a04c, 0x02010400}, | ||
| 236 | {0x0000a050, 0x02020300}, | ||
| 237 | {0x0000a054, 0x02020301}, | ||
| 238 | {0x0000a058, 0x02020302}, | ||
| 239 | {0x0000a05c, 0x02020303}, | ||
| 240 | {0x0000a060, 0x02020400}, | ||
| 241 | {0x0000a064, 0x02030300}, | ||
| 242 | {0x0000a068, 0x02030301}, | ||
| 243 | {0x0000a06c, 0x02030302}, | ||
| 244 | {0x0000a070, 0x02030303}, | ||
| 245 | {0x0000a074, 0x02030400}, | ||
| 246 | {0x0000a078, 0x02040300}, | ||
| 247 | {0x0000a07c, 0x02040301}, | ||
| 248 | {0x0000a080, 0x02040302}, | ||
| 249 | {0x0000a084, 0x02040303}, | ||
| 250 | {0x0000a088, 0x02030500}, | ||
| 251 | {0x0000a08c, 0x02040400}, | ||
| 252 | {0x0000a090, 0x02050203}, | ||
| 253 | {0x0000a094, 0x02050204}, | ||
| 254 | {0x0000a098, 0x02050205}, | ||
| 255 | {0x0000a09c, 0x02040500}, | ||
| 256 | {0x0000a0a0, 0x02050301}, | ||
| 257 | {0x0000a0a4, 0x02050302}, | ||
| 258 | {0x0000a0a8, 0x02050303}, | ||
| 259 | {0x0000a0ac, 0x02050400}, | ||
| 260 | {0x0000a0b0, 0x02050401}, | ||
| 261 | {0x0000a0b4, 0x02050402}, | ||
| 262 | {0x0000a0b8, 0x02050403}, | ||
| 263 | {0x0000a0bc, 0x02050500}, | ||
| 264 | {0x0000a0c0, 0x02050501}, | ||
| 265 | {0x0000a0c4, 0x02050502}, | ||
| 266 | {0x0000a0c8, 0x02050503}, | ||
| 267 | {0x0000a0cc, 0x02050504}, | ||
| 268 | {0x0000a0d0, 0x02050600}, | ||
| 269 | {0x0000a0d4, 0x02050601}, | ||
| 270 | {0x0000a0d8, 0x02050602}, | ||
| 271 | {0x0000a0dc, 0x02050603}, | ||
| 272 | {0x0000a0e0, 0x02050604}, | ||
| 273 | {0x0000a0e4, 0x02050700}, | ||
| 274 | {0x0000a0e8, 0x02050701}, | ||
| 275 | {0x0000a0ec, 0x02050702}, | ||
| 276 | {0x0000a0f0, 0x02050703}, | ||
| 277 | {0x0000a0f4, 0x02050704}, | ||
| 278 | {0x0000a0f8, 0x02050705}, | ||
| 279 | {0x0000a0fc, 0x02050708}, | ||
| 280 | {0x0000a100, 0x02050709}, | ||
| 281 | {0x0000a104, 0x0205070a}, | ||
| 282 | {0x0000a108, 0x0205070b}, | ||
| 283 | {0x0000a10c, 0x0205070c}, | ||
| 284 | {0x0000a110, 0x0205070d}, | ||
| 285 | {0x0000a114, 0x02050710}, | ||
| 286 | {0x0000a118, 0x02050711}, | ||
| 287 | {0x0000a11c, 0x02050712}, | ||
| 288 | {0x0000a120, 0x02050713}, | ||
| 289 | {0x0000a124, 0x02050714}, | ||
| 290 | {0x0000a128, 0x02050715}, | ||
| 291 | {0x0000a12c, 0x02050730}, | ||
| 292 | {0x0000a130, 0x02050731}, | ||
| 293 | {0x0000a134, 0x02050732}, | ||
| 294 | {0x0000a138, 0x02050733}, | ||
| 295 | {0x0000a13c, 0x02050734}, | ||
| 296 | {0x0000a140, 0x02050735}, | ||
| 297 | {0x0000a144, 0x02050750}, | ||
| 298 | {0x0000a148, 0x02050751}, | ||
| 299 | {0x0000a14c, 0x02050752}, | ||
| 300 | {0x0000a150, 0x02050753}, | ||
| 301 | {0x0000a154, 0x02050754}, | ||
| 302 | {0x0000a158, 0x02050755}, | ||
| 303 | {0x0000a15c, 0x02050770}, | ||
| 304 | {0x0000a160, 0x02050771}, | ||
| 305 | {0x0000a164, 0x02050772}, | ||
| 306 | {0x0000a168, 0x02050773}, | ||
| 307 | {0x0000a16c, 0x02050774}, | ||
| 308 | {0x0000a170, 0x02050775}, | ||
| 309 | {0x0000a174, 0x00000776}, | ||
| 310 | {0x0000a178, 0x00000776}, | ||
| 311 | {0x0000a17c, 0x00000776}, | ||
| 312 | {0x0000a180, 0x00000776}, | ||
| 313 | {0x0000a184, 0x00000776}, | ||
| 314 | {0x0000a188, 0x00000776}, | ||
| 315 | {0x0000a18c, 0x00000776}, | ||
| 316 | {0x0000a190, 0x00000776}, | ||
| 317 | {0x0000a194, 0x00000776}, | ||
| 318 | {0x0000a198, 0x00000776}, | ||
| 319 | {0x0000a19c, 0x00000776}, | ||
| 320 | {0x0000a1a0, 0x00000776}, | ||
| 321 | {0x0000a1a4, 0x00000776}, | ||
| 322 | {0x0000a1a8, 0x00000776}, | ||
| 323 | {0x0000a1ac, 0x00000776}, | ||
| 324 | {0x0000a1b0, 0x00000776}, | ||
| 325 | {0x0000a1b4, 0x00000776}, | ||
| 326 | {0x0000a1b8, 0x00000776}, | ||
| 327 | {0x0000a1bc, 0x00000776}, | ||
| 328 | {0x0000a1c0, 0x00000776}, | ||
| 329 | {0x0000a1c4, 0x00000776}, | ||
| 330 | {0x0000a1c8, 0x00000776}, | ||
| 331 | {0x0000a1cc, 0x00000776}, | ||
| 332 | {0x0000a1d0, 0x00000776}, | ||
| 333 | {0x0000a1d4, 0x00000776}, | ||
| 334 | {0x0000a1d8, 0x00000776}, | ||
| 335 | {0x0000a1dc, 0x00000776}, | ||
| 336 | {0x0000a1e0, 0x00000776}, | ||
| 337 | {0x0000a1e4, 0x00000776}, | ||
| 338 | {0x0000a1e8, 0x00000776}, | ||
| 339 | {0x0000a1ec, 0x00000776}, | ||
| 340 | {0x0000a1f0, 0x00000776}, | ||
| 341 | {0x0000a1f4, 0x00000776}, | ||
| 342 | {0x0000a1f8, 0x00000776}, | ||
| 343 | {0x0000a1fc, 0x00000776}, | ||
| 344 | {0x0000b000, 0x02000101}, | ||
| 345 | {0x0000b004, 0x02000102}, | ||
| 346 | {0x0000b008, 0x02000103}, | ||
| 347 | {0x0000b00c, 0x02000104}, | ||
| 348 | {0x0000b010, 0x02000200}, | ||
| 349 | {0x0000b014, 0x02000201}, | ||
| 350 | {0x0000b018, 0x02000202}, | ||
| 351 | {0x0000b01c, 0x02000203}, | ||
| 352 | {0x0000b020, 0x02000204}, | ||
| 353 | {0x0000b024, 0x02000205}, | ||
| 354 | {0x0000b028, 0x02000208}, | ||
| 355 | {0x0000b02c, 0x02000302}, | ||
| 356 | {0x0000b030, 0x02000303}, | ||
| 357 | {0x0000b034, 0x02000304}, | ||
| 358 | {0x0000b038, 0x02000400}, | ||
| 359 | {0x0000b03c, 0x02010300}, | ||
| 360 | {0x0000b040, 0x02010301}, | ||
| 361 | {0x0000b044, 0x02010302}, | ||
| 362 | {0x0000b048, 0x02000500}, | ||
| 363 | {0x0000b04c, 0x02010400}, | ||
| 364 | {0x0000b050, 0x02020300}, | ||
| 365 | {0x0000b054, 0x02020301}, | ||
| 366 | {0x0000b058, 0x02020302}, | ||
| 367 | {0x0000b05c, 0x02020303}, | ||
| 368 | {0x0000b060, 0x02020400}, | ||
| 369 | {0x0000b064, 0x02030300}, | ||
| 370 | {0x0000b068, 0x02030301}, | ||
| 371 | {0x0000b06c, 0x02030302}, | ||
| 372 | {0x0000b070, 0x02030303}, | ||
| 373 | {0x0000b074, 0x02030400}, | ||
| 374 | {0x0000b078, 0x02040300}, | ||
| 375 | {0x0000b07c, 0x02040301}, | ||
| 376 | {0x0000b080, 0x02040302}, | ||
| 377 | {0x0000b084, 0x02040303}, | ||
| 378 | {0x0000b088, 0x02030500}, | ||
| 379 | {0x0000b08c, 0x02040400}, | ||
| 380 | {0x0000b090, 0x02050203}, | ||
| 381 | {0x0000b094, 0x02050204}, | ||
| 382 | {0x0000b098, 0x02050205}, | ||
| 383 | {0x0000b09c, 0x02040500}, | ||
| 384 | {0x0000b0a0, 0x02050301}, | ||
| 385 | {0x0000b0a4, 0x02050302}, | ||
| 386 | {0x0000b0a8, 0x02050303}, | ||
| 387 | {0x0000b0ac, 0x02050400}, | ||
| 388 | {0x0000b0b0, 0x02050401}, | ||
| 389 | {0x0000b0b4, 0x02050402}, | ||
| 390 | {0x0000b0b8, 0x02050403}, | ||
| 391 | {0x0000b0bc, 0x02050500}, | ||
| 392 | {0x0000b0c0, 0x02050501}, | ||
| 393 | {0x0000b0c4, 0x02050502}, | ||
| 394 | {0x0000b0c8, 0x02050503}, | ||
| 395 | {0x0000b0cc, 0x02050504}, | ||
| 396 | {0x0000b0d0, 0x02050600}, | ||
| 397 | {0x0000b0d4, 0x02050601}, | ||
| 398 | {0x0000b0d8, 0x02050602}, | ||
| 399 | {0x0000b0dc, 0x02050603}, | ||
| 400 | {0x0000b0e0, 0x02050604}, | ||
| 401 | {0x0000b0e4, 0x02050700}, | ||
| 402 | {0x0000b0e8, 0x02050701}, | ||
| 403 | {0x0000b0ec, 0x02050702}, | ||
| 404 | {0x0000b0f0, 0x02050703}, | ||
| 405 | {0x0000b0f4, 0x02050704}, | ||
| 406 | {0x0000b0f8, 0x02050705}, | ||
| 407 | {0x0000b0fc, 0x02050708}, | ||
| 408 | {0x0000b100, 0x02050709}, | ||
| 409 | {0x0000b104, 0x0205070a}, | ||
| 410 | {0x0000b108, 0x0205070b}, | ||
| 411 | {0x0000b10c, 0x0205070c}, | ||
| 412 | {0x0000b110, 0x0205070d}, | ||
| 413 | {0x0000b114, 0x02050710}, | ||
| 414 | {0x0000b118, 0x02050711}, | ||
| 415 | {0x0000b11c, 0x02050712}, | ||
| 416 | {0x0000b120, 0x02050713}, | ||
| 417 | {0x0000b124, 0x02050714}, | ||
| 418 | {0x0000b128, 0x02050715}, | ||
| 419 | {0x0000b12c, 0x02050730}, | ||
| 420 | {0x0000b130, 0x02050731}, | ||
| 421 | {0x0000b134, 0x02050732}, | ||
| 422 | {0x0000b138, 0x02050733}, | ||
| 423 | {0x0000b13c, 0x02050734}, | ||
| 424 | {0x0000b140, 0x02050735}, | ||
| 425 | {0x0000b144, 0x02050750}, | ||
| 426 | {0x0000b148, 0x02050751}, | ||
| 427 | {0x0000b14c, 0x02050752}, | ||
| 428 | {0x0000b150, 0x02050753}, | ||
| 429 | {0x0000b154, 0x02050754}, | ||
| 430 | {0x0000b158, 0x02050755}, | ||
| 431 | {0x0000b15c, 0x02050770}, | ||
| 432 | {0x0000b160, 0x02050771}, | ||
| 433 | {0x0000b164, 0x02050772}, | ||
| 434 | {0x0000b168, 0x02050773}, | ||
| 435 | {0x0000b16c, 0x02050774}, | ||
| 436 | {0x0000b170, 0x02050775}, | ||
| 437 | {0x0000b174, 0x00000776}, | ||
| 438 | {0x0000b178, 0x00000776}, | ||
| 439 | {0x0000b17c, 0x00000776}, | ||
| 440 | {0x0000b180, 0x00000776}, | ||
| 441 | {0x0000b184, 0x00000776}, | ||
| 442 | {0x0000b188, 0x00000776}, | ||
| 443 | {0x0000b18c, 0x00000776}, | ||
| 444 | {0x0000b190, 0x00000776}, | ||
| 445 | {0x0000b194, 0x00000776}, | ||
| 446 | {0x0000b198, 0x00000776}, | ||
| 447 | {0x0000b19c, 0x00000776}, | ||
| 448 | {0x0000b1a0, 0x00000776}, | ||
| 449 | {0x0000b1a4, 0x00000776}, | ||
| 450 | {0x0000b1a8, 0x00000776}, | ||
| 451 | {0x0000b1ac, 0x00000776}, | ||
| 452 | {0x0000b1b0, 0x00000776}, | ||
| 453 | {0x0000b1b4, 0x00000776}, | ||
| 454 | {0x0000b1b8, 0x00000776}, | ||
| 455 | {0x0000b1bc, 0x00000776}, | ||
| 456 | {0x0000b1c0, 0x00000776}, | ||
| 457 | {0x0000b1c4, 0x00000776}, | ||
| 458 | {0x0000b1c8, 0x00000776}, | ||
| 459 | {0x0000b1cc, 0x00000776}, | ||
| 460 | {0x0000b1d0, 0x00000776}, | ||
| 461 | {0x0000b1d4, 0x00000776}, | ||
| 462 | {0x0000b1d8, 0x00000776}, | ||
| 463 | {0x0000b1dc, 0x00000776}, | ||
| 464 | {0x0000b1e0, 0x00000776}, | ||
| 465 | {0x0000b1e4, 0x00000776}, | ||
| 466 | {0x0000b1e8, 0x00000776}, | ||
| 467 | {0x0000b1ec, 0x00000776}, | ||
| 468 | {0x0000b1f0, 0x00000776}, | ||
| 469 | {0x0000b1f4, 0x00000776}, | ||
| 470 | {0x0000b1f8, 0x00000776}, | ||
| 471 | {0x0000b1fc, 0x00000776}, | ||
| 472 | }; | ||
| 473 | |||
| 474 | static const u32 ar9200_ar9280_2p0_radio_core_1p0[][2] = { | ||
| 475 | /* Addr allmodes */ | ||
| 476 | {0x00007800, 0x00040000}, | ||
| 477 | {0x00007804, 0xdb005012}, | ||
| 478 | {0x00007808, 0x04924914}, | ||
| 479 | {0x0000780c, 0x21084210}, | ||
| 480 | {0x00007810, 0x6d801300}, | ||
| 481 | {0x00007814, 0x0019beff}, | ||
| 482 | {0x00007818, 0x07e41000}, | ||
| 483 | {0x0000781c, 0x00392000}, | ||
| 484 | {0x00007820, 0x92592480}, | ||
| 485 | {0x00007824, 0x00040000}, | ||
| 486 | {0x00007828, 0xdb005012}, | ||
| 487 | {0x0000782c, 0x04924914}, | ||
| 488 | {0x00007830, 0x21084210}, | ||
| 489 | {0x00007834, 0x6d801300}, | ||
| 490 | {0x00007838, 0x0019beff}, | ||
| 491 | {0x0000783c, 0x07e40000}, | ||
| 492 | {0x00007840, 0x00392000}, | ||
| 493 | {0x00007844, 0x92592480}, | ||
| 494 | {0x00007848, 0x00100000}, | ||
| 495 | {0x0000784c, 0x773f0567}, | ||
| 496 | {0x00007850, 0x54214514}, | ||
| 497 | {0x00007854, 0x12035828}, | ||
| 498 | {0x00007858, 0x92592692}, | ||
| 499 | {0x0000785c, 0x00000000}, | ||
| 500 | {0x00007860, 0x56400000}, | ||
| 501 | {0x00007864, 0x0a8e370e}, | ||
| 502 | {0x00007868, 0xc0102850}, | ||
| 503 | {0x0000786c, 0x812d4000}, | ||
| 504 | {0x00007870, 0x807ec400}, | ||
| 505 | {0x00007874, 0x001b6db0}, | ||
| 506 | {0x00007878, 0x00376b63}, | ||
| 507 | {0x0000787c, 0x06db6db6}, | ||
| 508 | {0x00007880, 0x006d8000}, | ||
| 509 | {0x00007884, 0xffeffffe}, | ||
| 510 | {0x00007888, 0xffeffffe}, | ||
| 511 | {0x0000788c, 0x00010000}, | ||
| 512 | {0x00007890, 0x02060aeb}, | ||
| 513 | {0x00007894, 0x5a108000}, | ||
| 514 | }; | ||
| 515 | |||
| 516 | static const u32 ar9480_1p0_baseband_postamble_emulation[][5] = { | ||
| 517 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 518 | {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 519 | {0x00009e3c, 0xcf946221, 0xcf946221, 0xcf946221, 0xcf946221}, | ||
| 520 | {0x00009e44, 0x005c0000, 0x005c0000, 0x005c0000, 0x005c0000}, | ||
| 521 | {0x0000a258, 0x02020200, 0x02020200, 0x02020200, 0x02020200}, | ||
| 522 | {0x0000a25c, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, | ||
| 523 | {0x0000a28c, 0x00011111, 0x00011111, 0x00011111, 0x00011111}, | ||
| 524 | {0x0000a2c4, 0x00148d18, 0x00148d18, 0x00148d20, 0x00148d20}, | ||
| 525 | {0x0000a2d8, 0xf999a800, 0xf999a800, 0xf999a80c, 0xf999a80c}, | ||
| 526 | {0x0000a50c, 0x0000c00a, 0x0000c00a, 0x0000c00a, 0x0000c00a}, | ||
| 527 | {0x0000a538, 0x00038e8c, 0x00038e8c, 0x00038e8c, 0x00038e8c}, | ||
| 528 | {0x0000a53c, 0x0003cecc, 0x0003cecc, 0x0003cecc, 0x0003cecc}, | ||
| 529 | {0x0000a540, 0x00040ed4, 0x00040ed4, 0x00040ed4, 0x00040ed4}, | ||
| 530 | {0x0000a544, 0x00044edc, 0x00044edc, 0x00044edc, 0x00044edc}, | ||
| 531 | {0x0000a548, 0x00048ede, 0x00048ede, 0x00048ede, 0x00048ede}, | ||
| 532 | {0x0000a54c, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e}, | ||
| 533 | {0x0000a550, 0x00050f5e, 0x00050f5e, 0x00050f5e, 0x00050f5e}, | ||
| 534 | {0x0000a554, 0x00054f9e, 0x00054f9e, 0x00054f9e, 0x00054f9e}, | ||
| 535 | {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 536 | }; | ||
| 537 | |||
| 538 | static const u32 ar9480_pcie_phy_pll_on_clkreq_disable_L1_1p0[][2] = { | ||
| 539 | /* Addr allmodes */ | ||
| 540 | {0x00018c00, 0x10012e5e}, | ||
| 541 | {0x00018c04, 0x000801d8}, | ||
| 542 | {0x00018c08, 0x0000580c}, | ||
| 543 | }; | ||
| 544 | |||
| 545 | static const u32 ar9480_common_rx_gain_table_1p0[][2] = { | ||
| 546 | /* Addr allmodes */ | ||
| 547 | {0x0000a000, 0x00010000}, | ||
| 548 | {0x0000a004, 0x00030002}, | ||
| 549 | {0x0000a008, 0x00050004}, | ||
| 550 | {0x0000a00c, 0x00810080}, | ||
| 551 | {0x0000a010, 0x00830082}, | ||
| 552 | {0x0000a014, 0x01810180}, | ||
| 553 | {0x0000a018, 0x01830182}, | ||
| 554 | {0x0000a01c, 0x01850184}, | ||
| 555 | {0x0000a020, 0x01890188}, | ||
| 556 | {0x0000a024, 0x018b018a}, | ||
| 557 | {0x0000a028, 0x018d018c}, | ||
| 558 | {0x0000a02c, 0x01910190}, | ||
| 559 | {0x0000a030, 0x01930192}, | ||
| 560 | {0x0000a034, 0x01950194}, | ||
| 561 | {0x0000a038, 0x038a0196}, | ||
| 562 | {0x0000a03c, 0x038c038b}, | ||
| 563 | {0x0000a040, 0x0390038d}, | ||
| 564 | {0x0000a044, 0x03920391}, | ||
| 565 | {0x0000a048, 0x03940393}, | ||
| 566 | {0x0000a04c, 0x03960395}, | ||
| 567 | {0x0000a050, 0x00000000}, | ||
| 568 | {0x0000a054, 0x00000000}, | ||
| 569 | {0x0000a058, 0x00000000}, | ||
| 570 | {0x0000a05c, 0x00000000}, | ||
| 571 | {0x0000a060, 0x00000000}, | ||
| 572 | {0x0000a064, 0x00000000}, | ||
| 573 | {0x0000a068, 0x00000000}, | ||
| 574 | {0x0000a06c, 0x00000000}, | ||
| 575 | {0x0000a070, 0x00000000}, | ||
| 576 | {0x0000a074, 0x00000000}, | ||
| 577 | {0x0000a078, 0x00000000}, | ||
| 578 | {0x0000a07c, 0x00000000}, | ||
| 579 | {0x0000a080, 0x22222229}, | ||
| 580 | {0x0000a084, 0x1d1d1d1d}, | ||
| 581 | {0x0000a088, 0x1d1d1d1d}, | ||
| 582 | {0x0000a08c, 0x1d1d1d1d}, | ||
| 583 | {0x0000a090, 0x171d1d1d}, | ||
| 584 | {0x0000a094, 0x11111717}, | ||
| 585 | {0x0000a098, 0x00030311}, | ||
| 586 | {0x0000a09c, 0x00000000}, | ||
| 587 | {0x0000a0a0, 0x00000000}, | ||
| 588 | {0x0000a0a4, 0x00000000}, | ||
| 589 | {0x0000a0a8, 0x00000000}, | ||
| 590 | {0x0000a0ac, 0x00000000}, | ||
| 591 | {0x0000a0b0, 0x00000000}, | ||
| 592 | {0x0000a0b4, 0x00000000}, | ||
| 593 | {0x0000a0b8, 0x00000000}, | ||
| 594 | {0x0000a0bc, 0x00000000}, | ||
| 595 | {0x0000a0c0, 0x001f0000}, | ||
| 596 | {0x0000a0c4, 0x01000101}, | ||
| 597 | {0x0000a0c8, 0x011e011f}, | ||
| 598 | {0x0000a0cc, 0x011c011d}, | ||
| 599 | {0x0000a0d0, 0x02030204}, | ||
| 600 | {0x0000a0d4, 0x02010202}, | ||
| 601 | {0x0000a0d8, 0x021f0200}, | ||
| 602 | {0x0000a0dc, 0x0302021e}, | ||
| 603 | {0x0000a0e0, 0x03000301}, | ||
| 604 | {0x0000a0e4, 0x031e031f}, | ||
| 605 | {0x0000a0e8, 0x0402031d}, | ||
| 606 | {0x0000a0ec, 0x04000401}, | ||
| 607 | {0x0000a0f0, 0x041e041f}, | ||
| 608 | {0x0000a0f4, 0x0502041d}, | ||
| 609 | {0x0000a0f8, 0x05000501}, | ||
| 610 | {0x0000a0fc, 0x051e051f}, | ||
| 611 | {0x0000a100, 0x06010602}, | ||
| 612 | {0x0000a104, 0x061f0600}, | ||
| 613 | {0x0000a108, 0x061d061e}, | ||
| 614 | {0x0000a10c, 0x07020703}, | ||
| 615 | {0x0000a110, 0x07000701}, | ||
| 616 | {0x0000a114, 0x00000000}, | ||
| 617 | {0x0000a118, 0x00000000}, | ||
| 618 | {0x0000a11c, 0x00000000}, | ||
| 619 | {0x0000a120, 0x00000000}, | ||
| 620 | {0x0000a124, 0x00000000}, | ||
| 621 | {0x0000a128, 0x00000000}, | ||
| 622 | {0x0000a12c, 0x00000000}, | ||
| 623 | {0x0000a130, 0x00000000}, | ||
| 624 | {0x0000a134, 0x00000000}, | ||
| 625 | {0x0000a138, 0x00000000}, | ||
| 626 | {0x0000a13c, 0x00000000}, | ||
| 627 | {0x0000a140, 0x001f0000}, | ||
| 628 | {0x0000a144, 0x01000101}, | ||
| 629 | {0x0000a148, 0x011e011f}, | ||
| 630 | {0x0000a14c, 0x011c011d}, | ||
| 631 | {0x0000a150, 0x02030204}, | ||
| 632 | {0x0000a154, 0x02010202}, | ||
| 633 | {0x0000a158, 0x021f0200}, | ||
| 634 | {0x0000a15c, 0x0302021e}, | ||
| 635 | {0x0000a160, 0x03000301}, | ||
| 636 | {0x0000a164, 0x031e031f}, | ||
| 637 | {0x0000a168, 0x0402031d}, | ||
| 638 | {0x0000a16c, 0x04000401}, | ||
| 639 | {0x0000a170, 0x041e041f}, | ||
| 640 | {0x0000a174, 0x0502041d}, | ||
| 641 | {0x0000a178, 0x05000501}, | ||
| 642 | {0x0000a17c, 0x051e051f}, | ||
| 643 | {0x0000a180, 0x06010602}, | ||
| 644 | {0x0000a184, 0x061f0600}, | ||
| 645 | {0x0000a188, 0x061d061e}, | ||
| 646 | {0x0000a18c, 0x07020703}, | ||
| 647 | {0x0000a190, 0x07000701}, | ||
| 648 | {0x0000a194, 0x00000000}, | ||
| 649 | {0x0000a198, 0x00000000}, | ||
| 650 | {0x0000a19c, 0x00000000}, | ||
| 651 | {0x0000a1a0, 0x00000000}, | ||
| 652 | {0x0000a1a4, 0x00000000}, | ||
| 653 | {0x0000a1a8, 0x00000000}, | ||
| 654 | {0x0000a1ac, 0x00000000}, | ||
| 655 | {0x0000a1b0, 0x00000000}, | ||
| 656 | {0x0000a1b4, 0x00000000}, | ||
| 657 | {0x0000a1b8, 0x00000000}, | ||
| 658 | {0x0000a1bc, 0x00000000}, | ||
| 659 | {0x0000a1c0, 0x00000000}, | ||
| 660 | {0x0000a1c4, 0x00000000}, | ||
| 661 | {0x0000a1c8, 0x00000000}, | ||
| 662 | {0x0000a1cc, 0x00000000}, | ||
| 663 | {0x0000a1d0, 0x00000000}, | ||
| 664 | {0x0000a1d4, 0x00000000}, | ||
| 665 | {0x0000a1d8, 0x00000000}, | ||
| 666 | {0x0000a1dc, 0x00000000}, | ||
| 667 | {0x0000a1e0, 0x00000000}, | ||
| 668 | {0x0000a1e4, 0x00000000}, | ||
| 669 | {0x0000a1e8, 0x00000000}, | ||
| 670 | {0x0000a1ec, 0x00000000}, | ||
| 671 | {0x0000a1f0, 0x00000396}, | ||
| 672 | {0x0000a1f4, 0x00000396}, | ||
| 673 | {0x0000a1f8, 0x00000396}, | ||
| 674 | {0x0000a1fc, 0x00000196}, | ||
| 675 | {0x0000b000, 0x00010000}, | ||
| 676 | {0x0000b004, 0x00030002}, | ||
| 677 | {0x0000b008, 0x00050004}, | ||
| 678 | {0x0000b00c, 0x00810080}, | ||
| 679 | {0x0000b010, 0x00830082}, | ||
| 680 | {0x0000b014, 0x01810180}, | ||
| 681 | {0x0000b018, 0x01830182}, | ||
| 682 | {0x0000b01c, 0x01850184}, | ||
| 683 | {0x0000b020, 0x02810280}, | ||
| 684 | {0x0000b024, 0x02830282}, | ||
| 685 | {0x0000b028, 0x02850284}, | ||
| 686 | {0x0000b02c, 0x02890288}, | ||
| 687 | {0x0000b030, 0x028b028a}, | ||
| 688 | {0x0000b034, 0x0388028c}, | ||
| 689 | {0x0000b038, 0x038a0389}, | ||
| 690 | {0x0000b03c, 0x038c038b}, | ||
| 691 | {0x0000b040, 0x0390038d}, | ||
| 692 | {0x0000b044, 0x03920391}, | ||
| 693 | {0x0000b048, 0x03940393}, | ||
| 694 | {0x0000b04c, 0x03960395}, | ||
| 695 | {0x0000b050, 0x00000000}, | ||
| 696 | {0x0000b054, 0x00000000}, | ||
| 697 | {0x0000b058, 0x00000000}, | ||
| 698 | {0x0000b05c, 0x00000000}, | ||
| 699 | {0x0000b060, 0x00000000}, | ||
| 700 | {0x0000b064, 0x00000000}, | ||
| 701 | {0x0000b068, 0x00000000}, | ||
| 702 | {0x0000b06c, 0x00000000}, | ||
| 703 | {0x0000b070, 0x00000000}, | ||
| 704 | {0x0000b074, 0x00000000}, | ||
| 705 | {0x0000b078, 0x00000000}, | ||
| 706 | {0x0000b07c, 0x00000000}, | ||
| 707 | {0x0000b080, 0x2a2d2f32}, | ||
| 708 | {0x0000b084, 0x21232328}, | ||
| 709 | {0x0000b088, 0x19191c1e}, | ||
| 710 | {0x0000b08c, 0x12141417}, | ||
| 711 | {0x0000b090, 0x07070e0e}, | ||
| 712 | {0x0000b094, 0x03030305}, | ||
| 713 | {0x0000b098, 0x00000003}, | ||
| 714 | {0x0000b09c, 0x00000000}, | ||
| 715 | {0x0000b0a0, 0x00000000}, | ||
| 716 | {0x0000b0a4, 0x00000000}, | ||
| 717 | {0x0000b0a8, 0x00000000}, | ||
| 718 | {0x0000b0ac, 0x00000000}, | ||
| 719 | {0x0000b0b0, 0x00000000}, | ||
| 720 | {0x0000b0b4, 0x00000000}, | ||
| 721 | {0x0000b0b8, 0x00000000}, | ||
| 722 | {0x0000b0bc, 0x00000000}, | ||
| 723 | {0x0000b0c0, 0x003f0020}, | ||
| 724 | {0x0000b0c4, 0x00400041}, | ||
| 725 | {0x0000b0c8, 0x0140005f}, | ||
| 726 | {0x0000b0cc, 0x0160015f}, | ||
| 727 | {0x0000b0d0, 0x017e017f}, | ||
| 728 | {0x0000b0d4, 0x02410242}, | ||
| 729 | {0x0000b0d8, 0x025f0240}, | ||
| 730 | {0x0000b0dc, 0x027f0260}, | ||
| 731 | {0x0000b0e0, 0x0341027e}, | ||
| 732 | {0x0000b0e4, 0x035f0340}, | ||
| 733 | {0x0000b0e8, 0x037f0360}, | ||
| 734 | {0x0000b0ec, 0x04400441}, | ||
| 735 | {0x0000b0f0, 0x0460045f}, | ||
| 736 | {0x0000b0f4, 0x0541047f}, | ||
| 737 | {0x0000b0f8, 0x055f0540}, | ||
| 738 | {0x0000b0fc, 0x057f0560}, | ||
| 739 | {0x0000b100, 0x06400641}, | ||
| 740 | {0x0000b104, 0x0660065f}, | ||
| 741 | {0x0000b108, 0x067e067f}, | ||
| 742 | {0x0000b10c, 0x07410742}, | ||
| 743 | {0x0000b110, 0x075f0740}, | ||
| 744 | {0x0000b114, 0x077f0760}, | ||
| 745 | {0x0000b118, 0x07800781}, | ||
| 746 | {0x0000b11c, 0x07a0079f}, | ||
| 747 | {0x0000b120, 0x07c107bf}, | ||
| 748 | {0x0000b124, 0x000007c0}, | ||
| 749 | {0x0000b128, 0x00000000}, | ||
| 750 | {0x0000b12c, 0x00000000}, | ||
| 751 | {0x0000b130, 0x00000000}, | ||
| 752 | {0x0000b134, 0x00000000}, | ||
| 753 | {0x0000b138, 0x00000000}, | ||
| 754 | {0x0000b13c, 0x00000000}, | ||
| 755 | {0x0000b140, 0x003f0020}, | ||
| 756 | {0x0000b144, 0x00400041}, | ||
| 757 | {0x0000b148, 0x0140005f}, | ||
| 758 | {0x0000b14c, 0x0160015f}, | ||
| 759 | {0x0000b150, 0x017e017f}, | ||
| 760 | {0x0000b154, 0x02410242}, | ||
| 761 | {0x0000b158, 0x025f0240}, | ||
| 762 | {0x0000b15c, 0x027f0260}, | ||
| 763 | {0x0000b160, 0x0341027e}, | ||
| 764 | {0x0000b164, 0x035f0340}, | ||
| 765 | {0x0000b168, 0x037f0360}, | ||
| 766 | {0x0000b16c, 0x04400441}, | ||
| 767 | {0x0000b170, 0x0460045f}, | ||
| 768 | {0x0000b174, 0x0541047f}, | ||
| 769 | {0x0000b178, 0x055f0540}, | ||
| 770 | {0x0000b17c, 0x057f0560}, | ||
| 771 | {0x0000b180, 0x06400641}, | ||
| 772 | {0x0000b184, 0x0660065f}, | ||
| 773 | {0x0000b188, 0x067e067f}, | ||
| 774 | {0x0000b18c, 0x07410742}, | ||
| 775 | {0x0000b190, 0x075f0740}, | ||
| 776 | {0x0000b194, 0x077f0760}, | ||
| 777 | {0x0000b198, 0x07800781}, | ||
| 778 | {0x0000b19c, 0x07a0079f}, | ||
| 779 | {0x0000b1a0, 0x07c107bf}, | ||
| 780 | {0x0000b1a4, 0x000007c0}, | ||
| 781 | {0x0000b1a8, 0x00000000}, | ||
| 782 | {0x0000b1ac, 0x00000000}, | ||
| 783 | {0x0000b1b0, 0x00000000}, | ||
| 784 | {0x0000b1b4, 0x00000000}, | ||
| 785 | {0x0000b1b8, 0x00000000}, | ||
| 786 | {0x0000b1bc, 0x00000000}, | ||
| 787 | {0x0000b1c0, 0x00000000}, | ||
| 788 | {0x0000b1c4, 0x00000000}, | ||
| 789 | {0x0000b1c8, 0x00000000}, | ||
| 790 | {0x0000b1cc, 0x00000000}, | ||
| 791 | {0x0000b1d0, 0x00000000}, | ||
| 792 | {0x0000b1d4, 0x00000000}, | ||
| 793 | {0x0000b1d8, 0x00000000}, | ||
| 794 | {0x0000b1dc, 0x00000000}, | ||
| 795 | {0x0000b1e0, 0x00000000}, | ||
| 796 | {0x0000b1e4, 0x00000000}, | ||
| 797 | {0x0000b1e8, 0x00000000}, | ||
| 798 | {0x0000b1ec, 0x00000000}, | ||
| 799 | {0x0000b1f0, 0x00000396}, | ||
| 800 | {0x0000b1f4, 0x00000396}, | ||
| 801 | {0x0000b1f8, 0x00000396}, | ||
| 802 | {0x0000b1fc, 0x00000196}, | ||
| 803 | }; | ||
| 804 | |||
| 805 | static const u32 ar9480_modes_high_ob_db_tx_gain_table_1p0[][5] = { | ||
| 806 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 807 | {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, | ||
| 808 | {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, | ||
| 809 | {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, | ||
| 810 | {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, | ||
| 811 | {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, | ||
| 812 | {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, | ||
| 813 | {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002}, | ||
| 814 | {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004}, | ||
| 815 | {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200}, | ||
| 816 | {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202}, | ||
| 817 | {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400}, | ||
| 818 | {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402}, | ||
| 819 | {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404}, | ||
| 820 | {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603}, | ||
| 821 | {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02}, | ||
| 822 | {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04}, | ||
| 823 | {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20}, | ||
| 824 | {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20}, | ||
| 825 | {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22}, | ||
| 826 | {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24}, | ||
| 827 | {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640}, | ||
| 828 | {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660}, | ||
| 829 | {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861}, | ||
| 830 | {0x0000a548, 0x53025eb2, 0x53025eb2, 0x3e001a81, 0x3e001a81}, | ||
| 831 | {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83}, | ||
| 832 | {0x0000a550, 0x5f025ef6, 0x5f025ef6, 0x44001c84, 0x44001c84}, | ||
| 833 | {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3}, | ||
| 834 | {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5}, | ||
| 835 | {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9}, | ||
| 836 | {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb}, | ||
| 837 | {0x0000a564, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 838 | {0x0000a568, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 839 | {0x0000a56c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 840 | {0x0000a570, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 841 | {0x0000a574, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 842 | {0x0000a578, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 843 | {0x0000a57c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 844 | {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 845 | {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 846 | {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 847 | {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 848 | {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000}, | ||
| 849 | {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000}, | ||
| 850 | {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501}, | ||
| 851 | {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501}, | ||
| 852 | {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03}, | ||
| 853 | {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04}, | ||
| 854 | {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04}, | ||
| 855 | {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, | ||
| 856 | {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, | ||
| 857 | {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, | ||
| 858 | {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, | ||
| 859 | {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, | ||
| 860 | {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, | ||
| 861 | {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, | ||
| 862 | {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, | ||
| 863 | {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, | ||
| 864 | {0x00016044, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4}, | ||
| 865 | {0x00016048, 0x8db49060, 0x8db49060, 0x8db49060, 0x8db49060}, | ||
| 866 | {0x00016444, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4}, | ||
| 867 | {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000}, | ||
| 868 | }; | ||
| 869 | |||
| 870 | static const u32 ar9480_common_wo_xlna_rx_gain_table_1p0[][2] = { | ||
| 871 | /* Addr allmodes */ | ||
| 872 | {0x0000a000, 0x00010000}, | ||
| 873 | {0x0000a004, 0x00030002}, | ||
| 874 | {0x0000a008, 0x00050004}, | ||
| 875 | {0x0000a00c, 0x00810080}, | ||
| 876 | {0x0000a010, 0x00830082}, | ||
| 877 | {0x0000a014, 0x01810180}, | ||
| 878 | {0x0000a018, 0x01830182}, | ||
| 879 | {0x0000a01c, 0x01850184}, | ||
| 880 | {0x0000a020, 0x01890188}, | ||
| 881 | {0x0000a024, 0x018b018a}, | ||
| 882 | {0x0000a028, 0x018d018c}, | ||
| 883 | {0x0000a02c, 0x03820190}, | ||
| 884 | {0x0000a030, 0x03840383}, | ||
| 885 | {0x0000a034, 0x03880385}, | ||
| 886 | {0x0000a038, 0x038a0389}, | ||
| 887 | {0x0000a03c, 0x038c038b}, | ||
| 888 | {0x0000a040, 0x0390038d}, | ||
| 889 | {0x0000a044, 0x03920391}, | ||
| 890 | {0x0000a048, 0x03940393}, | ||
| 891 | {0x0000a04c, 0x03960395}, | ||
| 892 | {0x0000a050, 0x00000000}, | ||
| 893 | {0x0000a054, 0x00000000}, | ||
| 894 | {0x0000a058, 0x00000000}, | ||
| 895 | {0x0000a05c, 0x00000000}, | ||
| 896 | {0x0000a060, 0x00000000}, | ||
| 897 | {0x0000a064, 0x00000000}, | ||
| 898 | {0x0000a068, 0x00000000}, | ||
| 899 | {0x0000a06c, 0x00000000}, | ||
| 900 | {0x0000a070, 0x00000000}, | ||
| 901 | {0x0000a074, 0x00000000}, | ||
| 902 | {0x0000a078, 0x00000000}, | ||
| 903 | {0x0000a07c, 0x00000000}, | ||
| 904 | {0x0000a080, 0x29292929}, | ||
| 905 | {0x0000a084, 0x29292929}, | ||
| 906 | {0x0000a088, 0x29292929}, | ||
| 907 | {0x0000a08c, 0x29292929}, | ||
| 908 | {0x0000a090, 0x22292929}, | ||
| 909 | {0x0000a094, 0x1d1d2222}, | ||
| 910 | {0x0000a098, 0x0c111117}, | ||
| 911 | {0x0000a09c, 0x00030303}, | ||
| 912 | {0x0000a0a0, 0x00000000}, | ||
| 913 | {0x0000a0a4, 0x00000000}, | ||
| 914 | {0x0000a0a8, 0x00000000}, | ||
| 915 | {0x0000a0ac, 0x00000000}, | ||
| 916 | {0x0000a0b0, 0x00000000}, | ||
| 917 | {0x0000a0b4, 0x00000000}, | ||
| 918 | {0x0000a0b8, 0x00000000}, | ||
| 919 | {0x0000a0bc, 0x00000000}, | ||
| 920 | {0x0000a0c0, 0x001f0000}, | ||
| 921 | {0x0000a0c4, 0x01000101}, | ||
| 922 | {0x0000a0c8, 0x011e011f}, | ||
| 923 | {0x0000a0cc, 0x011c011d}, | ||
| 924 | {0x0000a0d0, 0x02030204}, | ||
| 925 | {0x0000a0d4, 0x02010202}, | ||
| 926 | {0x0000a0d8, 0x021f0200}, | ||
| 927 | {0x0000a0dc, 0x0302021e}, | ||
| 928 | {0x0000a0e0, 0x03000301}, | ||
| 929 | {0x0000a0e4, 0x031e031f}, | ||
| 930 | {0x0000a0e8, 0x0402031d}, | ||
| 931 | {0x0000a0ec, 0x04000401}, | ||
| 932 | {0x0000a0f0, 0x041e041f}, | ||
| 933 | {0x0000a0f4, 0x0502041d}, | ||
| 934 | {0x0000a0f8, 0x05000501}, | ||
| 935 | {0x0000a0fc, 0x051e051f}, | ||
| 936 | {0x0000a100, 0x06010602}, | ||
| 937 | {0x0000a104, 0x061f0600}, | ||
| 938 | {0x0000a108, 0x061d061e}, | ||
| 939 | {0x0000a10c, 0x07020703}, | ||
| 940 | {0x0000a110, 0x07000701}, | ||
| 941 | {0x0000a114, 0x00000000}, | ||
| 942 | {0x0000a118, 0x00000000}, | ||
| 943 | {0x0000a11c, 0x00000000}, | ||
| 944 | {0x0000a120, 0x00000000}, | ||
| 945 | {0x0000a124, 0x00000000}, | ||
| 946 | {0x0000a128, 0x00000000}, | ||
| 947 | {0x0000a12c, 0x00000000}, | ||
| 948 | {0x0000a130, 0x00000000}, | ||
| 949 | {0x0000a134, 0x00000000}, | ||
| 950 | {0x0000a138, 0x00000000}, | ||
| 951 | {0x0000a13c, 0x00000000}, | ||
| 952 | {0x0000a140, 0x001f0000}, | ||
| 953 | {0x0000a144, 0x01000101}, | ||
| 954 | {0x0000a148, 0x011e011f}, | ||
| 955 | {0x0000a14c, 0x011c011d}, | ||
| 956 | {0x0000a150, 0x02030204}, | ||
| 957 | {0x0000a154, 0x02010202}, | ||
| 958 | {0x0000a158, 0x021f0200}, | ||
| 959 | {0x0000a15c, 0x0302021e}, | ||
| 960 | {0x0000a160, 0x03000301}, | ||
| 961 | {0x0000a164, 0x031e031f}, | ||
| 962 | {0x0000a168, 0x0402031d}, | ||
| 963 | {0x0000a16c, 0x04000401}, | ||
| 964 | {0x0000a170, 0x041e041f}, | ||
| 965 | {0x0000a174, 0x0502041d}, | ||
| 966 | {0x0000a178, 0x05000501}, | ||
| 967 | {0x0000a17c, 0x051e051f}, | ||
| 968 | {0x0000a180, 0x06010602}, | ||
| 969 | {0x0000a184, 0x061f0600}, | ||
| 970 | {0x0000a188, 0x061d061e}, | ||
| 971 | {0x0000a18c, 0x07020703}, | ||
| 972 | {0x0000a190, 0x07000701}, | ||
| 973 | {0x0000a194, 0x00000000}, | ||
| 974 | {0x0000a198, 0x00000000}, | ||
| 975 | {0x0000a19c, 0x00000000}, | ||
| 976 | {0x0000a1a0, 0x00000000}, | ||
| 977 | {0x0000a1a4, 0x00000000}, | ||
| 978 | {0x0000a1a8, 0x00000000}, | ||
| 979 | {0x0000a1ac, 0x00000000}, | ||
| 980 | {0x0000a1b0, 0x00000000}, | ||
| 981 | {0x0000a1b4, 0x00000000}, | ||
| 982 | {0x0000a1b8, 0x00000000}, | ||
| 983 | {0x0000a1bc, 0x00000000}, | ||
| 984 | {0x0000a1c0, 0x00000000}, | ||
| 985 | {0x0000a1c4, 0x00000000}, | ||
| 986 | {0x0000a1c8, 0x00000000}, | ||
| 987 | {0x0000a1cc, 0x00000000}, | ||
| 988 | {0x0000a1d0, 0x00000000}, | ||
| 989 | {0x0000a1d4, 0x00000000}, | ||
| 990 | {0x0000a1d8, 0x00000000}, | ||
| 991 | {0x0000a1dc, 0x00000000}, | ||
| 992 | {0x0000a1e0, 0x00000000}, | ||
| 993 | {0x0000a1e4, 0x00000000}, | ||
| 994 | {0x0000a1e8, 0x00000000}, | ||
| 995 | {0x0000a1ec, 0x00000000}, | ||
| 996 | {0x0000a1f0, 0x00000396}, | ||
| 997 | {0x0000a1f4, 0x00000396}, | ||
| 998 | {0x0000a1f8, 0x00000396}, | ||
| 999 | {0x0000a1fc, 0x00000196}, | ||
| 1000 | {0x0000b000, 0x00010000}, | ||
| 1001 | {0x0000b004, 0x00030002}, | ||
| 1002 | {0x0000b008, 0x00050004}, | ||
| 1003 | {0x0000b00c, 0x00810080}, | ||
| 1004 | {0x0000b010, 0x00830082}, | ||
| 1005 | {0x0000b014, 0x01810180}, | ||
| 1006 | {0x0000b018, 0x01830182}, | ||
| 1007 | {0x0000b01c, 0x01850184}, | ||
| 1008 | {0x0000b020, 0x02810280}, | ||
| 1009 | {0x0000b024, 0x02830282}, | ||
| 1010 | {0x0000b028, 0x02850284}, | ||
| 1011 | {0x0000b02c, 0x02890288}, | ||
| 1012 | {0x0000b030, 0x028b028a}, | ||
| 1013 | {0x0000b034, 0x0388028c}, | ||
| 1014 | {0x0000b038, 0x038a0389}, | ||
| 1015 | {0x0000b03c, 0x038c038b}, | ||
| 1016 | {0x0000b040, 0x0390038d}, | ||
| 1017 | {0x0000b044, 0x03920391}, | ||
| 1018 | {0x0000b048, 0x03940393}, | ||
| 1019 | {0x0000b04c, 0x03960395}, | ||
| 1020 | {0x0000b050, 0x00000000}, | ||
| 1021 | {0x0000b054, 0x00000000}, | ||
| 1022 | {0x0000b058, 0x00000000}, | ||
| 1023 | {0x0000b05c, 0x00000000}, | ||
| 1024 | {0x0000b060, 0x00000000}, | ||
| 1025 | {0x0000b064, 0x00000000}, | ||
| 1026 | {0x0000b068, 0x00000000}, | ||
| 1027 | {0x0000b06c, 0x00000000}, | ||
| 1028 | {0x0000b070, 0x00000000}, | ||
| 1029 | {0x0000b074, 0x00000000}, | ||
| 1030 | {0x0000b078, 0x00000000}, | ||
| 1031 | {0x0000b07c, 0x00000000}, | ||
| 1032 | {0x0000b080, 0x32323232}, | ||
| 1033 | {0x0000b084, 0x2f2f3232}, | ||
| 1034 | {0x0000b088, 0x23282a2d}, | ||
| 1035 | {0x0000b08c, 0x1c1e2123}, | ||
| 1036 | {0x0000b090, 0x14171919}, | ||
| 1037 | {0x0000b094, 0x0e0e1214}, | ||
| 1038 | {0x0000b098, 0x03050707}, | ||
| 1039 | {0x0000b09c, 0x00030303}, | ||
| 1040 | {0x0000b0a0, 0x00000000}, | ||
| 1041 | {0x0000b0a4, 0x00000000}, | ||
| 1042 | {0x0000b0a8, 0x00000000}, | ||
| 1043 | {0x0000b0ac, 0x00000000}, | ||
| 1044 | {0x0000b0b0, 0x00000000}, | ||
| 1045 | {0x0000b0b4, 0x00000000}, | ||
| 1046 | {0x0000b0b8, 0x00000000}, | ||
| 1047 | {0x0000b0bc, 0x00000000}, | ||
| 1048 | {0x0000b0c0, 0x003f0020}, | ||
| 1049 | {0x0000b0c4, 0x00400041}, | ||
| 1050 | {0x0000b0c8, 0x0140005f}, | ||
| 1051 | {0x0000b0cc, 0x0160015f}, | ||
| 1052 | {0x0000b0d0, 0x017e017f}, | ||
| 1053 | {0x0000b0d4, 0x02410242}, | ||
| 1054 | {0x0000b0d8, 0x025f0240}, | ||
| 1055 | {0x0000b0dc, 0x027f0260}, | ||
| 1056 | {0x0000b0e0, 0x0341027e}, | ||
| 1057 | {0x0000b0e4, 0x035f0340}, | ||
| 1058 | {0x0000b0e8, 0x037f0360}, | ||
| 1059 | {0x0000b0ec, 0x04400441}, | ||
| 1060 | {0x0000b0f0, 0x0460045f}, | ||
| 1061 | {0x0000b0f4, 0x0541047f}, | ||
| 1062 | {0x0000b0f8, 0x055f0540}, | ||
| 1063 | {0x0000b0fc, 0x057f0560}, | ||
| 1064 | {0x0000b100, 0x06400641}, | ||
| 1065 | {0x0000b104, 0x0660065f}, | ||
| 1066 | {0x0000b108, 0x067e067f}, | ||
| 1067 | {0x0000b10c, 0x07410742}, | ||
| 1068 | {0x0000b110, 0x075f0740}, | ||
| 1069 | {0x0000b114, 0x077f0760}, | ||
| 1070 | {0x0000b118, 0x07800781}, | ||
| 1071 | {0x0000b11c, 0x07a0079f}, | ||
| 1072 | {0x0000b120, 0x07c107bf}, | ||
| 1073 | {0x0000b124, 0x000007c0}, | ||
| 1074 | {0x0000b128, 0x00000000}, | ||
| 1075 | {0x0000b12c, 0x00000000}, | ||
| 1076 | {0x0000b130, 0x00000000}, | ||
| 1077 | {0x0000b134, 0x00000000}, | ||
| 1078 | {0x0000b138, 0x00000000}, | ||
| 1079 | {0x0000b13c, 0x00000000}, | ||
| 1080 | {0x0000b140, 0x003f0020}, | ||
| 1081 | {0x0000b144, 0x00400041}, | ||
| 1082 | {0x0000b148, 0x0140005f}, | ||
| 1083 | {0x0000b14c, 0x0160015f}, | ||
| 1084 | {0x0000b150, 0x017e017f}, | ||
| 1085 | {0x0000b154, 0x02410242}, | ||
| 1086 | {0x0000b158, 0x025f0240}, | ||
| 1087 | {0x0000b15c, 0x027f0260}, | ||
| 1088 | {0x0000b160, 0x0341027e}, | ||
| 1089 | {0x0000b164, 0x035f0340}, | ||
| 1090 | {0x0000b168, 0x037f0360}, | ||
| 1091 | {0x0000b16c, 0x04400441}, | ||
| 1092 | {0x0000b170, 0x0460045f}, | ||
| 1093 | {0x0000b174, 0x0541047f}, | ||
| 1094 | {0x0000b178, 0x055f0540}, | ||
| 1095 | {0x0000b17c, 0x057f0560}, | ||
| 1096 | {0x0000b180, 0x06400641}, | ||
| 1097 | {0x0000b184, 0x0660065f}, | ||
| 1098 | {0x0000b188, 0x067e067f}, | ||
| 1099 | {0x0000b18c, 0x07410742}, | ||
| 1100 | {0x0000b190, 0x075f0740}, | ||
| 1101 | {0x0000b194, 0x077f0760}, | ||
| 1102 | {0x0000b198, 0x07800781}, | ||
| 1103 | {0x0000b19c, 0x07a0079f}, | ||
| 1104 | {0x0000b1a0, 0x07c107bf}, | ||
| 1105 | {0x0000b1a4, 0x000007c0}, | ||
| 1106 | {0x0000b1a8, 0x00000000}, | ||
| 1107 | {0x0000b1ac, 0x00000000}, | ||
| 1108 | {0x0000b1b0, 0x00000000}, | ||
| 1109 | {0x0000b1b4, 0x00000000}, | ||
| 1110 | {0x0000b1b8, 0x00000000}, | ||
| 1111 | {0x0000b1bc, 0x00000000}, | ||
| 1112 | {0x0000b1c0, 0x00000000}, | ||
| 1113 | {0x0000b1c4, 0x00000000}, | ||
| 1114 | {0x0000b1c8, 0x00000000}, | ||
| 1115 | {0x0000b1cc, 0x00000000}, | ||
| 1116 | {0x0000b1d0, 0x00000000}, | ||
| 1117 | {0x0000b1d4, 0x00000000}, | ||
| 1118 | {0x0000b1d8, 0x00000000}, | ||
| 1119 | {0x0000b1dc, 0x00000000}, | ||
| 1120 | {0x0000b1e0, 0x00000000}, | ||
| 1121 | {0x0000b1e4, 0x00000000}, | ||
| 1122 | {0x0000b1e8, 0x00000000}, | ||
| 1123 | {0x0000b1ec, 0x00000000}, | ||
| 1124 | {0x0000b1f0, 0x00000396}, | ||
| 1125 | {0x0000b1f4, 0x00000396}, | ||
| 1126 | {0x0000b1f8, 0x00000396}, | ||
| 1127 | {0x0000b1fc, 0x00000196}, | ||
| 1128 | }; | ||
| 1129 | |||
| 1130 | static const u32 ar9480_1p0_mac_postamble[][5] = { | ||
| 1131 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 1132 | {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, | ||
| 1133 | {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, | ||
| 1134 | {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38}, | ||
| 1135 | {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00}, | ||
| 1136 | {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b}, | ||
| 1137 | {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810}, | ||
| 1138 | {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a}, | ||
| 1139 | {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, | ||
| 1140 | }; | ||
| 1141 | |||
| 1142 | static const u32 ar9480_1p0_mac_postamble_emulation[][5] = { | ||
| 1143 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 1144 | {0x00008014, 0x10f810f8, 0x10f810f8, 0x10f810f8, 0x10f810f8}, | ||
| 1145 | {0x0000801c, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017}, | ||
| 1146 | }; | ||
| 1147 | |||
| 1148 | static const u32 ar9480_1p0_tx_gain_table_baseband_postamble_emulation[][5] = { | ||
| 1149 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 1150 | {0x0000a410, 0x000000d5, 0x000000d5, 0x000000d5, 0x000000d5}, | ||
| 1151 | {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1152 | {0x0000a504, 0x00004002, 0x00004002, 0x00004002, 0x00004002}, | ||
| 1153 | {0x0000a508, 0x00008004, 0x00008004, 0x00008004, 0x00008004}, | ||
| 1154 | {0x0000a510, 0x0001000c, 0x0001000c, 0x0001000c, 0x0001000c}, | ||
| 1155 | {0x0000a514, 0x0001420b, 0x0001420b, 0x0001420b, 0x0001420b}, | ||
| 1156 | {0x0000a518, 0x0001824a, 0x0001824a, 0x0001824a, 0x0001824a}, | ||
| 1157 | {0x0000a51c, 0x0001c44a, 0x0001c44a, 0x0001c44a, 0x0001c44a}, | ||
| 1158 | {0x0000a520, 0x0002064a, 0x0002064a, 0x0002064a, 0x0002064a}, | ||
| 1159 | {0x0000a524, 0x0002484a, 0x0002484a, 0x0002484a, 0x0002484a}, | ||
| 1160 | {0x0000a528, 0x00028a4a, 0x00028a4a, 0x00028a4a, 0x00028a4a}, | ||
| 1161 | {0x0000a52c, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a}, | ||
| 1162 | {0x0000a530, 0x00030e4a, 0x00030e4a, 0x00030e4a, 0x00030e4a}, | ||
| 1163 | {0x0000a534, 0x00034e8a, 0x00034e8a, 0x00034e8a, 0x00034e8a}, | ||
| 1164 | }; | ||
| 1165 | |||
| 1166 | static const u32 ar9480_1p0_radio_postamble[][5] = { | ||
| 1167 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 1168 | {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524}, | ||
| 1169 | {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24646c08, 0x24646c08}, | ||
| 1170 | {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70}, | ||
| 1171 | {0x0001610c, 0x48000000, 0x40000000, 0x40000000, 0x40000000}, | ||
| 1172 | {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, | ||
| 1173 | {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000}, | ||
| 1174 | {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, | ||
| 1175 | }; | ||
| 1176 | |||
| 1177 | static const u32 ar9480_1p0_soc_postamble_emulation[][5] = { | ||
| 1178 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 1179 | {0x00007010, 0x00001133, 0x00001133, 0x00001133, 0x00001133}, | ||
| 1180 | }; | ||
| 1181 | |||
| 1182 | static const u32 ar9480_1p0_baseband_core[][2] = { | ||
| 1183 | /* Addr allmodes */ | ||
| 1184 | {0x00009800, 0xafe68e30}, | ||
| 1185 | {0x00009804, 0xfd14e000}, | ||
| 1186 | {0x00009808, 0x9c0a9f6b}, | ||
| 1187 | {0x0000980c, 0x04900000}, | ||
| 1188 | {0x00009814, 0x9280c00a}, | ||
| 1189 | {0x00009818, 0x00000000}, | ||
| 1190 | {0x0000981c, 0x00020028}, | ||
| 1191 | {0x00009834, 0x6400a290}, | ||
| 1192 | {0x00009838, 0x0108ecff}, | ||
| 1193 | {0x0000983c, 0x0d000600}, | ||
| 1194 | {0x00009880, 0x201fff00}, | ||
| 1195 | {0x00009884, 0x00001042}, | ||
| 1196 | {0x000098a4, 0x00200400}, | ||
| 1197 | {0x000098b0, 0x32840bbe}, | ||
| 1198 | {0x000098d0, 0x004b6a8e}, | ||
| 1199 | {0x000098d4, 0x00000820}, | ||
| 1200 | {0x000098dc, 0x00000000}, | ||
| 1201 | {0x000098e4, 0x01ffffff}, | ||
| 1202 | {0x000098e8, 0x01ffffff}, | ||
| 1203 | {0x000098ec, 0x01ffffff}, | ||
| 1204 | {0x000098f0, 0x00000000}, | ||
| 1205 | {0x000098f4, 0x00000000}, | ||
| 1206 | {0x00009c04, 0xff55ff55}, | ||
| 1207 | {0x00009c08, 0x0320ff55}, | ||
| 1208 | {0x00009c0c, 0x00000000}, | ||
| 1209 | {0x00009c10, 0x00000000}, | ||
| 1210 | {0x00009c14, 0x00046384}, | ||
| 1211 | {0x00009c18, 0x05b6b440}, | ||
| 1212 | {0x00009c1c, 0x00b6b440}, | ||
| 1213 | {0x00009d00, 0xc080a333}, | ||
| 1214 | {0x00009d04, 0x40206c10}, | ||
| 1215 | {0x00009d08, 0x009c4060}, | ||
| 1216 | {0x00009d0c, 0x9883800a}, | ||
| 1217 | {0x00009d10, 0x01834061}, | ||
| 1218 | {0x00009d14, 0x00c0040b}, | ||
| 1219 | {0x00009d18, 0x00000000}, | ||
| 1220 | {0x00009e08, 0x0038230c}, | ||
| 1221 | {0x00009e24, 0x990bb514}, | ||
| 1222 | {0x00009e28, 0x0c6f0000}, | ||
| 1223 | {0x00009e30, 0x06336f77}, | ||
| 1224 | {0x00009e34, 0x6af6532f}, | ||
| 1225 | {0x00009e38, 0x0cc80c00}, | ||
| 1226 | {0x00009e40, 0x0d261820}, | ||
| 1227 | {0x00009e4c, 0x00001004}, | ||
| 1228 | {0x00009e50, 0x00ff03f1}, | ||
| 1229 | {0x00009e54, 0x64c355c7}, | ||
| 1230 | {0x00009e58, 0xfd897735}, | ||
| 1231 | {0x00009e5c, 0xe9198724}, | ||
| 1232 | {0x00009fc0, 0x803e4788}, | ||
| 1233 | {0x00009fc4, 0x0001efb5}, | ||
| 1234 | {0x00009fcc, 0x40000014}, | ||
| 1235 | {0x00009fd0, 0x01193b93}, | ||
| 1236 | {0x0000a20c, 0x00000000}, | ||
| 1237 | {0x0000a220, 0x00000000}, | ||
| 1238 | {0x0000a224, 0x00000000}, | ||
| 1239 | {0x0000a228, 0x10002310}, | ||
| 1240 | {0x0000a23c, 0x00000000}, | ||
| 1241 | {0x0000a244, 0x0c000000}, | ||
| 1242 | {0x0000a2a0, 0x00000001}, | ||
| 1243 | {0x0000a2c0, 0x00000001}, | ||
| 1244 | {0x0000a2c8, 0x00000000}, | ||
| 1245 | {0x0000a2cc, 0x18c43433}, | ||
| 1246 | {0x0000a2d4, 0x00000000}, | ||
| 1247 | {0x0000a2ec, 0x00000000}, | ||
| 1248 | {0x0000a2f0, 0x00000000}, | ||
| 1249 | {0x0000a2f4, 0x00000000}, | ||
| 1250 | {0x0000a2f8, 0x00000000}, | ||
| 1251 | {0x0000a344, 0x00000000}, | ||
| 1252 | {0x0000a34c, 0x00000000}, | ||
| 1253 | {0x0000a350, 0x0000a000}, | ||
| 1254 | {0x0000a364, 0x00000000}, | ||
| 1255 | {0x0000a370, 0x00000000}, | ||
| 1256 | {0x0000a390, 0x00000001}, | ||
| 1257 | {0x0000a394, 0x00000444}, | ||
| 1258 | {0x0000a398, 0x001f0e0f}, | ||
| 1259 | {0x0000a39c, 0x0075393f}, | ||
| 1260 | {0x0000a3a0, 0xb79f6427}, | ||
| 1261 | {0x0000a3a4, 0x00000000}, | ||
| 1262 | {0x0000a3a8, 0xaaaaaaaa}, | ||
| 1263 | {0x0000a3ac, 0x3c466478}, | ||
| 1264 | {0x0000a3c0, 0x20202020}, | ||
| 1265 | {0x0000a3c4, 0x22222220}, | ||
| 1266 | {0x0000a3c8, 0x20200020}, | ||
| 1267 | {0x0000a3cc, 0x20202020}, | ||
| 1268 | {0x0000a3d0, 0x20202020}, | ||
| 1269 | {0x0000a3d4, 0x20202020}, | ||
| 1270 | {0x0000a3d8, 0x20202020}, | ||
| 1271 | {0x0000a3dc, 0x20202020}, | ||
| 1272 | {0x0000a3e0, 0x20202020}, | ||
| 1273 | {0x0000a3e4, 0x20202020}, | ||
| 1274 | {0x0000a3e8, 0x20202020}, | ||
| 1275 | {0x0000a3ec, 0x20202020}, | ||
| 1276 | {0x0000a3f0, 0x00000000}, | ||
| 1277 | {0x0000a3f4, 0x00000006}, | ||
| 1278 | {0x0000a3f8, 0x0c9bd380}, | ||
| 1279 | {0x0000a3fc, 0x000f0f01}, | ||
| 1280 | {0x0000a400, 0x8fa91f01}, | ||
| 1281 | {0x0000a404, 0x00000000}, | ||
| 1282 | {0x0000a408, 0x0e79e5c6}, | ||
| 1283 | {0x0000a40c, 0x00820820}, | ||
| 1284 | {0x0000a414, 0x1ce739ce}, | ||
| 1285 | {0x0000a418, 0x2d001dce}, | ||
| 1286 | {0x0000a41c, 0x1ce739ce}, | ||
| 1287 | {0x0000a420, 0x000001ce}, | ||
| 1288 | {0x0000a424, 0x1ce739ce}, | ||
| 1289 | {0x0000a428, 0x000001ce}, | ||
| 1290 | {0x0000a42c, 0x1ce739ce}, | ||
| 1291 | {0x0000a430, 0x1ce739ce}, | ||
| 1292 | {0x0000a434, 0x00000000}, | ||
| 1293 | {0x0000a438, 0x00001801}, | ||
| 1294 | {0x0000a43c, 0x00100000}, | ||
| 1295 | {0x0000a440, 0x00000000}, | ||
| 1296 | {0x0000a444, 0x00000000}, | ||
| 1297 | {0x0000a448, 0x05000080}, | ||
| 1298 | {0x0000a44c, 0x00000001}, | ||
| 1299 | {0x0000a450, 0x00010000}, | ||
| 1300 | {0x0000a458, 0x00000000}, | ||
| 1301 | {0x0000a644, 0xbfad9d74}, | ||
| 1302 | {0x0000a648, 0x0048060a}, | ||
| 1303 | {0x0000a64c, 0x00003c37}, | ||
| 1304 | {0x0000a670, 0x03020100}, | ||
| 1305 | {0x0000a674, 0x09080504}, | ||
| 1306 | {0x0000a678, 0x0d0c0b0a}, | ||
| 1307 | {0x0000a67c, 0x13121110}, | ||
| 1308 | {0x0000a680, 0x31301514}, | ||
| 1309 | {0x0000a684, 0x35343332}, | ||
| 1310 | {0x0000a688, 0x00000036}, | ||
| 1311 | {0x0000a690, 0x00000838}, | ||
| 1312 | {0x0000a6b0, 0x0000000a}, | ||
| 1313 | {0x0000a6b4, 0x28f12c01}, | ||
| 1314 | {0x0000a7c0, 0x00000000}, | ||
| 1315 | {0x0000a7c4, 0xfffffffc}, | ||
| 1316 | {0x0000a7c8, 0x00000000}, | ||
| 1317 | {0x0000a7cc, 0x00000000}, | ||
| 1318 | {0x0000a7d0, 0x00000000}, | ||
| 1319 | {0x0000a7d4, 0x00000004}, | ||
| 1320 | {0x0000a7dc, 0x00000001}, | ||
| 1321 | {0x0000a8d0, 0x004b6a8e}, | ||
| 1322 | {0x0000a8d4, 0x00000820}, | ||
| 1323 | {0x0000a8dc, 0x00000000}, | ||
| 1324 | {0x0000a8f0, 0x00000000}, | ||
| 1325 | {0x0000a8f4, 0x00000000}, | ||
| 1326 | {0x0000b2d0, 0x00000080}, | ||
| 1327 | {0x0000b2d4, 0x00000000}, | ||
| 1328 | {0x0000b2ec, 0x00000000}, | ||
| 1329 | {0x0000b2f0, 0x00000000}, | ||
| 1330 | {0x0000b2f4, 0x00000000}, | ||
| 1331 | {0x0000b2f8, 0x00000000}, | ||
| 1332 | {0x0000b408, 0x0e79e5c0}, | ||
| 1333 | {0x0000b40c, 0x00820820}, | ||
| 1334 | {0x0000b420, 0x00000000}, | ||
| 1335 | {0x0000b6b0, 0x0000000a}, | ||
| 1336 | {0x0000b6b4, 0x00c00001}, | ||
| 1337 | }; | ||
| 1338 | |||
| 1339 | static const u32 ar9480_1p0_baseband_postamble[][5] = { | ||
| 1340 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 1341 | {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011}, | ||
| 1342 | {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e}, | ||
| 1343 | {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, | ||
| 1344 | {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881}, | ||
| 1345 | {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, | ||
| 1346 | {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c}, | ||
| 1347 | {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4}, | ||
| 1348 | {0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a0}, | ||
| 1349 | {0x00009e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020}, | ||
| 1350 | {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2}, | ||
| 1351 | {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e}, | ||
| 1352 | {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3379605e, 0x33795d5e}, | ||
| 1353 | {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1354 | {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c}, | ||
| 1355 | {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce}, | ||
| 1356 | {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021}, | ||
| 1357 | {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c782}, | ||
| 1358 | {0x00009e44, 0x02321e27, 0x02321e27, 0x02291e27, 0x02291e27}, | ||
| 1359 | {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012}, | ||
| 1360 | {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000}, | ||
| 1361 | {0x0000a204, 0x0131b7c0, 0x0131b7c4, 0x0131b7c4, 0x0131b7c0}, | ||
| 1362 | {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004}, | ||
| 1363 | {0x0000a22c, 0x01026a2f, 0x01026a27, 0x01026a2f, 0x01026a2f}, | ||
| 1364 | {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b}, | ||
| 1365 | {0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff}, | ||
| 1366 | {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018}, | ||
| 1367 | {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, | ||
| 1368 | {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, | ||
| 1369 | {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002}, | ||
| 1370 | {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e}, | ||
| 1371 | {0x0000a260, 0x0a021501, 0x0a021501, 0x3a021501, 0x3a021501}, | ||
| 1372 | {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, | ||
| 1373 | {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b}, | ||
| 1374 | {0x0000a284, 0x00000000, 0x00000000, 0x00000150, 0x00000150}, | ||
| 1375 | {0x0000a288, 0x00000110, 0x00000110, 0x00100110, 0x00100110}, | ||
| 1376 | {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222}, | ||
| 1377 | {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18}, | ||
| 1378 | {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982}, | ||
| 1379 | {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b}, | ||
| 1380 | {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1381 | {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, | ||
| 1382 | {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x00100000}, | ||
| 1383 | {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1384 | {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, | ||
| 1385 | {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce}, | ||
| 1386 | {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550}, | ||
| 1387 | }; | ||
| 1388 | |||
| 1389 | static const u32 ar9480_modes_fast_clock_1p0[][3] = { | ||
| 1390 | /* Addr 5G_HT20 5G_HT40 */ | ||
| 1391 | {0x00001030, 0x00000268, 0x000004d0}, | ||
| 1392 | {0x00001070, 0x0000018c, 0x00000318}, | ||
| 1393 | {0x000010b0, 0x00000fd0, 0x00001fa0}, | ||
| 1394 | {0x00008014, 0x044c044c, 0x08980898}, | ||
| 1395 | {0x0000801c, 0x148ec02b, 0x148ec057}, | ||
| 1396 | {0x00008318, 0x000044c0, 0x00008980}, | ||
| 1397 | {0x00009e00, 0x0372131c, 0x0372131c}, | ||
| 1398 | {0x0000a230, 0x0000400b, 0x00004016}, | ||
| 1399 | {0x0000a254, 0x00000898, 0x00001130}, | ||
| 1400 | }; | ||
| 1401 | |||
| 1402 | static const u32 ar9480_modes_low_ob_db_tx_gain_table_1p0[][5] = { | ||
| 1403 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 1404 | {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, | ||
| 1405 | {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, | ||
| 1406 | {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, | ||
| 1407 | {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, | ||
| 1408 | {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, | ||
| 1409 | {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1410 | {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002}, | ||
| 1411 | {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004}, | ||
| 1412 | {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200}, | ||
| 1413 | {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202}, | ||
| 1414 | {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400}, | ||
| 1415 | {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402}, | ||
| 1416 | {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404}, | ||
| 1417 | {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603}, | ||
| 1418 | {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02}, | ||
| 1419 | {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04}, | ||
| 1420 | {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20}, | ||
| 1421 | {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20}, | ||
| 1422 | {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22}, | ||
| 1423 | {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24}, | ||
| 1424 | {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640}, | ||
| 1425 | {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660}, | ||
| 1426 | {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861}, | ||
| 1427 | {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81}, | ||
| 1428 | {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83}, | ||
| 1429 | {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84}, | ||
| 1430 | {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3}, | ||
| 1431 | {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5}, | ||
| 1432 | {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9}, | ||
| 1433 | {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb}, | ||
| 1434 | {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, | ||
| 1435 | {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, | ||
| 1436 | {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, | ||
| 1437 | {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, | ||
| 1438 | {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, | ||
| 1439 | {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, | ||
| 1440 | {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, | ||
| 1441 | {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1442 | {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1443 | {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1444 | {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1445 | {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1446 | {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000}, | ||
| 1447 | {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501}, | ||
| 1448 | {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501}, | ||
| 1449 | {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03}, | ||
| 1450 | {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04}, | ||
| 1451 | {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04}, | ||
| 1452 | {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005}, | ||
| 1453 | {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, | ||
| 1454 | {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, | ||
| 1455 | {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, | ||
| 1456 | {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, | ||
| 1457 | {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, | ||
| 1458 | {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, | ||
| 1459 | {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, | ||
| 1460 | {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, | ||
| 1461 | {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4}, | ||
| 1462 | {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060}, | ||
| 1463 | {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4}, | ||
| 1464 | {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000}, | ||
| 1465 | }; | ||
| 1466 | |||
| 1467 | static const u32 ar9480_1p0_soc_postamble[][5] = { | ||
| 1468 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 1469 | {0x00007010, 0x00002233, 0x00002233, 0x00002233, 0x00002233}, | ||
| 1470 | }; | ||
| 1471 | |||
| 1472 | static const u32 ar9480_common_mixed_rx_gain_table_1p0[][2] = { | ||
| 1473 | /* Addr allmodes */ | ||
| 1474 | {0x0000a000, 0x00010000}, | ||
| 1475 | {0x0000a004, 0x00030002}, | ||
| 1476 | {0x0000a008, 0x00050004}, | ||
| 1477 | {0x0000a00c, 0x00810080}, | ||
| 1478 | {0x0000a010, 0x00830082}, | ||
| 1479 | {0x0000a014, 0x01810180}, | ||
| 1480 | {0x0000a018, 0x01830182}, | ||
| 1481 | {0x0000a01c, 0x01850184}, | ||
| 1482 | {0x0000a020, 0x01890188}, | ||
| 1483 | {0x0000a024, 0x018b018a}, | ||
| 1484 | {0x0000a028, 0x018d018c}, | ||
| 1485 | {0x0000a02c, 0x03820190}, | ||
| 1486 | {0x0000a030, 0x03840383}, | ||
| 1487 | {0x0000a034, 0x03880385}, | ||
| 1488 | {0x0000a038, 0x038a0389}, | ||
| 1489 | {0x0000a03c, 0x038c038b}, | ||
| 1490 | {0x0000a040, 0x0390038d}, | ||
| 1491 | {0x0000a044, 0x03920391}, | ||
| 1492 | {0x0000a048, 0x03940393}, | ||
| 1493 | {0x0000a04c, 0x03960395}, | ||
| 1494 | {0x0000a050, 0x00000000}, | ||
| 1495 | {0x0000a054, 0x00000000}, | ||
| 1496 | {0x0000a058, 0x00000000}, | ||
| 1497 | {0x0000a05c, 0x00000000}, | ||
| 1498 | {0x0000a060, 0x00000000}, | ||
| 1499 | {0x0000a064, 0x00000000}, | ||
| 1500 | {0x0000a068, 0x00000000}, | ||
| 1501 | {0x0000a06c, 0x00000000}, | ||
| 1502 | {0x0000a070, 0x00000000}, | ||
| 1503 | {0x0000a074, 0x00000000}, | ||
| 1504 | {0x0000a078, 0x00000000}, | ||
| 1505 | {0x0000a07c, 0x00000000}, | ||
| 1506 | {0x0000a080, 0x29292929}, | ||
| 1507 | {0x0000a084, 0x29292929}, | ||
| 1508 | {0x0000a088, 0x29292929}, | ||
| 1509 | {0x0000a08c, 0x29292929}, | ||
| 1510 | {0x0000a090, 0x22292929}, | ||
| 1511 | {0x0000a094, 0x1d1d2222}, | ||
| 1512 | {0x0000a098, 0x0c111117}, | ||
| 1513 | {0x0000a09c, 0x00030303}, | ||
| 1514 | {0x0000a0a0, 0x00000000}, | ||
| 1515 | {0x0000a0a4, 0x00000000}, | ||
| 1516 | {0x0000a0a8, 0x00000000}, | ||
| 1517 | {0x0000a0ac, 0x00000000}, | ||
| 1518 | {0x0000a0b0, 0x00000000}, | ||
| 1519 | {0x0000a0b4, 0x00000000}, | ||
| 1520 | {0x0000a0b8, 0x00000000}, | ||
| 1521 | {0x0000a0bc, 0x00000000}, | ||
| 1522 | {0x0000a0c0, 0x001f0000}, | ||
| 1523 | {0x0000a0c4, 0x01000101}, | ||
| 1524 | {0x0000a0c8, 0x011e011f}, | ||
| 1525 | {0x0000a0cc, 0x011c011d}, | ||
| 1526 | {0x0000a0d0, 0x02030204}, | ||
| 1527 | {0x0000a0d4, 0x02010202}, | ||
| 1528 | {0x0000a0d8, 0x021f0200}, | ||
| 1529 | {0x0000a0dc, 0x0302021e}, | ||
| 1530 | {0x0000a0e0, 0x03000301}, | ||
| 1531 | {0x0000a0e4, 0x031e031f}, | ||
| 1532 | {0x0000a0e8, 0x0402031d}, | ||
| 1533 | {0x0000a0ec, 0x04000401}, | ||
| 1534 | {0x0000a0f0, 0x041e041f}, | ||
| 1535 | {0x0000a0f4, 0x0502041d}, | ||
| 1536 | {0x0000a0f8, 0x05000501}, | ||
| 1537 | {0x0000a0fc, 0x051e051f}, | ||
| 1538 | {0x0000a100, 0x06010602}, | ||
| 1539 | {0x0000a104, 0x061f0600}, | ||
| 1540 | {0x0000a108, 0x061d061e}, | ||
| 1541 | {0x0000a10c, 0x07020703}, | ||
| 1542 | {0x0000a110, 0x07000701}, | ||
| 1543 | {0x0000a114, 0x00000000}, | ||
| 1544 | {0x0000a118, 0x00000000}, | ||
| 1545 | {0x0000a11c, 0x00000000}, | ||
| 1546 | {0x0000a120, 0x00000000}, | ||
| 1547 | {0x0000a124, 0x00000000}, | ||
| 1548 | {0x0000a128, 0x00000000}, | ||
| 1549 | {0x0000a12c, 0x00000000}, | ||
| 1550 | {0x0000a130, 0x00000000}, | ||
| 1551 | {0x0000a134, 0x00000000}, | ||
| 1552 | {0x0000a138, 0x00000000}, | ||
| 1553 | {0x0000a13c, 0x00000000}, | ||
| 1554 | {0x0000a140, 0x001f0000}, | ||
| 1555 | {0x0000a144, 0x01000101}, | ||
| 1556 | {0x0000a148, 0x011e011f}, | ||
| 1557 | {0x0000a14c, 0x011c011d}, | ||
| 1558 | {0x0000a150, 0x02030204}, | ||
| 1559 | {0x0000a154, 0x02010202}, | ||
| 1560 | {0x0000a158, 0x021f0200}, | ||
| 1561 | {0x0000a15c, 0x0302021e}, | ||
| 1562 | {0x0000a160, 0x03000301}, | ||
| 1563 | {0x0000a164, 0x031e031f}, | ||
| 1564 | {0x0000a168, 0x0402031d}, | ||
| 1565 | {0x0000a16c, 0x04000401}, | ||
| 1566 | {0x0000a170, 0x041e041f}, | ||
| 1567 | {0x0000a174, 0x0502041d}, | ||
| 1568 | {0x0000a178, 0x05000501}, | ||
| 1569 | {0x0000a17c, 0x051e051f}, | ||
| 1570 | {0x0000a180, 0x06010602}, | ||
| 1571 | {0x0000a184, 0x061f0600}, | ||
| 1572 | {0x0000a188, 0x061d061e}, | ||
| 1573 | {0x0000a18c, 0x07020703}, | ||
| 1574 | {0x0000a190, 0x07000701}, | ||
| 1575 | {0x0000a194, 0x00000000}, | ||
| 1576 | {0x0000a198, 0x00000000}, | ||
| 1577 | {0x0000a19c, 0x00000000}, | ||
| 1578 | {0x0000a1a0, 0x00000000}, | ||
| 1579 | {0x0000a1a4, 0x00000000}, | ||
| 1580 | {0x0000a1a8, 0x00000000}, | ||
| 1581 | {0x0000a1ac, 0x00000000}, | ||
| 1582 | {0x0000a1b0, 0x00000000}, | ||
| 1583 | {0x0000a1b4, 0x00000000}, | ||
| 1584 | {0x0000a1b8, 0x00000000}, | ||
| 1585 | {0x0000a1bc, 0x00000000}, | ||
| 1586 | {0x0000a1c0, 0x00000000}, | ||
| 1587 | {0x0000a1c4, 0x00000000}, | ||
| 1588 | {0x0000a1c8, 0x00000000}, | ||
| 1589 | {0x0000a1cc, 0x00000000}, | ||
| 1590 | {0x0000a1d0, 0x00000000}, | ||
| 1591 | {0x0000a1d4, 0x00000000}, | ||
| 1592 | {0x0000a1d8, 0x00000000}, | ||
| 1593 | {0x0000a1dc, 0x00000000}, | ||
| 1594 | {0x0000a1e0, 0x00000000}, | ||
| 1595 | {0x0000a1e4, 0x00000000}, | ||
| 1596 | {0x0000a1e8, 0x00000000}, | ||
| 1597 | {0x0000a1ec, 0x00000000}, | ||
| 1598 | {0x0000a1f0, 0x00000396}, | ||
| 1599 | {0x0000a1f4, 0x00000396}, | ||
| 1600 | {0x0000a1f8, 0x00000396}, | ||
| 1601 | {0x0000a1fc, 0x00000196}, | ||
| 1602 | {0x0000b000, 0x00010000}, | ||
| 1603 | {0x0000b004, 0x00030002}, | ||
| 1604 | {0x0000b008, 0x00050004}, | ||
| 1605 | {0x0000b00c, 0x00810080}, | ||
| 1606 | {0x0000b010, 0x00830082}, | ||
| 1607 | {0x0000b014, 0x01810180}, | ||
| 1608 | {0x0000b018, 0x01830182}, | ||
| 1609 | {0x0000b01c, 0x01850184}, | ||
| 1610 | {0x0000b020, 0x02810280}, | ||
| 1611 | {0x0000b024, 0x02830282}, | ||
| 1612 | {0x0000b028, 0x02850284}, | ||
| 1613 | {0x0000b02c, 0x02890288}, | ||
| 1614 | {0x0000b030, 0x028b028a}, | ||
| 1615 | {0x0000b034, 0x0388028c}, | ||
| 1616 | {0x0000b038, 0x038a0389}, | ||
| 1617 | {0x0000b03c, 0x038c038b}, | ||
| 1618 | {0x0000b040, 0x0390038d}, | ||
| 1619 | {0x0000b044, 0x03920391}, | ||
| 1620 | {0x0000b048, 0x03940393}, | ||
| 1621 | {0x0000b04c, 0x03960395}, | ||
| 1622 | {0x0000b050, 0x00000000}, | ||
| 1623 | {0x0000b054, 0x00000000}, | ||
| 1624 | {0x0000b058, 0x00000000}, | ||
| 1625 | {0x0000b05c, 0x00000000}, | ||
| 1626 | {0x0000b060, 0x00000000}, | ||
| 1627 | {0x0000b064, 0x00000000}, | ||
| 1628 | {0x0000b068, 0x00000000}, | ||
| 1629 | {0x0000b06c, 0x00000000}, | ||
| 1630 | {0x0000b070, 0x00000000}, | ||
| 1631 | {0x0000b074, 0x00000000}, | ||
| 1632 | {0x0000b078, 0x00000000}, | ||
| 1633 | {0x0000b07c, 0x00000000}, | ||
| 1634 | {0x0000b080, 0x2a2d2f32}, | ||
| 1635 | {0x0000b084, 0x21232328}, | ||
| 1636 | {0x0000b088, 0x19191c1e}, | ||
| 1637 | {0x0000b08c, 0x12141417}, | ||
| 1638 | {0x0000b090, 0x07070e0e}, | ||
| 1639 | {0x0000b094, 0x03030305}, | ||
| 1640 | {0x0000b098, 0x00000003}, | ||
| 1641 | {0x0000b09c, 0x00000000}, | ||
| 1642 | {0x0000b0a0, 0x00000000}, | ||
| 1643 | {0x0000b0a4, 0x00000000}, | ||
| 1644 | {0x0000b0a8, 0x00000000}, | ||
| 1645 | {0x0000b0ac, 0x00000000}, | ||
| 1646 | {0x0000b0b0, 0x00000000}, | ||
| 1647 | {0x0000b0b4, 0x00000000}, | ||
| 1648 | {0x0000b0b8, 0x00000000}, | ||
| 1649 | {0x0000b0bc, 0x00000000}, | ||
| 1650 | {0x0000b0c0, 0x003f0020}, | ||
| 1651 | {0x0000b0c4, 0x00400041}, | ||
| 1652 | {0x0000b0c8, 0x0140005f}, | ||
| 1653 | {0x0000b0cc, 0x0160015f}, | ||
| 1654 | {0x0000b0d0, 0x017e017f}, | ||
| 1655 | {0x0000b0d4, 0x02410242}, | ||
| 1656 | {0x0000b0d8, 0x025f0240}, | ||
| 1657 | {0x0000b0dc, 0x027f0260}, | ||
| 1658 | {0x0000b0e0, 0x0341027e}, | ||
| 1659 | {0x0000b0e4, 0x035f0340}, | ||
| 1660 | {0x0000b0e8, 0x037f0360}, | ||
| 1661 | {0x0000b0ec, 0x04400441}, | ||
| 1662 | {0x0000b0f0, 0x0460045f}, | ||
| 1663 | {0x0000b0f4, 0x0541047f}, | ||
| 1664 | {0x0000b0f8, 0x055f0540}, | ||
| 1665 | {0x0000b0fc, 0x057f0560}, | ||
| 1666 | {0x0000b100, 0x06400641}, | ||
| 1667 | {0x0000b104, 0x0660065f}, | ||
| 1668 | {0x0000b108, 0x067e067f}, | ||
| 1669 | {0x0000b10c, 0x07410742}, | ||
| 1670 | {0x0000b110, 0x075f0740}, | ||
| 1671 | {0x0000b114, 0x077f0760}, | ||
| 1672 | {0x0000b118, 0x07800781}, | ||
| 1673 | {0x0000b11c, 0x07a0079f}, | ||
| 1674 | {0x0000b120, 0x07c107bf}, | ||
| 1675 | {0x0000b124, 0x000007c0}, | ||
| 1676 | {0x0000b128, 0x00000000}, | ||
| 1677 | {0x0000b12c, 0x00000000}, | ||
| 1678 | {0x0000b130, 0x00000000}, | ||
| 1679 | {0x0000b134, 0x00000000}, | ||
| 1680 | {0x0000b138, 0x00000000}, | ||
| 1681 | {0x0000b13c, 0x00000000}, | ||
| 1682 | {0x0000b140, 0x003f0020}, | ||
| 1683 | {0x0000b144, 0x00400041}, | ||
| 1684 | {0x0000b148, 0x0140005f}, | ||
| 1685 | {0x0000b14c, 0x0160015f}, | ||
| 1686 | {0x0000b150, 0x017e017f}, | ||
| 1687 | {0x0000b154, 0x02410242}, | ||
| 1688 | {0x0000b158, 0x025f0240}, | ||
| 1689 | {0x0000b15c, 0x027f0260}, | ||
| 1690 | {0x0000b160, 0x0341027e}, | ||
| 1691 | {0x0000b164, 0x035f0340}, | ||
| 1692 | {0x0000b168, 0x037f0360}, | ||
| 1693 | {0x0000b16c, 0x04400441}, | ||
| 1694 | {0x0000b170, 0x0460045f}, | ||
| 1695 | {0x0000b174, 0x0541047f}, | ||
| 1696 | {0x0000b178, 0x055f0540}, | ||
| 1697 | {0x0000b17c, 0x057f0560}, | ||
| 1698 | {0x0000b180, 0x06400641}, | ||
| 1699 | {0x0000b184, 0x0660065f}, | ||
| 1700 | {0x0000b188, 0x067e067f}, | ||
| 1701 | {0x0000b18c, 0x07410742}, | ||
| 1702 | {0x0000b190, 0x075f0740}, | ||
| 1703 | {0x0000b194, 0x077f0760}, | ||
| 1704 | {0x0000b198, 0x07800781}, | ||
| 1705 | {0x0000b19c, 0x07a0079f}, | ||
| 1706 | {0x0000b1a0, 0x07c107bf}, | ||
| 1707 | {0x0000b1a4, 0x000007c0}, | ||
| 1708 | {0x0000b1a8, 0x00000000}, | ||
| 1709 | {0x0000b1ac, 0x00000000}, | ||
| 1710 | {0x0000b1b0, 0x00000000}, | ||
| 1711 | {0x0000b1b4, 0x00000000}, | ||
| 1712 | {0x0000b1b8, 0x00000000}, | ||
| 1713 | {0x0000b1bc, 0x00000000}, | ||
| 1714 | {0x0000b1c0, 0x00000000}, | ||
| 1715 | {0x0000b1c4, 0x00000000}, | ||
| 1716 | {0x0000b1c8, 0x00000000}, | ||
| 1717 | {0x0000b1cc, 0x00000000}, | ||
| 1718 | {0x0000b1d0, 0x00000000}, | ||
| 1719 | {0x0000b1d4, 0x00000000}, | ||
| 1720 | {0x0000b1d8, 0x00000000}, | ||
| 1721 | {0x0000b1dc, 0x00000000}, | ||
| 1722 | {0x0000b1e0, 0x00000000}, | ||
| 1723 | {0x0000b1e4, 0x00000000}, | ||
| 1724 | {0x0000b1e8, 0x00000000}, | ||
| 1725 | {0x0000b1ec, 0x00000000}, | ||
| 1726 | {0x0000b1f0, 0x00000396}, | ||
| 1727 | {0x0000b1f4, 0x00000396}, | ||
| 1728 | {0x0000b1f8, 0x00000396}, | ||
| 1729 | {0x0000b1fc, 0x00000196}, | ||
| 1730 | }; | ||
| 1731 | |||
| 1732 | static const u32 ar9480_pcie_phy_clkreq_disable_L1_1p0[][2] = { | ||
| 1733 | /* Addr allmodes */ | ||
| 1734 | {0x00018c00, 0x10013e5e}, | ||
| 1735 | {0x00018c04, 0x000801d8}, | ||
| 1736 | {0x00018c08, 0x0000580c}, | ||
| 1737 | }; | ||
| 1738 | |||
| 1739 | static const u32 ar9480_1p0_baseband_core_emulation[][2] = { | ||
| 1740 | /* Addr allmodes */ | ||
| 1741 | {0x00009800, 0xafa68e30}, | ||
| 1742 | {0x00009884, 0x00002842}, | ||
| 1743 | {0x00009c04, 0xff55ff55}, | ||
| 1744 | {0x00009c08, 0x0320ff55}, | ||
| 1745 | {0x00009e50, 0x00000000}, | ||
| 1746 | {0x00009fcc, 0x00000014}, | ||
| 1747 | {0x0000a344, 0x00000010}, | ||
| 1748 | {0x0000a398, 0x00000000}, | ||
| 1749 | {0x0000a39c, 0x71733d01}, | ||
| 1750 | {0x0000a3a0, 0xd0ad5c12}, | ||
| 1751 | {0x0000a3c0, 0x22222220}, | ||
| 1752 | {0x0000a3c4, 0x22222222}, | ||
| 1753 | {0x0000a404, 0x00418a11}, | ||
| 1754 | {0x0000a418, 0x050001ce}, | ||
| 1755 | {0x0000a438, 0x00001800}, | ||
| 1756 | {0x0000a458, 0x01444452}, | ||
| 1757 | {0x0000a644, 0x3fad9d74}, | ||
| 1758 | {0x0000a690, 0x00000038}, | ||
| 1759 | }; | ||
| 1760 | |||
| 1761 | static const u32 ar9480_1p0_radio_core[][2] = { | ||
| 1762 | /* Addr allmodes */ | ||
| 1763 | {0x00016000, 0x36db6db6}, | ||
| 1764 | {0x00016004, 0x6db6db40}, | ||
| 1765 | {0x00016008, 0x73f00000}, | ||
| 1766 | {0x0001600c, 0x00000000}, | ||
| 1767 | {0x00016010, 0x6d820001}, | ||
| 1768 | {0x00016040, 0x7f80fff8}, | ||
| 1769 | {0x0001604c, 0x2699e04f}, | ||
| 1770 | {0x00016050, 0x6db6db6c}, | ||
| 1771 | {0x00016054, 0x6db60000}, | ||
| 1772 | {0x00016058, 0x6c200000}, | ||
| 1773 | {0x00016080, 0x00040000}, | ||
| 1774 | {0x00016084, 0x9a68048c}, | ||
| 1775 | {0x00016088, 0x54214514}, | ||
| 1776 | {0x0001608c, 0x12030409}, | ||
| 1777 | {0x00016090, 0x24926490}, | ||
| 1778 | {0x00016098, 0xd2888888}, | ||
| 1779 | {0x000160a0, 0x0a108ffe}, | ||
| 1780 | {0x000160a4, 0x812fc490}, | ||
| 1781 | {0x000160a8, 0x423c8000}, | ||
| 1782 | {0x000160b4, 0x92000000}, | ||
| 1783 | {0x000160b8, 0x0285dddc}, | ||
| 1784 | {0x000160bc, 0x02908888}, | ||
| 1785 | {0x000160c0, 0x00adb6d0}, | ||
| 1786 | {0x000160c4, 0x6db6db60}, | ||
| 1787 | {0x000160c8, 0x6db6db6c}, | ||
| 1788 | {0x000160cc, 0x0de6c1b0}, | ||
| 1789 | {0x00016100, 0x3fffbe04}, | ||
| 1790 | {0x00016104, 0xfff80000}, | ||
| 1791 | {0x00016108, 0x00200400}, | ||
| 1792 | {0x00016110, 0x00000000}, | ||
| 1793 | {0x00016144, 0x02084080}, | ||
| 1794 | {0x00016148, 0x000080c0}, | ||
| 1795 | {0x00016280, 0x050a0001}, | ||
| 1796 | {0x00016284, 0x3d841400}, | ||
| 1797 | {0x00016288, 0x00000000}, | ||
| 1798 | {0x0001628c, 0xe3000000}, | ||
| 1799 | {0x00016290, 0xa1005080}, | ||
| 1800 | {0x00016294, 0x00000020}, | ||
| 1801 | {0x00016298, 0x50a02900}, | ||
| 1802 | {0x00016340, 0x121e4276}, | ||
| 1803 | {0x00016344, 0x00300000}, | ||
| 1804 | {0x00016400, 0x36db6db6}, | ||
| 1805 | {0x00016404, 0x6db6db40}, | ||
| 1806 | {0x00016408, 0x73f00000}, | ||
| 1807 | {0x0001640c, 0x00000000}, | ||
| 1808 | {0x00016410, 0x6c800001}, | ||
| 1809 | {0x00016440, 0x7f80fff8}, | ||
| 1810 | {0x0001644c, 0x4699e04f}, | ||
| 1811 | {0x00016450, 0x6db6db6c}, | ||
| 1812 | {0x00016454, 0x6db60000}, | ||
| 1813 | {0x00016500, 0x3fffbe04}, | ||
| 1814 | {0x00016504, 0xfff80000}, | ||
| 1815 | {0x00016508, 0x00200400}, | ||
| 1816 | {0x00016510, 0x00000000}, | ||
| 1817 | {0x00016544, 0x02084080}, | ||
| 1818 | {0x00016548, 0x000080c0}, | ||
| 1819 | }; | ||
| 1820 | |||
| 1821 | static const u32 ar9480_1p0_soc_preamble[][2] = { | ||
| 1822 | /* Addr allmodes */ | ||
| 1823 | {0x00007020, 0x00000000}, | ||
| 1824 | {0x00007034, 0x00000002}, | ||
| 1825 | {0x00007038, 0x000004c2}, | ||
| 1826 | }; | ||
| 1827 | |||
| 1828 | static const u32 ar9480_1p0_sys2ant[][2] = { | ||
| 1829 | /* Addr allmodes */ | ||
| 1830 | {0x00063120, 0x00801980}, | ||
| 1831 | }; | ||
| 1832 | |||
| 1833 | #endif /* INITVALS_9480_1P0_H */ | ||
diff --git a/drivers/net/wireless/ath/ath9k/ar9480_2p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9480_2p0_initvals.h new file mode 100644 index 000000000000..d54163d8d69f --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/ar9480_2p0_initvals.h | |||
| @@ -0,0 +1,1928 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2010 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef INITVALS_9480_2P0_H | ||
| 18 | #define INITVALS_9480_2P0_H | ||
| 19 | |||
| 20 | /* AR9480 2.0 */ | ||
| 21 | |||
| 22 | static const u32 ar9480_modes_fast_clock_2p0[][3] = { | ||
| 23 | /* Addr 5G_HT20 5G_HT40 */ | ||
| 24 | {0x00001030, 0x00000268, 0x000004d0}, | ||
| 25 | {0x00001070, 0x0000018c, 0x00000318}, | ||
| 26 | {0x000010b0, 0x00000fd0, 0x00001fa0}, | ||
| 27 | {0x00008014, 0x044c044c, 0x08980898}, | ||
| 28 | {0x0000801c, 0x148ec02b, 0x148ec057}, | ||
| 29 | {0x00008318, 0x000044c0, 0x00008980}, | ||
| 30 | {0x00009e00, 0x0372131c, 0x0372131c}, | ||
| 31 | {0x0000a230, 0x0000400b, 0x00004016}, | ||
| 32 | {0x0000a254, 0x00000898, 0x00001130}, | ||
| 33 | }; | ||
| 34 | |||
| 35 | static const u32 ar9480_pciephy_clkreq_enable_L1_2p0[][2] = { | ||
| 36 | /* Addr allmodes */ | ||
| 37 | {0x00018c00, 0x18253ede}, | ||
| 38 | {0x00018c04, 0x000801d8}, | ||
| 39 | {0x00018c08, 0x0003580c}, | ||
| 40 | }; | ||
| 41 | |||
| 42 | static const u32 ar9480_2p0_baseband_postamble[][5] = { | ||
| 43 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 44 | {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011}, | ||
| 45 | {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e}, | ||
| 46 | {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, | ||
| 47 | {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881}, | ||
| 48 | {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, | ||
| 49 | {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c}, | ||
| 50 | {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4}, | ||
| 51 | {0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a0}, | ||
| 52 | {0x00009e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020}, | ||
| 53 | {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2}, | ||
| 54 | {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e}, | ||
| 55 | {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3039605e, 0x33795d5e}, | ||
| 56 | {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 57 | {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c}, | ||
| 58 | {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce}, | ||
| 59 | {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021}, | ||
| 60 | {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c782}, | ||
| 61 | {0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27}, | ||
| 62 | {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012}, | ||
| 63 | {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000}, | ||
| 64 | {0x0000a204, 0x013187c0, 0x013187c4, 0x013187c4, 0x013187c0}, | ||
| 65 | {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004}, | ||
| 66 | {0x0000a22c, 0x01026a2f, 0x01026a27, 0x01026a2f, 0x01026a2f}, | ||
| 67 | {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b}, | ||
| 68 | {0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff}, | ||
| 69 | {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018}, | ||
| 70 | {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, | ||
| 71 | {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, | ||
| 72 | {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002}, | ||
| 73 | {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e}, | ||
| 74 | {0x0000a260, 0x0a021501, 0x0a021501, 0x3a021501, 0x3a021501}, | ||
| 75 | {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, | ||
| 76 | {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b}, | ||
| 77 | {0x0000a284, 0x00000000, 0x00000000, 0x00000150, 0x00000150}, | ||
| 78 | {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110}, | ||
| 79 | {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222}, | ||
| 80 | {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18}, | ||
| 81 | {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982}, | ||
| 82 | {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b}, | ||
| 83 | {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 84 | {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, | ||
| 85 | {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x00100000}, | ||
| 86 | {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 87 | {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, | ||
| 88 | {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce}, | ||
| 89 | {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550}, | ||
| 90 | }; | ||
| 91 | |||
| 92 | static const u32 ar9480_2p0_mac_core_emulation[][2] = { | ||
| 93 | /* Addr allmodes */ | ||
| 94 | {0x00000030, 0x000e0085}, | ||
| 95 | {0x00000044, 0x00000008}, | ||
| 96 | {0x0000805c, 0xffffc7ff}, | ||
| 97 | {0x00008344, 0xaa4a105b}, | ||
| 98 | }; | ||
| 99 | |||
| 100 | static const u32 ar9480_common_rx_gain_table_2p0[][2] = { | ||
| 101 | /* Addr allmodes */ | ||
| 102 | {0x0000a000, 0x00010000}, | ||
| 103 | {0x0000a004, 0x00030002}, | ||
| 104 | {0x0000a008, 0x00050004}, | ||
| 105 | {0x0000a00c, 0x00810080}, | ||
| 106 | {0x0000a010, 0x00830082}, | ||
| 107 | {0x0000a014, 0x01810180}, | ||
| 108 | {0x0000a018, 0x01830182}, | ||
| 109 | {0x0000a01c, 0x01850184}, | ||
| 110 | {0x0000a020, 0x01890188}, | ||
| 111 | {0x0000a024, 0x018b018a}, | ||
| 112 | {0x0000a028, 0x018d018c}, | ||
| 113 | {0x0000a02c, 0x01910190}, | ||
| 114 | {0x0000a030, 0x01930192}, | ||
| 115 | {0x0000a034, 0x01950194}, | ||
| 116 | {0x0000a038, 0x038a0196}, | ||
| 117 | {0x0000a03c, 0x038c038b}, | ||
| 118 | {0x0000a040, 0x0390038d}, | ||
| 119 | {0x0000a044, 0x03920391}, | ||
| 120 | {0x0000a048, 0x03940393}, | ||
| 121 | {0x0000a04c, 0x03960395}, | ||
| 122 | {0x0000a050, 0x00000000}, | ||
| 123 | {0x0000a054, 0x00000000}, | ||
| 124 | {0x0000a058, 0x00000000}, | ||
| 125 | {0x0000a05c, 0x00000000}, | ||
| 126 | {0x0000a060, 0x00000000}, | ||
| 127 | {0x0000a064, 0x00000000}, | ||
| 128 | {0x0000a068, 0x00000000}, | ||
| 129 | {0x0000a06c, 0x00000000}, | ||
| 130 | {0x0000a070, 0x00000000}, | ||
| 131 | {0x0000a074, 0x00000000}, | ||
| 132 | {0x0000a078, 0x00000000}, | ||
| 133 | {0x0000a07c, 0x00000000}, | ||
| 134 | {0x0000a080, 0x22222229}, | ||
| 135 | {0x0000a084, 0x1d1d1d1d}, | ||
| 136 | {0x0000a088, 0x1d1d1d1d}, | ||
| 137 | {0x0000a08c, 0x1d1d1d1d}, | ||
| 138 | {0x0000a090, 0x171d1d1d}, | ||
| 139 | {0x0000a094, 0x11111717}, | ||
| 140 | {0x0000a098, 0x00030311}, | ||
| 141 | {0x0000a09c, 0x00000000}, | ||
| 142 | {0x0000a0a0, 0x00000000}, | ||
| 143 | {0x0000a0a4, 0x00000000}, | ||
| 144 | {0x0000a0a8, 0x00000000}, | ||
| 145 | {0x0000a0ac, 0x00000000}, | ||
| 146 | {0x0000a0b0, 0x00000000}, | ||
| 147 | {0x0000a0b4, 0x00000000}, | ||
| 148 | {0x0000a0b8, 0x00000000}, | ||
| 149 | {0x0000a0bc, 0x00000000}, | ||
| 150 | {0x0000a0c0, 0x001f0000}, | ||
| 151 | {0x0000a0c4, 0x01000101}, | ||
| 152 | {0x0000a0c8, 0x011e011f}, | ||
| 153 | {0x0000a0cc, 0x011c011d}, | ||
| 154 | {0x0000a0d0, 0x02030204}, | ||
| 155 | {0x0000a0d4, 0x02010202}, | ||
| 156 | {0x0000a0d8, 0x021f0200}, | ||
| 157 | {0x0000a0dc, 0x0302021e}, | ||
| 158 | {0x0000a0e0, 0x03000301}, | ||
| 159 | {0x0000a0e4, 0x031e031f}, | ||
| 160 | {0x0000a0e8, 0x0402031d}, | ||
| 161 | {0x0000a0ec, 0x04000401}, | ||
| 162 | {0x0000a0f0, 0x041e041f}, | ||
| 163 | {0x0000a0f4, 0x0502041d}, | ||
| 164 | {0x0000a0f8, 0x05000501}, | ||
| 165 | {0x0000a0fc, 0x051e051f}, | ||
| 166 | {0x0000a100, 0x06010602}, | ||
| 167 | {0x0000a104, 0x061f0600}, | ||
| 168 | {0x0000a108, 0x061d061e}, | ||
| 169 | {0x0000a10c, 0x07020703}, | ||
| 170 | {0x0000a110, 0x07000701}, | ||
| 171 | {0x0000a114, 0x00000000}, | ||
| 172 | {0x0000a118, 0x00000000}, | ||
| 173 | {0x0000a11c, 0x00000000}, | ||
| 174 | {0x0000a120, 0x00000000}, | ||
| 175 | {0x0000a124, 0x00000000}, | ||
| 176 | {0x0000a128, 0x00000000}, | ||
| 177 | {0x0000a12c, 0x00000000}, | ||
| 178 | {0x0000a130, 0x00000000}, | ||
| 179 | {0x0000a134, 0x00000000}, | ||
| 180 | {0x0000a138, 0x00000000}, | ||
| 181 | {0x0000a13c, 0x00000000}, | ||
| 182 | {0x0000a140, 0x001f0000}, | ||
| 183 | {0x0000a144, 0x01000101}, | ||
| 184 | {0x0000a148, 0x011e011f}, | ||
| 185 | {0x0000a14c, 0x011c011d}, | ||
| 186 | {0x0000a150, 0x02030204}, | ||
| 187 | {0x0000a154, 0x02010202}, | ||
| 188 | {0x0000a158, 0x021f0200}, | ||
| 189 | {0x0000a15c, 0x0302021e}, | ||
| 190 | {0x0000a160, 0x03000301}, | ||
| 191 | {0x0000a164, 0x031e031f}, | ||
| 192 | {0x0000a168, 0x0402031d}, | ||
| 193 | {0x0000a16c, 0x04000401}, | ||
| 194 | {0x0000a170, 0x041e041f}, | ||
| 195 | {0x0000a174, 0x0502041d}, | ||
| 196 | {0x0000a178, 0x05000501}, | ||
| 197 | {0x0000a17c, 0x051e051f}, | ||
| 198 | {0x0000a180, 0x06010602}, | ||
| 199 | {0x0000a184, 0x061f0600}, | ||
| 200 | {0x0000a188, 0x061d061e}, | ||
| 201 | {0x0000a18c, 0x07020703}, | ||
| 202 | {0x0000a190, 0x07000701}, | ||
| 203 | {0x0000a194, 0x00000000}, | ||
| 204 | {0x0000a198, 0x00000000}, | ||
| 205 | {0x0000a19c, 0x00000000}, | ||
| 206 | {0x0000a1a0, 0x00000000}, | ||
| 207 | {0x0000a1a4, 0x00000000}, | ||
| 208 | {0x0000a1a8, 0x00000000}, | ||
| 209 | {0x0000a1ac, 0x00000000}, | ||
| 210 | {0x0000a1b0, 0x00000000}, | ||
| 211 | {0x0000a1b4, 0x00000000}, | ||
| 212 | {0x0000a1b8, 0x00000000}, | ||
| 213 | {0x0000a1bc, 0x00000000}, | ||
| 214 | {0x0000a1c0, 0x00000000}, | ||
| 215 | {0x0000a1c4, 0x00000000}, | ||
| 216 | {0x0000a1c8, 0x00000000}, | ||
| 217 | {0x0000a1cc, 0x00000000}, | ||
| 218 | {0x0000a1d0, 0x00000000}, | ||
| 219 | {0x0000a1d4, 0x00000000}, | ||
| 220 | {0x0000a1d8, 0x00000000}, | ||
| 221 | {0x0000a1dc, 0x00000000}, | ||
| 222 | {0x0000a1e0, 0x00000000}, | ||
| 223 | {0x0000a1e4, 0x00000000}, | ||
| 224 | {0x0000a1e8, 0x00000000}, | ||
| 225 | {0x0000a1ec, 0x00000000}, | ||
| 226 | {0x0000a1f0, 0x00000396}, | ||
| 227 | {0x0000a1f4, 0x00000396}, | ||
| 228 | {0x0000a1f8, 0x00000396}, | ||
| 229 | {0x0000a1fc, 0x00000196}, | ||
| 230 | {0x0000b000, 0x00010000}, | ||
| 231 | {0x0000b004, 0x00030002}, | ||
| 232 | {0x0000b008, 0x00050004}, | ||
| 233 | {0x0000b00c, 0x00810080}, | ||
| 234 | {0x0000b010, 0x00830082}, | ||
| 235 | {0x0000b014, 0x01810180}, | ||
| 236 | {0x0000b018, 0x01830182}, | ||
| 237 | {0x0000b01c, 0x01850184}, | ||
| 238 | {0x0000b020, 0x02810280}, | ||
| 239 | {0x0000b024, 0x02830282}, | ||
| 240 | {0x0000b028, 0x02850284}, | ||
| 241 | {0x0000b02c, 0x02890288}, | ||
| 242 | {0x0000b030, 0x028b028a}, | ||
| 243 | {0x0000b034, 0x0388028c}, | ||
| 244 | {0x0000b038, 0x038a0389}, | ||
| 245 | {0x0000b03c, 0x038c038b}, | ||
| 246 | {0x0000b040, 0x0390038d}, | ||
| 247 | {0x0000b044, 0x03920391}, | ||
| 248 | {0x0000b048, 0x03940393}, | ||
| 249 | {0x0000b04c, 0x03960395}, | ||
| 250 | {0x0000b050, 0x00000000}, | ||
| 251 | {0x0000b054, 0x00000000}, | ||
| 252 | {0x0000b058, 0x00000000}, | ||
| 253 | {0x0000b05c, 0x00000000}, | ||
| 254 | {0x0000b060, 0x00000000}, | ||
| 255 | {0x0000b064, 0x00000000}, | ||
| 256 | {0x0000b068, 0x00000000}, | ||
| 257 | {0x0000b06c, 0x00000000}, | ||
| 258 | {0x0000b070, 0x00000000}, | ||
| 259 | {0x0000b074, 0x00000000}, | ||
| 260 | {0x0000b078, 0x00000000}, | ||
| 261 | {0x0000b07c, 0x00000000}, | ||
| 262 | {0x0000b080, 0x2a2d2f32}, | ||
| 263 | {0x0000b084, 0x21232328}, | ||
| 264 | {0x0000b088, 0x19191c1e}, | ||
| 265 | {0x0000b08c, 0x12141417}, | ||
| 266 | {0x0000b090, 0x07070e0e}, | ||
| 267 | {0x0000b094, 0x03030305}, | ||
| 268 | {0x0000b098, 0x00000003}, | ||
| 269 | {0x0000b09c, 0x00000000}, | ||
| 270 | {0x0000b0a0, 0x00000000}, | ||
| 271 | {0x0000b0a4, 0x00000000}, | ||
| 272 | {0x0000b0a8, 0x00000000}, | ||
| 273 | {0x0000b0ac, 0x00000000}, | ||
| 274 | {0x0000b0b0, 0x00000000}, | ||
| 275 | {0x0000b0b4, 0x00000000}, | ||
| 276 | {0x0000b0b8, 0x00000000}, | ||
| 277 | {0x0000b0bc, 0x00000000}, | ||
| 278 | {0x0000b0c0, 0x003f0020}, | ||
| 279 | {0x0000b0c4, 0x00400041}, | ||
| 280 | {0x0000b0c8, 0x0140005f}, | ||
| 281 | {0x0000b0cc, 0x0160015f}, | ||
| 282 | {0x0000b0d0, 0x017e017f}, | ||
| 283 | {0x0000b0d4, 0x02410242}, | ||
| 284 | {0x0000b0d8, 0x025f0240}, | ||
| 285 | {0x0000b0dc, 0x027f0260}, | ||
| 286 | {0x0000b0e0, 0x0341027e}, | ||
| 287 | {0x0000b0e4, 0x035f0340}, | ||
| 288 | {0x0000b0e8, 0x037f0360}, | ||
| 289 | {0x0000b0ec, 0x04400441}, | ||
| 290 | {0x0000b0f0, 0x0460045f}, | ||
| 291 | {0x0000b0f4, 0x0541047f}, | ||
| 292 | {0x0000b0f8, 0x055f0540}, | ||
| 293 | {0x0000b0fc, 0x057f0560}, | ||
| 294 | {0x0000b100, 0x06400641}, | ||
| 295 | {0x0000b104, 0x0660065f}, | ||
| 296 | {0x0000b108, 0x067e067f}, | ||
| 297 | {0x0000b10c, 0x07410742}, | ||
| 298 | {0x0000b110, 0x075f0740}, | ||
| 299 | {0x0000b114, 0x077f0760}, | ||
| 300 | {0x0000b118, 0x07800781}, | ||
| 301 | {0x0000b11c, 0x07a0079f}, | ||
| 302 | {0x0000b120, 0x07c107bf}, | ||
| 303 | {0x0000b124, 0x000007c0}, | ||
| 304 | {0x0000b128, 0x00000000}, | ||
| 305 | {0x0000b12c, 0x00000000}, | ||
| 306 | {0x0000b130, 0x00000000}, | ||
| 307 | {0x0000b134, 0x00000000}, | ||
| 308 | {0x0000b138, 0x00000000}, | ||
| 309 | {0x0000b13c, 0x00000000}, | ||
| 310 | {0x0000b140, 0x003f0020}, | ||
| 311 | {0x0000b144, 0x00400041}, | ||
| 312 | {0x0000b148, 0x0140005f}, | ||
| 313 | {0x0000b14c, 0x0160015f}, | ||
| 314 | {0x0000b150, 0x017e017f}, | ||
| 315 | {0x0000b154, 0x02410242}, | ||
| 316 | {0x0000b158, 0x025f0240}, | ||
| 317 | {0x0000b15c, 0x027f0260}, | ||
| 318 | {0x0000b160, 0x0341027e}, | ||
| 319 | {0x0000b164, 0x035f0340}, | ||
| 320 | {0x0000b168, 0x037f0360}, | ||
| 321 | {0x0000b16c, 0x04400441}, | ||
| 322 | {0x0000b170, 0x0460045f}, | ||
| 323 | {0x0000b174, 0x0541047f}, | ||
| 324 | {0x0000b178, 0x055f0540}, | ||
| 325 | {0x0000b17c, 0x057f0560}, | ||
| 326 | {0x0000b180, 0x06400641}, | ||
| 327 | {0x0000b184, 0x0660065f}, | ||
| 328 | {0x0000b188, 0x067e067f}, | ||
| 329 | {0x0000b18c, 0x07410742}, | ||
| 330 | {0x0000b190, 0x075f0740}, | ||
| 331 | {0x0000b194, 0x077f0760}, | ||
| 332 | {0x0000b198, 0x07800781}, | ||
| 333 | {0x0000b19c, 0x07a0079f}, | ||
| 334 | {0x0000b1a0, 0x07c107bf}, | ||
| 335 | {0x0000b1a4, 0x000007c0}, | ||
| 336 | {0x0000b1a8, 0x00000000}, | ||
| 337 | {0x0000b1ac, 0x00000000}, | ||
| 338 | {0x0000b1b0, 0x00000000}, | ||
| 339 | {0x0000b1b4, 0x00000000}, | ||
| 340 | {0x0000b1b8, 0x00000000}, | ||
| 341 | {0x0000b1bc, 0x00000000}, | ||
| 342 | {0x0000b1c0, 0x00000000}, | ||
| 343 | {0x0000b1c4, 0x00000000}, | ||
| 344 | {0x0000b1c8, 0x00000000}, | ||
| 345 | {0x0000b1cc, 0x00000000}, | ||
| 346 | {0x0000b1d0, 0x00000000}, | ||
| 347 | {0x0000b1d4, 0x00000000}, | ||
| 348 | {0x0000b1d8, 0x00000000}, | ||
| 349 | {0x0000b1dc, 0x00000000}, | ||
| 350 | {0x0000b1e0, 0x00000000}, | ||
| 351 | {0x0000b1e4, 0x00000000}, | ||
| 352 | {0x0000b1e8, 0x00000000}, | ||
| 353 | {0x0000b1ec, 0x00000000}, | ||
| 354 | {0x0000b1f0, 0x00000396}, | ||
| 355 | {0x0000b1f4, 0x00000396}, | ||
| 356 | {0x0000b1f8, 0x00000396}, | ||
| 357 | {0x0000b1fc, 0x00000196}, | ||
| 358 | }; | ||
| 359 | |||
| 360 | static const u32 ar9480_pciephy_clkreq_disable_L1_2p0[][2] = { | ||
| 361 | /* Addr allmodes */ | ||
| 362 | {0x00018c00, 0x18213ede}, | ||
| 363 | {0x00018c04, 0x000801d8}, | ||
| 364 | {0x00018c08, 0x0003580c}, | ||
| 365 | }; | ||
| 366 | |||
| 367 | static const u32 ar9480_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = { | ||
| 368 | /* Addr allmodes */ | ||
| 369 | {0x00018c00, 0x18212ede}, | ||
| 370 | {0x00018c04, 0x000801d8}, | ||
| 371 | {0x00018c08, 0x0003580c}, | ||
| 372 | }; | ||
| 373 | |||
| 374 | static const u32 ar9480_2p0_sys3ant[][2] = { | ||
| 375 | /* Addr allmodes */ | ||
| 376 | {0x00063280, 0x00040807}, | ||
| 377 | {0x00063284, 0x104ccccc}, | ||
| 378 | }; | ||
| 379 | |||
| 380 | static const u32 ar9480_common_rx_gain_table_ar9280_2p0[][2] = { | ||
| 381 | /* Addr allmodes */ | ||
| 382 | {0x0000a000, 0x02000101}, | ||
| 383 | {0x0000a004, 0x02000102}, | ||
| 384 | {0x0000a008, 0x02000103}, | ||
| 385 | {0x0000a00c, 0x02000104}, | ||
| 386 | {0x0000a010, 0x02000200}, | ||
| 387 | {0x0000a014, 0x02000201}, | ||
| 388 | {0x0000a018, 0x02000202}, | ||
| 389 | {0x0000a01c, 0x02000203}, | ||
| 390 | {0x0000a020, 0x02000204}, | ||
| 391 | {0x0000a024, 0x02000205}, | ||
| 392 | {0x0000a028, 0x02000208}, | ||
| 393 | {0x0000a02c, 0x02000302}, | ||
| 394 | {0x0000a030, 0x02000303}, | ||
| 395 | {0x0000a034, 0x02000304}, | ||
| 396 | {0x0000a038, 0x02000400}, | ||
| 397 | {0x0000a03c, 0x02010300}, | ||
| 398 | {0x0000a040, 0x02010301}, | ||
| 399 | {0x0000a044, 0x02010302}, | ||
| 400 | {0x0000a048, 0x02000500}, | ||
| 401 | {0x0000a04c, 0x02010400}, | ||
| 402 | {0x0000a050, 0x02020300}, | ||
| 403 | {0x0000a054, 0x02020301}, | ||
| 404 | {0x0000a058, 0x02020302}, | ||
| 405 | {0x0000a05c, 0x02020303}, | ||
| 406 | {0x0000a060, 0x02020400}, | ||
| 407 | {0x0000a064, 0x02030300}, | ||
| 408 | {0x0000a068, 0x02030301}, | ||
| 409 | {0x0000a06c, 0x02030302}, | ||
| 410 | {0x0000a070, 0x02030303}, | ||
| 411 | {0x0000a074, 0x02030400}, | ||
| 412 | {0x0000a078, 0x02040300}, | ||
| 413 | {0x0000a07c, 0x02040301}, | ||
| 414 | {0x0000a080, 0x02040302}, | ||
| 415 | {0x0000a084, 0x02040303}, | ||
| 416 | {0x0000a088, 0x02030500}, | ||
| 417 | {0x0000a08c, 0x02040400}, | ||
| 418 | {0x0000a090, 0x02050203}, | ||
| 419 | {0x0000a094, 0x02050204}, | ||
| 420 | {0x0000a098, 0x02050205}, | ||
| 421 | {0x0000a09c, 0x02040500}, | ||
| 422 | {0x0000a0a0, 0x02050301}, | ||
| 423 | {0x0000a0a4, 0x02050302}, | ||
| 424 | {0x0000a0a8, 0x02050303}, | ||
| 425 | {0x0000a0ac, 0x02050400}, | ||
| 426 | {0x0000a0b0, 0x02050401}, | ||
| 427 | {0x0000a0b4, 0x02050402}, | ||
| 428 | {0x0000a0b8, 0x02050403}, | ||
| 429 | {0x0000a0bc, 0x02050500}, | ||
| 430 | {0x0000a0c0, 0x02050501}, | ||
| 431 | {0x0000a0c4, 0x02050502}, | ||
| 432 | {0x0000a0c8, 0x02050503}, | ||
| 433 | {0x0000a0cc, 0x02050504}, | ||
| 434 | {0x0000a0d0, 0x02050600}, | ||
| 435 | {0x0000a0d4, 0x02050601}, | ||
| 436 | {0x0000a0d8, 0x02050602}, | ||
| 437 | {0x0000a0dc, 0x02050603}, | ||
| 438 | {0x0000a0e0, 0x02050604}, | ||
| 439 | {0x0000a0e4, 0x02050700}, | ||
| 440 | {0x0000a0e8, 0x02050701}, | ||
| 441 | {0x0000a0ec, 0x02050702}, | ||
| 442 | {0x0000a0f0, 0x02050703}, | ||
| 443 | {0x0000a0f4, 0x02050704}, | ||
| 444 | {0x0000a0f8, 0x02050705}, | ||
| 445 | {0x0000a0fc, 0x02050708}, | ||
| 446 | {0x0000a100, 0x02050709}, | ||
| 447 | {0x0000a104, 0x0205070a}, | ||
| 448 | {0x0000a108, 0x0205070b}, | ||
| 449 | {0x0000a10c, 0x0205070c}, | ||
| 450 | {0x0000a110, 0x0205070d}, | ||
| 451 | {0x0000a114, 0x02050710}, | ||
| 452 | {0x0000a118, 0x02050711}, | ||
| 453 | {0x0000a11c, 0x02050712}, | ||
| 454 | {0x0000a120, 0x02050713}, | ||
| 455 | {0x0000a124, 0x02050714}, | ||
| 456 | {0x0000a128, 0x02050715}, | ||
| 457 | {0x0000a12c, 0x02050730}, | ||
| 458 | {0x0000a130, 0x02050731}, | ||
| 459 | {0x0000a134, 0x02050732}, | ||
| 460 | {0x0000a138, 0x02050733}, | ||
| 461 | {0x0000a13c, 0x02050734}, | ||
| 462 | {0x0000a140, 0x02050735}, | ||
| 463 | {0x0000a144, 0x02050750}, | ||
| 464 | {0x0000a148, 0x02050751}, | ||
| 465 | {0x0000a14c, 0x02050752}, | ||
| 466 | {0x0000a150, 0x02050753}, | ||
| 467 | {0x0000a154, 0x02050754}, | ||
| 468 | {0x0000a158, 0x02050755}, | ||
| 469 | {0x0000a15c, 0x02050770}, | ||
| 470 | {0x0000a160, 0x02050771}, | ||
| 471 | {0x0000a164, 0x02050772}, | ||
| 472 | {0x0000a168, 0x02050773}, | ||
| 473 | {0x0000a16c, 0x02050774}, | ||
| 474 | {0x0000a170, 0x02050775}, | ||
| 475 | {0x0000a174, 0x00000776}, | ||
| 476 | {0x0000a178, 0x00000776}, | ||
| 477 | {0x0000a17c, 0x00000776}, | ||
| 478 | {0x0000a180, 0x00000776}, | ||
| 479 | {0x0000a184, 0x00000776}, | ||
| 480 | {0x0000a188, 0x00000776}, | ||
| 481 | {0x0000a18c, 0x00000776}, | ||
| 482 | {0x0000a190, 0x00000776}, | ||
| 483 | {0x0000a194, 0x00000776}, | ||
| 484 | {0x0000a198, 0x00000776}, | ||
| 485 | {0x0000a19c, 0x00000776}, | ||
| 486 | {0x0000a1a0, 0x00000776}, | ||
| 487 | {0x0000a1a4, 0x00000776}, | ||
| 488 | {0x0000a1a8, 0x00000776}, | ||
| 489 | {0x0000a1ac, 0x00000776}, | ||
| 490 | {0x0000a1b0, 0x00000776}, | ||
| 491 | {0x0000a1b4, 0x00000776}, | ||
| 492 | {0x0000a1b8, 0x00000776}, | ||
| 493 | {0x0000a1bc, 0x00000776}, | ||
| 494 | {0x0000a1c0, 0x00000776}, | ||
| 495 | {0x0000a1c4, 0x00000776}, | ||
| 496 | {0x0000a1c8, 0x00000776}, | ||
| 497 | {0x0000a1cc, 0x00000776}, | ||
| 498 | {0x0000a1d0, 0x00000776}, | ||
| 499 | {0x0000a1d4, 0x00000776}, | ||
| 500 | {0x0000a1d8, 0x00000776}, | ||
| 501 | {0x0000a1dc, 0x00000776}, | ||
| 502 | {0x0000a1e0, 0x00000776}, | ||
| 503 | {0x0000a1e4, 0x00000776}, | ||
| 504 | {0x0000a1e8, 0x00000776}, | ||
| 505 | {0x0000a1ec, 0x00000776}, | ||
| 506 | {0x0000a1f0, 0x00000776}, | ||
| 507 | {0x0000a1f4, 0x00000776}, | ||
| 508 | {0x0000a1f8, 0x00000776}, | ||
| 509 | {0x0000a1fc, 0x00000776}, | ||
| 510 | {0x0000b000, 0x02000101}, | ||
| 511 | {0x0000b004, 0x02000102}, | ||
| 512 | {0x0000b008, 0x02000103}, | ||
| 513 | {0x0000b00c, 0x02000104}, | ||
| 514 | {0x0000b010, 0x02000200}, | ||
| 515 | {0x0000b014, 0x02000201}, | ||
| 516 | {0x0000b018, 0x02000202}, | ||
| 517 | {0x0000b01c, 0x02000203}, | ||
| 518 | {0x0000b020, 0x02000204}, | ||
| 519 | {0x0000b024, 0x02000205}, | ||
| 520 | {0x0000b028, 0x02000208}, | ||
| 521 | {0x0000b02c, 0x02000302}, | ||
| 522 | {0x0000b030, 0x02000303}, | ||
| 523 | {0x0000b034, 0x02000304}, | ||
| 524 | {0x0000b038, 0x02000400}, | ||
| 525 | {0x0000b03c, 0x02010300}, | ||
| 526 | {0x0000b040, 0x02010301}, | ||
| 527 | {0x0000b044, 0x02010302}, | ||
| 528 | {0x0000b048, 0x02000500}, | ||
| 529 | {0x0000b04c, 0x02010400}, | ||
| 530 | {0x0000b050, 0x02020300}, | ||
| 531 | {0x0000b054, 0x02020301}, | ||
| 532 | {0x0000b058, 0x02020302}, | ||
| 533 | {0x0000b05c, 0x02020303}, | ||
| 534 | {0x0000b060, 0x02020400}, | ||
| 535 | {0x0000b064, 0x02030300}, | ||
| 536 | {0x0000b068, 0x02030301}, | ||
| 537 | {0x0000b06c, 0x02030302}, | ||
| 538 | {0x0000b070, 0x02030303}, | ||
| 539 | {0x0000b074, 0x02030400}, | ||
| 540 | {0x0000b078, 0x02040300}, | ||
| 541 | {0x0000b07c, 0x02040301}, | ||
| 542 | {0x0000b080, 0x02040302}, | ||
| 543 | {0x0000b084, 0x02040303}, | ||
| 544 | {0x0000b088, 0x02030500}, | ||
| 545 | {0x0000b08c, 0x02040400}, | ||
| 546 | {0x0000b090, 0x02050203}, | ||
| 547 | {0x0000b094, 0x02050204}, | ||
| 548 | {0x0000b098, 0x02050205}, | ||
| 549 | {0x0000b09c, 0x02040500}, | ||
| 550 | {0x0000b0a0, 0x02050301}, | ||
| 551 | {0x0000b0a4, 0x02050302}, | ||
| 552 | {0x0000b0a8, 0x02050303}, | ||
| 553 | {0x0000b0ac, 0x02050400}, | ||
| 554 | {0x0000b0b0, 0x02050401}, | ||
| 555 | {0x0000b0b4, 0x02050402}, | ||
| 556 | {0x0000b0b8, 0x02050403}, | ||
| 557 | {0x0000b0bc, 0x02050500}, | ||
| 558 | {0x0000b0c0, 0x02050501}, | ||
| 559 | {0x0000b0c4, 0x02050502}, | ||
| 560 | {0x0000b0c8, 0x02050503}, | ||
| 561 | {0x0000b0cc, 0x02050504}, | ||
| 562 | {0x0000b0d0, 0x02050600}, | ||
| 563 | {0x0000b0d4, 0x02050601}, | ||
| 564 | {0x0000b0d8, 0x02050602}, | ||
| 565 | {0x0000b0dc, 0x02050603}, | ||
| 566 | {0x0000b0e0, 0x02050604}, | ||
| 567 | {0x0000b0e4, 0x02050700}, | ||
| 568 | {0x0000b0e8, 0x02050701}, | ||
| 569 | {0x0000b0ec, 0x02050702}, | ||
| 570 | {0x0000b0f0, 0x02050703}, | ||
| 571 | {0x0000b0f4, 0x02050704}, | ||
| 572 | {0x0000b0f8, 0x02050705}, | ||
| 573 | {0x0000b0fc, 0x02050708}, | ||
| 574 | {0x0000b100, 0x02050709}, | ||
| 575 | {0x0000b104, 0x0205070a}, | ||
| 576 | {0x0000b108, 0x0205070b}, | ||
| 577 | {0x0000b10c, 0x0205070c}, | ||
| 578 | {0x0000b110, 0x0205070d}, | ||
| 579 | {0x0000b114, 0x02050710}, | ||
| 580 | {0x0000b118, 0x02050711}, | ||
| 581 | {0x0000b11c, 0x02050712}, | ||
| 582 | {0x0000b120, 0x02050713}, | ||
| 583 | {0x0000b124, 0x02050714}, | ||
| 584 | {0x0000b128, 0x02050715}, | ||
| 585 | {0x0000b12c, 0x02050730}, | ||
| 586 | {0x0000b130, 0x02050731}, | ||
| 587 | {0x0000b134, 0x02050732}, | ||
| 588 | {0x0000b138, 0x02050733}, | ||
| 589 | {0x0000b13c, 0x02050734}, | ||
| 590 | {0x0000b140, 0x02050735}, | ||
| 591 | {0x0000b144, 0x02050750}, | ||
| 592 | {0x0000b148, 0x02050751}, | ||
| 593 | {0x0000b14c, 0x02050752}, | ||
| 594 | {0x0000b150, 0x02050753}, | ||
| 595 | {0x0000b154, 0x02050754}, | ||
| 596 | {0x0000b158, 0x02050755}, | ||
| 597 | {0x0000b15c, 0x02050770}, | ||
| 598 | {0x0000b160, 0x02050771}, | ||
| 599 | {0x0000b164, 0x02050772}, | ||
| 600 | {0x0000b168, 0x02050773}, | ||
| 601 | {0x0000b16c, 0x02050774}, | ||
| 602 | {0x0000b170, 0x02050775}, | ||
| 603 | {0x0000b174, 0x00000776}, | ||
| 604 | {0x0000b178, 0x00000776}, | ||
| 605 | {0x0000b17c, 0x00000776}, | ||
| 606 | {0x0000b180, 0x00000776}, | ||
| 607 | {0x0000b184, 0x00000776}, | ||
| 608 | {0x0000b188, 0x00000776}, | ||
| 609 | {0x0000b18c, 0x00000776}, | ||
| 610 | {0x0000b190, 0x00000776}, | ||
| 611 | {0x0000b194, 0x00000776}, | ||
| 612 | {0x0000b198, 0x00000776}, | ||
| 613 | {0x0000b19c, 0x00000776}, | ||
| 614 | {0x0000b1a0, 0x00000776}, | ||
| 615 | {0x0000b1a4, 0x00000776}, | ||
| 616 | {0x0000b1a8, 0x00000776}, | ||
| 617 | {0x0000b1ac, 0x00000776}, | ||
| 618 | {0x0000b1b0, 0x00000776}, | ||
| 619 | {0x0000b1b4, 0x00000776}, | ||
| 620 | {0x0000b1b8, 0x00000776}, | ||
| 621 | {0x0000b1bc, 0x00000776}, | ||
| 622 | {0x0000b1c0, 0x00000776}, | ||
| 623 | {0x0000b1c4, 0x00000776}, | ||
| 624 | {0x0000b1c8, 0x00000776}, | ||
| 625 | {0x0000b1cc, 0x00000776}, | ||
| 626 | {0x0000b1d0, 0x00000776}, | ||
| 627 | {0x0000b1d4, 0x00000776}, | ||
| 628 | {0x0000b1d8, 0x00000776}, | ||
| 629 | {0x0000b1dc, 0x00000776}, | ||
| 630 | {0x0000b1e0, 0x00000776}, | ||
| 631 | {0x0000b1e4, 0x00000776}, | ||
| 632 | {0x0000b1e8, 0x00000776}, | ||
| 633 | {0x0000b1ec, 0x00000776}, | ||
| 634 | {0x0000b1f0, 0x00000776}, | ||
| 635 | {0x0000b1f4, 0x00000776}, | ||
| 636 | {0x0000b1f8, 0x00000776}, | ||
| 637 | {0x0000b1fc, 0x00000776}, | ||
| 638 | }; | ||
| 639 | |||
| 640 | static const u32 ar9200_ar9280_2p0_radio_core[][2] = { | ||
| 641 | /* Addr allmodes */ | ||
| 642 | {0x00007800, 0x00040000}, | ||
| 643 | {0x00007804, 0xdb005012}, | ||
| 644 | {0x00007808, 0x04924914}, | ||
| 645 | {0x0000780c, 0x21084210}, | ||
| 646 | {0x00007810, 0x6d801300}, | ||
| 647 | {0x00007814, 0x0019beff}, | ||
| 648 | {0x00007818, 0x07e41000}, | ||
| 649 | {0x0000781c, 0x00392000}, | ||
| 650 | {0x00007820, 0x92592480}, | ||
| 651 | {0x00007824, 0x00040000}, | ||
| 652 | {0x00007828, 0xdb005012}, | ||
| 653 | {0x0000782c, 0x04924914}, | ||
| 654 | {0x00007830, 0x21084210}, | ||
| 655 | {0x00007834, 0x6d801300}, | ||
| 656 | {0x00007838, 0x0019beff}, | ||
| 657 | {0x0000783c, 0x07e40000}, | ||
| 658 | {0x00007840, 0x00392000}, | ||
| 659 | {0x00007844, 0x92592480}, | ||
| 660 | {0x00007848, 0x00100000}, | ||
| 661 | {0x0000784c, 0x773f0567}, | ||
| 662 | {0x00007850, 0x54214514}, | ||
| 663 | {0x00007854, 0x12035828}, | ||
| 664 | {0x00007858, 0x92592692}, | ||
| 665 | {0x0000785c, 0x00000000}, | ||
| 666 | {0x00007860, 0x56400000}, | ||
| 667 | {0x00007864, 0x0a8e370e}, | ||
| 668 | {0x00007868, 0xc0102850}, | ||
| 669 | {0x0000786c, 0x812d4000}, | ||
| 670 | {0x00007870, 0x807ec400}, | ||
| 671 | {0x00007874, 0x001b6db0}, | ||
| 672 | {0x00007878, 0x00376b63}, | ||
| 673 | {0x0000787c, 0x06db6db6}, | ||
| 674 | {0x00007880, 0x006d8000}, | ||
| 675 | {0x00007884, 0xffeffffe}, | ||
| 676 | {0x00007888, 0xffeffffe}, | ||
| 677 | {0x0000788c, 0x00010000}, | ||
| 678 | {0x00007890, 0x02060aeb}, | ||
| 679 | {0x00007894, 0x5a108000}, | ||
| 680 | }; | ||
| 681 | |||
| 682 | static const u32 ar9480_2p0_mac_postamble_emulation[][5] = { | ||
| 683 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 684 | {0x00008014, 0x10f810f8, 0x10f810f8, 0x10f810f8, 0x10f810f8}, | ||
| 685 | {0x0000801c, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017}, | ||
| 686 | }; | ||
| 687 | |||
| 688 | static const u32 ar9480_2p0_radio_postamble_sys3ant[][5] = { | ||
| 689 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 690 | {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808}, | ||
| 691 | {0x00016140, 0x10804008, 0x10804008, 0x90804008, 0x90804008}, | ||
| 692 | {0x00016540, 0x10804008, 0x10804008, 0x90804008, 0x90804008}, | ||
| 693 | }; | ||
| 694 | |||
| 695 | static const u32 ar9480_2p0_baseband_postamble_emulation[][5] = { | ||
| 696 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 697 | {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 698 | {0x00009e3c, 0xcf946221, 0xcf946221, 0xcf946221, 0xcf946221}, | ||
| 699 | {0x00009e44, 0xfc5c0000, 0xfc5c0000, 0xfc5c0000, 0xfc5c0000}, | ||
| 700 | {0x0000a258, 0x02020200, 0x02020200, 0x02020200, 0x02020200}, | ||
| 701 | {0x0000a25c, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, | ||
| 702 | {0x0000a28c, 0x00011111, 0x00011111, 0x00011111, 0x00011111}, | ||
| 703 | {0x0000a2c4, 0x00148d18, 0x00148d18, 0x00148d20, 0x00148d20}, | ||
| 704 | {0x0000a2d8, 0xf999a800, 0xf999a800, 0xf999a80c, 0xf999a80c}, | ||
| 705 | {0x0000a50c, 0x0000c00a, 0x0000c00a, 0x0000c00a, 0x0000c00a}, | ||
| 706 | {0x0000a538, 0x00038e8c, 0x00038e8c, 0x00038e8c, 0x00038e8c}, | ||
| 707 | {0x0000a53c, 0x0003cecc, 0x0003cecc, 0x0003cecc, 0x0003cecc}, | ||
| 708 | {0x0000a540, 0x00040ed4, 0x00040ed4, 0x00040ed4, 0x00040ed4}, | ||
| 709 | {0x0000a544, 0x00044edc, 0x00044edc, 0x00044edc, 0x00044edc}, | ||
| 710 | {0x0000a548, 0x00048ede, 0x00048ede, 0x00048ede, 0x00048ede}, | ||
| 711 | {0x0000a54c, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e}, | ||
| 712 | {0x0000a550, 0x00050f5e, 0x00050f5e, 0x00050f5e, 0x00050f5e}, | ||
| 713 | {0x0000a554, 0x00054f9e, 0x00054f9e, 0x00054f9e, 0x00054f9e}, | ||
| 714 | {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 715 | }; | ||
| 716 | |||
| 717 | static const u32 ar9480_2p0_radio_postamble_sys2ant[][5] = { | ||
| 718 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 719 | {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808}, | ||
| 720 | {0x00016140, 0x10804008, 0x10804008, 0x90804008, 0x90804008}, | ||
| 721 | {0x00016540, 0x10804008, 0x10804008, 0x90804008, 0x90804008}, | ||
| 722 | }; | ||
| 723 | |||
| 724 | static const u32 ar9480_common_wo_xlna_rx_gain_table_2p0[][2] = { | ||
| 725 | /* Addr allmodes */ | ||
| 726 | {0x0000a000, 0x00010000}, | ||
| 727 | {0x0000a004, 0x00030002}, | ||
| 728 | {0x0000a008, 0x00050004}, | ||
| 729 | {0x0000a00c, 0x00810080}, | ||
| 730 | {0x0000a010, 0x00830082}, | ||
| 731 | {0x0000a014, 0x01810180}, | ||
| 732 | {0x0000a018, 0x01830182}, | ||
| 733 | {0x0000a01c, 0x01850184}, | ||
| 734 | {0x0000a020, 0x01890188}, | ||
| 735 | {0x0000a024, 0x018b018a}, | ||
| 736 | {0x0000a028, 0x018d018c}, | ||
| 737 | {0x0000a02c, 0x03820190}, | ||
| 738 | {0x0000a030, 0x03840383}, | ||
| 739 | {0x0000a034, 0x03880385}, | ||
| 740 | {0x0000a038, 0x038a0389}, | ||
| 741 | {0x0000a03c, 0x038c038b}, | ||
| 742 | {0x0000a040, 0x0390038d}, | ||
| 743 | {0x0000a044, 0x03920391}, | ||
| 744 | {0x0000a048, 0x03940393}, | ||
| 745 | {0x0000a04c, 0x03960395}, | ||
| 746 | {0x0000a050, 0x00000000}, | ||
| 747 | {0x0000a054, 0x00000000}, | ||
| 748 | {0x0000a058, 0x00000000}, | ||
| 749 | {0x0000a05c, 0x00000000}, | ||
| 750 | {0x0000a060, 0x00000000}, | ||
| 751 | {0x0000a064, 0x00000000}, | ||
| 752 | {0x0000a068, 0x00000000}, | ||
| 753 | {0x0000a06c, 0x00000000}, | ||
| 754 | {0x0000a070, 0x00000000}, | ||
| 755 | {0x0000a074, 0x00000000}, | ||
| 756 | {0x0000a078, 0x00000000}, | ||
| 757 | {0x0000a07c, 0x00000000}, | ||
| 758 | {0x0000a080, 0x29292929}, | ||
| 759 | {0x0000a084, 0x29292929}, | ||
| 760 | {0x0000a088, 0x29292929}, | ||
| 761 | {0x0000a08c, 0x29292929}, | ||
| 762 | {0x0000a090, 0x22292929}, | ||
| 763 | {0x0000a094, 0x1d1d2222}, | ||
| 764 | {0x0000a098, 0x0c111117}, | ||
| 765 | {0x0000a09c, 0x00030303}, | ||
| 766 | {0x0000a0a0, 0x00000000}, | ||
| 767 | {0x0000a0a4, 0x00000000}, | ||
| 768 | {0x0000a0a8, 0x00000000}, | ||
| 769 | {0x0000a0ac, 0x00000000}, | ||
| 770 | {0x0000a0b0, 0x00000000}, | ||
| 771 | {0x0000a0b4, 0x00000000}, | ||
| 772 | {0x0000a0b8, 0x00000000}, | ||
| 773 | {0x0000a0bc, 0x00000000}, | ||
| 774 | {0x0000a0c0, 0x001f0000}, | ||
| 775 | {0x0000a0c4, 0x01000101}, | ||
| 776 | {0x0000a0c8, 0x011e011f}, | ||
| 777 | {0x0000a0cc, 0x011c011d}, | ||
| 778 | {0x0000a0d0, 0x02030204}, | ||
| 779 | {0x0000a0d4, 0x02010202}, | ||
| 780 | {0x0000a0d8, 0x021f0200}, | ||
| 781 | {0x0000a0dc, 0x0302021e}, | ||
| 782 | {0x0000a0e0, 0x03000301}, | ||
| 783 | {0x0000a0e4, 0x031e031f}, | ||
| 784 | {0x0000a0e8, 0x0402031d}, | ||
| 785 | {0x0000a0ec, 0x04000401}, | ||
| 786 | {0x0000a0f0, 0x041e041f}, | ||
| 787 | {0x0000a0f4, 0x0502041d}, | ||
| 788 | {0x0000a0f8, 0x05000501}, | ||
| 789 | {0x0000a0fc, 0x051e051f}, | ||
| 790 | {0x0000a100, 0x06010602}, | ||
| 791 | {0x0000a104, 0x061f0600}, | ||
| 792 | {0x0000a108, 0x061d061e}, | ||
| 793 | {0x0000a10c, 0x07020703}, | ||
| 794 | {0x0000a110, 0x07000701}, | ||
| 795 | {0x0000a114, 0x00000000}, | ||
| 796 | {0x0000a118, 0x00000000}, | ||
| 797 | {0x0000a11c, 0x00000000}, | ||
| 798 | {0x0000a120, 0x00000000}, | ||
| 799 | {0x0000a124, 0x00000000}, | ||
| 800 | {0x0000a128, 0x00000000}, | ||
| 801 | {0x0000a12c, 0x00000000}, | ||
| 802 | {0x0000a130, 0x00000000}, | ||
| 803 | {0x0000a134, 0x00000000}, | ||
| 804 | {0x0000a138, 0x00000000}, | ||
| 805 | {0x0000a13c, 0x00000000}, | ||
| 806 | {0x0000a140, 0x001f0000}, | ||
| 807 | {0x0000a144, 0x01000101}, | ||
| 808 | {0x0000a148, 0x011e011f}, | ||
| 809 | {0x0000a14c, 0x011c011d}, | ||
| 810 | {0x0000a150, 0x02030204}, | ||
| 811 | {0x0000a154, 0x02010202}, | ||
| 812 | {0x0000a158, 0x021f0200}, | ||
| 813 | {0x0000a15c, 0x0302021e}, | ||
| 814 | {0x0000a160, 0x03000301}, | ||
| 815 | {0x0000a164, 0x031e031f}, | ||
| 816 | {0x0000a168, 0x0402031d}, | ||
| 817 | {0x0000a16c, 0x04000401}, | ||
| 818 | {0x0000a170, 0x041e041f}, | ||
| 819 | {0x0000a174, 0x0502041d}, | ||
| 820 | {0x0000a178, 0x05000501}, | ||
| 821 | {0x0000a17c, 0x051e051f}, | ||
| 822 | {0x0000a180, 0x06010602}, | ||
| 823 | {0x0000a184, 0x061f0600}, | ||
| 824 | {0x0000a188, 0x061d061e}, | ||
| 825 | {0x0000a18c, 0x07020703}, | ||
| 826 | {0x0000a190, 0x07000701}, | ||
| 827 | {0x0000a194, 0x00000000}, | ||
| 828 | {0x0000a198, 0x00000000}, | ||
| 829 | {0x0000a19c, 0x00000000}, | ||
| 830 | {0x0000a1a0, 0x00000000}, | ||
| 831 | {0x0000a1a4, 0x00000000}, | ||
| 832 | {0x0000a1a8, 0x00000000}, | ||
| 833 | {0x0000a1ac, 0x00000000}, | ||
| 834 | {0x0000a1b0, 0x00000000}, | ||
| 835 | {0x0000a1b4, 0x00000000}, | ||
| 836 | {0x0000a1b8, 0x00000000}, | ||
| 837 | {0x0000a1bc, 0x00000000}, | ||
| 838 | {0x0000a1c0, 0x00000000}, | ||
| 839 | {0x0000a1c4, 0x00000000}, | ||
| 840 | {0x0000a1c8, 0x00000000}, | ||
| 841 | {0x0000a1cc, 0x00000000}, | ||
| 842 | {0x0000a1d0, 0x00000000}, | ||
| 843 | {0x0000a1d4, 0x00000000}, | ||
| 844 | {0x0000a1d8, 0x00000000}, | ||
| 845 | {0x0000a1dc, 0x00000000}, | ||
| 846 | {0x0000a1e0, 0x00000000}, | ||
| 847 | {0x0000a1e4, 0x00000000}, | ||
| 848 | {0x0000a1e8, 0x00000000}, | ||
| 849 | {0x0000a1ec, 0x00000000}, | ||
| 850 | {0x0000a1f0, 0x00000396}, | ||
| 851 | {0x0000a1f4, 0x00000396}, | ||
| 852 | {0x0000a1f8, 0x00000396}, | ||
| 853 | {0x0000a1fc, 0x00000196}, | ||
| 854 | {0x0000b000, 0x00010000}, | ||
| 855 | {0x0000b004, 0x00030002}, | ||
| 856 | {0x0000b008, 0x00050004}, | ||
| 857 | {0x0000b00c, 0x00810080}, | ||
| 858 | {0x0000b010, 0x00830082}, | ||
| 859 | {0x0000b014, 0x01810180}, | ||
| 860 | {0x0000b018, 0x01830182}, | ||
| 861 | {0x0000b01c, 0x01850184}, | ||
| 862 | {0x0000b020, 0x02810280}, | ||
| 863 | {0x0000b024, 0x02830282}, | ||
| 864 | {0x0000b028, 0x02850284}, | ||
| 865 | {0x0000b02c, 0x02890288}, | ||
| 866 | {0x0000b030, 0x028b028a}, | ||
| 867 | {0x0000b034, 0x0388028c}, | ||
| 868 | {0x0000b038, 0x038a0389}, | ||
| 869 | {0x0000b03c, 0x038c038b}, | ||
| 870 | {0x0000b040, 0x0390038d}, | ||
| 871 | {0x0000b044, 0x03920391}, | ||
| 872 | {0x0000b048, 0x03940393}, | ||
| 873 | {0x0000b04c, 0x03960395}, | ||
| 874 | {0x0000b050, 0x00000000}, | ||
| 875 | {0x0000b054, 0x00000000}, | ||
| 876 | {0x0000b058, 0x00000000}, | ||
| 877 | {0x0000b05c, 0x00000000}, | ||
| 878 | {0x0000b060, 0x00000000}, | ||
| 879 | {0x0000b064, 0x00000000}, | ||
| 880 | {0x0000b068, 0x00000000}, | ||
| 881 | {0x0000b06c, 0x00000000}, | ||
| 882 | {0x0000b070, 0x00000000}, | ||
| 883 | {0x0000b074, 0x00000000}, | ||
| 884 | {0x0000b078, 0x00000000}, | ||
| 885 | {0x0000b07c, 0x00000000}, | ||
| 886 | {0x0000b080, 0x32323232}, | ||
| 887 | {0x0000b084, 0x2f2f3232}, | ||
| 888 | {0x0000b088, 0x23282a2d}, | ||
| 889 | {0x0000b08c, 0x1c1e2123}, | ||
| 890 | {0x0000b090, 0x14171919}, | ||
| 891 | {0x0000b094, 0x0e0e1214}, | ||
| 892 | {0x0000b098, 0x03050707}, | ||
| 893 | {0x0000b09c, 0x00030303}, | ||
| 894 | {0x0000b0a0, 0x00000000}, | ||
| 895 | {0x0000b0a4, 0x00000000}, | ||
| 896 | {0x0000b0a8, 0x00000000}, | ||
| 897 | {0x0000b0ac, 0x00000000}, | ||
| 898 | {0x0000b0b0, 0x00000000}, | ||
| 899 | {0x0000b0b4, 0x00000000}, | ||
| 900 | {0x0000b0b8, 0x00000000}, | ||
| 901 | {0x0000b0bc, 0x00000000}, | ||
| 902 | {0x0000b0c0, 0x003f0020}, | ||
| 903 | {0x0000b0c4, 0x00400041}, | ||
| 904 | {0x0000b0c8, 0x0140005f}, | ||
| 905 | {0x0000b0cc, 0x0160015f}, | ||
| 906 | {0x0000b0d0, 0x017e017f}, | ||
| 907 | {0x0000b0d4, 0x02410242}, | ||
| 908 | {0x0000b0d8, 0x025f0240}, | ||
| 909 | {0x0000b0dc, 0x027f0260}, | ||
| 910 | {0x0000b0e0, 0x0341027e}, | ||
| 911 | {0x0000b0e4, 0x035f0340}, | ||
| 912 | {0x0000b0e8, 0x037f0360}, | ||
| 913 | {0x0000b0ec, 0x04400441}, | ||
| 914 | {0x0000b0f0, 0x0460045f}, | ||
| 915 | {0x0000b0f4, 0x0541047f}, | ||
| 916 | {0x0000b0f8, 0x055f0540}, | ||
| 917 | {0x0000b0fc, 0x057f0560}, | ||
| 918 | {0x0000b100, 0x06400641}, | ||
| 919 | {0x0000b104, 0x0660065f}, | ||
| 920 | {0x0000b108, 0x067e067f}, | ||
| 921 | {0x0000b10c, 0x07410742}, | ||
| 922 | {0x0000b110, 0x075f0740}, | ||
| 923 | {0x0000b114, 0x077f0760}, | ||
| 924 | {0x0000b118, 0x07800781}, | ||
| 925 | {0x0000b11c, 0x07a0079f}, | ||
| 926 | {0x0000b120, 0x07c107bf}, | ||
| 927 | {0x0000b124, 0x000007c0}, | ||
| 928 | {0x0000b128, 0x00000000}, | ||
| 929 | {0x0000b12c, 0x00000000}, | ||
| 930 | {0x0000b130, 0x00000000}, | ||
| 931 | {0x0000b134, 0x00000000}, | ||
| 932 | {0x0000b138, 0x00000000}, | ||
| 933 | {0x0000b13c, 0x00000000}, | ||
| 934 | {0x0000b140, 0x003f0020}, | ||
| 935 | {0x0000b144, 0x00400041}, | ||
| 936 | {0x0000b148, 0x0140005f}, | ||
| 937 | {0x0000b14c, 0x0160015f}, | ||
| 938 | {0x0000b150, 0x017e017f}, | ||
| 939 | {0x0000b154, 0x02410242}, | ||
| 940 | {0x0000b158, 0x025f0240}, | ||
| 941 | {0x0000b15c, 0x027f0260}, | ||
| 942 | {0x0000b160, 0x0341027e}, | ||
| 943 | {0x0000b164, 0x035f0340}, | ||
| 944 | {0x0000b168, 0x037f0360}, | ||
| 945 | {0x0000b16c, 0x04400441}, | ||
| 946 | {0x0000b170, 0x0460045f}, | ||
| 947 | {0x0000b174, 0x0541047f}, | ||
| 948 | {0x0000b178, 0x055f0540}, | ||
| 949 | {0x0000b17c, 0x057f0560}, | ||
| 950 | {0x0000b180, 0x06400641}, | ||
| 951 | {0x0000b184, 0x0660065f}, | ||
| 952 | {0x0000b188, 0x067e067f}, | ||
| 953 | {0x0000b18c, 0x07410742}, | ||
| 954 | {0x0000b190, 0x075f0740}, | ||
| 955 | {0x0000b194, 0x077f0760}, | ||
| 956 | {0x0000b198, 0x07800781}, | ||
| 957 | {0x0000b19c, 0x07a0079f}, | ||
| 958 | {0x0000b1a0, 0x07c107bf}, | ||
| 959 | {0x0000b1a4, 0x000007c0}, | ||
| 960 | {0x0000b1a8, 0x00000000}, | ||
| 961 | {0x0000b1ac, 0x00000000}, | ||
| 962 | {0x0000b1b0, 0x00000000}, | ||
| 963 | {0x0000b1b4, 0x00000000}, | ||
| 964 | {0x0000b1b8, 0x00000000}, | ||
| 965 | {0x0000b1bc, 0x00000000}, | ||
| 966 | {0x0000b1c0, 0x00000000}, | ||
| 967 | {0x0000b1c4, 0x00000000}, | ||
| 968 | {0x0000b1c8, 0x00000000}, | ||
| 969 | {0x0000b1cc, 0x00000000}, | ||
| 970 | {0x0000b1d0, 0x00000000}, | ||
| 971 | {0x0000b1d4, 0x00000000}, | ||
| 972 | {0x0000b1d8, 0x00000000}, | ||
| 973 | {0x0000b1dc, 0x00000000}, | ||
| 974 | {0x0000b1e0, 0x00000000}, | ||
| 975 | {0x0000b1e4, 0x00000000}, | ||
| 976 | {0x0000b1e8, 0x00000000}, | ||
| 977 | {0x0000b1ec, 0x00000000}, | ||
| 978 | {0x0000b1f0, 0x00000396}, | ||
| 979 | {0x0000b1f4, 0x00000396}, | ||
| 980 | {0x0000b1f8, 0x00000396}, | ||
| 981 | {0x0000b1fc, 0x00000196}, | ||
| 982 | }; | ||
| 983 | |||
| 984 | static const u32 ar9480_2p0_baseband_core_txfir_coeff_japan_2484[][2] = { | ||
| 985 | /* Addr allmodes */ | ||
| 986 | {0x0000a398, 0x00000000}, | ||
| 987 | {0x0000a39c, 0x6f7f0301}, | ||
| 988 | {0x0000a3a0, 0xca9228ee}, | ||
| 989 | }; | ||
| 990 | |||
| 991 | static const u32 ar9480_modes_low_ob_db_tx_gain_table_2p0[][5] = { | ||
| 992 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 993 | {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, | ||
| 994 | {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, | ||
| 995 | {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, | ||
| 996 | {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, | ||
| 997 | {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, | ||
| 998 | {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, | ||
| 999 | {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1000 | {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1001 | {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002}, | ||
| 1002 | {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004}, | ||
| 1003 | {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200}, | ||
| 1004 | {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202}, | ||
| 1005 | {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400}, | ||
| 1006 | {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402}, | ||
| 1007 | {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404}, | ||
| 1008 | {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603}, | ||
| 1009 | {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02}, | ||
| 1010 | {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04}, | ||
| 1011 | {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20}, | ||
| 1012 | {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20}, | ||
| 1013 | {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22}, | ||
| 1014 | {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24}, | ||
| 1015 | {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640}, | ||
| 1016 | {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660}, | ||
| 1017 | {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861}, | ||
| 1018 | {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81}, | ||
| 1019 | {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83}, | ||
| 1020 | {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84}, | ||
| 1021 | {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3}, | ||
| 1022 | {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5}, | ||
| 1023 | {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9}, | ||
| 1024 | {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb}, | ||
| 1025 | {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, | ||
| 1026 | {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, | ||
| 1027 | {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, | ||
| 1028 | {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, | ||
| 1029 | {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, | ||
| 1030 | {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, | ||
| 1031 | {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, | ||
| 1032 | {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1033 | {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1034 | {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1035 | {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1036 | {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1037 | {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000}, | ||
| 1038 | {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501}, | ||
| 1039 | {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501}, | ||
| 1040 | {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03}, | ||
| 1041 | {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04}, | ||
| 1042 | {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04}, | ||
| 1043 | {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005}, | ||
| 1044 | {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, | ||
| 1045 | {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, | ||
| 1046 | {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, | ||
| 1047 | {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, | ||
| 1048 | {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, | ||
| 1049 | {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, | ||
| 1050 | {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, | ||
| 1051 | {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, | ||
| 1052 | {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4}, | ||
| 1053 | {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060}, | ||
| 1054 | {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, | ||
| 1055 | {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4}, | ||
| 1056 | {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000}, | ||
| 1057 | {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, | ||
| 1058 | }; | ||
| 1059 | |||
| 1060 | static const u32 ar9480_2p0_soc_postamble[][5] = { | ||
| 1061 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 1062 | {0x00007010, 0x00002233, 0x00002233, 0x00002233, 0x00002233}, | ||
| 1063 | }; | ||
| 1064 | |||
| 1065 | static const u32 ar9480_2p0_baseband_core[][2] = { | ||
| 1066 | /* Addr allmodes */ | ||
| 1067 | {0x00009800, 0xafe68e30}, | ||
| 1068 | {0x00009804, 0xfd14e000}, | ||
| 1069 | {0x00009808, 0x9c0a9f6b}, | ||
| 1070 | {0x0000980c, 0x04900000}, | ||
| 1071 | {0x00009814, 0x9280c00a}, | ||
| 1072 | {0x00009818, 0x00000000}, | ||
| 1073 | {0x0000981c, 0x00020028}, | ||
| 1074 | {0x00009834, 0x6400a290}, | ||
| 1075 | {0x00009838, 0x0108ecff}, | ||
| 1076 | {0x0000983c, 0x0d000600}, | ||
| 1077 | {0x00009880, 0x201fff00}, | ||
| 1078 | {0x00009884, 0x00001042}, | ||
| 1079 | {0x000098a4, 0x00200400}, | ||
| 1080 | {0x000098b0, 0x32440bbe}, | ||
| 1081 | {0x000098d0, 0x004b6a8e}, | ||
| 1082 | {0x000098d4, 0x00000820}, | ||
| 1083 | {0x000098dc, 0x00000000}, | ||
| 1084 | {0x000098e4, 0x01ffffff}, | ||
| 1085 | {0x000098e8, 0x01ffffff}, | ||
| 1086 | {0x000098ec, 0x01ffffff}, | ||
| 1087 | {0x000098f0, 0x00000000}, | ||
| 1088 | {0x000098f4, 0x00000000}, | ||
| 1089 | {0x00009bf0, 0x80000000}, | ||
| 1090 | {0x00009c04, 0xff55ff55}, | ||
| 1091 | {0x00009c08, 0x0320ff55}, | ||
| 1092 | {0x00009c0c, 0x00000000}, | ||
| 1093 | {0x00009c10, 0x00000000}, | ||
| 1094 | {0x00009c14, 0x00046384}, | ||
| 1095 | {0x00009c18, 0x05b6b440}, | ||
| 1096 | {0x00009c1c, 0x00b6b440}, | ||
| 1097 | {0x00009d00, 0xc080a333}, | ||
| 1098 | {0x00009d04, 0x40206c10}, | ||
| 1099 | {0x00009d08, 0x009c4060}, | ||
| 1100 | {0x00009d0c, 0x9883800a}, | ||
| 1101 | {0x00009d10, 0x01834061}, | ||
| 1102 | {0x00009d14, 0x00c0040b}, | ||
| 1103 | {0x00009d18, 0x00000000}, | ||
| 1104 | {0x00009e08, 0x0038230c}, | ||
| 1105 | {0x00009e24, 0x990bb515}, | ||
| 1106 | {0x00009e28, 0x0c6f0000}, | ||
| 1107 | {0x00009e30, 0x06336f77}, | ||
| 1108 | {0x00009e34, 0x6af6532f}, | ||
| 1109 | {0x00009e38, 0x0cc80c00}, | ||
| 1110 | {0x00009e40, 0x0d261820}, | ||
| 1111 | {0x00009e4c, 0x00001004}, | ||
| 1112 | {0x00009e50, 0x00ff03f1}, | ||
| 1113 | {0x00009e54, 0xe4c355c7}, | ||
| 1114 | {0x00009e58, 0xfd897735}, | ||
| 1115 | {0x00009e5c, 0xe9198724}, | ||
| 1116 | {0x00009fc0, 0x803e4788}, | ||
| 1117 | {0x00009fc4, 0x0001efb5}, | ||
| 1118 | {0x00009fcc, 0x40000014}, | ||
| 1119 | {0x00009fd0, 0x01193b93}, | ||
| 1120 | {0x0000a20c, 0x00000000}, | ||
| 1121 | {0x0000a220, 0x00000000}, | ||
| 1122 | {0x0000a224, 0x00000000}, | ||
| 1123 | {0x0000a228, 0x10002310}, | ||
| 1124 | {0x0000a23c, 0x00000000}, | ||
| 1125 | {0x0000a244, 0x0c000000}, | ||
| 1126 | {0x0000a2a0, 0x00000001}, | ||
| 1127 | {0x0000a2c0, 0x00000001}, | ||
| 1128 | {0x0000a2c8, 0x00000000}, | ||
| 1129 | {0x0000a2cc, 0x18c43433}, | ||
| 1130 | {0x0000a2d4, 0x00000000}, | ||
| 1131 | {0x0000a2ec, 0x00000000}, | ||
| 1132 | {0x0000a2f0, 0x00000000}, | ||
| 1133 | {0x0000a2f4, 0x00000000}, | ||
| 1134 | {0x0000a2f8, 0x00000000}, | ||
| 1135 | {0x0000a344, 0x00000000}, | ||
| 1136 | {0x0000a34c, 0x00000000}, | ||
| 1137 | {0x0000a350, 0x0000a000}, | ||
| 1138 | {0x0000a364, 0x00000000}, | ||
| 1139 | {0x0000a370, 0x00000000}, | ||
| 1140 | {0x0000a390, 0x00000001}, | ||
| 1141 | {0x0000a394, 0x00000444}, | ||
| 1142 | {0x0000a398, 0x001f0e0f}, | ||
| 1143 | {0x0000a39c, 0x0075393f}, | ||
| 1144 | {0x0000a3a0, 0xb79f6427}, | ||
| 1145 | {0x0000a3a4, 0x00000000}, | ||
| 1146 | {0x0000a3a8, 0xaaaaaaaa}, | ||
| 1147 | {0x0000a3ac, 0x3c466478}, | ||
| 1148 | {0x0000a3c0, 0x20202020}, | ||
| 1149 | {0x0000a3c4, 0x22222220}, | ||
| 1150 | {0x0000a3c8, 0x20200020}, | ||
| 1151 | {0x0000a3cc, 0x20202020}, | ||
| 1152 | {0x0000a3d0, 0x20202020}, | ||
| 1153 | {0x0000a3d4, 0x20202020}, | ||
| 1154 | {0x0000a3d8, 0x20202020}, | ||
| 1155 | {0x0000a3dc, 0x20202020}, | ||
| 1156 | {0x0000a3e0, 0x20202020}, | ||
| 1157 | {0x0000a3e4, 0x20202020}, | ||
| 1158 | {0x0000a3e8, 0x20202020}, | ||
| 1159 | {0x0000a3ec, 0x20202020}, | ||
| 1160 | {0x0000a3f0, 0x00000000}, | ||
| 1161 | {0x0000a3f4, 0x00000006}, | ||
| 1162 | {0x0000a3f8, 0x0c9bd380}, | ||
| 1163 | {0x0000a3fc, 0x000f0f01}, | ||
| 1164 | {0x0000a400, 0x8fa91f01}, | ||
| 1165 | {0x0000a404, 0x00000000}, | ||
| 1166 | {0x0000a408, 0x0e79e5c6}, | ||
| 1167 | {0x0000a40c, 0x00820820}, | ||
| 1168 | {0x0000a414, 0x1ce739ce}, | ||
| 1169 | {0x0000a418, 0x2d001dce}, | ||
| 1170 | {0x0000a41c, 0x1ce739ce}, | ||
| 1171 | {0x0000a420, 0x000001ce}, | ||
| 1172 | {0x0000a424, 0x1ce739ce}, | ||
| 1173 | {0x0000a428, 0x000001ce}, | ||
| 1174 | {0x0000a42c, 0x1ce739ce}, | ||
| 1175 | {0x0000a430, 0x1ce739ce}, | ||
| 1176 | {0x0000a434, 0x00000000}, | ||
| 1177 | {0x0000a438, 0x00001801}, | ||
| 1178 | {0x0000a43c, 0x00100000}, | ||
| 1179 | {0x0000a444, 0x00000000}, | ||
| 1180 | {0x0000a448, 0x05000080}, | ||
| 1181 | {0x0000a44c, 0x00000001}, | ||
| 1182 | {0x0000a450, 0x00010000}, | ||
| 1183 | {0x0000a454, 0x07000000}, | ||
| 1184 | {0x0000a644, 0xbfad9d74}, | ||
| 1185 | {0x0000a648, 0x0048060a}, | ||
| 1186 | {0x0000a64c, 0x00002037}, | ||
| 1187 | {0x0000a670, 0x03020100}, | ||
| 1188 | {0x0000a674, 0x09080504}, | ||
| 1189 | {0x0000a678, 0x0d0c0b0a}, | ||
| 1190 | {0x0000a67c, 0x13121110}, | ||
| 1191 | {0x0000a680, 0x31301514}, | ||
| 1192 | {0x0000a684, 0x35343332}, | ||
| 1193 | {0x0000a688, 0x00000036}, | ||
| 1194 | {0x0000a690, 0x00000838}, | ||
| 1195 | {0x0000a6b0, 0x0000000a}, | ||
| 1196 | {0x0000a6b4, 0x00512c01}, | ||
| 1197 | {0x0000a7c0, 0x00000000}, | ||
| 1198 | {0x0000a7c4, 0xfffffffc}, | ||
| 1199 | {0x0000a7c8, 0x00000000}, | ||
| 1200 | {0x0000a7cc, 0x00000000}, | ||
| 1201 | {0x0000a7d0, 0x00000000}, | ||
| 1202 | {0x0000a7d4, 0x00000004}, | ||
| 1203 | {0x0000a7dc, 0x00000001}, | ||
| 1204 | {0x0000a7f0, 0x80000000}, | ||
| 1205 | {0x0000a8d0, 0x004b6a8e}, | ||
| 1206 | {0x0000a8d4, 0x00000820}, | ||
| 1207 | {0x0000a8dc, 0x00000000}, | ||
| 1208 | {0x0000a8f0, 0x00000000}, | ||
| 1209 | {0x0000a8f4, 0x00000000}, | ||
| 1210 | {0x0000abf0, 0x80000000}, | ||
| 1211 | {0x0000b2d0, 0x00000080}, | ||
| 1212 | {0x0000b2d4, 0x00000000}, | ||
| 1213 | {0x0000b2ec, 0x00000000}, | ||
| 1214 | {0x0000b2f0, 0x00000000}, | ||
| 1215 | {0x0000b2f4, 0x00000000}, | ||
| 1216 | {0x0000b2f8, 0x00000000}, | ||
| 1217 | {0x0000b408, 0x0e79e5c0}, | ||
| 1218 | {0x0000b40c, 0x00820820}, | ||
| 1219 | {0x0000b420, 0x00000000}, | ||
| 1220 | {0x0000b6b0, 0x0000000a}, | ||
| 1221 | {0x0000b6b4, 0x00000001}, | ||
| 1222 | }; | ||
| 1223 | |||
| 1224 | static const u32 ar9480_2p0_radio_postamble[][5] = { | ||
| 1225 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 1226 | {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524}, | ||
| 1227 | {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70}, | ||
| 1228 | {0x0001610c, 0x48000000, 0x40000000, 0x40000000, 0x40000000}, | ||
| 1229 | {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000}, | ||
| 1230 | }; | ||
| 1231 | |||
| 1232 | static const u32 ar9480_modes_high_ob_db_tx_gain_table_2p0[][5] = { | ||
| 1233 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 1234 | {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, | ||
| 1235 | {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, | ||
| 1236 | {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, | ||
| 1237 | {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, | ||
| 1238 | {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, | ||
| 1239 | {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, | ||
| 1240 | {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1241 | {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, | ||
| 1242 | {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002}, | ||
| 1243 | {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004}, | ||
| 1244 | {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200}, | ||
| 1245 | {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202}, | ||
| 1246 | {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400}, | ||
| 1247 | {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402}, | ||
| 1248 | {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404}, | ||
| 1249 | {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603}, | ||
| 1250 | {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02}, | ||
| 1251 | {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04}, | ||
| 1252 | {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20}, | ||
| 1253 | {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20}, | ||
| 1254 | {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22}, | ||
| 1255 | {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24}, | ||
| 1256 | {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640}, | ||
| 1257 | {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660}, | ||
| 1258 | {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861}, | ||
| 1259 | {0x0000a548, 0x53025eb2, 0x53025eb2, 0x3e001a81, 0x3e001a81}, | ||
| 1260 | {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83}, | ||
| 1261 | {0x0000a550, 0x5f025ef6, 0x5f025ef6, 0x44001c84, 0x44001c84}, | ||
| 1262 | {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3}, | ||
| 1263 | {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5}, | ||
| 1264 | {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9}, | ||
| 1265 | {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb}, | ||
| 1266 | {0x0000a564, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 1267 | {0x0000a568, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 1268 | {0x0000a56c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 1269 | {0x0000a570, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 1270 | {0x0000a574, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 1271 | {0x0000a578, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 1272 | {0x0000a57c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 1273 | {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1274 | {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1275 | {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1276 | {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1277 | {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000}, | ||
| 1278 | {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000}, | ||
| 1279 | {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501}, | ||
| 1280 | {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501}, | ||
| 1281 | {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03}, | ||
| 1282 | {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04}, | ||
| 1283 | {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04}, | ||
| 1284 | {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, | ||
| 1285 | {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, | ||
| 1286 | {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, | ||
| 1287 | {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, | ||
| 1288 | {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, | ||
| 1289 | {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, | ||
| 1290 | {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, | ||
| 1291 | {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, | ||
| 1292 | {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, | ||
| 1293 | {0x00016044, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4}, | ||
| 1294 | {0x00016048, 0x8db49060, 0x8db49060, 0x8db49060, 0x8db49060}, | ||
| 1295 | {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, | ||
| 1296 | {0x00016444, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4}, | ||
| 1297 | {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000}, | ||
| 1298 | {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, | ||
| 1299 | }; | ||
| 1300 | |||
| 1301 | static const u32 ar9480_2p0_radio_core[][2] = { | ||
| 1302 | /* Addr allmodes */ | ||
| 1303 | {0x00016000, 0x36db6db6}, | ||
| 1304 | {0x00016004, 0x6db6db40}, | ||
| 1305 | {0x00016008, 0x73f00000}, | ||
| 1306 | {0x0001600c, 0x00000000}, | ||
| 1307 | {0x00016010, 0x6d820001}, | ||
| 1308 | {0x00016040, 0x7f80fff8}, | ||
| 1309 | {0x0001604c, 0x2699e04f}, | ||
| 1310 | {0x00016050, 0x6db6db6c}, | ||
| 1311 | {0x00016058, 0x6c200000}, | ||
| 1312 | {0x00016080, 0x00040000}, | ||
| 1313 | {0x00016084, 0x9a68048c}, | ||
| 1314 | {0x00016088, 0x54214514}, | ||
| 1315 | {0x0001608c, 0x1203040b}, | ||
| 1316 | {0x00016090, 0x24926490}, | ||
| 1317 | {0x00016098, 0xd2888888}, | ||
| 1318 | {0x000160a0, 0x0a108ffe}, | ||
| 1319 | {0x000160a4, 0x812fc491}, | ||
| 1320 | {0x000160a8, 0x423c8000}, | ||
| 1321 | {0x000160b4, 0x92000000}, | ||
| 1322 | {0x000160b8, 0x0285dddc}, | ||
| 1323 | {0x000160bc, 0x02908888}, | ||
| 1324 | {0x000160c0, 0x00adb6d0}, | ||
| 1325 | {0x000160c4, 0x6db6db60}, | ||
| 1326 | {0x000160c8, 0x6db6db6c}, | ||
| 1327 | {0x000160cc, 0x0de6c1b0}, | ||
| 1328 | {0x00016100, 0x3fffbe04}, | ||
| 1329 | {0x00016104, 0xfff80000}, | ||
| 1330 | {0x00016108, 0x00200400}, | ||
| 1331 | {0x00016110, 0x00000000}, | ||
| 1332 | {0x00016144, 0x02084080}, | ||
| 1333 | {0x00016148, 0x000080c0}, | ||
| 1334 | {0x00016280, 0x050a0001}, | ||
| 1335 | {0x00016284, 0x3d841400}, | ||
| 1336 | {0x00016288, 0x00000000}, | ||
| 1337 | {0x0001628c, 0xe3000000}, | ||
| 1338 | {0x00016290, 0xa1005080}, | ||
| 1339 | {0x00016294, 0x00000020}, | ||
| 1340 | {0x00016298, 0x54a82900}, | ||
| 1341 | {0x00016340, 0x121e4276}, | ||
| 1342 | {0x00016344, 0x00300000}, | ||
| 1343 | {0x00016400, 0x36db6db6}, | ||
| 1344 | {0x00016404, 0x6db6db40}, | ||
| 1345 | {0x00016408, 0x73f00000}, | ||
| 1346 | {0x0001640c, 0x00000000}, | ||
| 1347 | {0x00016410, 0x6c800001}, | ||
| 1348 | {0x00016440, 0x7f80fff8}, | ||
| 1349 | {0x0001644c, 0x4699e04f}, | ||
| 1350 | {0x00016450, 0x6db6db6c}, | ||
| 1351 | {0x00016500, 0x3fffbe04}, | ||
| 1352 | {0x00016504, 0xfff80000}, | ||
| 1353 | {0x00016508, 0x00200400}, | ||
| 1354 | {0x00016510, 0x00000000}, | ||
| 1355 | {0x00016544, 0x02084080}, | ||
| 1356 | {0x00016548, 0x000080c0}, | ||
| 1357 | }; | ||
| 1358 | |||
| 1359 | static const u32 ar9480_2p0_tx_gain_table_baseband_postamble_emulation[][5] = { | ||
| 1360 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 1361 | {0x0000a410, 0x000000d5, 0x000000d5, 0x000000d5, 0x000000d5}, | ||
| 1362 | {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1363 | {0x0000a504, 0x00004002, 0x00004002, 0x00004002, 0x00004002}, | ||
| 1364 | {0x0000a508, 0x00008004, 0x00008004, 0x00008004, 0x00008004}, | ||
| 1365 | {0x0000a510, 0x0001000c, 0x0001000c, 0x0001000c, 0x0001000c}, | ||
| 1366 | {0x0000a514, 0x0001420b, 0x0001420b, 0x0001420b, 0x0001420b}, | ||
| 1367 | {0x0000a518, 0x0001824a, 0x0001824a, 0x0001824a, 0x0001824a}, | ||
| 1368 | {0x0000a51c, 0x0001c44a, 0x0001c44a, 0x0001c44a, 0x0001c44a}, | ||
| 1369 | {0x0000a520, 0x0002064a, 0x0002064a, 0x0002064a, 0x0002064a}, | ||
| 1370 | {0x0000a524, 0x0002484a, 0x0002484a, 0x0002484a, 0x0002484a}, | ||
| 1371 | {0x0000a528, 0x00028a4a, 0x00028a4a, 0x00028a4a, 0x00028a4a}, | ||
| 1372 | {0x0000a52c, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a}, | ||
| 1373 | {0x0000a530, 0x00030e4a, 0x00030e4a, 0x00030e4a, 0x00030e4a}, | ||
| 1374 | {0x0000a534, 0x00034e8a, 0x00034e8a, 0x00034e8a, 0x00034e8a}, | ||
| 1375 | }; | ||
| 1376 | |||
| 1377 | static const u32 ar9480_2p0_soc_preamble[][2] = { | ||
| 1378 | /* Addr allmodes */ | ||
| 1379 | {0x00007020, 0x00000000}, | ||
| 1380 | {0x00007034, 0x00000002}, | ||
| 1381 | {0x00007038, 0x000004c2}, | ||
| 1382 | }; | ||
| 1383 | |||
| 1384 | static const u32 ar9480_2p0_sys2ant[][2] = { | ||
| 1385 | /* Addr allmodes */ | ||
| 1386 | {0x00063120, 0x00801980}, | ||
| 1387 | }; | ||
| 1388 | |||
| 1389 | static const u32 ar9480_2p0_mac_core[][2] = { | ||
| 1390 | /* Addr allmodes */ | ||
| 1391 | {0x00000008, 0x00000000}, | ||
| 1392 | {0x00000030, 0x000e0085}, | ||
| 1393 | {0x00000034, 0x00000005}, | ||
| 1394 | {0x00000040, 0x00000000}, | ||
| 1395 | {0x00000044, 0x00000000}, | ||
| 1396 | {0x00000048, 0x00000008}, | ||
| 1397 | {0x0000004c, 0x00000010}, | ||
| 1398 | {0x00000050, 0x00000000}, | ||
| 1399 | {0x00001040, 0x002ffc0f}, | ||
| 1400 | {0x00001044, 0x002ffc0f}, | ||
| 1401 | {0x00001048, 0x002ffc0f}, | ||
| 1402 | {0x0000104c, 0x002ffc0f}, | ||
| 1403 | {0x00001050, 0x002ffc0f}, | ||
| 1404 | {0x00001054, 0x002ffc0f}, | ||
| 1405 | {0x00001058, 0x002ffc0f}, | ||
| 1406 | {0x0000105c, 0x002ffc0f}, | ||
| 1407 | {0x00001060, 0x002ffc0f}, | ||
| 1408 | {0x00001064, 0x002ffc0f}, | ||
| 1409 | {0x000010f0, 0x00000100}, | ||
| 1410 | {0x00001270, 0x00000000}, | ||
| 1411 | {0x000012b0, 0x00000000}, | ||
| 1412 | {0x000012f0, 0x00000000}, | ||
| 1413 | {0x0000143c, 0x00000000}, | ||
| 1414 | {0x0000147c, 0x00000000}, | ||
| 1415 | {0x00001810, 0x0f000003}, | ||
| 1416 | {0x00008000, 0x00000000}, | ||
| 1417 | {0x00008004, 0x00000000}, | ||
| 1418 | {0x00008008, 0x00000000}, | ||
| 1419 | {0x0000800c, 0x00000000}, | ||
| 1420 | {0x00008018, 0x00000000}, | ||
| 1421 | {0x00008020, 0x00000000}, | ||
| 1422 | {0x00008038, 0x00000000}, | ||
| 1423 | {0x0000803c, 0x00080000}, | ||
| 1424 | {0x00008040, 0x00000000}, | ||
| 1425 | {0x00008044, 0x00000000}, | ||
| 1426 | {0x00008048, 0x00000000}, | ||
| 1427 | {0x0000804c, 0xffffffff}, | ||
| 1428 | {0x00008050, 0xffffffff}, | ||
| 1429 | {0x00008054, 0x00000000}, | ||
| 1430 | {0x00008058, 0x00000000}, | ||
| 1431 | {0x0000805c, 0x000fc78f}, | ||
| 1432 | {0x00008060, 0x0000000f}, | ||
| 1433 | {0x00008064, 0x00000000}, | ||
| 1434 | {0x00008070, 0x00000310}, | ||
| 1435 | {0x00008074, 0x00000020}, | ||
| 1436 | {0x00008078, 0x00000000}, | ||
| 1437 | {0x0000809c, 0x0000000f}, | ||
| 1438 | {0x000080a0, 0x00000000}, | ||
| 1439 | {0x000080a4, 0x02ff0000}, | ||
| 1440 | {0x000080a8, 0x0e070605}, | ||
| 1441 | {0x000080ac, 0x0000000d}, | ||
| 1442 | {0x000080b0, 0x00000000}, | ||
| 1443 | {0x000080b4, 0x00000000}, | ||
| 1444 | {0x000080b8, 0x00000000}, | ||
| 1445 | {0x000080bc, 0x00000000}, | ||
| 1446 | {0x000080c0, 0x2a800000}, | ||
| 1447 | {0x000080c4, 0x06900168}, | ||
| 1448 | {0x000080c8, 0x13881c20}, | ||
| 1449 | {0x000080cc, 0x01f40000}, | ||
| 1450 | {0x000080d0, 0x00252500}, | ||
| 1451 | {0x000080d4, 0x00b00005}, | ||
| 1452 | {0x000080d8, 0x00400002}, | ||
| 1453 | {0x000080dc, 0x00000000}, | ||
| 1454 | {0x000080e0, 0xffffffff}, | ||
| 1455 | {0x000080e4, 0x0000ffff}, | ||
| 1456 | {0x000080e8, 0x3f3f3f3f}, | ||
| 1457 | {0x000080ec, 0x00000000}, | ||
| 1458 | {0x000080f0, 0x00000000}, | ||
| 1459 | {0x000080f4, 0x00000000}, | ||
| 1460 | {0x000080fc, 0x00020000}, | ||
| 1461 | {0x00008100, 0x00000000}, | ||
| 1462 | {0x00008108, 0x00000052}, | ||
| 1463 | {0x0000810c, 0x00000000}, | ||
| 1464 | {0x00008110, 0x00000000}, | ||
| 1465 | {0x00008114, 0x000007ff}, | ||
| 1466 | {0x00008118, 0x000000aa}, | ||
| 1467 | {0x0000811c, 0x00003210}, | ||
| 1468 | {0x00008124, 0x00000000}, | ||
| 1469 | {0x00008128, 0x00000000}, | ||
| 1470 | {0x0000812c, 0x00000000}, | ||
| 1471 | {0x00008130, 0x00000000}, | ||
| 1472 | {0x00008134, 0x00000000}, | ||
| 1473 | {0x00008138, 0x00000000}, | ||
| 1474 | {0x0000813c, 0x0000ffff}, | ||
| 1475 | {0x00008144, 0xffffffff}, | ||
| 1476 | {0x00008168, 0x00000000}, | ||
| 1477 | {0x0000816c, 0x00000000}, | ||
| 1478 | {0x00008170, 0x18486e00}, | ||
| 1479 | {0x00008174, 0x33332210}, | ||
| 1480 | {0x00008178, 0x00000000}, | ||
| 1481 | {0x0000817c, 0x00020000}, | ||
| 1482 | {0x000081c4, 0x33332210}, | ||
| 1483 | {0x000081c8, 0x00000000}, | ||
| 1484 | {0x000081cc, 0x00000000}, | ||
| 1485 | {0x000081d4, 0x00000000}, | ||
| 1486 | {0x000081ec, 0x00000000}, | ||
| 1487 | {0x000081f0, 0x00000000}, | ||
| 1488 | {0x000081f4, 0x00000000}, | ||
| 1489 | {0x000081f8, 0x00000000}, | ||
| 1490 | {0x000081fc, 0x00000000}, | ||
| 1491 | {0x00008240, 0x00100000}, | ||
| 1492 | {0x00008244, 0x0010f400}, | ||
| 1493 | {0x00008248, 0x00000800}, | ||
| 1494 | {0x0000824c, 0x0001e800}, | ||
| 1495 | {0x00008250, 0x00000000}, | ||
| 1496 | {0x00008254, 0x00000000}, | ||
| 1497 | {0x00008258, 0x00000000}, | ||
| 1498 | {0x0000825c, 0x40000000}, | ||
| 1499 | {0x00008260, 0x00080922}, | ||
| 1500 | {0x00008264, 0x99c00010}, | ||
| 1501 | {0x00008268, 0xffffffff}, | ||
| 1502 | {0x0000826c, 0x0000ffff}, | ||
| 1503 | {0x00008270, 0x00000000}, | ||
| 1504 | {0x00008274, 0x40000000}, | ||
| 1505 | {0x00008278, 0x003e4180}, | ||
| 1506 | {0x0000827c, 0x00000004}, | ||
| 1507 | {0x00008284, 0x0000002c}, | ||
| 1508 | {0x00008288, 0x0000002c}, | ||
| 1509 | {0x0000828c, 0x000000ff}, | ||
| 1510 | {0x00008294, 0x00000000}, | ||
| 1511 | {0x00008298, 0x00000000}, | ||
| 1512 | {0x0000829c, 0x00000000}, | ||
| 1513 | {0x00008300, 0x00000140}, | ||
| 1514 | {0x00008314, 0x00000000}, | ||
| 1515 | {0x0000831c, 0x0000010d}, | ||
| 1516 | {0x00008328, 0x00000000}, | ||
| 1517 | {0x0000832c, 0x0000001f}, | ||
| 1518 | {0x00008330, 0x00000302}, | ||
| 1519 | {0x00008334, 0x00000700}, | ||
| 1520 | {0x00008338, 0xffff0000}, | ||
| 1521 | {0x0000833c, 0x02400000}, | ||
| 1522 | {0x00008340, 0x000107ff}, | ||
| 1523 | {0x00008344, 0xaa48105b}, | ||
| 1524 | {0x00008348, 0x008f0000}, | ||
| 1525 | {0x0000835c, 0x00000000}, | ||
| 1526 | {0x00008360, 0xffffffff}, | ||
| 1527 | {0x00008364, 0xffffffff}, | ||
| 1528 | {0x00008368, 0x00000000}, | ||
| 1529 | {0x00008370, 0x00000000}, | ||
| 1530 | {0x00008374, 0x000000ff}, | ||
| 1531 | {0x00008378, 0x00000000}, | ||
| 1532 | {0x0000837c, 0x00000000}, | ||
| 1533 | {0x00008380, 0xffffffff}, | ||
| 1534 | {0x00008384, 0xffffffff}, | ||
| 1535 | {0x00008390, 0xffffffff}, | ||
| 1536 | {0x00008394, 0xffffffff}, | ||
| 1537 | {0x00008398, 0x00000000}, | ||
| 1538 | {0x0000839c, 0x00000000}, | ||
| 1539 | {0x000083a4, 0x0000fa14}, | ||
| 1540 | {0x000083a8, 0x000f0c00}, | ||
| 1541 | {0x000083ac, 0x33332210}, | ||
| 1542 | {0x000083b0, 0x33332210}, | ||
| 1543 | {0x000083b4, 0x33332210}, | ||
| 1544 | {0x000083b8, 0x33332210}, | ||
| 1545 | {0x000083bc, 0x00000000}, | ||
| 1546 | {0x000083c0, 0x00000000}, | ||
| 1547 | {0x000083c4, 0x00000000}, | ||
| 1548 | {0x000083c8, 0x00000000}, | ||
| 1549 | {0x000083cc, 0x00000200}, | ||
| 1550 | {0x000083d0, 0x000301ff}, | ||
| 1551 | }; | ||
| 1552 | |||
| 1553 | static const u32 ar9480_2p0_mac_postamble[][5] = { | ||
| 1554 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 1555 | {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, | ||
| 1556 | {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, | ||
| 1557 | {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38}, | ||
| 1558 | {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00}, | ||
| 1559 | {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b}, | ||
| 1560 | {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810}, | ||
| 1561 | {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a}, | ||
| 1562 | {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, | ||
| 1563 | }; | ||
| 1564 | |||
| 1565 | static const u32 ar9480_common_mixed_rx_gain_table_2p0[][2] = { | ||
| 1566 | /* Addr allmodes */ | ||
| 1567 | {0x0000a000, 0x00010000}, | ||
| 1568 | {0x0000a004, 0x00030002}, | ||
| 1569 | {0x0000a008, 0x00050004}, | ||
| 1570 | {0x0000a00c, 0x00810080}, | ||
| 1571 | {0x0000a010, 0x00830082}, | ||
| 1572 | {0x0000a014, 0x01810180}, | ||
| 1573 | {0x0000a018, 0x01830182}, | ||
| 1574 | {0x0000a01c, 0x01850184}, | ||
| 1575 | {0x0000a020, 0x01890188}, | ||
| 1576 | {0x0000a024, 0x018b018a}, | ||
| 1577 | {0x0000a028, 0x018d018c}, | ||
| 1578 | {0x0000a02c, 0x03820190}, | ||
| 1579 | {0x0000a030, 0x03840383}, | ||
| 1580 | {0x0000a034, 0x03880385}, | ||
| 1581 | {0x0000a038, 0x038a0389}, | ||
| 1582 | {0x0000a03c, 0x038c038b}, | ||
| 1583 | {0x0000a040, 0x0390038d}, | ||
| 1584 | {0x0000a044, 0x03920391}, | ||
| 1585 | {0x0000a048, 0x03940393}, | ||
| 1586 | {0x0000a04c, 0x03960395}, | ||
| 1587 | {0x0000a050, 0x00000000}, | ||
| 1588 | {0x0000a054, 0x00000000}, | ||
| 1589 | {0x0000a058, 0x00000000}, | ||
| 1590 | {0x0000a05c, 0x00000000}, | ||
| 1591 | {0x0000a060, 0x00000000}, | ||
| 1592 | {0x0000a064, 0x00000000}, | ||
| 1593 | {0x0000a068, 0x00000000}, | ||
| 1594 | {0x0000a06c, 0x00000000}, | ||
| 1595 | {0x0000a070, 0x00000000}, | ||
| 1596 | {0x0000a074, 0x00000000}, | ||
| 1597 | {0x0000a078, 0x00000000}, | ||
| 1598 | {0x0000a07c, 0x00000000}, | ||
| 1599 | {0x0000a080, 0x29292929}, | ||
| 1600 | {0x0000a084, 0x29292929}, | ||
| 1601 | {0x0000a088, 0x29292929}, | ||
| 1602 | {0x0000a08c, 0x29292929}, | ||
| 1603 | {0x0000a090, 0x22292929}, | ||
| 1604 | {0x0000a094, 0x1d1d2222}, | ||
| 1605 | {0x0000a098, 0x0c111117}, | ||
| 1606 | {0x0000a09c, 0x00030303}, | ||
| 1607 | {0x0000a0a0, 0x00000000}, | ||
| 1608 | {0x0000a0a4, 0x00000000}, | ||
| 1609 | {0x0000a0a8, 0x00000000}, | ||
| 1610 | {0x0000a0ac, 0x00000000}, | ||
| 1611 | {0x0000a0b0, 0x00000000}, | ||
| 1612 | {0x0000a0b4, 0x00000000}, | ||
| 1613 | {0x0000a0b8, 0x00000000}, | ||
| 1614 | {0x0000a0bc, 0x00000000}, | ||
| 1615 | {0x0000a0c0, 0x001f0000}, | ||
| 1616 | {0x0000a0c4, 0x01000101}, | ||
| 1617 | {0x0000a0c8, 0x011e011f}, | ||
| 1618 | {0x0000a0cc, 0x011c011d}, | ||
| 1619 | {0x0000a0d0, 0x02030204}, | ||
| 1620 | {0x0000a0d4, 0x02010202}, | ||
| 1621 | {0x0000a0d8, 0x021f0200}, | ||
| 1622 | {0x0000a0dc, 0x0302021e}, | ||
| 1623 | {0x0000a0e0, 0x03000301}, | ||
| 1624 | {0x0000a0e4, 0x031e031f}, | ||
| 1625 | {0x0000a0e8, 0x0402031d}, | ||
| 1626 | {0x0000a0ec, 0x04000401}, | ||
| 1627 | {0x0000a0f0, 0x041e041f}, | ||
| 1628 | {0x0000a0f4, 0x0502041d}, | ||
| 1629 | {0x0000a0f8, 0x05000501}, | ||
| 1630 | {0x0000a0fc, 0x051e051f}, | ||
| 1631 | {0x0000a100, 0x06010602}, | ||
| 1632 | {0x0000a104, 0x061f0600}, | ||
| 1633 | {0x0000a108, 0x061d061e}, | ||
| 1634 | {0x0000a10c, 0x07020703}, | ||
| 1635 | {0x0000a110, 0x07000701}, | ||
| 1636 | {0x0000a114, 0x00000000}, | ||
| 1637 | {0x0000a118, 0x00000000}, | ||
| 1638 | {0x0000a11c, 0x00000000}, | ||
| 1639 | {0x0000a120, 0x00000000}, | ||
| 1640 | {0x0000a124, 0x00000000}, | ||
| 1641 | {0x0000a128, 0x00000000}, | ||
| 1642 | {0x0000a12c, 0x00000000}, | ||
| 1643 | {0x0000a130, 0x00000000}, | ||
| 1644 | {0x0000a134, 0x00000000}, | ||
| 1645 | {0x0000a138, 0x00000000}, | ||
| 1646 | {0x0000a13c, 0x00000000}, | ||
| 1647 | {0x0000a140, 0x001f0000}, | ||
| 1648 | {0x0000a144, 0x01000101}, | ||
| 1649 | {0x0000a148, 0x011e011f}, | ||
| 1650 | {0x0000a14c, 0x011c011d}, | ||
| 1651 | {0x0000a150, 0x02030204}, | ||
| 1652 | {0x0000a154, 0x02010202}, | ||
| 1653 | {0x0000a158, 0x021f0200}, | ||
| 1654 | {0x0000a15c, 0x0302021e}, | ||
| 1655 | {0x0000a160, 0x03000301}, | ||
| 1656 | {0x0000a164, 0x031e031f}, | ||
| 1657 | {0x0000a168, 0x0402031d}, | ||
| 1658 | {0x0000a16c, 0x04000401}, | ||
| 1659 | {0x0000a170, 0x041e041f}, | ||
| 1660 | {0x0000a174, 0x0502041d}, | ||
| 1661 | {0x0000a178, 0x05000501}, | ||
| 1662 | {0x0000a17c, 0x051e051f}, | ||
| 1663 | {0x0000a180, 0x06010602}, | ||
| 1664 | {0x0000a184, 0x061f0600}, | ||
| 1665 | {0x0000a188, 0x061d061e}, | ||
| 1666 | {0x0000a18c, 0x07020703}, | ||
| 1667 | {0x0000a190, 0x07000701}, | ||
| 1668 | {0x0000a194, 0x00000000}, | ||
| 1669 | {0x0000a198, 0x00000000}, | ||
| 1670 | {0x0000a19c, 0x00000000}, | ||
| 1671 | {0x0000a1a0, 0x00000000}, | ||
| 1672 | {0x0000a1a4, 0x00000000}, | ||
| 1673 | {0x0000a1a8, 0x00000000}, | ||
| 1674 | {0x0000a1ac, 0x00000000}, | ||
| 1675 | {0x0000a1b0, 0x00000000}, | ||
| 1676 | {0x0000a1b4, 0x00000000}, | ||
| 1677 | {0x0000a1b8, 0x00000000}, | ||
| 1678 | {0x0000a1bc, 0x00000000}, | ||
| 1679 | {0x0000a1c0, 0x00000000}, | ||
| 1680 | {0x0000a1c4, 0x00000000}, | ||
| 1681 | {0x0000a1c8, 0x00000000}, | ||
| 1682 | {0x0000a1cc, 0x00000000}, | ||
| 1683 | {0x0000a1d0, 0x00000000}, | ||
| 1684 | {0x0000a1d4, 0x00000000}, | ||
| 1685 | {0x0000a1d8, 0x00000000}, | ||
| 1686 | {0x0000a1dc, 0x00000000}, | ||
| 1687 | {0x0000a1e0, 0x00000000}, | ||
| 1688 | {0x0000a1e4, 0x00000000}, | ||
| 1689 | {0x0000a1e8, 0x00000000}, | ||
| 1690 | {0x0000a1ec, 0x00000000}, | ||
| 1691 | {0x0000a1f0, 0x00000396}, | ||
| 1692 | {0x0000a1f4, 0x00000396}, | ||
| 1693 | {0x0000a1f8, 0x00000396}, | ||
| 1694 | {0x0000a1fc, 0x00000196}, | ||
| 1695 | {0x0000b000, 0x00010000}, | ||
| 1696 | {0x0000b004, 0x00030002}, | ||
| 1697 | {0x0000b008, 0x00050004}, | ||
| 1698 | {0x0000b00c, 0x00810080}, | ||
| 1699 | {0x0000b010, 0x00830082}, | ||
| 1700 | {0x0000b014, 0x01810180}, | ||
| 1701 | {0x0000b018, 0x01830182}, | ||
| 1702 | {0x0000b01c, 0x01850184}, | ||
| 1703 | {0x0000b020, 0x02810280}, | ||
| 1704 | {0x0000b024, 0x02830282}, | ||
| 1705 | {0x0000b028, 0x02850284}, | ||
| 1706 | {0x0000b02c, 0x02890288}, | ||
| 1707 | {0x0000b030, 0x028b028a}, | ||
| 1708 | {0x0000b034, 0x0388028c}, | ||
| 1709 | {0x0000b038, 0x038a0389}, | ||
| 1710 | {0x0000b03c, 0x038c038b}, | ||
| 1711 | {0x0000b040, 0x0390038d}, | ||
| 1712 | {0x0000b044, 0x03920391}, | ||
| 1713 | {0x0000b048, 0x03940393}, | ||
| 1714 | {0x0000b04c, 0x03960395}, | ||
| 1715 | {0x0000b050, 0x00000000}, | ||
| 1716 | {0x0000b054, 0x00000000}, | ||
| 1717 | {0x0000b058, 0x00000000}, | ||
| 1718 | {0x0000b05c, 0x00000000}, | ||
| 1719 | {0x0000b060, 0x00000000}, | ||
| 1720 | {0x0000b064, 0x00000000}, | ||
| 1721 | {0x0000b068, 0x00000000}, | ||
| 1722 | {0x0000b06c, 0x00000000}, | ||
| 1723 | {0x0000b070, 0x00000000}, | ||
| 1724 | {0x0000b074, 0x00000000}, | ||
| 1725 | {0x0000b078, 0x00000000}, | ||
| 1726 | {0x0000b07c, 0x00000000}, | ||
| 1727 | {0x0000b080, 0x2a2d2f32}, | ||
| 1728 | {0x0000b084, 0x21232328}, | ||
| 1729 | {0x0000b088, 0x19191c1e}, | ||
| 1730 | {0x0000b08c, 0x12141417}, | ||
| 1731 | {0x0000b090, 0x07070e0e}, | ||
| 1732 | {0x0000b094, 0x03030305}, | ||
| 1733 | {0x0000b098, 0x00000003}, | ||
| 1734 | {0x0000b09c, 0x00000000}, | ||
| 1735 | {0x0000b0a0, 0x00000000}, | ||
| 1736 | {0x0000b0a4, 0x00000000}, | ||
| 1737 | {0x0000b0a8, 0x00000000}, | ||
| 1738 | {0x0000b0ac, 0x00000000}, | ||
| 1739 | {0x0000b0b0, 0x00000000}, | ||
| 1740 | {0x0000b0b4, 0x00000000}, | ||
| 1741 | {0x0000b0b8, 0x00000000}, | ||
| 1742 | {0x0000b0bc, 0x00000000}, | ||
| 1743 | {0x0000b0c0, 0x003f0020}, | ||
| 1744 | {0x0000b0c4, 0x00400041}, | ||
| 1745 | {0x0000b0c8, 0x0140005f}, | ||
| 1746 | {0x0000b0cc, 0x0160015f}, | ||
| 1747 | {0x0000b0d0, 0x017e017f}, | ||
| 1748 | {0x0000b0d4, 0x02410242}, | ||
| 1749 | {0x0000b0d8, 0x025f0240}, | ||
| 1750 | {0x0000b0dc, 0x027f0260}, | ||
| 1751 | {0x0000b0e0, 0x0341027e}, | ||
| 1752 | {0x0000b0e4, 0x035f0340}, | ||
| 1753 | {0x0000b0e8, 0x037f0360}, | ||
| 1754 | {0x0000b0ec, 0x04400441}, | ||
| 1755 | {0x0000b0f0, 0x0460045f}, | ||
| 1756 | {0x0000b0f4, 0x0541047f}, | ||
| 1757 | {0x0000b0f8, 0x055f0540}, | ||
| 1758 | {0x0000b0fc, 0x057f0560}, | ||
| 1759 | {0x0000b100, 0x06400641}, | ||
| 1760 | {0x0000b104, 0x0660065f}, | ||
| 1761 | {0x0000b108, 0x067e067f}, | ||
| 1762 | {0x0000b10c, 0x07410742}, | ||
| 1763 | {0x0000b110, 0x075f0740}, | ||
| 1764 | {0x0000b114, 0x077f0760}, | ||
| 1765 | {0x0000b118, 0x07800781}, | ||
| 1766 | {0x0000b11c, 0x07a0079f}, | ||
| 1767 | {0x0000b120, 0x07c107bf}, | ||
| 1768 | {0x0000b124, 0x000007c0}, | ||
| 1769 | {0x0000b128, 0x00000000}, | ||
| 1770 | {0x0000b12c, 0x00000000}, | ||
| 1771 | {0x0000b130, 0x00000000}, | ||
| 1772 | {0x0000b134, 0x00000000}, | ||
| 1773 | {0x0000b138, 0x00000000}, | ||
| 1774 | {0x0000b13c, 0x00000000}, | ||
| 1775 | {0x0000b140, 0x003f0020}, | ||
| 1776 | {0x0000b144, 0x00400041}, | ||
| 1777 | {0x0000b148, 0x0140005f}, | ||
| 1778 | {0x0000b14c, 0x0160015f}, | ||
| 1779 | {0x0000b150, 0x017e017f}, | ||
| 1780 | {0x0000b154, 0x02410242}, | ||
| 1781 | {0x0000b158, 0x025f0240}, | ||
| 1782 | {0x0000b15c, 0x027f0260}, | ||
| 1783 | {0x0000b160, 0x0341027e}, | ||
| 1784 | {0x0000b164, 0x035f0340}, | ||
| 1785 | {0x0000b168, 0x037f0360}, | ||
| 1786 | {0x0000b16c, 0x04400441}, | ||
| 1787 | {0x0000b170, 0x0460045f}, | ||
| 1788 | {0x0000b174, 0x0541047f}, | ||
| 1789 | {0x0000b178, 0x055f0540}, | ||
| 1790 | {0x0000b17c, 0x057f0560}, | ||
| 1791 | {0x0000b180, 0x06400641}, | ||
| 1792 | {0x0000b184, 0x0660065f}, | ||
| 1793 | {0x0000b188, 0x067e067f}, | ||
| 1794 | {0x0000b18c, 0x07410742}, | ||
| 1795 | {0x0000b190, 0x075f0740}, | ||
| 1796 | {0x0000b194, 0x077f0760}, | ||
| 1797 | {0x0000b198, 0x07800781}, | ||
| 1798 | {0x0000b19c, 0x07a0079f}, | ||
| 1799 | {0x0000b1a0, 0x07c107bf}, | ||
| 1800 | {0x0000b1a4, 0x000007c0}, | ||
| 1801 | {0x0000b1a8, 0x00000000}, | ||
| 1802 | {0x0000b1ac, 0x00000000}, | ||
| 1803 | {0x0000b1b0, 0x00000000}, | ||
| 1804 | {0x0000b1b4, 0x00000000}, | ||
| 1805 | {0x0000b1b8, 0x00000000}, | ||
| 1806 | {0x0000b1bc, 0x00000000}, | ||
| 1807 | {0x0000b1c0, 0x00000000}, | ||
| 1808 | {0x0000b1c4, 0x00000000}, | ||
| 1809 | {0x0000b1c8, 0x00000000}, | ||
| 1810 | {0x0000b1cc, 0x00000000}, | ||
| 1811 | {0x0000b1d0, 0x00000000}, | ||
| 1812 | {0x0000b1d4, 0x00000000}, | ||
| 1813 | {0x0000b1d8, 0x00000000}, | ||
| 1814 | {0x0000b1dc, 0x00000000}, | ||
| 1815 | {0x0000b1e0, 0x00000000}, | ||
| 1816 | {0x0000b1e4, 0x00000000}, | ||
| 1817 | {0x0000b1e8, 0x00000000}, | ||
| 1818 | {0x0000b1ec, 0x00000000}, | ||
| 1819 | {0x0000b1f0, 0x00000396}, | ||
| 1820 | {0x0000b1f4, 0x00000396}, | ||
| 1821 | {0x0000b1f8, 0x00000396}, | ||
| 1822 | {0x0000b1fc, 0x00000196}, | ||
| 1823 | }; | ||
| 1824 | |||
| 1825 | static const u32 ar9480_modes_green_ob_db_tx_gain_table_2p0[][5] = { | ||
| 1826 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | ||
| 1827 | {0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003}, | ||
| 1828 | {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, | ||
| 1829 | {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, | ||
| 1830 | {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, | ||
| 1831 | {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, | ||
| 1832 | {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, | ||
| 1833 | {0x0000a458, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, | ||
| 1834 | {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, | ||
| 1835 | {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002}, | ||
| 1836 | {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004}, | ||
| 1837 | {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200}, | ||
| 1838 | {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202}, | ||
| 1839 | {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400}, | ||
| 1840 | {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402}, | ||
| 1841 | {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404}, | ||
| 1842 | {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603}, | ||
| 1843 | {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02}, | ||
| 1844 | {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04}, | ||
| 1845 | {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20}, | ||
| 1846 | {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20}, | ||
| 1847 | {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22}, | ||
| 1848 | {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24}, | ||
| 1849 | {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640}, | ||
| 1850 | {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660}, | ||
| 1851 | {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861}, | ||
| 1852 | {0x0000a548, 0x53025eb2, 0x53025eb2, 0x3e001a81, 0x3e001a81}, | ||
| 1853 | {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83}, | ||
| 1854 | {0x0000a550, 0x5f025ef6, 0x5f025ef6, 0x44001c84, 0x44001c84}, | ||
| 1855 | {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3}, | ||
| 1856 | {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5}, | ||
| 1857 | {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9}, | ||
| 1858 | {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb}, | ||
| 1859 | {0x0000a564, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 1860 | {0x0000a568, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 1861 | {0x0000a56c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 1862 | {0x0000a570, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 1863 | {0x0000a574, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 1864 | {0x0000a578, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 1865 | {0x0000a57c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec}, | ||
| 1866 | {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1867 | {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1868 | {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1869 | {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, | ||
| 1870 | {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000}, | ||
| 1871 | {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000}, | ||
| 1872 | {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501}, | ||
| 1873 | {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501}, | ||
| 1874 | {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03}, | ||
| 1875 | {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04}, | ||
| 1876 | {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04}, | ||
| 1877 | {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, | ||
| 1878 | {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, | ||
| 1879 | {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, | ||
| 1880 | {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, | ||
| 1881 | {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, | ||
| 1882 | {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, | ||
| 1883 | {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, | ||
| 1884 | {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, | ||
| 1885 | {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, | ||
| 1886 | {0x00016044, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4}, | ||
| 1887 | {0x00016048, 0x8db49060, 0x8db49060, 0x8db49060, 0x8db49060}, | ||
| 1888 | {0x00016054, 0x6db60180, 0x6db60180, 0x6db60180, 0x6db60180}, | ||
| 1889 | {0x00016444, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4}, | ||
| 1890 | {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000}, | ||
| 1891 | {0x00016454, 0x6db60180, 0x6db60180, 0x6db60180, 0x6db60180}, | ||
| 1892 | }; | ||
| 1893 | |||
| 1894 | static const u32 ar9480_2p0_BTCOEX_MAX_TXPWR_table[][2] = { | ||
| 1895 | /* Addr allmodes */ | ||
| 1896 | {0x000018c0, 0x10101010}, | ||
| 1897 | {0x000018c4, 0x10101010}, | ||
| 1898 | {0x000018c8, 0x10101010}, | ||
| 1899 | {0x000018cc, 0x10101010}, | ||
| 1900 | {0x000018d0, 0x10101010}, | ||
| 1901 | {0x000018d4, 0x10101010}, | ||
| 1902 | {0x000018d8, 0x10101010}, | ||
| 1903 | {0x000018dc, 0x10101010}, | ||
| 1904 | }; | ||
| 1905 | |||
| 1906 | static const u32 ar9480_2p0_baseband_core_emulation[][2] = { | ||
| 1907 | /* Addr allmodes */ | ||
| 1908 | {0x00009800, 0xafa68e30}, | ||
| 1909 | {0x00009884, 0x00002842}, | ||
| 1910 | {0x00009c04, 0xff55ff55}, | ||
| 1911 | {0x00009c08, 0x0320ff55}, | ||
| 1912 | {0x00009e50, 0x00000000}, | ||
| 1913 | {0x00009fcc, 0x00000014}, | ||
| 1914 | {0x0000a344, 0x00000010}, | ||
| 1915 | {0x0000a398, 0x00000000}, | ||
| 1916 | {0x0000a39c, 0x71733d01}, | ||
| 1917 | {0x0000a3a0, 0xd0ad5c12}, | ||
| 1918 | {0x0000a3c0, 0x22222220}, | ||
| 1919 | {0x0000a3c4, 0x22222222}, | ||
| 1920 | {0x0000a404, 0x00418a11}, | ||
| 1921 | {0x0000a418, 0x050001ce}, | ||
| 1922 | {0x0000a438, 0x00001800}, | ||
| 1923 | {0x0000a458, 0x01444452}, | ||
| 1924 | {0x0000a644, 0x3fad9d74}, | ||
| 1925 | {0x0000a690, 0x00000038}, | ||
| 1926 | }; | ||
| 1927 | |||
| 1928 | #endif /* INITVALS_9480_2P0_H */ | ||
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h index 5d9a9aabe476..94d887b65e69 100644 --- a/drivers/net/wireless/ath/ath9k/ath9k.h +++ b/drivers/net/wireless/ath/ath9k/ath9k.h | |||
| @@ -87,17 +87,14 @@ struct ath_config { | |||
| 87 | * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) | 87 | * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) |
| 88 | * @BUF_AGGR: Indicates whether the buffer can be aggregated | 88 | * @BUF_AGGR: Indicates whether the buffer can be aggregated |
| 89 | * (used in aggregation scheduling) | 89 | * (used in aggregation scheduling) |
| 90 | * @BUF_XRETRY: To denote excessive retries of the buffer | ||
| 91 | */ | 90 | */ |
| 92 | enum buffer_type { | 91 | enum buffer_type { |
| 93 | BUF_AMPDU = BIT(0), | 92 | BUF_AMPDU = BIT(0), |
| 94 | BUF_AGGR = BIT(1), | 93 | BUF_AGGR = BIT(1), |
| 95 | BUF_XRETRY = BIT(2), | ||
| 96 | }; | 94 | }; |
| 97 | 95 | ||
| 98 | #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) | 96 | #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) |
| 99 | #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) | 97 | #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) |
| 100 | #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) | ||
| 101 | 98 | ||
| 102 | #define ATH_TXSTATUS_RING_SIZE 64 | 99 | #define ATH_TXSTATUS_RING_SIZE 64 |
| 103 | 100 | ||
| @@ -216,6 +213,7 @@ struct ath_frame_info { | |||
| 216 | struct ath_buf_state { | 213 | struct ath_buf_state { |
| 217 | u8 bf_type; | 214 | u8 bf_type; |
| 218 | u8 bfs_paprd; | 215 | u8 bfs_paprd; |
| 216 | u8 ndelim; | ||
| 219 | u16 seqno; | 217 | u16 seqno; |
| 220 | unsigned long bfs_paprd_timestamp; | 218 | unsigned long bfs_paprd_timestamp; |
| 221 | }; | 219 | }; |
| @@ -230,7 +228,6 @@ struct ath_buf { | |||
| 230 | dma_addr_t bf_daddr; /* physical addr of desc */ | 228 | dma_addr_t bf_daddr; /* physical addr of desc */ |
| 231 | dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ | 229 | dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ |
| 232 | bool bf_stale; | 230 | bool bf_stale; |
| 233 | u16 bf_flags; | ||
| 234 | struct ath_buf_state bf_state; | 231 | struct ath_buf_state bf_state; |
| 235 | }; | 232 | }; |
| 236 | 233 | ||
| @@ -277,8 +274,7 @@ struct ath_tx_control { | |||
| 277 | }; | 274 | }; |
| 278 | 275 | ||
| 279 | #define ATH_TX_ERROR 0x01 | 276 | #define ATH_TX_ERROR 0x01 |
| 280 | #define ATH_TX_XRETRY 0x02 | 277 | #define ATH_TX_BAR 0x02 |
| 281 | #define ATH_TX_BAR 0x04 | ||
| 282 | 278 | ||
| 283 | /** | 279 | /** |
| 284 | * @txq_map: Index is mac80211 queue number. This is | 280 | * @txq_map: Index is mac80211 queue number. This is |
| @@ -425,6 +421,7 @@ void ath9k_set_beaconing_status(struct ath_softc *sc, bool status); | |||
| 425 | 421 | ||
| 426 | #define ATH_PAPRD_TIMEOUT 100 /* msecs */ | 422 | #define ATH_PAPRD_TIMEOUT 100 /* msecs */ |
| 427 | 423 | ||
| 424 | void ath_reset_work(struct work_struct *work); | ||
| 428 | void ath_hw_check(struct work_struct *work); | 425 | void ath_hw_check(struct work_struct *work); |
| 429 | void ath_hw_pll_work(struct work_struct *work); | 426 | void ath_hw_pll_work(struct work_struct *work); |
| 430 | void ath_paprd_calibrate(struct work_struct *work); | 427 | void ath_paprd_calibrate(struct work_struct *work); |
| @@ -460,6 +457,7 @@ void ath9k_btcoex_timer_pause(struct ath_softc *sc); | |||
| 460 | #define ATH_LED_PIN_9287 8 | 457 | #define ATH_LED_PIN_9287 8 |
| 461 | #define ATH_LED_PIN_9300 10 | 458 | #define ATH_LED_PIN_9300 10 |
| 462 | #define ATH_LED_PIN_9485 6 | 459 | #define ATH_LED_PIN_9485 6 |
| 460 | #define ATH_LED_PIN_9480 0 | ||
| 463 | 461 | ||
| 464 | #ifdef CONFIG_MAC80211_LEDS | 462 | #ifdef CONFIG_MAC80211_LEDS |
| 465 | void ath_init_leds(struct ath_softc *sc); | 463 | void ath_init_leds(struct ath_softc *sc); |
| @@ -604,6 +602,7 @@ struct ath_softc { | |||
| 604 | struct mutex mutex; | 602 | struct mutex mutex; |
| 605 | struct work_struct paprd_work; | 603 | struct work_struct paprd_work; |
| 606 | struct work_struct hw_check_work; | 604 | struct work_struct hw_check_work; |
| 605 | struct work_struct hw_reset_work; | ||
| 607 | struct completion paprd_complete; | 606 | struct completion paprd_complete; |
| 608 | 607 | ||
| 609 | unsigned int hw_busy_count; | 608 | unsigned int hw_busy_count; |
| @@ -647,10 +646,10 @@ struct ath_softc { | |||
| 647 | struct ath_descdma txsdma; | 646 | struct ath_descdma txsdma; |
| 648 | 647 | ||
| 649 | struct ath_ant_comb ant_comb; | 648 | struct ath_ant_comb ant_comb; |
| 649 | u8 ant_tx, ant_rx; | ||
| 650 | }; | 650 | }; |
| 651 | 651 | ||
| 652 | void ath9k_tasklet(unsigned long data); | 652 | void ath9k_tasklet(unsigned long data); |
| 653 | int ath_reset(struct ath_softc *sc, bool retry_tx); | ||
| 654 | int ath_cabq_update(struct ath_softc *); | 653 | int ath_cabq_update(struct ath_softc *); |
| 655 | 654 | ||
| 656 | static inline void ath_read_cachesize(struct ath_common *common, int *csz) | 655 | static inline void ath_read_cachesize(struct ath_common *common, int *csz) |
| @@ -668,6 +667,7 @@ int ath9k_init_device(u16 devid, struct ath_softc *sc, | |||
| 668 | const struct ath_bus_ops *bus_ops); | 667 | const struct ath_bus_ops *bus_ops); |
| 669 | void ath9k_deinit_device(struct ath_softc *sc); | 668 | void ath9k_deinit_device(struct ath_softc *sc); |
| 670 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); | 669 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); |
| 670 | void ath9k_reload_chainmask_settings(struct ath_softc *sc); | ||
| 671 | 671 | ||
| 672 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw); | 672 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw); |
| 673 | bool ath9k_uses_beacons(int type); | 673 | bool ath9k_uses_beacons(int type); |
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c index 086c9c816bf7..9cdeaebc844f 100644 --- a/drivers/net/wireless/ath/ath9k/beacon.c +++ b/drivers/net/wireless/ath/ath9k/beacon.c | |||
| @@ -73,44 +73,39 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp, | |||
| 73 | struct sk_buff *skb = bf->bf_mpdu; | 73 | struct sk_buff *skb = bf->bf_mpdu; |
| 74 | struct ath_hw *ah = sc->sc_ah; | 74 | struct ath_hw *ah = sc->sc_ah; |
| 75 | struct ath_common *common = ath9k_hw_common(ah); | 75 | struct ath_common *common = ath9k_hw_common(ah); |
| 76 | struct ath_desc *ds; | 76 | struct ath_tx_info info; |
| 77 | struct ath9k_11n_rate_series series[4]; | ||
| 78 | int flags, ctsrate = 0, ctsduration = 0; | ||
| 79 | struct ieee80211_supported_band *sband; | 77 | struct ieee80211_supported_band *sband; |
| 78 | u8 chainmask = ah->txchainmask; | ||
| 80 | u8 rate = 0; | 79 | u8 rate = 0; |
| 81 | 80 | ||
| 82 | ath9k_reset_beacon_status(sc); | 81 | ath9k_reset_beacon_status(sc); |
| 83 | 82 | ||
| 84 | ds = bf->bf_desc; | ||
| 85 | flags = ATH9K_TXDESC_NOACK; | ||
| 86 | |||
| 87 | ds->ds_link = 0; | ||
| 88 | |||
| 89 | sband = &sc->sbands[common->hw->conf.channel->band]; | 83 | sband = &sc->sbands[common->hw->conf.channel->band]; |
| 90 | rate = sband->bitrates[rateidx].hw_value; | 84 | rate = sband->bitrates[rateidx].hw_value; |
| 91 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) | 85 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) |
| 92 | rate |= sband->bitrates[rateidx].hw_value_short; | 86 | rate |= sband->bitrates[rateidx].hw_value_short; |
| 93 | 87 | ||
| 94 | ath9k_hw_set11n_txdesc(ah, ds, skb->len + FCS_LEN, | 88 | memset(&info, 0, sizeof(info)); |
| 95 | ATH9K_PKT_TYPE_BEACON, | 89 | info.pkt_len = skb->len + FCS_LEN; |
| 96 | MAX_RATE_POWER, | 90 | info.type = ATH9K_PKT_TYPE_BEACON; |
| 97 | ATH9K_TXKEYIX_INVALID, | 91 | info.txpower = MAX_RATE_POWER; |
| 98 | ATH9K_KEY_TYPE_CLEAR, | 92 | info.keyix = ATH9K_TXKEYIX_INVALID; |
| 99 | flags); | 93 | info.keytype = ATH9K_KEY_TYPE_CLEAR; |
| 100 | 94 | info.flags = ATH9K_TXDESC_NOACK; | |
| 101 | /* NB: beacon's BufLen must be a multiple of 4 bytes */ | 95 | |
| 102 | ath9k_hw_filltxdesc(ah, ds, roundup(skb->len, 4), | 96 | info.buf_addr[0] = bf->bf_buf_addr; |
| 103 | true, true, ds, bf->bf_buf_addr, | 97 | info.buf_len[0] = roundup(skb->len, 4); |
| 104 | sc->beacon.beaconq); | 98 | |
| 105 | 99 | info.is_first = true; | |
| 106 | memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); | 100 | info.is_last = true; |
| 107 | series[0].Tries = 1; | 101 | |
| 108 | series[0].Rate = rate; | 102 | info.qcu = sc->beacon.beaconq; |
| 109 | series[0].ChSel = ath_txchainmask_reduction(sc, | 103 | |
| 110 | common->tx_chainmask, series[0].Rate); | 104 | info.rates[0].Tries = 1; |
| 111 | series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0; | 105 | info.rates[0].Rate = rate; |
| 112 | ath9k_hw_set11n_ratescenario(ah, ds, ds, 0, ctsrate, ctsduration, | 106 | info.rates[0].ChSel = ath_txchainmask_reduction(sc, chainmask, rate); |
| 113 | series, 4, 0); | 107 | |
| 108 | ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); | ||
| 114 | } | 109 | } |
| 115 | 110 | ||
| 116 | static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) | 111 | static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) |
| @@ -386,9 +381,7 @@ void ath_beacon_tasklet(unsigned long data) | |||
| 386 | ath_dbg(common, ATH_DBG_BSTUCK, | 381 | ath_dbg(common, ATH_DBG_BSTUCK, |
| 387 | "beacon is officially stuck\n"); | 382 | "beacon is officially stuck\n"); |
| 388 | sc->sc_flags |= SC_OP_TSF_RESET; | 383 | sc->sc_flags |= SC_OP_TSF_RESET; |
| 389 | spin_lock(&sc->sc_pcu_lock); | 384 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
| 390 | ath_reset(sc, true); | ||
| 391 | spin_unlock(&sc->sc_pcu_lock); | ||
| 392 | } | 385 | } |
| 393 | 386 | ||
| 394 | return; | 387 | return; |
| @@ -519,6 +512,7 @@ static void ath_beacon_config_ap(struct ath_softc *sc, | |||
| 519 | /* Set the computed AP beacon timers */ | 512 | /* Set the computed AP beacon timers */ |
| 520 | 513 | ||
| 521 | ath9k_hw_disable_interrupts(ah); | 514 | ath9k_hw_disable_interrupts(ah); |
| 515 | sc->sc_flags |= SC_OP_TSF_RESET; | ||
| 522 | ath9k_beacon_init(sc, nexttbtt, intval); | 516 | ath9k_beacon_init(sc, nexttbtt, intval); |
| 523 | sc->beacon.bmisscnt = 0; | 517 | sc->beacon.bmisscnt = 0; |
| 524 | ath9k_hw_set_interrupts(ah, ah->imask); | 518 | ath9k_hw_set_interrupts(ah, ah->imask); |
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c index 727e8de22fda..179da2099270 100644 --- a/drivers/net/wireless/ath/ath9k/debug.c +++ b/drivers/net/wireless/ath/ath9k/debug.c | |||
| @@ -95,11 +95,11 @@ static ssize_t read_file_tx_chainmask(struct file *file, char __user *user_buf, | |||
| 95 | size_t count, loff_t *ppos) | 95 | size_t count, loff_t *ppos) |
| 96 | { | 96 | { |
| 97 | struct ath_softc *sc = file->private_data; | 97 | struct ath_softc *sc = file->private_data; |
| 98 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | 98 | struct ath_hw *ah = sc->sc_ah; |
| 99 | char buf[32]; | 99 | char buf[32]; |
| 100 | unsigned int len; | 100 | unsigned int len; |
| 101 | 101 | ||
| 102 | len = sprintf(buf, "0x%08x\n", common->tx_chainmask); | 102 | len = sprintf(buf, "0x%08x\n", ah->txchainmask); |
| 103 | return simple_read_from_buffer(user_buf, count, ppos, buf, len); | 103 | return simple_read_from_buffer(user_buf, count, ppos, buf, len); |
| 104 | } | 104 | } |
| 105 | 105 | ||
| @@ -107,7 +107,7 @@ static ssize_t write_file_tx_chainmask(struct file *file, const char __user *use | |||
| 107 | size_t count, loff_t *ppos) | 107 | size_t count, loff_t *ppos) |
| 108 | { | 108 | { |
| 109 | struct ath_softc *sc = file->private_data; | 109 | struct ath_softc *sc = file->private_data; |
| 110 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | 110 | struct ath_hw *ah = sc->sc_ah; |
| 111 | unsigned long mask; | 111 | unsigned long mask; |
| 112 | char buf[32]; | 112 | char buf[32]; |
| 113 | ssize_t len; | 113 | ssize_t len; |
| @@ -120,8 +120,8 @@ static ssize_t write_file_tx_chainmask(struct file *file, const char __user *use | |||
| 120 | if (strict_strtoul(buf, 0, &mask)) | 120 | if (strict_strtoul(buf, 0, &mask)) |
| 121 | return -EINVAL; | 121 | return -EINVAL; |
| 122 | 122 | ||
| 123 | common->tx_chainmask = mask; | 123 | ah->txchainmask = mask; |
| 124 | sc->sc_ah->caps.tx_chainmask = mask; | 124 | ah->caps.tx_chainmask = mask; |
| 125 | return count; | 125 | return count; |
| 126 | } | 126 | } |
| 127 | 127 | ||
| @@ -138,11 +138,11 @@ static ssize_t read_file_rx_chainmask(struct file *file, char __user *user_buf, | |||
| 138 | size_t count, loff_t *ppos) | 138 | size_t count, loff_t *ppos) |
| 139 | { | 139 | { |
| 140 | struct ath_softc *sc = file->private_data; | 140 | struct ath_softc *sc = file->private_data; |
| 141 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | 141 | struct ath_hw *ah = sc->sc_ah; |
| 142 | char buf[32]; | 142 | char buf[32]; |
| 143 | unsigned int len; | 143 | unsigned int len; |
| 144 | 144 | ||
| 145 | len = sprintf(buf, "0x%08x\n", common->rx_chainmask); | 145 | len = sprintf(buf, "0x%08x\n", ah->rxchainmask); |
| 146 | return simple_read_from_buffer(user_buf, count, ppos, buf, len); | 146 | return simple_read_from_buffer(user_buf, count, ppos, buf, len); |
| 147 | } | 147 | } |
| 148 | 148 | ||
| @@ -150,7 +150,7 @@ static ssize_t write_file_rx_chainmask(struct file *file, const char __user *use | |||
| 150 | size_t count, loff_t *ppos) | 150 | size_t count, loff_t *ppos) |
| 151 | { | 151 | { |
| 152 | struct ath_softc *sc = file->private_data; | 152 | struct ath_softc *sc = file->private_data; |
| 153 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | 153 | struct ath_hw *ah = sc->sc_ah; |
| 154 | unsigned long mask; | 154 | unsigned long mask; |
| 155 | char buf[32]; | 155 | char buf[32]; |
| 156 | ssize_t len; | 156 | ssize_t len; |
| @@ -163,8 +163,8 @@ static ssize_t write_file_rx_chainmask(struct file *file, const char __user *use | |||
| 163 | if (strict_strtoul(buf, 0, &mask)) | 163 | if (strict_strtoul(buf, 0, &mask)) |
| 164 | return -EINVAL; | 164 | return -EINVAL; |
| 165 | 165 | ||
| 166 | common->rx_chainmask = mask; | 166 | ah->rxchainmask = mask; |
| 167 | sc->sc_ah->caps.rx_chainmask = mask; | 167 | ah->caps.rx_chainmask = mask; |
| 168 | return count; | 168 | return count; |
| 169 | } | 169 | } |
| 170 | 170 | ||
| @@ -826,7 +826,8 @@ static ssize_t read_file_misc(struct file *file, char __user *user_buf, | |||
| 826 | } | 826 | } |
| 827 | 827 | ||
| 828 | void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf, | 828 | void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf, |
| 829 | struct ath_tx_status *ts, struct ath_txq *txq) | 829 | struct ath_tx_status *ts, struct ath_txq *txq, |
| 830 | unsigned int flags) | ||
| 830 | { | 831 | { |
| 831 | #define TX_SAMP_DBG(c) (sc->debug.bb_mac_samp[sc->debug.sampidx].ts\ | 832 | #define TX_SAMP_DBG(c) (sc->debug.bb_mac_samp[sc->debug.sampidx].ts\ |
| 832 | [sc->debug.tsidx].c) | 833 | [sc->debug.tsidx].c) |
| @@ -836,12 +837,12 @@ void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf, | |||
| 836 | sc->debug.stats.txstats[qnum].tx_bytes_all += bf->bf_mpdu->len; | 837 | sc->debug.stats.txstats[qnum].tx_bytes_all += bf->bf_mpdu->len; |
| 837 | 838 | ||
| 838 | if (bf_isampdu(bf)) { | 839 | if (bf_isampdu(bf)) { |
| 839 | if (bf_isxretried(bf)) | 840 | if (flags & ATH_TX_BAR) |
| 840 | TX_STAT_INC(qnum, a_xretries); | 841 | TX_STAT_INC(qnum, a_xretries); |
| 841 | else | 842 | else |
| 842 | TX_STAT_INC(qnum, a_completed); | 843 | TX_STAT_INC(qnum, a_completed); |
| 843 | } else { | 844 | } else { |
| 844 | if (bf_isxretried(bf)) | 845 | if (ts->ts_status & ATH9K_TXERR_XRETRY) |
| 845 | TX_STAT_INC(qnum, xretries); | 846 | TX_STAT_INC(qnum, xretries); |
| 846 | else | 847 | else |
| 847 | TX_STAT_INC(qnum, completed); | 848 | TX_STAT_INC(qnum, completed); |
| @@ -1323,16 +1324,17 @@ void ath9k_debug_samp_bb_mac(struct ath_softc *sc) | |||
| 1323 | 1324 | ||
| 1324 | ath9k_ps_wakeup(sc); | 1325 | ath9k_ps_wakeup(sc); |
| 1325 | 1326 | ||
| 1327 | spin_lock_bh(&sc->debug.samp_lock); | ||
| 1328 | |||
| 1326 | spin_lock_irqsave(&common->cc_lock, flags); | 1329 | spin_lock_irqsave(&common->cc_lock, flags); |
| 1327 | ath_hw_cycle_counters_update(common); | 1330 | ath_hw_cycle_counters_update(common); |
| 1328 | spin_unlock_irqrestore(&common->cc_lock, flags); | ||
| 1329 | |||
| 1330 | spin_lock_bh(&sc->debug.samp_lock); | ||
| 1331 | 1331 | ||
| 1332 | ATH_SAMP_DBG(cc.cycles) = common->cc_ani.cycles; | 1332 | ATH_SAMP_DBG(cc.cycles) = common->cc_ani.cycles; |
| 1333 | ATH_SAMP_DBG(cc.rx_busy) = common->cc_ani.rx_busy; | 1333 | ATH_SAMP_DBG(cc.rx_busy) = common->cc_ani.rx_busy; |
| 1334 | ATH_SAMP_DBG(cc.rx_frame) = common->cc_ani.rx_frame; | 1334 | ATH_SAMP_DBG(cc.rx_frame) = common->cc_ani.rx_frame; |
| 1335 | ATH_SAMP_DBG(cc.tx_frame) = common->cc_ani.tx_frame; | 1335 | ATH_SAMP_DBG(cc.tx_frame) = common->cc_ani.tx_frame; |
| 1336 | spin_unlock_irqrestore(&common->cc_lock, flags); | ||
| 1337 | |||
| 1336 | ATH_SAMP_DBG(noise) = ah->noise; | 1338 | ATH_SAMP_DBG(noise) = ah->noise; |
| 1337 | 1339 | ||
| 1338 | REG_WRITE_D(ah, AR_MACMISC, | 1340 | REG_WRITE_D(ah, AR_MACMISC, |
| @@ -1373,6 +1375,9 @@ static int open_file_bb_mac_samps(struct inode *inode, struct file *file) | |||
| 1373 | u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask; | 1375 | u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask; |
| 1374 | u8 nread; | 1376 | u8 nread; |
| 1375 | 1377 | ||
| 1378 | if (sc->sc_flags & SC_OP_INVALID) | ||
| 1379 | return -EAGAIN; | ||
| 1380 | |||
| 1376 | buf = vmalloc(size); | 1381 | buf = vmalloc(size); |
| 1377 | if (!buf) | 1382 | if (!buf) |
| 1378 | return -ENOMEM; | 1383 | return -ENOMEM; |
| @@ -1381,10 +1386,14 @@ static int open_file_bb_mac_samps(struct inode *inode, struct file *file) | |||
| 1381 | vfree(buf); | 1386 | vfree(buf); |
| 1382 | return -ENOMEM; | 1387 | return -ENOMEM; |
| 1383 | } | 1388 | } |
| 1389 | /* Account the current state too */ | ||
| 1390 | ath9k_debug_samp_bb_mac(sc); | ||
| 1384 | 1391 | ||
| 1385 | spin_lock_bh(&sc->debug.samp_lock); | 1392 | spin_lock_bh(&sc->debug.samp_lock); |
| 1386 | memcpy(bb_mac_samp, sc->debug.bb_mac_samp, | 1393 | memcpy(bb_mac_samp, sc->debug.bb_mac_samp, |
| 1387 | sizeof(*bb_mac_samp) * ATH_DBG_MAX_SAMPLES); | 1394 | sizeof(*bb_mac_samp) * ATH_DBG_MAX_SAMPLES); |
| 1395 | len += snprintf(buf + len, size - len, | ||
| 1396 | "Current Sample Index: %d\n", sc->debug.sampidx); | ||
| 1388 | spin_unlock_bh(&sc->debug.samp_lock); | 1397 | spin_unlock_bh(&sc->debug.samp_lock); |
| 1389 | 1398 | ||
| 1390 | len += snprintf(buf + len, size - len, | 1399 | len += snprintf(buf + len, size - len, |
diff --git a/drivers/net/wireless/ath/ath9k/debug.h b/drivers/net/wireless/ath/ath9k/debug.h index 95f85bdc8db7..39f89bc9abcd 100644 --- a/drivers/net/wireless/ath/ath9k/debug.h +++ b/drivers/net/wireless/ath/ath9k/debug.h | |||
| @@ -230,7 +230,8 @@ int ath9k_init_debug(struct ath_hw *ah); | |||
| 230 | void ath9k_debug_samp_bb_mac(struct ath_softc *sc); | 230 | void ath9k_debug_samp_bb_mac(struct ath_softc *sc); |
| 231 | void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status); | 231 | void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status); |
| 232 | void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf, | 232 | void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf, |
| 233 | struct ath_tx_status *ts, struct ath_txq *txq); | 233 | struct ath_tx_status *ts, struct ath_txq *txq, |
| 234 | unsigned int flags); | ||
| 234 | void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs); | 235 | void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs); |
| 235 | 236 | ||
| 236 | #else | 237 | #else |
| @@ -252,7 +253,8 @@ static inline void ath_debug_stat_interrupt(struct ath_softc *sc, | |||
| 252 | static inline void ath_debug_stat_tx(struct ath_softc *sc, | 253 | static inline void ath_debug_stat_tx(struct ath_softc *sc, |
| 253 | struct ath_buf *bf, | 254 | struct ath_buf *bf, |
| 254 | struct ath_tx_status *ts, | 255 | struct ath_tx_status *ts, |
| 255 | struct ath_txq *txq) | 256 | struct ath_txq *txq, |
| 257 | unsigned int flags) | ||
| 256 | { | 258 | { |
| 257 | } | 259 | } |
| 258 | 260 | ||
diff --git a/drivers/net/wireless/ath/ath9k/gpio.c b/drivers/net/wireless/ath/ath9k/gpio.c index 5113dd80c99f..afbf5400a52a 100644 --- a/drivers/net/wireless/ath/ath9k/gpio.c +++ b/drivers/net/wireless/ath/ath9k/gpio.c | |||
| @@ -48,6 +48,8 @@ void ath_init_leds(struct ath_softc *sc) | |||
| 48 | sc->sc_ah->led_pin = ATH_LED_PIN_9485; | 48 | sc->sc_ah->led_pin = ATH_LED_PIN_9485; |
| 49 | else if (AR_SREV_9300(sc->sc_ah)) | 49 | else if (AR_SREV_9300(sc->sc_ah)) |
| 50 | sc->sc_ah->led_pin = ATH_LED_PIN_9300; | 50 | sc->sc_ah->led_pin = ATH_LED_PIN_9300; |
| 51 | else if (AR_SREV_9480(sc->sc_ah)) | ||
| 52 | sc->sc_ah->led_pin = ATH_LED_PIN_9480; | ||
| 51 | else | 53 | else |
| 52 | sc->sc_ah->led_pin = ATH_LED_PIN_DEF; | 54 | sc->sc_ah->led_pin = ATH_LED_PIN_DEF; |
| 53 | } | 55 | } |
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c index 9cf42f6973aa..966661c9e586 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c | |||
| @@ -509,8 +509,8 @@ static void setup_ht_cap(struct ath9k_htc_priv *priv, | |||
| 509 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | 509 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); |
| 510 | 510 | ||
| 511 | /* ath9k_htc supports only 1 or 2 stream devices */ | 511 | /* ath9k_htc supports only 1 or 2 stream devices */ |
| 512 | tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2); | 512 | tx_streams = ath9k_cmn_count_streams(priv->ah->txchainmask, 2); |
| 513 | rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2); | 513 | rx_streams = ath9k_cmn_count_streams(priv->ah->rxchainmask, 2); |
| 514 | 514 | ||
| 515 | ath_dbg(common, ATH_DBG_CONFIG, | 515 | ath_dbg(common, ATH_DBG_CONFIG, |
| 516 | "TX streams %d, RX streams: %d\n", | 516 | "TX streams %d, RX streams: %d\n", |
| @@ -601,9 +601,6 @@ static void ath9k_init_misc(struct ath9k_htc_priv *priv) | |||
| 601 | { | 601 | { |
| 602 | struct ath_common *common = ath9k_hw_common(priv->ah); | 602 | struct ath_common *common = ath9k_hw_common(priv->ah); |
| 603 | 603 | ||
| 604 | common->tx_chainmask = priv->ah->caps.tx_chainmask; | ||
| 605 | common->rx_chainmask = priv->ah->caps.rx_chainmask; | ||
| 606 | |||
| 607 | memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); | 604 | memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); |
| 608 | 605 | ||
| 609 | priv->ah->opmode = NL80211_IFTYPE_STATION; | 606 | priv->ah->opmode = NL80211_IFTYPE_STATION; |
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c index b9de1511add9..495fdf680a6c 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c | |||
| @@ -826,8 +826,7 @@ void ath9k_htc_ani_work(struct work_struct *work) | |||
| 826 | if (longcal || shortcal) | 826 | if (longcal || shortcal) |
| 827 | common->ani.caldone = | 827 | common->ani.caldone = |
| 828 | ath9k_hw_calibrate(ah, ah->curchan, | 828 | ath9k_hw_calibrate(ah, ah->curchan, |
| 829 | common->rx_chainmask, | 829 | ah->rxchainmask, longcal); |
| 830 | longcal); | ||
| 831 | 830 | ||
| 832 | ath9k_htc_ps_restore(priv); | 831 | ath9k_htc_ps_restore(priv); |
| 833 | } | 832 | } |
diff --git a/drivers/net/wireless/ath/ath9k/hw-ops.h b/drivers/net/wireless/ath/ath9k/hw-ops.h index dd9003ee123b..41f4bf363d3d 100644 --- a/drivers/net/wireless/ath/ath9k/hw-ops.h +++ b/drivers/net/wireless/ath/ath9k/hw-ops.h | |||
| @@ -54,13 +54,10 @@ static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) | |||
| 54 | return ath9k_hw_ops(ah)->get_isr(ah, masked); | 54 | return ath9k_hw_ops(ah)->get_isr(ah, masked); |
| 55 | } | 55 | } |
| 56 | 56 | ||
| 57 | static inline void ath9k_hw_filltxdesc(struct ath_hw *ah, void *ds, u32 seglen, | 57 | static inline void ath9k_hw_set_txdesc(struct ath_hw *ah, void *ds, |
| 58 | bool is_firstseg, bool is_lastseg, | 58 | struct ath_tx_info *i) |
| 59 | const void *ds0, dma_addr_t buf_addr, | ||
| 60 | unsigned int qcu) | ||
| 61 | { | 59 | { |
| 62 | ath9k_hw_ops(ah)->fill_txdesc(ah, ds, seglen, is_firstseg, is_lastseg, | 60 | return ath9k_hw_ops(ah)->set_txdesc(ah, ds, i); |
| 63 | ds0, buf_addr, qcu); | ||
| 64 | } | 61 | } |
| 65 | 62 | ||
| 66 | static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds, | 63 | static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds, |
| @@ -69,55 +66,6 @@ static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds, | |||
| 69 | return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts); | 66 | return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts); |
| 70 | } | 67 | } |
| 71 | 68 | ||
| 72 | static inline void ath9k_hw_set11n_txdesc(struct ath_hw *ah, void *ds, | ||
| 73 | u32 pktLen, enum ath9k_pkt_type type, | ||
| 74 | u32 txPower, u32 keyIx, | ||
| 75 | enum ath9k_key_type keyType, | ||
| 76 | u32 flags) | ||
| 77 | { | ||
| 78 | ath9k_hw_ops(ah)->set11n_txdesc(ah, ds, pktLen, type, txPower, keyIx, | ||
| 79 | keyType, flags); | ||
| 80 | } | ||
| 81 | |||
| 82 | static inline void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, void *ds, | ||
| 83 | void *lastds, | ||
| 84 | u32 durUpdateEn, u32 rtsctsRate, | ||
| 85 | u32 rtsctsDuration, | ||
| 86 | struct ath9k_11n_rate_series series[], | ||
| 87 | u32 nseries, u32 flags) | ||
| 88 | { | ||
| 89 | ath9k_hw_ops(ah)->set11n_ratescenario(ah, ds, lastds, durUpdateEn, | ||
| 90 | rtsctsRate, rtsctsDuration, series, | ||
| 91 | nseries, flags); | ||
| 92 | } | ||
| 93 | |||
| 94 | static inline void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, void *ds, | ||
| 95 | u32 aggrLen) | ||
| 96 | { | ||
| 97 | ath9k_hw_ops(ah)->set11n_aggr_first(ah, ds, aggrLen); | ||
| 98 | } | ||
| 99 | |||
| 100 | static inline void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds, | ||
| 101 | u32 numDelims) | ||
| 102 | { | ||
| 103 | ath9k_hw_ops(ah)->set11n_aggr_middle(ah, ds, numDelims); | ||
| 104 | } | ||
| 105 | |||
| 106 | static inline void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, void *ds) | ||
| 107 | { | ||
| 108 | ath9k_hw_ops(ah)->set11n_aggr_last(ah, ds); | ||
| 109 | } | ||
| 110 | |||
| 111 | static inline void ath9k_hw_clr11n_aggr(struct ath_hw *ah, void *ds) | ||
| 112 | { | ||
| 113 | ath9k_hw_ops(ah)->clr11n_aggr(ah, ds); | ||
| 114 | } | ||
| 115 | |||
| 116 | static inline void ath9k_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val) | ||
| 117 | { | ||
| 118 | ath9k_hw_ops(ah)->set_clrdmask(ah, ds, val); | ||
| 119 | } | ||
| 120 | |||
| 121 | static inline void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah, | 69 | static inline void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah, |
| 122 | struct ath_hw_antcomb_conf *antconf) | 70 | struct ath_hw_antcomb_conf *antconf) |
| 123 | { | 71 | { |
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index 3a16ba256ef9..f2de7ee047ce 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c | |||
| @@ -580,6 +580,7 @@ static int __ath9k_hw_init(struct ath_hw *ah) | |||
| 580 | case AR_SREV_VERSION_9330: | 580 | case AR_SREV_VERSION_9330: |
| 581 | case AR_SREV_VERSION_9485: | 581 | case AR_SREV_VERSION_9485: |
| 582 | case AR_SREV_VERSION_9340: | 582 | case AR_SREV_VERSION_9340: |
| 583 | case AR_SREV_VERSION_9480: | ||
| 583 | break; | 584 | break; |
| 584 | default: | 585 | default: |
| 585 | ath_err(common, | 586 | ath_err(common, |
| @@ -664,6 +665,7 @@ int ath9k_hw_init(struct ath_hw *ah) | |||
| 664 | case AR9300_DEVID_AR9330: | 665 | case AR9300_DEVID_AR9330: |
| 665 | case AR9300_DEVID_AR9340: | 666 | case AR9300_DEVID_AR9340: |
| 666 | case AR9300_DEVID_AR9580: | 667 | case AR9300_DEVID_AR9580: |
| 668 | case AR9300_DEVID_AR9480: | ||
| 667 | break; | 669 | break; |
| 668 | default: | 670 | default: |
| 669 | if (common->bus_ops->ath_bus_type == ATH_USB) | 671 | if (common->bus_ops->ath_bus_type == ATH_USB) |
| @@ -960,7 +962,7 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah) | |||
| 960 | struct ath_common *common = ath9k_hw_common(ah); | 962 | struct ath_common *common = ath9k_hw_common(ah); |
| 961 | struct ieee80211_conf *conf = &common->hw->conf; | 963 | struct ieee80211_conf *conf = &common->hw->conf; |
| 962 | const struct ath9k_channel *chan = ah->curchan; | 964 | const struct ath9k_channel *chan = ah->curchan; |
| 963 | int acktimeout; | 965 | int acktimeout, ctstimeout; |
| 964 | int slottime; | 966 | int slottime; |
| 965 | int sifstime; | 967 | int sifstime; |
| 966 | int rx_lat = 0, tx_lat = 0, eifs = 0; | 968 | int rx_lat = 0, tx_lat = 0, eifs = 0; |
| @@ -975,7 +977,10 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah) | |||
| 975 | if (ah->misc_mode != 0) | 977 | if (ah->misc_mode != 0) |
| 976 | REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); | 978 | REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); |
| 977 | 979 | ||
| 978 | rx_lat = 37; | 980 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) |
| 981 | rx_lat = 41; | ||
| 982 | else | ||
| 983 | rx_lat = 37; | ||
| 979 | tx_lat = 54; | 984 | tx_lat = 54; |
| 980 | 985 | ||
| 981 | if (IS_CHAN_HALF_RATE(chan)) { | 986 | if (IS_CHAN_HALF_RATE(chan)) { |
| @@ -989,7 +994,7 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah) | |||
| 989 | sifstime = 32; | 994 | sifstime = 32; |
| 990 | } else if (IS_CHAN_QUARTER_RATE(chan)) { | 995 | } else if (IS_CHAN_QUARTER_RATE(chan)) { |
| 991 | eifs = 340; | 996 | eifs = 340; |
| 992 | rx_lat *= 4; | 997 | rx_lat = (rx_lat * 4) - 1; |
| 993 | tx_lat *= 4; | 998 | tx_lat *= 4; |
| 994 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) | 999 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) |
| 995 | tx_lat += 22; | 1000 | tx_lat += 22; |
| @@ -1017,6 +1022,7 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah) | |||
| 1017 | 1022 | ||
| 1018 | /* As defined by IEEE 802.11-2007 17.3.8.6 */ | 1023 | /* As defined by IEEE 802.11-2007 17.3.8.6 */ |
| 1019 | acktimeout = slottime + sifstime + 3 * ah->coverage_class; | 1024 | acktimeout = slottime + sifstime + 3 * ah->coverage_class; |
| 1025 | ctstimeout = acktimeout; | ||
| 1020 | 1026 | ||
| 1021 | /* | 1027 | /* |
| 1022 | * Workaround for early ACK timeouts, add an offset to match the | 1028 | * Workaround for early ACK timeouts, add an offset to match the |
| @@ -1031,7 +1037,7 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah) | |||
| 1031 | ath9k_hw_set_sifs_time(ah, sifstime); | 1037 | ath9k_hw_set_sifs_time(ah, sifstime); |
| 1032 | ath9k_hw_setslottime(ah, slottime); | 1038 | ath9k_hw_setslottime(ah, slottime); |
| 1033 | ath9k_hw_set_ack_timeout(ah, acktimeout); | 1039 | ath9k_hw_set_ack_timeout(ah, acktimeout); |
| 1034 | ath9k_hw_set_cts_timeout(ah, acktimeout); | 1040 | ath9k_hw_set_cts_timeout(ah, ctstimeout); |
| 1035 | if (ah->globaltxtimeout != (u32) -1) | 1041 | if (ah->globaltxtimeout != (u32) -1) |
| 1036 | ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); | 1042 | ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); |
| 1037 | 1043 | ||
| @@ -1336,6 +1342,7 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) | |||
| 1336 | 1342 | ||
| 1337 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) | 1343 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) |
| 1338 | { | 1344 | { |
| 1345 | |||
| 1339 | if (AR_SREV_9300_20_OR_LATER(ah)) { | 1346 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 1340 | REG_WRITE(ah, AR_WA, ah->WARegVal); | 1347 | REG_WRITE(ah, AR_WA, ah->WARegVal); |
| 1341 | udelay(10); | 1348 | udelay(10); |
| @@ -1475,9 +1482,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, | |||
| 1475 | u64 tsf = 0; | 1482 | u64 tsf = 0; |
| 1476 | int i, r; | 1483 | int i, r; |
| 1477 | 1484 | ||
| 1478 | ah->txchainmask = common->tx_chainmask; | ||
| 1479 | ah->rxchainmask = common->rx_chainmask; | ||
| 1480 | |||
| 1481 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) | 1485 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
| 1482 | return -EIO; | 1486 | return -EIO; |
| 1483 | 1487 | ||
| @@ -1495,14 +1499,16 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, | |||
| 1495 | } | 1499 | } |
| 1496 | ah->noise = ath9k_hw_getchan_noise(ah, chan); | 1500 | ah->noise = ath9k_hw_getchan_noise(ah, chan); |
| 1497 | 1501 | ||
| 1502 | if ((AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) || | ||
| 1503 | (AR_SREV_9300_20_OR_LATER(ah) && IS_CHAN_5GHZ(chan))) | ||
| 1504 | bChannelChange = false; | ||
| 1505 | |||
| 1498 | if (bChannelChange && | 1506 | if (bChannelChange && |
| 1499 | (ah->chip_fullsleep != true) && | 1507 | (ah->chip_fullsleep != true) && |
| 1500 | (ah->curchan != NULL) && | 1508 | (ah->curchan != NULL) && |
| 1501 | (chan->channel != ah->curchan->channel) && | 1509 | (chan->channel != ah->curchan->channel) && |
| 1502 | ((chan->channelFlags & CHANNEL_ALL) == | 1510 | ((chan->channelFlags & CHANNEL_ALL) == |
| 1503 | (ah->curchan->channelFlags & CHANNEL_ALL)) && | 1511 | (ah->curchan->channelFlags & CHANNEL_ALL))) { |
| 1504 | (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) { | ||
| 1505 | |||
| 1506 | if (ath9k_hw_channel_change(ah, chan)) { | 1512 | if (ath9k_hw_channel_change(ah, chan)) { |
| 1507 | ath9k_hw_loadnf(ah, ah->curchan); | 1513 | ath9k_hw_loadnf(ah, ah->curchan); |
| 1508 | ath9k_hw_start_nfcal(ah, true); | 1514 | ath9k_hw_start_nfcal(ah, true); |
| @@ -1742,25 +1748,41 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) | |||
| 1742 | { | 1748 | { |
| 1743 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); | 1749 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 1744 | if (setChip) { | 1750 | if (setChip) { |
| 1751 | if (AR_SREV_9480(ah)) { | ||
| 1752 | REG_WRITE(ah, AR_TIMER_MODE, | ||
| 1753 | REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00); | ||
| 1754 | REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah, | ||
| 1755 | AR_NDP2_TIMER_MODE) & 0xFFFFFF00); | ||
| 1756 | REG_WRITE(ah, AR_SLP32_INC, | ||
| 1757 | REG_READ(ah, AR_SLP32_INC) & 0xFFF00000); | ||
| 1758 | /* xxx Required for WLAN only case ? */ | ||
| 1759 | REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); | ||
| 1760 | udelay(100); | ||
| 1761 | } | ||
| 1762 | |||
| 1745 | /* | 1763 | /* |
| 1746 | * Clear the RTC force wake bit to allow the | 1764 | * Clear the RTC force wake bit to allow the |
| 1747 | * mac to go to sleep. | 1765 | * mac to go to sleep. |
| 1748 | */ | 1766 | */ |
| 1749 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, | 1767 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); |
| 1750 | AR_RTC_FORCE_WAKE_EN); | 1768 | |
| 1769 | if (AR_SREV_9480(ah)) | ||
| 1770 | udelay(100); | ||
| 1771 | |||
| 1751 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) | 1772 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
| 1752 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); | 1773 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); |
| 1753 | 1774 | ||
| 1754 | /* Shutdown chip. Active low */ | 1775 | /* Shutdown chip. Active low */ |
| 1755 | if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) | 1776 | if (!AR_SREV_5416(ah) && |
| 1756 | REG_CLR_BIT(ah, (AR_RTC_RESET), | 1777 | !AR_SREV_9271(ah) && !AR_SREV_9480_10(ah)) { |
| 1757 | AR_RTC_RESET_EN); | 1778 | REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); |
| 1779 | udelay(2); | ||
| 1780 | } | ||
| 1758 | } | 1781 | } |
| 1759 | 1782 | ||
| 1760 | /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ | 1783 | /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ |
| 1761 | if (AR_SREV_9300_20_OR_LATER(ah)) | 1784 | if (!AR_SREV_9480(ah)) |
| 1762 | REG_WRITE(ah, AR_WA, | 1785 | REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); |
| 1763 | ah->WARegVal & ~AR_WA_D3_L1_DISABLE); | ||
| 1764 | } | 1786 | } |
| 1765 | 1787 | ||
| 1766 | /* | 1788 | /* |
| @@ -1770,6 +1792,8 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) | |||
| 1770 | */ | 1792 | */ |
| 1771 | static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) | 1793 | static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) |
| 1772 | { | 1794 | { |
| 1795 | u32 val; | ||
| 1796 | |||
| 1773 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); | 1797 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 1774 | if (setChip) { | 1798 | if (setChip) { |
| 1775 | struct ath9k_hw_capabilities *pCap = &ah->caps; | 1799 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
| @@ -1779,12 +1803,30 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) | |||
| 1779 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, | 1803 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
| 1780 | AR_RTC_FORCE_WAKE_ON_INT); | 1804 | AR_RTC_FORCE_WAKE_ON_INT); |
| 1781 | } else { | 1805 | } else { |
| 1806 | |||
| 1807 | /* When chip goes into network sleep, it could be waken | ||
| 1808 | * up by MCI_INT interrupt caused by BT's HW messages | ||
| 1809 | * (LNA_xxx, CONT_xxx) which chould be in a very fast | ||
| 1810 | * rate (~100us). This will cause chip to leave and | ||
| 1811 | * re-enter network sleep mode frequently, which in | ||
| 1812 | * consequence will have WLAN MCI HW to generate lots of | ||
| 1813 | * SYS_WAKING and SYS_SLEEPING messages which will make | ||
| 1814 | * BT CPU to busy to process. | ||
| 1815 | */ | ||
| 1816 | if (AR_SREV_9480(ah)) { | ||
| 1817 | val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) & | ||
| 1818 | ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK; | ||
| 1819 | REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val); | ||
| 1820 | } | ||
| 1782 | /* | 1821 | /* |
| 1783 | * Clear the RTC force wake bit to allow the | 1822 | * Clear the RTC force wake bit to allow the |
| 1784 | * mac to go to sleep. | 1823 | * mac to go to sleep. |
| 1785 | */ | 1824 | */ |
| 1786 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, | 1825 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
| 1787 | AR_RTC_FORCE_WAKE_EN); | 1826 | AR_RTC_FORCE_WAKE_EN); |
| 1827 | |||
| 1828 | if (AR_SREV_9480(ah)) | ||
| 1829 | udelay(30); | ||
| 1788 | } | 1830 | } |
| 1789 | } | 1831 | } |
| 1790 | 1832 | ||
| @@ -2091,6 +2133,8 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah) | |||
| 2091 | 2133 | ||
| 2092 | pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); | 2134 | pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); |
| 2093 | pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); | 2135 | pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); |
| 2136 | ah->txchainmask = pCap->tx_chainmask; | ||
| 2137 | ah->rxchainmask = pCap->rx_chainmask; | ||
| 2094 | 2138 | ||
| 2095 | ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; | 2139 | ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; |
| 2096 | 2140 | ||
| @@ -2401,6 +2445,9 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) | |||
| 2401 | 2445 | ||
| 2402 | ENABLE_REGWRITE_BUFFER(ah); | 2446 | ENABLE_REGWRITE_BUFFER(ah); |
| 2403 | 2447 | ||
| 2448 | if (AR_SREV_9480(ah)) | ||
| 2449 | bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; | ||
| 2450 | |||
| 2404 | REG_WRITE(ah, AR_RX_FILTER, bits); | 2451 | REG_WRITE(ah, AR_RX_FILTER, bits); |
| 2405 | 2452 | ||
| 2406 | phybits = 0; | 2453 | phybits = 0; |
| @@ -2447,13 +2494,13 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) | |||
| 2447 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); | 2494 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
| 2448 | struct ath9k_channel *chan = ah->curchan; | 2495 | struct ath9k_channel *chan = ah->curchan; |
| 2449 | struct ieee80211_channel *channel = chan->chan; | 2496 | struct ieee80211_channel *channel = chan->chan; |
| 2450 | int reg_pwr = min_t(int, MAX_RATE_POWER, regulatory->power_limit); | 2497 | int reg_pwr = min_t(int, MAX_RATE_POWER, limit); |
| 2451 | int chan_pwr = channel->max_power * 2; | 2498 | int chan_pwr = channel->max_power * 2; |
| 2452 | 2499 | ||
| 2453 | if (test) | 2500 | if (test) |
| 2454 | reg_pwr = chan_pwr = MAX_RATE_POWER; | 2501 | reg_pwr = chan_pwr = MAX_RATE_POWER; |
| 2455 | 2502 | ||
| 2456 | regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); | 2503 | regulatory->power_limit = reg_pwr; |
| 2457 | 2504 | ||
| 2458 | ah->eep_ops->set_txpower(ah, chan, | 2505 | ah->eep_ops->set_txpower(ah, chan, |
| 2459 | ath9k_regd_get_ctl(regulatory, chan), | 2506 | ath9k_regd_get_ctl(regulatory, chan), |
| @@ -2657,6 +2704,20 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah, | |||
| 2657 | REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, | 2704 | REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, |
| 2658 | gen_tmr_configuration[timer->index].mode_mask); | 2705 | gen_tmr_configuration[timer->index].mode_mask); |
| 2659 | 2706 | ||
| 2707 | if (AR_SREV_9480(ah)) { | ||
| 2708 | /* | ||
| 2709 | * Starting from AR9480, each generic timer can select which tsf | ||
| 2710 | * to use. But we still follow the old rule, 0 - 7 use tsf and | ||
| 2711 | * 8 - 15 use tsf2. | ||
| 2712 | */ | ||
| 2713 | if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) | ||
| 2714 | REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, | ||
| 2715 | (1 << timer->index)); | ||
| 2716 | else | ||
| 2717 | REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, | ||
| 2718 | (1 << timer->index)); | ||
| 2719 | } | ||
| 2720 | |||
| 2660 | /* Enable both trigger and thresh interrupt masks */ | 2721 | /* Enable both trigger and thresh interrupt masks */ |
| 2661 | REG_SET_BIT(ah, AR_IMR_S5, | 2722 | REG_SET_BIT(ah, AR_IMR_S5, |
| 2662 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | | 2723 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | |
| @@ -2762,6 +2823,7 @@ static struct { | |||
| 2762 | { AR_SREV_VERSION_9330, "9330" }, | 2823 | { AR_SREV_VERSION_9330, "9330" }, |
| 2763 | { AR_SREV_VERSION_9340, "9340" }, | 2824 | { AR_SREV_VERSION_9340, "9340" }, |
| 2764 | { AR_SREV_VERSION_9485, "9485" }, | 2825 | { AR_SREV_VERSION_9485, "9485" }, |
| 2826 | { AR_SREV_VERSION_9480, "9480" }, | ||
| 2765 | }; | 2827 | }; |
| 2766 | 2828 | ||
| 2767 | /* For devices with external radios */ | 2829 | /* For devices with external radios */ |
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h index c8af86c795e5..bf38e2fc8f78 100644 --- a/drivers/net/wireless/ath/ath9k/hw.h +++ b/drivers/net/wireless/ath/ath9k/hw.h | |||
| @@ -46,6 +46,7 @@ | |||
| 46 | #define AR9300_DEVID_AR9340 0x0031 | 46 | #define AR9300_DEVID_AR9340 0x0031 |
| 47 | #define AR9300_DEVID_AR9485_PCIE 0x0032 | 47 | #define AR9300_DEVID_AR9485_PCIE 0x0032 |
| 48 | #define AR9300_DEVID_AR9580 0x0033 | 48 | #define AR9300_DEVID_AR9580 0x0033 |
| 49 | #define AR9300_DEVID_AR9480 0x0034 | ||
| 49 | #define AR9300_DEVID_AR9330 0x0035 | 50 | #define AR9300_DEVID_AR9330 0x0035 |
| 50 | 51 | ||
| 51 | #define AR5416_AR9100_DEVID 0x000b | 52 | #define AR5416_AR9100_DEVID 0x000b |
| @@ -615,30 +616,10 @@ struct ath_hw_ops { | |||
| 615 | u8 rxchainmask, | 616 | u8 rxchainmask, |
| 616 | bool longcal); | 617 | bool longcal); |
| 617 | bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); | 618 | bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); |
| 618 | void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen, | 619 | void (*set_txdesc)(struct ath_hw *ah, void *ds, |
| 619 | bool is_firstseg, bool is_is_lastseg, | 620 | struct ath_tx_info *i); |
| 620 | const void *ds0, dma_addr_t buf_addr, | ||
| 621 | unsigned int qcu); | ||
| 622 | int (*proc_txdesc)(struct ath_hw *ah, void *ds, | 621 | int (*proc_txdesc)(struct ath_hw *ah, void *ds, |
| 623 | struct ath_tx_status *ts); | 622 | struct ath_tx_status *ts); |
| 624 | void (*set11n_txdesc)(struct ath_hw *ah, void *ds, | ||
| 625 | u32 pktLen, enum ath9k_pkt_type type, | ||
| 626 | u32 txPower, u8 keyIx, | ||
| 627 | enum ath9k_key_type keyType, | ||
| 628 | u32 flags); | ||
| 629 | void (*set11n_ratescenario)(struct ath_hw *ah, void *ds, | ||
| 630 | void *lastds, | ||
| 631 | u32 durUpdateEn, u32 rtsctsRate, | ||
| 632 | u32 rtsctsDuration, | ||
| 633 | struct ath9k_11n_rate_series series[], | ||
| 634 | u32 nseries, u32 flags); | ||
| 635 | void (*set11n_aggr_first)(struct ath_hw *ah, void *ds, | ||
| 636 | u32 aggrLen); | ||
| 637 | void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds, | ||
| 638 | u32 numDelims); | ||
| 639 | void (*set11n_aggr_last)(struct ath_hw *ah, void *ds); | ||
| 640 | void (*clr11n_aggr)(struct ath_hw *ah, void *ds); | ||
| 641 | void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val); | ||
| 642 | void (*antdiv_comb_conf_get)(struct ath_hw *ah, | 623 | void (*antdiv_comb_conf_get)(struct ath_hw *ah, |
| 643 | struct ath_hw_antcomb_conf *antconf); | 624 | struct ath_hw_antcomb_conf *antconf); |
| 644 | void (*antdiv_comb_conf_set)(struct ath_hw *ah, | 625 | void (*antdiv_comb_conf_set)(struct ath_hw *ah, |
| @@ -827,11 +808,14 @@ struct ath_hw { | |||
| 827 | struct ar5416IniArray iniModes_9271_1_0_only; | 808 | struct ar5416IniArray iniModes_9271_1_0_only; |
| 828 | struct ar5416IniArray iniCckfirNormal; | 809 | struct ar5416IniArray iniCckfirNormal; |
| 829 | struct ar5416IniArray iniCckfirJapan2484; | 810 | struct ar5416IniArray iniCckfirJapan2484; |
| 811 | struct ar5416IniArray ini_japan2484; | ||
| 830 | struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271; | 812 | struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271; |
| 831 | struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271; | 813 | struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271; |
| 832 | struct ar5416IniArray iniModes_9271_ANI_reg; | 814 | struct ar5416IniArray iniModes_9271_ANI_reg; |
| 833 | struct ar5416IniArray iniModes_high_power_tx_gain_9271; | 815 | struct ar5416IniArray iniModes_high_power_tx_gain_9271; |
| 834 | struct ar5416IniArray iniModes_normal_power_tx_gain_9271; | 816 | struct ar5416IniArray iniModes_normal_power_tx_gain_9271; |
| 817 | struct ar5416IniArray ini_radio_post_sys2ant; | ||
| 818 | struct ar5416IniArray ini_BTCOEX_MAX_TXPWR; | ||
| 835 | 819 | ||
| 836 | struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; | 820 | struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; |
| 837 | struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; | 821 | struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; |
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c index dd71a5f77516..9b34c4bab937 100644 --- a/drivers/net/wireless/ath/ath9k/init.c +++ b/drivers/net/wireless/ath/ath9k/init.c | |||
| @@ -270,8 +270,8 @@ static void setup_ht_cap(struct ath_softc *sc, | |||
| 270 | 270 | ||
| 271 | /* set up supported mcs set */ | 271 | /* set up supported mcs set */ |
| 272 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | 272 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); |
| 273 | tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams); | 273 | tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams); |
| 274 | rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams); | 274 | rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams); |
| 275 | 275 | ||
| 276 | ath_dbg(common, ATH_DBG_CONFIG, | 276 | ath_dbg(common, ATH_DBG_CONFIG, |
| 277 | "TX streams %d, RX streams: %d\n", | 277 | "TX streams %d, RX streams: %d\n", |
| @@ -506,9 +506,6 @@ static void ath9k_init_misc(struct ath_softc *sc) | |||
| 506 | sc->sc_flags |= SC_OP_RXAGGR; | 506 | sc->sc_flags |= SC_OP_RXAGGR; |
| 507 | } | 507 | } |
| 508 | 508 | ||
| 509 | common->tx_chainmask = sc->sc_ah->caps.tx_chainmask; | ||
| 510 | common->rx_chainmask = sc->sc_ah->caps.rx_chainmask; | ||
| 511 | |||
| 512 | ath9k_hw_set_diversity(sc->sc_ah, true); | 509 | ath9k_hw_set_diversity(sc->sc_ah, true); |
| 513 | sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah); | 510 | sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah); |
| 514 | 511 | ||
| @@ -646,10 +643,8 @@ static void ath9k_init_band_txpower(struct ath_softc *sc, int band) | |||
| 646 | static void ath9k_init_txpower_limits(struct ath_softc *sc) | 643 | static void ath9k_init_txpower_limits(struct ath_softc *sc) |
| 647 | { | 644 | { |
| 648 | struct ath_hw *ah = sc->sc_ah; | 645 | struct ath_hw *ah = sc->sc_ah; |
| 649 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | ||
| 650 | struct ath9k_channel *curchan = ah->curchan; | 646 | struct ath9k_channel *curchan = ah->curchan; |
| 651 | 647 | ||
| 652 | ah->txchainmask = common->tx_chainmask; | ||
| 653 | if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | 648 | if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
| 654 | ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); | 649 | ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); |
| 655 | if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | 650 | if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
| @@ -658,9 +653,22 @@ static void ath9k_init_txpower_limits(struct ath_softc *sc) | |||
| 658 | ah->curchan = curchan; | 653 | ah->curchan = curchan; |
| 659 | } | 654 | } |
| 660 | 655 | ||
| 656 | void ath9k_reload_chainmask_settings(struct ath_softc *sc) | ||
| 657 | { | ||
| 658 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)) | ||
| 659 | return; | ||
| 660 | |||
| 661 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | ||
| 662 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); | ||
| 663 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | ||
| 664 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); | ||
| 665 | } | ||
| 666 | |||
| 667 | |||
| 661 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) | 668 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
| 662 | { | 669 | { |
| 663 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | 670 | struct ath_hw *ah = sc->sc_ah; |
| 671 | struct ath_common *common = ath9k_hw_common(ah); | ||
| 664 | 672 | ||
| 665 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | | 673 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
| 666 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | 674 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
| @@ -698,6 +706,16 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) | |||
| 698 | hw->sta_data_size = sizeof(struct ath_node); | 706 | hw->sta_data_size = sizeof(struct ath_node); |
| 699 | hw->vif_data_size = sizeof(struct ath_vif); | 707 | hw->vif_data_size = sizeof(struct ath_vif); |
| 700 | 708 | ||
| 709 | hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; | ||
| 710 | hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; | ||
| 711 | |||
| 712 | /* single chain devices with rx diversity */ | ||
| 713 | if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | ||
| 714 | hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); | ||
| 715 | |||
| 716 | sc->ant_rx = hw->wiphy->available_antennas_rx; | ||
| 717 | sc->ant_tx = hw->wiphy->available_antennas_tx; | ||
| 718 | |||
| 701 | #ifdef CONFIG_ATH9K_RATE_CONTROL | 719 | #ifdef CONFIG_ATH9K_RATE_CONTROL |
| 702 | hw->rate_control_algorithm = "ath9k_rate_control"; | 720 | hw->rate_control_algorithm = "ath9k_rate_control"; |
| 703 | #endif | 721 | #endif |
| @@ -709,12 +727,7 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) | |||
| 709 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | 727 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = |
| 710 | &sc->sbands[IEEE80211_BAND_5GHZ]; | 728 | &sc->sbands[IEEE80211_BAND_5GHZ]; |
| 711 | 729 | ||
| 712 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { | 730 | ath9k_reload_chainmask_settings(sc); |
| 713 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | ||
| 714 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); | ||
| 715 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | ||
| 716 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); | ||
| 717 | } | ||
| 718 | 731 | ||
| 719 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); | 732 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); |
| 720 | } | 733 | } |
| @@ -782,6 +795,7 @@ int ath9k_init_device(u16 devid, struct ath_softc *sc, | |||
| 782 | goto error_world; | 795 | goto error_world; |
| 783 | } | 796 | } |
| 784 | 797 | ||
| 798 | INIT_WORK(&sc->hw_reset_work, ath_reset_work); | ||
| 785 | INIT_WORK(&sc->hw_check_work, ath_hw_check); | 799 | INIT_WORK(&sc->hw_check_work, ath_hw_check); |
| 786 | INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); | 800 | INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); |
| 787 | INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); | 801 | INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); |
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c index 7ce9b320f0d9..786587ac40a7 100644 --- a/drivers/net/wireless/ath/ath9k/mac.c +++ b/drivers/net/wireless/ath/ath9k/mac.c | |||
| @@ -62,18 +62,6 @@ void ath9k_hw_txstart(struct ath_hw *ah, u32 q) | |||
| 62 | } | 62 | } |
| 63 | EXPORT_SYMBOL(ath9k_hw_txstart); | 63 | EXPORT_SYMBOL(ath9k_hw_txstart); |
| 64 | 64 | ||
| 65 | void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds) | ||
| 66 | { | ||
| 67 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 68 | |||
| 69 | ads->ds_txstatus0 = ads->ds_txstatus1 = 0; | ||
| 70 | ads->ds_txstatus2 = ads->ds_txstatus3 = 0; | ||
| 71 | ads->ds_txstatus4 = ads->ds_txstatus5 = 0; | ||
| 72 | ads->ds_txstatus6 = ads->ds_txstatus7 = 0; | ||
| 73 | ads->ds_txstatus8 = ads->ds_txstatus9 = 0; | ||
| 74 | } | ||
| 75 | EXPORT_SYMBOL(ath9k_hw_cleartxdesc); | ||
| 76 | |||
| 77 | u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q) | 65 | u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q) |
| 78 | { | 66 | { |
| 79 | u32 npend; | 67 | u32 npend; |
diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h index acb83bfd05a0..ac5a1d265d39 100644 --- a/drivers/net/wireless/ath/ath9k/mac.h +++ b/drivers/net/wireless/ath/ath9k/mac.h | |||
| @@ -263,7 +263,11 @@ struct ath_desc { | |||
| 263 | #define ATH9K_TXDESC_VMF 0x0100 | 263 | #define ATH9K_TXDESC_VMF 0x0100 |
| 264 | #define ATH9K_TXDESC_FRAG_IS_ON 0x0200 | 264 | #define ATH9K_TXDESC_FRAG_IS_ON 0x0200 |
| 265 | #define ATH9K_TXDESC_LOWRXCHAIN 0x0400 | 265 | #define ATH9K_TXDESC_LOWRXCHAIN 0x0400 |
| 266 | #define ATH9K_TXDESC_LDPC 0x00010000 | 266 | #define ATH9K_TXDESC_LDPC 0x0800 |
| 267 | #define ATH9K_TXDESC_CLRDMASK 0x1000 | ||
| 268 | |||
| 269 | #define ATH9K_TXDESC_PAPRD 0x70000 | ||
| 270 | #define ATH9K_TXDESC_PAPRD_S 16 | ||
| 267 | 271 | ||
| 268 | #define ATH9K_RXDESC_INTREQ 0x0020 | 272 | #define ATH9K_RXDESC_INTREQ 0x0020 |
| 269 | 273 | ||
| @@ -644,6 +648,7 @@ enum ath9k_rx_filter { | |||
| 644 | ATH9K_RX_FILTER_PSPOLL = 0x00004000, | 648 | ATH9K_RX_FILTER_PSPOLL = 0x00004000, |
| 645 | ATH9K_RX_FILTER_PHYRADAR = 0x00002000, | 649 | ATH9K_RX_FILTER_PHYRADAR = 0x00002000, |
| 646 | ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, | 650 | ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, |
| 651 | ATH9K_RX_FILTER_CONTROL_WRAPPER = 0x00080000, | ||
| 647 | }; | 652 | }; |
| 648 | 653 | ||
| 649 | #define ATH9K_RATESERIES_RTS_CTS 0x0001 | 654 | #define ATH9K_RATESERIES_RTS_CTS 0x0001 |
| @@ -659,6 +664,13 @@ struct ath9k_11n_rate_series { | |||
| 659 | u32 RateFlags; | 664 | u32 RateFlags; |
| 660 | }; | 665 | }; |
| 661 | 666 | ||
| 667 | enum aggr_type { | ||
| 668 | AGGR_BUF_NONE, | ||
| 669 | AGGR_BUF_FIRST, | ||
| 670 | AGGR_BUF_MIDDLE, | ||
| 671 | AGGR_BUF_LAST, | ||
| 672 | }; | ||
| 673 | |||
| 662 | enum ath9k_key_type { | 674 | enum ath9k_key_type { |
| 663 | ATH9K_KEY_TYPE_CLEAR, | 675 | ATH9K_KEY_TYPE_CLEAR, |
| 664 | ATH9K_KEY_TYPE_WEP, | 676 | ATH9K_KEY_TYPE_WEP, |
| @@ -666,6 +678,33 @@ enum ath9k_key_type { | |||
| 666 | ATH9K_KEY_TYPE_TKIP, | 678 | ATH9K_KEY_TYPE_TKIP, |
| 667 | }; | 679 | }; |
| 668 | 680 | ||
| 681 | struct ath_tx_info { | ||
| 682 | u8 qcu; | ||
| 683 | |||
| 684 | bool is_first; | ||
| 685 | bool is_last; | ||
| 686 | |||
| 687 | enum aggr_type aggr; | ||
| 688 | u8 ndelim; | ||
| 689 | u16 aggr_len; | ||
| 690 | |||
| 691 | dma_addr_t link; | ||
| 692 | int pkt_len; | ||
| 693 | u32 flags; | ||
| 694 | |||
| 695 | dma_addr_t buf_addr[4]; | ||
| 696 | int buf_len[4]; | ||
| 697 | |||
| 698 | struct ath9k_11n_rate_series rates[4]; | ||
| 699 | u8 rtscts_rate; | ||
| 700 | bool dur_update; | ||
| 701 | |||
| 702 | enum ath9k_pkt_type type; | ||
| 703 | enum ath9k_key_type keytype; | ||
| 704 | u8 keyix; | ||
| 705 | u8 txpower; | ||
| 706 | }; | ||
| 707 | |||
| 669 | struct ath_hw; | 708 | struct ath_hw; |
| 670 | struct ath9k_channel; | 709 | struct ath9k_channel; |
| 671 | enum ath9k_int; | 710 | enum ath9k_int; |
| @@ -673,7 +712,6 @@ enum ath9k_int; | |||
| 673 | u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q); | 712 | u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q); |
| 674 | void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp); | 713 | void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp); |
| 675 | void ath9k_hw_txstart(struct ath_hw *ah, u32 q); | 714 | void ath9k_hw_txstart(struct ath_hw *ah, u32 q); |
| 676 | void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds); | ||
| 677 | u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q); | 715 | u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q); |
| 678 | bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel); | 716 | bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel); |
| 679 | bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q); | 717 | bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q); |
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c index 7b7864dfab75..7910165cf0e6 100644 --- a/drivers/net/wireless/ath/ath9k/main.c +++ b/drivers/net/wireless/ath/ath9k/main.c | |||
| @@ -111,24 +111,29 @@ void ath9k_ps_wakeup(struct ath_softc *sc) | |||
| 111 | void ath9k_ps_restore(struct ath_softc *sc) | 111 | void ath9k_ps_restore(struct ath_softc *sc) |
| 112 | { | 112 | { |
| 113 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | 113 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
| 114 | enum ath9k_power_mode mode; | ||
| 114 | unsigned long flags; | 115 | unsigned long flags; |
| 115 | 116 | ||
| 116 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | 117 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
| 117 | if (--sc->ps_usecount != 0) | 118 | if (--sc->ps_usecount != 0) |
| 118 | goto unlock; | 119 | goto unlock; |
| 119 | 120 | ||
| 120 | spin_lock(&common->cc_lock); | ||
| 121 | ath_hw_cycle_counters_update(common); | ||
| 122 | spin_unlock(&common->cc_lock); | ||
| 123 | |||
| 124 | if (sc->ps_idle) | 121 | if (sc->ps_idle) |
| 125 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | 122 | mode = ATH9K_PM_FULL_SLEEP; |
| 126 | else if (sc->ps_enabled && | 123 | else if (sc->ps_enabled && |
| 127 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | 124 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | |
| 128 | PS_WAIT_FOR_CAB | | 125 | PS_WAIT_FOR_CAB | |
| 129 | PS_WAIT_FOR_PSPOLL_DATA | | 126 | PS_WAIT_FOR_PSPOLL_DATA | |
| 130 | PS_WAIT_FOR_TX_ACK))) | 127 | PS_WAIT_FOR_TX_ACK))) |
| 131 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); | 128 | mode = ATH9K_PM_NETWORK_SLEEP; |
| 129 | else | ||
| 130 | goto unlock; | ||
| 131 | |||
| 132 | spin_lock(&common->cc_lock); | ||
| 133 | ath_hw_cycle_counters_update(common); | ||
| 134 | spin_unlock(&common->cc_lock); | ||
| 135 | |||
| 136 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); | ||
| 132 | 137 | ||
| 133 | unlock: | 138 | unlock: |
| 134 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | 139 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
| @@ -212,83 +217,58 @@ static int ath_update_survey_stats(struct ath_softc *sc) | |||
| 212 | return ret; | 217 | return ret; |
| 213 | } | 218 | } |
| 214 | 219 | ||
| 215 | /* | 220 | static void __ath_cancel_work(struct ath_softc *sc) |
| 216 | * Set/change channels. If the channel is really being changed, it's done | ||
| 217 | * by reseting the chip. To accomplish this we must first cleanup any pending | ||
| 218 | * DMA, then restart stuff. | ||
| 219 | */ | ||
| 220 | static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | ||
| 221 | struct ath9k_channel *hchan) | ||
| 222 | { | 221 | { |
| 223 | struct ath_hw *ah = sc->sc_ah; | ||
| 224 | struct ath_common *common = ath9k_hw_common(ah); | ||
| 225 | struct ieee80211_conf *conf = &common->hw->conf; | ||
| 226 | bool fastcc = true, stopped; | ||
| 227 | struct ieee80211_channel *channel = hw->conf.channel; | ||
| 228 | struct ath9k_hw_cal_data *caldata = NULL; | ||
| 229 | int r; | ||
| 230 | |||
| 231 | if (sc->sc_flags & SC_OP_INVALID) | ||
| 232 | return -EIO; | ||
| 233 | |||
| 234 | sc->hw_busy_count = 0; | ||
| 235 | |||
| 236 | del_timer_sync(&common->ani.timer); | ||
| 237 | cancel_work_sync(&sc->paprd_work); | 222 | cancel_work_sync(&sc->paprd_work); |
| 238 | cancel_work_sync(&sc->hw_check_work); | 223 | cancel_work_sync(&sc->hw_check_work); |
| 239 | cancel_delayed_work_sync(&sc->tx_complete_work); | 224 | cancel_delayed_work_sync(&sc->tx_complete_work); |
| 240 | cancel_delayed_work_sync(&sc->hw_pll_work); | 225 | cancel_delayed_work_sync(&sc->hw_pll_work); |
| 226 | } | ||
| 241 | 227 | ||
| 242 | ath9k_ps_wakeup(sc); | 228 | static void ath_cancel_work(struct ath_softc *sc) |
| 229 | { | ||
| 230 | __ath_cancel_work(sc); | ||
| 231 | cancel_work_sync(&sc->hw_reset_work); | ||
| 232 | } | ||
| 243 | 233 | ||
| 244 | spin_lock_bh(&sc->sc_pcu_lock); | 234 | static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush) |
| 235 | { | ||
| 236 | struct ath_hw *ah = sc->sc_ah; | ||
| 237 | struct ath_common *common = ath9k_hw_common(ah); | ||
| 238 | bool ret; | ||
| 245 | 239 | ||
| 246 | /* | 240 | ieee80211_stop_queues(sc->hw); |
| 247 | * This is only performed if the channel settings have | ||
| 248 | * actually changed. | ||
| 249 | * | ||
| 250 | * To switch channels clear any pending DMA operations; | ||
| 251 | * wait long enough for the RX fifo to drain, reset the | ||
| 252 | * hardware at the new frequency, and then re-enable | ||
| 253 | * the relevant bits of the h/w. | ||
| 254 | */ | ||
| 255 | ath9k_hw_disable_interrupts(ah); | ||
| 256 | stopped = ath_drain_all_txq(sc, false); | ||
| 257 | 241 | ||
| 258 | if (!ath_stoprecv(sc)) | 242 | sc->hw_busy_count = 0; |
| 259 | stopped = false; | 243 | del_timer_sync(&common->ani.timer); |
| 260 | 244 | ||
| 261 | if (!ath9k_hw_check_alive(ah)) | 245 | ath9k_debug_samp_bb_mac(sc); |
| 262 | stopped = false; | 246 | ath9k_hw_disable_interrupts(ah); |
| 263 | 247 | ||
| 264 | /* XXX: do not flush receive queue here. We don't want | 248 | ret = ath_drain_all_txq(sc, retry_tx); |
| 265 | * to flush data frames already in queue because of | ||
| 266 | * changing channel. */ | ||
| 267 | 249 | ||
| 268 | if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL)) | 250 | if (!ath_stoprecv(sc)) |
| 269 | fastcc = false; | 251 | ret = false; |
| 270 | 252 | ||
| 271 | if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) | 253 | if (!flush) { |
| 272 | caldata = &sc->caldata; | 254 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
| 255 | ath_rx_tasklet(sc, 1, true); | ||
| 256 | ath_rx_tasklet(sc, 1, false); | ||
| 257 | } else { | ||
| 258 | ath_flushrecv(sc); | ||
| 259 | } | ||
| 273 | 260 | ||
| 274 | ath_dbg(common, ATH_DBG_CONFIG, | 261 | return ret; |
| 275 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n", | 262 | } |
| 276 | sc->sc_ah->curchan->channel, | ||
| 277 | channel->center_freq, conf_is_ht40(conf), | ||
| 278 | fastcc); | ||
| 279 | 263 | ||
| 280 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); | 264 | static bool ath_complete_reset(struct ath_softc *sc, bool start) |
| 281 | if (r) { | 265 | { |
| 282 | ath_err(common, | 266 | struct ath_hw *ah = sc->sc_ah; |
| 283 | "Unable to reset channel (%u MHz), reset status %d\n", | 267 | struct ath_common *common = ath9k_hw_common(ah); |
| 284 | channel->center_freq, r); | ||
| 285 | goto ps_restore; | ||
| 286 | } | ||
| 287 | 268 | ||
| 288 | if (ath_startrecv(sc) != 0) { | 269 | if (ath_startrecv(sc) != 0) { |
| 289 | ath_err(common, "Unable to restart recv logic\n"); | 270 | ath_err(common, "Unable to restart recv logic\n"); |
| 290 | r = -EIO; | 271 | return false; |
| 291 | goto ps_restore; | ||
| 292 | } | 272 | } |
| 293 | 273 | ||
| 294 | ath9k_cmn_update_txpow(ah, sc->curtxpow, | 274 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
| @@ -296,21 +276,109 @@ static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |||
| 296 | ath9k_hw_set_interrupts(ah, ah->imask); | 276 | ath9k_hw_set_interrupts(ah, ah->imask); |
| 297 | ath9k_hw_enable_interrupts(ah); | 277 | ath9k_hw_enable_interrupts(ah); |
| 298 | 278 | ||
| 299 | if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) { | 279 | if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) { |
| 300 | if (sc->sc_flags & SC_OP_BEACONS) | 280 | if (sc->sc_flags & SC_OP_BEACONS) |
| 301 | ath_set_beacon(sc); | 281 | ath_set_beacon(sc); |
| 282 | |||
| 302 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); | 283 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
| 303 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2); | 284 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2); |
| 304 | if (!common->disable_ani) | 285 | if (!common->disable_ani) |
| 305 | ath_start_ani(common); | 286 | ath_start_ani(common); |
| 306 | } | 287 | } |
| 307 | 288 | ||
| 308 | ps_restore: | 289 | if (ath9k_hw_ops(ah)->antdiv_comb_conf_get && sc->ant_rx != 3) { |
| 309 | ieee80211_wake_queues(hw); | 290 | struct ath_hw_antcomb_conf div_ant_conf; |
| 291 | u8 lna_conf; | ||
| 292 | |||
| 293 | ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf); | ||
| 294 | |||
| 295 | if (sc->ant_rx == 1) | ||
| 296 | lna_conf = ATH_ANT_DIV_COMB_LNA1; | ||
| 297 | else | ||
| 298 | lna_conf = ATH_ANT_DIV_COMB_LNA2; | ||
| 299 | div_ant_conf.main_lna_conf = lna_conf; | ||
| 300 | div_ant_conf.alt_lna_conf = lna_conf; | ||
| 301 | |||
| 302 | ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf); | ||
| 303 | } | ||
| 304 | |||
| 305 | ieee80211_wake_queues(sc->hw); | ||
| 306 | |||
| 307 | return true; | ||
| 308 | } | ||
| 309 | |||
| 310 | static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan, | ||
| 311 | bool retry_tx) | ||
| 312 | { | ||
| 313 | struct ath_hw *ah = sc->sc_ah; | ||
| 314 | struct ath_common *common = ath9k_hw_common(ah); | ||
| 315 | struct ath9k_hw_cal_data *caldata = NULL; | ||
| 316 | bool fastcc = true; | ||
| 317 | bool flush = false; | ||
| 318 | int r; | ||
| 319 | |||
| 320 | __ath_cancel_work(sc); | ||
| 321 | |||
| 322 | spin_lock_bh(&sc->sc_pcu_lock); | ||
| 323 | |||
| 324 | if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) { | ||
| 325 | fastcc = false; | ||
| 326 | caldata = &sc->caldata; | ||
| 327 | } | ||
| 328 | |||
| 329 | if (!hchan) { | ||
| 330 | fastcc = false; | ||
| 331 | flush = true; | ||
| 332 | hchan = ah->curchan; | ||
| 333 | } | ||
| 334 | |||
| 335 | if (fastcc && !ath9k_hw_check_alive(ah)) | ||
| 336 | fastcc = false; | ||
| 337 | |||
| 338 | if (!ath_prepare_reset(sc, retry_tx, flush)) | ||
| 339 | fastcc = false; | ||
| 310 | 340 | ||
| 341 | ath_dbg(common, ATH_DBG_CONFIG, | ||
| 342 | "Reset to %u MHz, HT40: %d fastcc: %d\n", | ||
| 343 | hchan->channel, !!(hchan->channelFlags & (CHANNEL_HT40MINUS | | ||
| 344 | CHANNEL_HT40PLUS)), | ||
| 345 | fastcc); | ||
| 346 | |||
| 347 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); | ||
| 348 | if (r) { | ||
| 349 | ath_err(common, | ||
| 350 | "Unable to reset channel, reset status %d\n", r); | ||
| 351 | goto out; | ||
| 352 | } | ||
| 353 | |||
| 354 | if (!ath_complete_reset(sc, true)) | ||
| 355 | r = -EIO; | ||
| 356 | |||
| 357 | out: | ||
| 311 | spin_unlock_bh(&sc->sc_pcu_lock); | 358 | spin_unlock_bh(&sc->sc_pcu_lock); |
| 359 | return r; | ||
| 360 | } | ||
| 361 | |||
| 362 | |||
| 363 | /* | ||
| 364 | * Set/change channels. If the channel is really being changed, it's done | ||
| 365 | * by reseting the chip. To accomplish this we must first cleanup any pending | ||
| 366 | * DMA, then restart stuff. | ||
| 367 | */ | ||
| 368 | static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | ||
| 369 | struct ath9k_channel *hchan) | ||
| 370 | { | ||
| 371 | int r; | ||
| 372 | |||
| 373 | if (sc->sc_flags & SC_OP_INVALID) | ||
| 374 | return -EIO; | ||
| 375 | |||
| 376 | ath9k_ps_wakeup(sc); | ||
| 377 | |||
| 378 | r = ath_reset_internal(sc, hchan, false); | ||
| 312 | 379 | ||
| 313 | ath9k_ps_restore(sc); | 380 | ath9k_ps_restore(sc); |
| 381 | |||
| 314 | return r; | 382 | return r; |
| 315 | } | 383 | } |
| 316 | 384 | ||
| @@ -318,7 +386,6 @@ static void ath_paprd_activate(struct ath_softc *sc) | |||
| 318 | { | 386 | { |
| 319 | struct ath_hw *ah = sc->sc_ah; | 387 | struct ath_hw *ah = sc->sc_ah; |
| 320 | struct ath9k_hw_cal_data *caldata = ah->caldata; | 388 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
| 321 | struct ath_common *common = ath9k_hw_common(ah); | ||
| 322 | int chain; | 389 | int chain; |
| 323 | 390 | ||
| 324 | if (!caldata || !caldata->paprd_done) | 391 | if (!caldata || !caldata->paprd_done) |
| @@ -327,7 +394,7 @@ static void ath_paprd_activate(struct ath_softc *sc) | |||
| 327 | ath9k_ps_wakeup(sc); | 394 | ath9k_ps_wakeup(sc); |
| 328 | ar9003_paprd_enable(ah, false); | 395 | ar9003_paprd_enable(ah, false); |
| 329 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { | 396 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
| 330 | if (!(common->tx_chainmask & BIT(chain))) | 397 | if (!(ah->txchainmask & BIT(chain))) |
| 331 | continue; | 398 | continue; |
| 332 | 399 | ||
| 333 | ar9003_paprd_populate_single_table(ah, caldata, chain); | 400 | ar9003_paprd_populate_single_table(ah, caldata, chain); |
| @@ -414,7 +481,7 @@ void ath_paprd_calibrate(struct work_struct *work) | |||
| 414 | memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); | 481 | memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); |
| 415 | 482 | ||
| 416 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { | 483 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
| 417 | if (!(common->tx_chainmask & BIT(chain))) | 484 | if (!(ah->txchainmask & BIT(chain))) |
| 418 | continue; | 485 | continue; |
| 419 | 486 | ||
| 420 | chain_ok = 0; | 487 | chain_ok = 0; |
| @@ -535,7 +602,7 @@ void ath_ani_calibrate(unsigned long data) | |||
| 535 | if (longcal || shortcal) { | 602 | if (longcal || shortcal) { |
| 536 | common->ani.caldone = | 603 | common->ani.caldone = |
| 537 | ath9k_hw_calibrate(ah, ah->curchan, | 604 | ath9k_hw_calibrate(ah, ah->curchan, |
| 538 | common->rx_chainmask, longcal); | 605 | ah->rxchainmask, longcal); |
| 539 | } | 606 | } |
| 540 | 607 | ||
| 541 | ath9k_ps_restore(sc); | 608 | ath9k_ps_restore(sc); |
| @@ -597,74 +664,6 @@ static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |||
| 597 | ath_tx_node_cleanup(sc, an); | 664 | ath_tx_node_cleanup(sc, an); |
| 598 | } | 665 | } |
| 599 | 666 | ||
| 600 | void ath_hw_check(struct work_struct *work) | ||
| 601 | { | ||
| 602 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); | ||
| 603 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | ||
| 604 | unsigned long flags; | ||
| 605 | int busy; | ||
| 606 | |||
| 607 | ath9k_ps_wakeup(sc); | ||
| 608 | if (ath9k_hw_check_alive(sc->sc_ah)) | ||
| 609 | goto out; | ||
| 610 | |||
| 611 | spin_lock_irqsave(&common->cc_lock, flags); | ||
| 612 | busy = ath_update_survey_stats(sc); | ||
| 613 | spin_unlock_irqrestore(&common->cc_lock, flags); | ||
| 614 | |||
| 615 | ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, " | ||
| 616 | "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1); | ||
| 617 | if (busy >= 99) { | ||
| 618 | if (++sc->hw_busy_count >= 3) { | ||
| 619 | spin_lock_bh(&sc->sc_pcu_lock); | ||
| 620 | ath_reset(sc, true); | ||
| 621 | spin_unlock_bh(&sc->sc_pcu_lock); | ||
| 622 | } | ||
| 623 | } else if (busy >= 0) | ||
| 624 | sc->hw_busy_count = 0; | ||
| 625 | |||
| 626 | out: | ||
| 627 | ath9k_ps_restore(sc); | ||
| 628 | } | ||
| 629 | |||
| 630 | static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum) | ||
| 631 | { | ||
| 632 | static int count; | ||
| 633 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | ||
| 634 | |||
| 635 | if (pll_sqsum >= 0x40000) { | ||
| 636 | count++; | ||
| 637 | if (count == 3) { | ||
| 638 | /* Rx is hung for more than 500ms. Reset it */ | ||
| 639 | ath_dbg(common, ATH_DBG_RESET, | ||
| 640 | "Possible RX hang, resetting"); | ||
| 641 | spin_lock_bh(&sc->sc_pcu_lock); | ||
| 642 | ath_reset(sc, true); | ||
| 643 | spin_unlock_bh(&sc->sc_pcu_lock); | ||
| 644 | count = 0; | ||
| 645 | } | ||
| 646 | } else | ||
| 647 | count = 0; | ||
| 648 | } | ||
| 649 | |||
| 650 | void ath_hw_pll_work(struct work_struct *work) | ||
| 651 | { | ||
| 652 | struct ath_softc *sc = container_of(work, struct ath_softc, | ||
| 653 | hw_pll_work.work); | ||
| 654 | u32 pll_sqsum; | ||
| 655 | |||
| 656 | if (AR_SREV_9485(sc->sc_ah)) { | ||
| 657 | |||
| 658 | ath9k_ps_wakeup(sc); | ||
| 659 | pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah); | ||
| 660 | ath9k_ps_restore(sc); | ||
| 661 | |||
| 662 | ath_hw_pll_rx_hang_check(sc, pll_sqsum); | ||
| 663 | |||
| 664 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5); | ||
| 665 | } | ||
| 666 | } | ||
| 667 | |||
| 668 | 667 | ||
| 669 | void ath9k_tasklet(unsigned long data) | 668 | void ath9k_tasklet(unsigned long data) |
| 670 | { | 669 | { |
| @@ -675,17 +674,15 @@ void ath9k_tasklet(unsigned long data) | |||
| 675 | u32 status = sc->intrstatus; | 674 | u32 status = sc->intrstatus; |
| 676 | u32 rxmask; | 675 | u32 rxmask; |
| 677 | 676 | ||
| 677 | ath9k_ps_wakeup(sc); | ||
| 678 | spin_lock(&sc->sc_pcu_lock); | ||
| 679 | |||
| 678 | if ((status & ATH9K_INT_FATAL) || | 680 | if ((status & ATH9K_INT_FATAL) || |
| 679 | (status & ATH9K_INT_BB_WATCHDOG)) { | 681 | (status & ATH9K_INT_BB_WATCHDOG)) { |
| 680 | spin_lock(&sc->sc_pcu_lock); | 682 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
| 681 | ath_reset(sc, true); | 683 | goto out; |
| 682 | spin_unlock(&sc->sc_pcu_lock); | ||
| 683 | return; | ||
| 684 | } | 684 | } |
| 685 | 685 | ||
| 686 | ath9k_ps_wakeup(sc); | ||
| 687 | spin_lock(&sc->sc_pcu_lock); | ||
| 688 | |||
| 689 | /* | 686 | /* |
| 690 | * Only run the baseband hang check if beacons stop working in AP or | 687 | * Only run the baseband hang check if beacons stop working in AP or |
| 691 | * IBSS mode, because it has a high false positive rate. For station | 688 | * IBSS mode, because it has a high false positive rate. For station |
| @@ -733,6 +730,7 @@ void ath9k_tasklet(unsigned long data) | |||
| 733 | if (status & ATH9K_INT_GENTIMER) | 730 | if (status & ATH9K_INT_GENTIMER) |
| 734 | ath_gen_timer_isr(sc->sc_ah); | 731 | ath_gen_timer_isr(sc->sc_ah); |
| 735 | 732 | ||
| 733 | out: | ||
| 736 | /* re-enable hardware interrupt */ | 734 | /* re-enable hardware interrupt */ |
| 737 | ath9k_hw_enable_interrupts(ah); | 735 | ath9k_hw_enable_interrupts(ah); |
| 738 | 736 | ||
| @@ -895,28 +893,13 @@ static void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) | |||
| 895 | channel->center_freq, r); | 893 | channel->center_freq, r); |
| 896 | } | 894 | } |
| 897 | 895 | ||
| 898 | ath9k_cmn_update_txpow(ah, sc->curtxpow, | 896 | ath_complete_reset(sc, true); |
| 899 | sc->config.txpowlimit, &sc->curtxpow); | ||
| 900 | if (ath_startrecv(sc) != 0) { | ||
| 901 | ath_err(common, "Unable to restart recv logic\n"); | ||
| 902 | goto out; | ||
| 903 | } | ||
| 904 | if (sc->sc_flags & SC_OP_BEACONS) | ||
| 905 | ath_set_beacon(sc); /* restart beacons */ | ||
| 906 | |||
| 907 | /* Re-Enable interrupts */ | ||
| 908 | ath9k_hw_set_interrupts(ah, ah->imask); | ||
| 909 | ath9k_hw_enable_interrupts(ah); | ||
| 910 | 897 | ||
| 911 | /* Enable LED */ | 898 | /* Enable LED */ |
| 912 | ath9k_hw_cfg_output(ah, ah->led_pin, | 899 | ath9k_hw_cfg_output(ah, ah->led_pin, |
| 913 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | 900 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
| 914 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); | 901 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
| 915 | 902 | ||
| 916 | ieee80211_wake_queues(hw); | ||
| 917 | ieee80211_queue_delayed_work(hw, &sc->hw_pll_work, HZ/2); | ||
| 918 | |||
| 919 | out: | ||
| 920 | spin_unlock_bh(&sc->sc_pcu_lock); | 903 | spin_unlock_bh(&sc->sc_pcu_lock); |
| 921 | 904 | ||
| 922 | ath9k_ps_restore(sc); | 905 | ath9k_ps_restore(sc); |
| @@ -929,11 +912,10 @@ void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) | |||
| 929 | int r; | 912 | int r; |
| 930 | 913 | ||
| 931 | ath9k_ps_wakeup(sc); | 914 | ath9k_ps_wakeup(sc); |
| 932 | cancel_delayed_work_sync(&sc->hw_pll_work); | ||
| 933 | 915 | ||
| 934 | spin_lock_bh(&sc->sc_pcu_lock); | 916 | ath_cancel_work(sc); |
| 935 | 917 | ||
| 936 | ieee80211_stop_queues(hw); | 918 | spin_lock_bh(&sc->sc_pcu_lock); |
| 937 | 919 | ||
| 938 | /* | 920 | /* |
| 939 | * Keep the LED on when the radio is disabled | 921 | * Keep the LED on when the radio is disabled |
| @@ -944,13 +926,7 @@ void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) | |||
| 944 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | 926 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); |
| 945 | } | 927 | } |
| 946 | 928 | ||
| 947 | /* Disable interrupts */ | 929 | ath_prepare_reset(sc, false, true); |
| 948 | ath9k_hw_disable_interrupts(ah); | ||
| 949 | |||
| 950 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ | ||
| 951 | |||
| 952 | ath_stoprecv(sc); /* turn off frame recv */ | ||
| 953 | ath_flushrecv(sc); /* flush recv queue */ | ||
| 954 | 930 | ||
| 955 | if (!ah->curchan) | 931 | if (!ah->curchan) |
| 956 | ah->curchan = ath9k_cmn_get_curchannel(hw, ah); | 932 | ah->curchan = ath9k_cmn_get_curchannel(hw, ah); |
| @@ -970,51 +946,13 @@ void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) | |||
| 970 | ath9k_ps_restore(sc); | 946 | ath9k_ps_restore(sc); |
| 971 | } | 947 | } |
| 972 | 948 | ||
| 973 | int ath_reset(struct ath_softc *sc, bool retry_tx) | 949 | static int ath_reset(struct ath_softc *sc, bool retry_tx) |
| 974 | { | 950 | { |
| 975 | struct ath_hw *ah = sc->sc_ah; | ||
| 976 | struct ath_common *common = ath9k_hw_common(ah); | ||
| 977 | struct ieee80211_hw *hw = sc->hw; | ||
| 978 | int r; | 951 | int r; |
| 979 | 952 | ||
| 980 | sc->hw_busy_count = 0; | ||
| 981 | |||
| 982 | ath9k_debug_samp_bb_mac(sc); | ||
| 983 | /* Stop ANI */ | ||
| 984 | |||
| 985 | del_timer_sync(&common->ani.timer); | ||
| 986 | |||
| 987 | ath9k_ps_wakeup(sc); | 953 | ath9k_ps_wakeup(sc); |
| 988 | 954 | ||
| 989 | ieee80211_stop_queues(hw); | 955 | r = ath_reset_internal(sc, NULL, retry_tx); |
| 990 | |||
| 991 | ath9k_hw_disable_interrupts(ah); | ||
| 992 | ath_drain_all_txq(sc, retry_tx); | ||
| 993 | |||
| 994 | ath_stoprecv(sc); | ||
| 995 | ath_flushrecv(sc); | ||
| 996 | |||
| 997 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false); | ||
| 998 | if (r) | ||
| 999 | ath_err(common, | ||
| 1000 | "Unable to reset hardware; reset status %d\n", r); | ||
| 1001 | |||
| 1002 | if (ath_startrecv(sc) != 0) | ||
| 1003 | ath_err(common, "Unable to start recv logic\n"); | ||
| 1004 | |||
| 1005 | /* | ||
| 1006 | * We may be doing a reset in response to a request | ||
| 1007 | * that changes the channel so update any state that | ||
| 1008 | * might change as a result. | ||
| 1009 | */ | ||
| 1010 | ath9k_cmn_update_txpow(ah, sc->curtxpow, | ||
| 1011 | sc->config.txpowlimit, &sc->curtxpow); | ||
| 1012 | |||
| 1013 | if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL))) | ||
| 1014 | ath_set_beacon(sc); /* restart beacons */ | ||
| 1015 | |||
| 1016 | ath9k_hw_set_interrupts(ah, ah->imask); | ||
| 1017 | ath9k_hw_enable_interrupts(ah); | ||
| 1018 | 956 | ||
| 1019 | if (retry_tx) { | 957 | if (retry_tx) { |
| 1020 | int i; | 958 | int i; |
| @@ -1027,15 +965,80 @@ int ath_reset(struct ath_softc *sc, bool retry_tx) | |||
| 1027 | } | 965 | } |
| 1028 | } | 966 | } |
| 1029 | 967 | ||
| 1030 | ieee80211_wake_queues(hw); | 968 | ath9k_ps_restore(sc); |
| 969 | |||
| 970 | return r; | ||
| 971 | } | ||
| 972 | |||
| 973 | void ath_reset_work(struct work_struct *work) | ||
| 974 | { | ||
| 975 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); | ||
| 976 | |||
| 977 | ath_reset(sc, true); | ||
| 978 | } | ||
| 979 | |||
| 980 | void ath_hw_check(struct work_struct *work) | ||
| 981 | { | ||
| 982 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); | ||
| 983 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | ||
| 984 | unsigned long flags; | ||
| 985 | int busy; | ||
| 1031 | 986 | ||
| 1032 | /* Start ANI */ | 987 | ath9k_ps_wakeup(sc); |
| 1033 | if (!common->disable_ani) | 988 | if (ath9k_hw_check_alive(sc->sc_ah)) |
| 1034 | ath_start_ani(common); | 989 | goto out; |
| 1035 | 990 | ||
| 991 | spin_lock_irqsave(&common->cc_lock, flags); | ||
| 992 | busy = ath_update_survey_stats(sc); | ||
| 993 | spin_unlock_irqrestore(&common->cc_lock, flags); | ||
| 994 | |||
| 995 | ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, " | ||
| 996 | "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1); | ||
| 997 | if (busy >= 99) { | ||
| 998 | if (++sc->hw_busy_count >= 3) | ||
| 999 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); | ||
| 1000 | |||
| 1001 | } else if (busy >= 0) | ||
| 1002 | sc->hw_busy_count = 0; | ||
| 1003 | |||
| 1004 | out: | ||
| 1036 | ath9k_ps_restore(sc); | 1005 | ath9k_ps_restore(sc); |
| 1006 | } | ||
| 1037 | 1007 | ||
| 1038 | return r; | 1008 | static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum) |
| 1009 | { | ||
| 1010 | static int count; | ||
| 1011 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | ||
| 1012 | |||
| 1013 | if (pll_sqsum >= 0x40000) { | ||
| 1014 | count++; | ||
| 1015 | if (count == 3) { | ||
| 1016 | /* Rx is hung for more than 500ms. Reset it */ | ||
| 1017 | ath_dbg(common, ATH_DBG_RESET, | ||
| 1018 | "Possible RX hang, resetting"); | ||
| 1019 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); | ||
| 1020 | count = 0; | ||
| 1021 | } | ||
| 1022 | } else | ||
| 1023 | count = 0; | ||
| 1024 | } | ||
| 1025 | |||
| 1026 | void ath_hw_pll_work(struct work_struct *work) | ||
| 1027 | { | ||
| 1028 | struct ath_softc *sc = container_of(work, struct ath_softc, | ||
| 1029 | hw_pll_work.work); | ||
| 1030 | u32 pll_sqsum; | ||
| 1031 | |||
| 1032 | if (AR_SREV_9485(sc->sc_ah)) { | ||
| 1033 | |||
| 1034 | ath9k_ps_wakeup(sc); | ||
| 1035 | pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah); | ||
| 1036 | ath9k_ps_restore(sc); | ||
| 1037 | |||
| 1038 | ath_hw_pll_rx_hang_check(sc, pll_sqsum); | ||
| 1039 | |||
| 1040 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5); | ||
| 1041 | } | ||
| 1039 | } | 1042 | } |
| 1040 | 1043 | ||
| 1041 | /**********************/ | 1044 | /**********************/ |
| @@ -1084,28 +1087,6 @@ static int ath9k_start(struct ieee80211_hw *hw) | |||
| 1084 | goto mutex_unlock; | 1087 | goto mutex_unlock; |
| 1085 | } | 1088 | } |
| 1086 | 1089 | ||
| 1087 | /* | ||
| 1088 | * This is needed only to setup initial state | ||
| 1089 | * but it's best done after a reset. | ||
| 1090 | */ | ||
| 1091 | ath9k_cmn_update_txpow(ah, sc->curtxpow, | ||
| 1092 | sc->config.txpowlimit, &sc->curtxpow); | ||
| 1093 | |||
| 1094 | /* | ||
| 1095 | * Setup the hardware after reset: | ||
| 1096 | * The receive engine is set going. | ||
| 1097 | * Frame transmit is handled entirely | ||
| 1098 | * in the frame output path; there's nothing to do | ||
| 1099 | * here except setup the interrupt mask. | ||
| 1100 | */ | ||
| 1101 | if (ath_startrecv(sc) != 0) { | ||
| 1102 | ath_err(common, "Unable to start recv logic\n"); | ||
| 1103 | r = -EIO; | ||
| 1104 | spin_unlock_bh(&sc->sc_pcu_lock); | ||
| 1105 | goto mutex_unlock; | ||
| 1106 | } | ||
| 1107 | spin_unlock_bh(&sc->sc_pcu_lock); | ||
| 1108 | |||
| 1109 | /* Setup our intr mask. */ | 1090 | /* Setup our intr mask. */ |
| 1110 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | | 1091 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
| 1111 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | 1092 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | |
| @@ -1128,12 +1109,14 @@ static int ath9k_start(struct ieee80211_hw *hw) | |||
| 1128 | 1109 | ||
| 1129 | /* Disable BMISS interrupt when we're not associated */ | 1110 | /* Disable BMISS interrupt when we're not associated */ |
| 1130 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); | 1111 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
| 1131 | ath9k_hw_set_interrupts(ah, ah->imask); | ||
| 1132 | ath9k_hw_enable_interrupts(ah); | ||
| 1133 | 1112 | ||
| 1134 | ieee80211_wake_queues(hw); | 1113 | if (!ath_complete_reset(sc, false)) { |
| 1114 | r = -EIO; | ||
| 1115 | spin_unlock_bh(&sc->sc_pcu_lock); | ||
| 1116 | goto mutex_unlock; | ||
| 1117 | } | ||
| 1135 | 1118 | ||
| 1136 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); | 1119 | spin_unlock_bh(&sc->sc_pcu_lock); |
| 1137 | 1120 | ||
| 1138 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && | 1121 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
| 1139 | !ah->btcoex_hw.enabled) { | 1122 | !ah->btcoex_hw.enabled) { |
| @@ -1226,10 +1209,7 @@ static void ath9k_stop(struct ieee80211_hw *hw) | |||
| 1226 | 1209 | ||
| 1227 | mutex_lock(&sc->mutex); | 1210 | mutex_lock(&sc->mutex); |
| 1228 | 1211 | ||
| 1229 | cancel_delayed_work_sync(&sc->tx_complete_work); | 1212 | ath_cancel_work(sc); |
| 1230 | cancel_delayed_work_sync(&sc->hw_pll_work); | ||
| 1231 | cancel_work_sync(&sc->paprd_work); | ||
| 1232 | cancel_work_sync(&sc->hw_check_work); | ||
| 1233 | 1213 | ||
| 1234 | if (sc->sc_flags & SC_OP_INVALID) { | 1214 | if (sc->sc_flags & SC_OP_INVALID) { |
| 1235 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); | 1215 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); |
| @@ -2340,9 +2320,11 @@ static void ath9k_flush(struct ieee80211_hw *hw, bool drop) | |||
| 2340 | ath9k_ps_wakeup(sc); | 2320 | ath9k_ps_wakeup(sc); |
| 2341 | spin_lock_bh(&sc->sc_pcu_lock); | 2321 | spin_lock_bh(&sc->sc_pcu_lock); |
| 2342 | drain_txq = ath_drain_all_txq(sc, false); | 2322 | drain_txq = ath_drain_all_txq(sc, false); |
| 2323 | spin_unlock_bh(&sc->sc_pcu_lock); | ||
| 2324 | |||
| 2343 | if (!drain_txq) | 2325 | if (!drain_txq) |
| 2344 | ath_reset(sc, false); | 2326 | ath_reset(sc, false); |
| 2345 | spin_unlock_bh(&sc->sc_pcu_lock); | 2327 | |
| 2346 | ath9k_ps_restore(sc); | 2328 | ath9k_ps_restore(sc); |
| 2347 | ieee80211_wake_queues(hw); | 2329 | ieee80211_wake_queues(hw); |
| 2348 | 2330 | ||
| @@ -2419,6 +2401,59 @@ static int ath9k_get_stats(struct ieee80211_hw *hw, | |||
| 2419 | return 0; | 2401 | return 0; |
| 2420 | } | 2402 | } |
| 2421 | 2403 | ||
| 2404 | static u32 fill_chainmask(u32 cap, u32 new) | ||
| 2405 | { | ||
| 2406 | u32 filled = 0; | ||
| 2407 | int i; | ||
| 2408 | |||
| 2409 | for (i = 0; cap && new; i++, cap >>= 1) { | ||
| 2410 | if (!(cap & BIT(0))) | ||
| 2411 | continue; | ||
| 2412 | |||
| 2413 | if (new & BIT(0)) | ||
| 2414 | filled |= BIT(i); | ||
| 2415 | |||
| 2416 | new >>= 1; | ||
| 2417 | } | ||
| 2418 | |||
| 2419 | return filled; | ||
| 2420 | } | ||
| 2421 | |||
| 2422 | static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) | ||
| 2423 | { | ||
| 2424 | struct ath_softc *sc = hw->priv; | ||
| 2425 | struct ath_hw *ah = sc->sc_ah; | ||
| 2426 | |||
| 2427 | if (!rx_ant || !tx_ant) | ||
| 2428 | return -EINVAL; | ||
| 2429 | |||
| 2430 | sc->ant_rx = rx_ant; | ||
| 2431 | sc->ant_tx = tx_ant; | ||
| 2432 | |||
| 2433 | if (ah->caps.rx_chainmask == 1) | ||
| 2434 | return 0; | ||
| 2435 | |||
| 2436 | /* AR9100 runs into calibration issues if not all rx chains are enabled */ | ||
| 2437 | if (AR_SREV_9100(ah)) | ||
| 2438 | ah->rxchainmask = 0x7; | ||
| 2439 | else | ||
| 2440 | ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); | ||
| 2441 | |||
| 2442 | ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); | ||
| 2443 | ath9k_reload_chainmask_settings(sc); | ||
| 2444 | |||
| 2445 | return 0; | ||
| 2446 | } | ||
| 2447 | |||
| 2448 | static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) | ||
| 2449 | { | ||
| 2450 | struct ath_softc *sc = hw->priv; | ||
| 2451 | |||
| 2452 | *tx_ant = sc->ant_tx; | ||
| 2453 | *rx_ant = sc->ant_rx; | ||
| 2454 | return 0; | ||
| 2455 | } | ||
| 2456 | |||
| 2422 | struct ieee80211_ops ath9k_ops = { | 2457 | struct ieee80211_ops ath9k_ops = { |
| 2423 | .tx = ath9k_tx, | 2458 | .tx = ath9k_tx, |
| 2424 | .start = ath9k_start, | 2459 | .start = ath9k_start, |
| @@ -2445,4 +2480,6 @@ struct ieee80211_ops ath9k_ops = { | |||
| 2445 | .tx_frames_pending = ath9k_tx_frames_pending, | 2480 | .tx_frames_pending = ath9k_tx_frames_pending, |
| 2446 | .tx_last_beacon = ath9k_tx_last_beacon, | 2481 | .tx_last_beacon = ath9k_tx_last_beacon, |
| 2447 | .get_stats = ath9k_get_stats, | 2482 | .get_stats = ath9k_get_stats, |
| 2483 | .set_antenna = ath9k_set_antenna, | ||
| 2484 | .get_antenna = ath9k_get_antenna, | ||
| 2448 | }; | 2485 | }; |
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c index 891661a61513..d67d6eee3954 100644 --- a/drivers/net/wireless/ath/ath9k/pci.c +++ b/drivers/net/wireless/ath/ath9k/pci.c | |||
| @@ -33,6 +33,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = { | |||
| 33 | { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ | 33 | { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ |
| 34 | { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ | 34 | { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ |
| 35 | { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ | 35 | { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ |
| 36 | { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9480 */ | ||
| 36 | { 0 } | 37 | { 0 } |
| 37 | }; | 38 | }; |
| 38 | 39 | ||
| @@ -332,16 +333,16 @@ static int ath_pci_resume(struct device *device) | |||
| 332 | if ((val & 0x0000ff00) != 0) | 333 | if ((val & 0x0000ff00) != 0) |
| 333 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | 334 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); |
| 334 | 335 | ||
| 336 | ath9k_ps_wakeup(sc); | ||
| 335 | /* Enable LED */ | 337 | /* Enable LED */ |
| 336 | ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin, | 338 | ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin, |
| 337 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | 339 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
| 338 | ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1); | 340 | ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0); |
| 339 | 341 | ||
| 340 | /* | 342 | /* |
| 341 | * Reset key cache to sane defaults (all entries cleared) instead of | 343 | * Reset key cache to sane defaults (all entries cleared) instead of |
| 342 | * semi-random values after suspend/resume. | 344 | * semi-random values after suspend/resume. |
| 343 | */ | 345 | */ |
| 344 | ath9k_ps_wakeup(sc); | ||
| 345 | ath9k_cmn_init_crypto(sc->sc_ah); | 346 | ath9k_cmn_init_crypto(sc->sc_ah); |
| 346 | ath9k_ps_restore(sc); | 347 | ath9k_ps_restore(sc); |
| 347 | 348 | ||
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c index 9c7f905f3871..bcc0b222ec18 100644 --- a/drivers/net/wireless/ath/ath9k/recv.c +++ b/drivers/net/wireless/ath/ath9k/recv.c | |||
| @@ -1839,7 +1839,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp) | |||
| 1839 | * If we're asked to flush receive queue, directly | 1839 | * If we're asked to flush receive queue, directly |
| 1840 | * chain it back at the queue without processing it. | 1840 | * chain it back at the queue without processing it. |
| 1841 | */ | 1841 | */ |
| 1842 | if (flush) | 1842 | if (sc->sc_flags & SC_OP_RXFLUSH) |
| 1843 | goto requeue_drop_frag; | 1843 | goto requeue_drop_frag; |
| 1844 | 1844 | ||
| 1845 | retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs, | 1845 | retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs, |
| @@ -1950,7 +1950,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp) | |||
| 1950 | ath_rx_ps(sc, skb); | 1950 | ath_rx_ps(sc, skb); |
| 1951 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | 1951 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
| 1952 | 1952 | ||
| 1953 | if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | 1953 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx == 3) |
| 1954 | ath_ant_comb_scan(sc, &rs); | 1954 | ath_ant_comb_scan(sc, &rs); |
| 1955 | 1955 | ||
| 1956 | ieee80211_rx(hw, skb); | 1956 | ieee80211_rx(hw, skb); |
| @@ -1967,7 +1967,8 @@ requeue: | |||
| 1967 | } else { | 1967 | } else { |
| 1968 | list_move_tail(&bf->list, &sc->rx.rxbuf); | 1968 | list_move_tail(&bf->list, &sc->rx.rxbuf); |
| 1969 | ath_rx_buf_link(sc, bf); | 1969 | ath_rx_buf_link(sc, bf); |
| 1970 | ath9k_hw_rxena(ah); | 1970 | if (!flush) |
| 1971 | ath9k_hw_rxena(ah); | ||
| 1971 | } | 1972 | } |
| 1972 | } while (1); | 1973 | } while (1); |
| 1973 | 1974 | ||
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h index 17a272f4d8d6..0846654b57ef 100644 --- a/drivers/net/wireless/ath/ath9k/reg.h +++ b/drivers/net/wireless/ath/ath9k/reg.h | |||
| @@ -796,6 +796,9 @@ | |||
| 796 | #define AR_SREV_VERSION_9340 0x300 | 796 | #define AR_SREV_VERSION_9340 0x300 |
| 797 | #define AR_SREV_VERSION_9580 0x1C0 | 797 | #define AR_SREV_VERSION_9580 0x1C0 |
| 798 | #define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */ | 798 | #define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */ |
| 799 | #define AR_SREV_VERSION_9480 0x280 | ||
| 800 | #define AR_SREV_REVISION_9480_10 0 | ||
| 801 | #define AR_SREV_REVISION_9480_20 2 | ||
| 799 | 802 | ||
| 800 | #define AR_SREV_5416(_ah) \ | 803 | #define AR_SREV_5416(_ah) \ |
| 801 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ | 804 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ |
| @@ -896,6 +899,21 @@ | |||
| 896 | (AR_SREV_9285_12_OR_LATER(_ah) && \ | 899 | (AR_SREV_9285_12_OR_LATER(_ah) && \ |
| 897 | ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) | 900 | ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) |
| 898 | 901 | ||
| 902 | #define AR_SREV_9480(_ah) \ | ||
| 903 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480)) | ||
| 904 | |||
| 905 | #define AR_SREV_9480_10(_ah) \ | ||
| 906 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480) && \ | ||
| 907 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9480_10)) | ||
| 908 | |||
| 909 | #define AR_SREV_9480_20(_ah) \ | ||
| 910 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480) && \ | ||
| 911 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9480_20)) | ||
| 912 | |||
| 913 | #define AR_SREV_9480_20_OR_LATER(_ah) \ | ||
| 914 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480) && \ | ||
| 915 | ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9480_20)) | ||
| 916 | |||
| 899 | #define AR_SREV_9580(_ah) \ | 917 | #define AR_SREV_9580(_ah) \ |
| 900 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \ | 918 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \ |
| 901 | ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9580_10)) | 919 | ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9580_10)) |
| @@ -1132,7 +1150,7 @@ enum { | |||
| 1132 | #define AR_INTR_PRIO_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4094 : 0x40d4) | 1150 | #define AR_INTR_PRIO_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4094 : 0x40d4) |
| 1133 | #define AR_ENT_OTP 0x40d8 | 1151 | #define AR_ENT_OTP 0x40d8 |
| 1134 | #define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000 | 1152 | #define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000 |
| 1135 | #define AR_ENT_OTP_MPSD 0x00800000 | 1153 | #define AR_ENT_OTP_MIN_PKT_SIZE_DISABLE 0x00800000 |
| 1136 | 1154 | ||
| 1137 | #define AR_CH0_BB_DPLL1 0x16180 | 1155 | #define AR_CH0_BB_DPLL1 0x16180 |
| 1138 | #define AR_CH0_BB_DPLL1_REFDIV 0xF8000000 | 1156 | #define AR_CH0_BB_DPLL1_REFDIV 0xF8000000 |
| @@ -1779,6 +1797,7 @@ enum { | |||
| 1779 | #define AR_TXOP_12_15 0x81fc | 1797 | #define AR_TXOP_12_15 0x81fc |
| 1780 | 1798 | ||
| 1781 | #define AR_NEXT_NDP2_TIMER 0x8180 | 1799 | #define AR_NEXT_NDP2_TIMER 0x8180 |
| 1800 | #define AR_GEN_TIMER_BANK_1_LEN 8 | ||
| 1782 | #define AR_FIRST_NDP_TIMER 7 | 1801 | #define AR_FIRST_NDP_TIMER 7 |
| 1783 | #define AR_NDP2_PERIOD 0x81a0 | 1802 | #define AR_NDP2_PERIOD 0x81a0 |
| 1784 | #define AR_NDP2_TIMER_MODE 0x81c0 | 1803 | #define AR_NDP2_TIMER_MODE 0x81c0 |
| @@ -1867,9 +1886,10 @@ enum { | |||
| 1867 | #define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 | 1886 | #define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 |
| 1868 | #define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000 | 1887 | #define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000 |
| 1869 | 1888 | ||
| 1870 | #define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 | 1889 | #define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 |
| 1871 | #define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 | 1890 | #define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 |
| 1872 | #define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 | 1891 | #define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 |
| 1892 | #define AR_MAC_PCU_GEN_TIMER_TSF_SEL 0x83d8 | ||
| 1873 | 1893 | ||
| 1874 | 1894 | ||
| 1875 | #define AR_AES_MUTE_MASK0 0x805c | 1895 | #define AR_AES_MUTE_MASK0 0x805c |
| @@ -1920,4 +1940,38 @@ enum { | |||
| 1920 | #define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0 | 1940 | #define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0 |
| 1921 | #define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 | 1941 | #define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 |
| 1922 | 1942 | ||
| 1943 | /* MCI Registers */ | ||
| 1944 | #define AR_MCI_INTERRUPT_RX_MSG_EN 0x183c | ||
| 1945 | #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001 | ||
| 1946 | #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0 | ||
| 1947 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002 | ||
| 1948 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S 1 | ||
| 1949 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004 | ||
| 1950 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S 2 | ||
| 1951 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008 | ||
| 1952 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S 3 | ||
| 1953 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010 | ||
| 1954 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S 4 | ||
| 1955 | #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020 | ||
| 1956 | #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S 5 | ||
| 1957 | #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040 | ||
| 1958 | #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S 6 | ||
| 1959 | #define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100 | ||
| 1960 | #define AR_MCI_INTERRUPT_RX_MSG_GPM_S 8 | ||
| 1961 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200 | ||
| 1962 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S 9 | ||
| 1963 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400 | ||
| 1964 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S 10 | ||
| 1965 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800 | ||
| 1966 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S 11 | ||
| 1967 | #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000 | ||
| 1968 | #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S 12 | ||
| 1969 | #define AR_MCI_INTERRUPT_RX_HW_MSG_MASK (AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \ | ||
| 1970 | AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL| \ | ||
| 1971 | AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ | ||
| 1972 | AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ | ||
| 1973 | AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ | ||
| 1974 | AR_MCI_INTERRUPT_RX_MSG_CONT_RST) | ||
| 1975 | |||
| 1976 | |||
| 1923 | #endif | 1977 | #endif |
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c index 68066c56e4e5..2c6aefad3728 100644 --- a/drivers/net/wireless/ath/ath9k/xmit.c +++ b/drivers/net/wireless/ath/ath9k/xmit.c | |||
| @@ -56,10 +56,9 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, | |||
| 56 | struct ath_tx_status *ts, int txok, int sendbar); | 56 | struct ath_tx_status *ts, int txok, int sendbar); |
| 57 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, | 57 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
| 58 | struct list_head *head, bool internal); | 58 | struct list_head *head, bool internal); |
| 59 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len); | ||
| 60 | static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, | 59 | static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, |
| 61 | struct ath_tx_status *ts, int nframes, int nbad, | 60 | struct ath_tx_status *ts, int nframes, int nbad, |
| 62 | int txok, bool update_rc); | 61 | int txok); |
| 63 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, | 62 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
| 64 | int seqno); | 63 | int seqno); |
| 65 | static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, | 64 | static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, |
| @@ -390,11 +389,9 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |||
| 390 | while (bf) { | 389 | while (bf) { |
| 391 | bf_next = bf->bf_next; | 390 | bf_next = bf->bf_next; |
| 392 | 391 | ||
| 393 | bf->bf_state.bf_type |= BUF_XRETRY; | ||
| 394 | if (!bf->bf_stale || bf_next != NULL) | 392 | if (!bf->bf_stale || bf_next != NULL) |
| 395 | list_move_tail(&bf->list, &bf_head); | 393 | list_move_tail(&bf->list, &bf_head); |
| 396 | 394 | ||
| 397 | ath_tx_rc_status(sc, bf, ts, 1, 1, 0, false); | ||
| 398 | ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, | 395 | ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, |
| 399 | 0, 0); | 396 | 0, 0); |
| 400 | 397 | ||
| @@ -470,7 +467,6 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |||
| 470 | clear_filter = true; | 467 | clear_filter = true; |
| 471 | txpending = 1; | 468 | txpending = 1; |
| 472 | } else { | 469 | } else { |
| 473 | bf->bf_state.bf_type |= BUF_XRETRY; | ||
| 474 | txfail = 1; | 470 | txfail = 1; |
| 475 | sendbar = 1; | 471 | sendbar = 1; |
| 476 | txfail_cnt++; | 472 | txfail_cnt++; |
| @@ -497,17 +493,14 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |||
| 497 | 493 | ||
| 498 | if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { | 494 | if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { |
| 499 | memcpy(tx_info->control.rates, rates, sizeof(rates)); | 495 | memcpy(tx_info->control.rates, rates, sizeof(rates)); |
| 500 | ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, true); | 496 | ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok); |
| 501 | rc_update = false; | 497 | rc_update = false; |
| 502 | } else { | ||
| 503 | ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, false); | ||
| 504 | } | 498 | } |
| 505 | 499 | ||
| 506 | ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, | 500 | ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, |
| 507 | !txfail, sendbar); | 501 | !txfail, sendbar); |
| 508 | } else { | 502 | } else { |
| 509 | /* retry the un-acked ones */ | 503 | /* retry the un-acked ones */ |
| 510 | ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, false); | ||
| 511 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) { | 504 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) { |
| 512 | if (bf->bf_next == NULL && bf_last->bf_stale) { | 505 | if (bf->bf_next == NULL && bf_last->bf_stale) { |
| 513 | struct ath_buf *tbf; | 506 | struct ath_buf *tbf; |
| @@ -523,26 +516,13 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |||
| 523 | ath_tx_update_baw(sc, tid, seqno); | 516 | ath_tx_update_baw(sc, tid, seqno); |
| 524 | spin_unlock_bh(&txq->axq_lock); | 517 | spin_unlock_bh(&txq->axq_lock); |
| 525 | 518 | ||
| 526 | bf->bf_state.bf_type |= | ||
| 527 | BUF_XRETRY; | ||
| 528 | ath_tx_rc_status(sc, bf, ts, nframes, | ||
| 529 | nbad, 0, false); | ||
| 530 | ath_tx_complete_buf(sc, bf, txq, | 519 | ath_tx_complete_buf(sc, bf, txq, |
| 531 | &bf_head, | 520 | &bf_head, |
| 532 | ts, 0, 0); | 521 | ts, 0, 1); |
| 533 | break; | 522 | break; |
| 534 | } | 523 | } |
| 535 | 524 | ||
| 536 | ath9k_hw_cleartxdesc(sc->sc_ah, | ||
| 537 | tbf->bf_desc); | ||
| 538 | fi->bf = tbf; | 525 | fi->bf = tbf; |
| 539 | } else { | ||
| 540 | /* | ||
| 541 | * Clear descriptor status words for | ||
| 542 | * software retry | ||
| 543 | */ | ||
| 544 | ath9k_hw_cleartxdesc(sc->sc_ah, | ||
| 545 | bf->bf_desc); | ||
| 546 | } | 526 | } |
| 547 | } | 527 | } |
| 548 | 528 | ||
| @@ -582,7 +562,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |||
| 582 | rcu_read_unlock(); | 562 | rcu_read_unlock(); |
| 583 | 563 | ||
| 584 | if (needreset) | 564 | if (needreset) |
| 585 | ath_reset(sc, false); | 565 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
| 586 | } | 566 | } |
| 587 | 567 | ||
| 588 | static bool ath_lookup_legacy(struct ath_buf *bf) | 568 | static bool ath_lookup_legacy(struct ath_buf *bf) |
| @@ -709,7 +689,8 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, | |||
| 709 | * Add delimiter when using RTS/CTS with aggregation | 689 | * Add delimiter when using RTS/CTS with aggregation |
| 710 | * and non enterprise AR9003 card | 690 | * and non enterprise AR9003 card |
| 711 | */ | 691 | */ |
| 712 | if (first_subfrm) | 692 | if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) && |
| 693 | (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE)) | ||
| 713 | ndelim = max(ndelim, FIRST_DESC_NDELIMS); | 694 | ndelim = max(ndelim, FIRST_DESC_NDELIMS); |
| 714 | 695 | ||
| 715 | /* | 696 | /* |
| @@ -777,7 +758,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, | |||
| 777 | if (!bf) | 758 | if (!bf) |
| 778 | continue; | 759 | continue; |
| 779 | 760 | ||
| 780 | bf->bf_state.bf_type |= BUF_AMPDU; | 761 | bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR; |
| 781 | seqno = bf->bf_state.seqno; | 762 | seqno = bf->bf_state.seqno; |
| 782 | if (!bf_first) | 763 | if (!bf_first) |
| 783 | bf_first = bf; | 764 | bf_first = bf; |
| @@ -804,8 +785,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, | |||
| 804 | } | 785 | } |
| 805 | 786 | ||
| 806 | tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); | 787 | tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); |
| 807 | if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) || | 788 | if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) |
| 808 | !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS))) | ||
| 809 | break; | 789 | break; |
| 810 | 790 | ||
| 811 | /* do not exceed subframe limit */ | 791 | /* do not exceed subframe limit */ |
| @@ -827,20 +807,17 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, | |||
| 827 | 807 | ||
| 828 | nframes++; | 808 | nframes++; |
| 829 | bf->bf_next = NULL; | 809 | bf->bf_next = NULL; |
| 830 | ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0); | ||
| 831 | 810 | ||
| 832 | /* link buffers of this frame to the aggregate */ | 811 | /* link buffers of this frame to the aggregate */ |
| 833 | if (!fi->retries) | 812 | if (!fi->retries) |
| 834 | ath_tx_addto_baw(sc, tid, seqno); | 813 | ath_tx_addto_baw(sc, tid, seqno); |
| 835 | ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim); | 814 | bf->bf_state.ndelim = ndelim; |
| 836 | 815 | ||
| 837 | __skb_unlink(skb, &tid->buf_q); | 816 | __skb_unlink(skb, &tid->buf_q); |
| 838 | list_add_tail(&bf->list, bf_q); | 817 | list_add_tail(&bf->list, bf_q); |
| 839 | if (bf_prev) { | 818 | if (bf_prev) |
| 840 | bf_prev->bf_next = bf; | 819 | bf_prev->bf_next = bf; |
| 841 | ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc, | 820 | |
| 842 | bf->bf_daddr); | ||
| 843 | } | ||
| 844 | bf_prev = bf; | 821 | bf_prev = bf; |
| 845 | 822 | ||
| 846 | } while (!skb_queue_empty(&tid->buf_q)); | 823 | } while (!skb_queue_empty(&tid->buf_q)); |
| @@ -851,12 +828,245 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, | |||
| 851 | #undef PADBYTES | 828 | #undef PADBYTES |
| 852 | } | 829 | } |
| 853 | 830 | ||
| 831 | /* | ||
| 832 | * rix - rate index | ||
| 833 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | ||
| 834 | * width - 0 for 20 MHz, 1 for 40 MHz | ||
| 835 | * half_gi - to use 4us v/s 3.6 us for symbol time | ||
| 836 | */ | ||
| 837 | static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, | ||
| 838 | int width, int half_gi, bool shortPreamble) | ||
| 839 | { | ||
| 840 | u32 nbits, nsymbits, duration, nsymbols; | ||
| 841 | int streams; | ||
| 842 | |||
| 843 | /* find number of symbols: PLCP + data */ | ||
| 844 | streams = HT_RC_2_STREAMS(rix); | ||
| 845 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | ||
| 846 | nsymbits = bits_per_symbol[rix % 8][width] * streams; | ||
| 847 | nsymbols = (nbits + nsymbits - 1) / nsymbits; | ||
| 848 | |||
| 849 | if (!half_gi) | ||
| 850 | duration = SYMBOL_TIME(nsymbols); | ||
| 851 | else | ||
| 852 | duration = SYMBOL_TIME_HALFGI(nsymbols); | ||
| 853 | |||
| 854 | /* addup duration for legacy/ht training and signal fields */ | ||
| 855 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); | ||
| 856 | |||
| 857 | return duration; | ||
| 858 | } | ||
| 859 | |||
| 860 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, | ||
| 861 | struct ath_tx_info *info, int len) | ||
| 862 | { | ||
| 863 | struct ath_hw *ah = sc->sc_ah; | ||
| 864 | struct sk_buff *skb; | ||
| 865 | struct ieee80211_tx_info *tx_info; | ||
| 866 | struct ieee80211_tx_rate *rates; | ||
| 867 | const struct ieee80211_rate *rate; | ||
| 868 | struct ieee80211_hdr *hdr; | ||
| 869 | int i; | ||
| 870 | u8 rix = 0; | ||
| 871 | |||
| 872 | skb = bf->bf_mpdu; | ||
| 873 | tx_info = IEEE80211_SKB_CB(skb); | ||
| 874 | rates = tx_info->control.rates; | ||
| 875 | hdr = (struct ieee80211_hdr *)skb->data; | ||
| 876 | |||
| 877 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ | ||
| 878 | info->dur_update = !ieee80211_is_pspoll(hdr->frame_control); | ||
| 879 | |||
| 880 | /* | ||
| 881 | * We check if Short Preamble is needed for the CTS rate by | ||
| 882 | * checking the BSS's global flag. | ||
| 883 | * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. | ||
| 884 | */ | ||
| 885 | rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info); | ||
| 886 | info->rtscts_rate = rate->hw_value; | ||
| 887 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) | ||
| 888 | info->rtscts_rate |= rate->hw_value_short; | ||
| 889 | |||
| 890 | for (i = 0; i < 4; i++) { | ||
| 891 | bool is_40, is_sgi, is_sp; | ||
| 892 | int phy; | ||
| 893 | |||
| 894 | if (!rates[i].count || (rates[i].idx < 0)) | ||
| 895 | continue; | ||
| 896 | |||
| 897 | rix = rates[i].idx; | ||
| 898 | info->rates[i].Tries = rates[i].count; | ||
| 899 | |||
| 900 | if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) { | ||
| 901 | info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | ||
| 902 | info->flags |= ATH9K_TXDESC_RTSENA; | ||
| 903 | } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { | ||
| 904 | info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | ||
| 905 | info->flags |= ATH9K_TXDESC_CTSENA; | ||
| 906 | } | ||
| 907 | |||
| 908 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | ||
| 909 | info->rates[i].RateFlags |= ATH9K_RATESERIES_2040; | ||
| 910 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) | ||
| 911 | info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI; | ||
| 912 | |||
| 913 | is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); | ||
| 914 | is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); | ||
| 915 | is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); | ||
| 916 | |||
| 917 | if (rates[i].flags & IEEE80211_TX_RC_MCS) { | ||
| 918 | /* MCS rates */ | ||
| 919 | info->rates[i].Rate = rix | 0x80; | ||
| 920 | info->rates[i].ChSel = ath_txchainmask_reduction(sc, | ||
| 921 | ah->txchainmask, info->rates[i].Rate); | ||
| 922 | info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len, | ||
| 923 | is_40, is_sgi, is_sp); | ||
| 924 | if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) | ||
| 925 | info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC; | ||
| 926 | continue; | ||
| 927 | } | ||
| 928 | |||
| 929 | /* legacy rates */ | ||
| 930 | if ((tx_info->band == IEEE80211_BAND_2GHZ) && | ||
| 931 | !(rate->flags & IEEE80211_RATE_ERP_G)) | ||
| 932 | phy = WLAN_RC_PHY_CCK; | ||
| 933 | else | ||
| 934 | phy = WLAN_RC_PHY_OFDM; | ||
| 935 | |||
| 936 | rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx]; | ||
| 937 | info->rates[i].Rate = rate->hw_value; | ||
| 938 | if (rate->hw_value_short) { | ||
| 939 | if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | ||
| 940 | info->rates[i].Rate |= rate->hw_value_short; | ||
| 941 | } else { | ||
| 942 | is_sp = false; | ||
| 943 | } | ||
| 944 | |||
| 945 | if (bf->bf_state.bfs_paprd) | ||
| 946 | info->rates[i].ChSel = ah->txchainmask; | ||
| 947 | else | ||
| 948 | info->rates[i].ChSel = ath_txchainmask_reduction(sc, | ||
| 949 | ah->txchainmask, info->rates[i].Rate); | ||
| 950 | |||
| 951 | info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, | ||
| 952 | phy, rate->bitrate * 100, len, rix, is_sp); | ||
| 953 | } | ||
| 954 | |||
| 955 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ | ||
| 956 | if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) | ||
| 957 | info->flags &= ~ATH9K_TXDESC_RTSENA; | ||
| 958 | |||
| 959 | /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ | ||
| 960 | if (info->flags & ATH9K_TXDESC_RTSENA) | ||
| 961 | info->flags &= ~ATH9K_TXDESC_CTSENA; | ||
| 962 | } | ||
| 963 | |||
| 964 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) | ||
| 965 | { | ||
| 966 | struct ieee80211_hdr *hdr; | ||
| 967 | enum ath9k_pkt_type htype; | ||
| 968 | __le16 fc; | ||
| 969 | |||
| 970 | hdr = (struct ieee80211_hdr *)skb->data; | ||
| 971 | fc = hdr->frame_control; | ||
| 972 | |||
| 973 | if (ieee80211_is_beacon(fc)) | ||
| 974 | htype = ATH9K_PKT_TYPE_BEACON; | ||
| 975 | else if (ieee80211_is_probe_resp(fc)) | ||
| 976 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | ||
| 977 | else if (ieee80211_is_atim(fc)) | ||
| 978 | htype = ATH9K_PKT_TYPE_ATIM; | ||
| 979 | else if (ieee80211_is_pspoll(fc)) | ||
| 980 | htype = ATH9K_PKT_TYPE_PSPOLL; | ||
| 981 | else | ||
| 982 | htype = ATH9K_PKT_TYPE_NORMAL; | ||
| 983 | |||
| 984 | return htype; | ||
| 985 | } | ||
| 986 | |||
| 987 | static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf, | ||
| 988 | struct ath_txq *txq, int len) | ||
| 989 | { | ||
| 990 | struct ath_hw *ah = sc->sc_ah; | ||
| 991 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); | ||
| 992 | struct ath_buf *bf_first = bf; | ||
| 993 | struct ath_tx_info info; | ||
| 994 | bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR); | ||
| 995 | |||
| 996 | memset(&info, 0, sizeof(info)); | ||
| 997 | info.is_first = true; | ||
| 998 | info.is_last = true; | ||
| 999 | info.txpower = MAX_RATE_POWER; | ||
| 1000 | info.qcu = txq->axq_qnum; | ||
| 1001 | |||
| 1002 | info.flags = ATH9K_TXDESC_INTREQ; | ||
| 1003 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | ||
| 1004 | info.flags |= ATH9K_TXDESC_NOACK; | ||
| 1005 | if (tx_info->flags & IEEE80211_TX_CTL_LDPC) | ||
| 1006 | info.flags |= ATH9K_TXDESC_LDPC; | ||
| 1007 | |||
| 1008 | ath_buf_set_rate(sc, bf, &info, len); | ||
| 1009 | |||
| 1010 | if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) | ||
| 1011 | info.flags |= ATH9K_TXDESC_CLRDMASK; | ||
| 1012 | |||
| 1013 | if (bf->bf_state.bfs_paprd) | ||
| 1014 | info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S; | ||
| 1015 | |||
| 1016 | |||
| 1017 | while (bf) { | ||
| 1018 | struct sk_buff *skb = bf->bf_mpdu; | ||
| 1019 | struct ath_frame_info *fi = get_frame_info(skb); | ||
| 1020 | struct ieee80211_hdr *hdr; | ||
| 1021 | int padpos, padsize; | ||
| 1022 | |||
| 1023 | info.type = get_hw_packet_type(skb); | ||
| 1024 | if (bf->bf_next) | ||
| 1025 | info.link = bf->bf_next->bf_daddr; | ||
| 1026 | else | ||
| 1027 | info.link = 0; | ||
| 1028 | |||
| 1029 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { | ||
| 1030 | hdr = (struct ieee80211_hdr *)skb->data; | ||
| 1031 | padpos = ath9k_cmn_padpos(hdr->frame_control); | ||
| 1032 | padsize = padpos & 3; | ||
| 1033 | |||
| 1034 | info.buf_addr[0] = bf->bf_buf_addr; | ||
| 1035 | info.buf_len[0] = padpos + padsize; | ||
| 1036 | info.buf_addr[1] = info.buf_addr[0] + padpos; | ||
| 1037 | info.buf_len[1] = skb->len - padpos; | ||
| 1038 | } else { | ||
| 1039 | info.buf_addr[0] = bf->bf_buf_addr; | ||
| 1040 | info.buf_len[0] = skb->len; | ||
| 1041 | } | ||
| 1042 | |||
| 1043 | info.pkt_len = fi->framelen; | ||
| 1044 | info.keyix = fi->keyix; | ||
| 1045 | info.keytype = fi->keytype; | ||
| 1046 | |||
| 1047 | if (aggr) { | ||
| 1048 | if (bf == bf_first) | ||
| 1049 | info.aggr = AGGR_BUF_FIRST; | ||
| 1050 | else if (!bf->bf_next) | ||
| 1051 | info.aggr = AGGR_BUF_LAST; | ||
| 1052 | else | ||
| 1053 | info.aggr = AGGR_BUF_MIDDLE; | ||
| 1054 | |||
| 1055 | info.ndelim = bf->bf_state.ndelim; | ||
| 1056 | info.aggr_len = len; | ||
| 1057 | } | ||
| 1058 | |||
| 1059 | ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); | ||
| 1060 | bf = bf->bf_next; | ||
| 1061 | } | ||
| 1062 | } | ||
| 1063 | |||
| 854 | static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, | 1064 | static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, |
| 855 | struct ath_atx_tid *tid) | 1065 | struct ath_atx_tid *tid) |
| 856 | { | 1066 | { |
| 857 | struct ath_buf *bf; | 1067 | struct ath_buf *bf; |
| 858 | enum ATH_AGGR_STATUS status; | 1068 | enum ATH_AGGR_STATUS status; |
| 859 | struct ath_frame_info *fi; | 1069 | struct ieee80211_tx_info *tx_info; |
| 860 | struct list_head bf_q; | 1070 | struct list_head bf_q; |
| 861 | int aggr_len; | 1071 | int aggr_len; |
| 862 | 1072 | ||
| @@ -877,34 +1087,25 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, | |||
| 877 | 1087 | ||
| 878 | bf = list_first_entry(&bf_q, struct ath_buf, list); | 1088 | bf = list_first_entry(&bf_q, struct ath_buf, list); |
| 879 | bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); | 1089 | bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); |
| 1090 | tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); | ||
| 880 | 1091 | ||
| 881 | if (tid->ac->clear_ps_filter) { | 1092 | if (tid->ac->clear_ps_filter) { |
| 882 | tid->ac->clear_ps_filter = false; | 1093 | tid->ac->clear_ps_filter = false; |
| 883 | ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true); | 1094 | tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; |
| 1095 | } else { | ||
| 1096 | tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT; | ||
| 884 | } | 1097 | } |
| 885 | 1098 | ||
| 886 | /* if only one frame, send as non-aggregate */ | 1099 | /* if only one frame, send as non-aggregate */ |
| 887 | if (bf == bf->bf_lastbf) { | 1100 | if (bf == bf->bf_lastbf) { |
| 888 | fi = get_frame_info(bf->bf_mpdu); | 1101 | aggr_len = get_frame_info(bf->bf_mpdu)->framelen; |
| 889 | 1102 | bf->bf_state.bf_type = BUF_AMPDU; | |
| 890 | bf->bf_state.bf_type &= ~BUF_AGGR; | 1103 | } else { |
| 891 | ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc); | 1104 | TX_STAT_INC(txq->axq_qnum, a_aggr); |
| 892 | ath_buf_set_rate(sc, bf, fi->framelen); | ||
| 893 | ath_tx_txqaddbuf(sc, txq, &bf_q, false); | ||
| 894 | continue; | ||
| 895 | } | 1105 | } |
| 896 | 1106 | ||
| 897 | /* setup first desc of aggregate */ | 1107 | ath_tx_fill_desc(sc, bf, txq, aggr_len); |
| 898 | bf->bf_state.bf_type |= BUF_AGGR; | ||
| 899 | ath_buf_set_rate(sc, bf, aggr_len); | ||
| 900 | ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len); | ||
| 901 | |||
| 902 | /* anchor last desc of aggregate */ | ||
| 903 | ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); | ||
| 904 | |||
| 905 | ath_tx_txqaddbuf(sc, txq, &bf_q, false); | 1108 | ath_tx_txqaddbuf(sc, txq, &bf_q, false); |
| 906 | TX_STAT_INC(txq->axq_qnum, a_aggr); | ||
| 907 | |||
| 908 | } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH && | 1109 | } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH && |
| 909 | status != ATH_AGGR_BAW_CLOSED); | 1110 | status != ATH_AGGR_BAW_CLOSED); |
| 910 | } | 1111 | } |
| @@ -1332,7 +1533,7 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) | |||
| 1332 | struct ath_atx_ac *ac, *ac_tmp, *last_ac; | 1533 | struct ath_atx_ac *ac, *ac_tmp, *last_ac; |
| 1333 | struct ath_atx_tid *tid, *last_tid; | 1534 | struct ath_atx_tid *tid, *last_tid; |
| 1334 | 1535 | ||
| 1335 | if (list_empty(&txq->axq_acq) || | 1536 | if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) || |
| 1336 | txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) | 1537 | txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) |
| 1337 | return; | 1538 | return; |
| 1338 | 1539 | ||
| @@ -1482,7 +1683,7 @@ static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, | |||
| 1482 | if (!bf) | 1683 | if (!bf) |
| 1483 | return; | 1684 | return; |
| 1484 | 1685 | ||
| 1485 | bf->bf_state.bf_type |= BUF_AMPDU; | 1686 | bf->bf_state.bf_type = BUF_AMPDU; |
| 1486 | INIT_LIST_HEAD(&bf_head); | 1687 | INIT_LIST_HEAD(&bf_head); |
| 1487 | list_add(&bf->list, &bf_head); | 1688 | list_add(&bf->list, &bf_head); |
| 1488 | 1689 | ||
| @@ -1492,7 +1693,7 @@ static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, | |||
| 1492 | /* Queue to h/w without aggregation */ | 1693 | /* Queue to h/w without aggregation */ |
| 1493 | TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw); | 1694 | TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw); |
| 1494 | bf->bf_lastbf = bf; | 1695 | bf->bf_lastbf = bf; |
| 1495 | ath_buf_set_rate(sc, bf, fi->framelen); | 1696 | ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen); |
| 1496 | ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false); | 1697 | ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false); |
| 1497 | } | 1698 | } |
| 1498 | 1699 | ||
| @@ -1512,41 +1713,18 @@ static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, | |||
| 1512 | 1713 | ||
| 1513 | INIT_LIST_HEAD(&bf_head); | 1714 | INIT_LIST_HEAD(&bf_head); |
| 1514 | list_add_tail(&bf->list, &bf_head); | 1715 | list_add_tail(&bf->list, &bf_head); |
| 1515 | bf->bf_state.bf_type &= ~BUF_AMPDU; | 1716 | bf->bf_state.bf_type = 0; |
| 1516 | 1717 | ||
| 1517 | /* update starting sequence number for subsequent ADDBA request */ | 1718 | /* update starting sequence number for subsequent ADDBA request */ |
| 1518 | if (tid) | 1719 | if (tid) |
| 1519 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | 1720 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); |
| 1520 | 1721 | ||
| 1521 | bf->bf_lastbf = bf; | 1722 | bf->bf_lastbf = bf; |
| 1522 | ath_buf_set_rate(sc, bf, fi->framelen); | 1723 | ath_tx_fill_desc(sc, bf, txq, fi->framelen); |
| 1523 | ath_tx_txqaddbuf(sc, txq, &bf_head, false); | 1724 | ath_tx_txqaddbuf(sc, txq, &bf_head, false); |
| 1524 | TX_STAT_INC(txq->axq_qnum, queued); | 1725 | TX_STAT_INC(txq->axq_qnum, queued); |
| 1525 | } | 1726 | } |
| 1526 | 1727 | ||
| 1527 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) | ||
| 1528 | { | ||
| 1529 | struct ieee80211_hdr *hdr; | ||
| 1530 | enum ath9k_pkt_type htype; | ||
| 1531 | __le16 fc; | ||
| 1532 | |||
| 1533 | hdr = (struct ieee80211_hdr *)skb->data; | ||
| 1534 | fc = hdr->frame_control; | ||
| 1535 | |||
| 1536 | if (ieee80211_is_beacon(fc)) | ||
| 1537 | htype = ATH9K_PKT_TYPE_BEACON; | ||
| 1538 | else if (ieee80211_is_probe_resp(fc)) | ||
| 1539 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | ||
| 1540 | else if (ieee80211_is_atim(fc)) | ||
| 1541 | htype = ATH9K_PKT_TYPE_ATIM; | ||
| 1542 | else if (ieee80211_is_pspoll(fc)) | ||
| 1543 | htype = ATH9K_PKT_TYPE_PSPOLL; | ||
| 1544 | else | ||
| 1545 | htype = ATH9K_PKT_TYPE_NORMAL; | ||
| 1546 | |||
| 1547 | return htype; | ||
| 1548 | } | ||
| 1549 | |||
| 1550 | static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb, | 1728 | static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb, |
| 1551 | int framelen) | 1729 | int framelen) |
| 1552 | { | 1730 | { |
| @@ -1574,51 +1752,6 @@ static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb, | |||
| 1574 | fi->framelen = framelen; | 1752 | fi->framelen = framelen; |
| 1575 | } | 1753 | } |
| 1576 | 1754 | ||
| 1577 | static int setup_tx_flags(struct sk_buff *skb) | ||
| 1578 | { | ||
| 1579 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | ||
| 1580 | int flags = 0; | ||
| 1581 | |||
| 1582 | flags |= ATH9K_TXDESC_INTREQ; | ||
| 1583 | |||
| 1584 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | ||
| 1585 | flags |= ATH9K_TXDESC_NOACK; | ||
| 1586 | |||
| 1587 | if (tx_info->flags & IEEE80211_TX_CTL_LDPC) | ||
| 1588 | flags |= ATH9K_TXDESC_LDPC; | ||
| 1589 | |||
| 1590 | return flags; | ||
| 1591 | } | ||
| 1592 | |||
| 1593 | /* | ||
| 1594 | * rix - rate index | ||
| 1595 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | ||
| 1596 | * width - 0 for 20 MHz, 1 for 40 MHz | ||
| 1597 | * half_gi - to use 4us v/s 3.6 us for symbol time | ||
| 1598 | */ | ||
| 1599 | static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, | ||
| 1600 | int width, int half_gi, bool shortPreamble) | ||
| 1601 | { | ||
| 1602 | u32 nbits, nsymbits, duration, nsymbols; | ||
| 1603 | int streams; | ||
| 1604 | |||
| 1605 | /* find number of symbols: PLCP + data */ | ||
| 1606 | streams = HT_RC_2_STREAMS(rix); | ||
| 1607 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | ||
| 1608 | nsymbits = bits_per_symbol[rix % 8][width] * streams; | ||
| 1609 | nsymbols = (nbits + nsymbits - 1) / nsymbits; | ||
| 1610 | |||
| 1611 | if (!half_gi) | ||
| 1612 | duration = SYMBOL_TIME(nsymbols); | ||
| 1613 | else | ||
| 1614 | duration = SYMBOL_TIME_HALFGI(nsymbols); | ||
| 1615 | |||
| 1616 | /* addup duration for legacy/ht training and signal fields */ | ||
| 1617 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); | ||
| 1618 | |||
| 1619 | return duration; | ||
| 1620 | } | ||
| 1621 | |||
| 1622 | u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) | 1755 | u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) |
| 1623 | { | 1756 | { |
| 1624 | struct ath_hw *ah = sc->sc_ah; | 1757 | struct ath_hw *ah = sc->sc_ah; |
| @@ -1631,118 +1764,6 @@ u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) | |||
| 1631 | return chainmask; | 1764 | return chainmask; |
| 1632 | } | 1765 | } |
| 1633 | 1766 | ||
| 1634 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len) | ||
| 1635 | { | ||
| 1636 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | ||
| 1637 | struct ath9k_11n_rate_series series[4]; | ||
| 1638 | struct sk_buff *skb; | ||
| 1639 | struct ieee80211_tx_info *tx_info; | ||
| 1640 | struct ieee80211_tx_rate *rates; | ||
| 1641 | const struct ieee80211_rate *rate; | ||
| 1642 | struct ieee80211_hdr *hdr; | ||
| 1643 | int i, flags = 0; | ||
| 1644 | u8 rix = 0, ctsrate = 0; | ||
| 1645 | bool is_pspoll; | ||
| 1646 | |||
| 1647 | memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); | ||
| 1648 | |||
| 1649 | skb = bf->bf_mpdu; | ||
| 1650 | tx_info = IEEE80211_SKB_CB(skb); | ||
| 1651 | rates = tx_info->control.rates; | ||
| 1652 | hdr = (struct ieee80211_hdr *)skb->data; | ||
| 1653 | is_pspoll = ieee80211_is_pspoll(hdr->frame_control); | ||
| 1654 | |||
| 1655 | /* | ||
| 1656 | * We check if Short Preamble is needed for the CTS rate by | ||
| 1657 | * checking the BSS's global flag. | ||
| 1658 | * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. | ||
| 1659 | */ | ||
| 1660 | rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info); | ||
| 1661 | ctsrate = rate->hw_value; | ||
| 1662 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) | ||
| 1663 | ctsrate |= rate->hw_value_short; | ||
| 1664 | |||
| 1665 | for (i = 0; i < 4; i++) { | ||
| 1666 | bool is_40, is_sgi, is_sp; | ||
| 1667 | int phy; | ||
| 1668 | |||
| 1669 | if (!rates[i].count || (rates[i].idx < 0)) | ||
| 1670 | continue; | ||
| 1671 | |||
| 1672 | rix = rates[i].idx; | ||
| 1673 | series[i].Tries = rates[i].count; | ||
| 1674 | |||
| 1675 | if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) { | ||
| 1676 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | ||
| 1677 | flags |= ATH9K_TXDESC_RTSENA; | ||
| 1678 | } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { | ||
| 1679 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | ||
| 1680 | flags |= ATH9K_TXDESC_CTSENA; | ||
| 1681 | } | ||
| 1682 | |||
| 1683 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | ||
| 1684 | series[i].RateFlags |= ATH9K_RATESERIES_2040; | ||
| 1685 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) | ||
| 1686 | series[i].RateFlags |= ATH9K_RATESERIES_HALFGI; | ||
| 1687 | |||
| 1688 | is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); | ||
| 1689 | is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); | ||
| 1690 | is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); | ||
| 1691 | |||
| 1692 | if (rates[i].flags & IEEE80211_TX_RC_MCS) { | ||
| 1693 | /* MCS rates */ | ||
| 1694 | series[i].Rate = rix | 0x80; | ||
| 1695 | series[i].ChSel = ath_txchainmask_reduction(sc, | ||
| 1696 | common->tx_chainmask, series[i].Rate); | ||
| 1697 | series[i].PktDuration = ath_pkt_duration(sc, rix, len, | ||
| 1698 | is_40, is_sgi, is_sp); | ||
| 1699 | if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) | ||
| 1700 | series[i].RateFlags |= ATH9K_RATESERIES_STBC; | ||
| 1701 | continue; | ||
| 1702 | } | ||
| 1703 | |||
| 1704 | /* legacy rates */ | ||
| 1705 | if ((tx_info->band == IEEE80211_BAND_2GHZ) && | ||
| 1706 | !(rate->flags & IEEE80211_RATE_ERP_G)) | ||
| 1707 | phy = WLAN_RC_PHY_CCK; | ||
| 1708 | else | ||
| 1709 | phy = WLAN_RC_PHY_OFDM; | ||
| 1710 | |||
| 1711 | rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx]; | ||
| 1712 | series[i].Rate = rate->hw_value; | ||
| 1713 | if (rate->hw_value_short) { | ||
| 1714 | if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | ||
| 1715 | series[i].Rate |= rate->hw_value_short; | ||
| 1716 | } else { | ||
| 1717 | is_sp = false; | ||
| 1718 | } | ||
| 1719 | |||
| 1720 | if (bf->bf_state.bfs_paprd) | ||
| 1721 | series[i].ChSel = common->tx_chainmask; | ||
| 1722 | else | ||
| 1723 | series[i].ChSel = ath_txchainmask_reduction(sc, | ||
| 1724 | common->tx_chainmask, series[i].Rate); | ||
| 1725 | |||
| 1726 | series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, | ||
| 1727 | phy, rate->bitrate * 100, len, rix, is_sp); | ||
| 1728 | } | ||
| 1729 | |||
| 1730 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ | ||
| 1731 | if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) | ||
| 1732 | flags &= ~ATH9K_TXDESC_RTSENA; | ||
| 1733 | |||
| 1734 | /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ | ||
| 1735 | if (flags & ATH9K_TXDESC_RTSENA) | ||
| 1736 | flags &= ~ATH9K_TXDESC_CTSENA; | ||
| 1737 | |||
| 1738 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ | ||
| 1739 | ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc, | ||
| 1740 | bf->bf_lastbf->bf_desc, | ||
| 1741 | !is_pspoll, ctsrate, | ||
| 1742 | 0, series, 4, flags); | ||
| 1743 | |||
| 1744 | } | ||
| 1745 | |||
| 1746 | /* | 1767 | /* |
| 1747 | * Assign a descriptor (and sequence number if necessary, | 1768 | * Assign a descriptor (and sequence number if necessary, |
| 1748 | * and map buffer for DMA. Frees skb on error | 1769 | * and map buffer for DMA. Frees skb on error |
| @@ -1752,13 +1773,10 @@ static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, | |||
| 1752 | struct ath_atx_tid *tid, | 1773 | struct ath_atx_tid *tid, |
| 1753 | struct sk_buff *skb) | 1774 | struct sk_buff *skb) |
| 1754 | { | 1775 | { |
| 1755 | struct ath_hw *ah = sc->sc_ah; | ||
| 1756 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | 1776 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
| 1757 | struct ath_frame_info *fi = get_frame_info(skb); | 1777 | struct ath_frame_info *fi = get_frame_info(skb); |
| 1758 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | 1778 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
| 1759 | struct ath_buf *bf; | 1779 | struct ath_buf *bf; |
| 1760 | struct ath_desc *ds; | ||
| 1761 | int frm_type; | ||
| 1762 | u16 seqno; | 1780 | u16 seqno; |
| 1763 | 1781 | ||
| 1764 | bf = ath_tx_get_buffer(sc); | 1782 | bf = ath_tx_get_buffer(sc); |
| @@ -1776,7 +1794,6 @@ static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, | |||
| 1776 | bf->bf_state.seqno = seqno; | 1794 | bf->bf_state.seqno = seqno; |
| 1777 | } | 1795 | } |
| 1778 | 1796 | ||
| 1779 | bf->bf_flags = setup_tx_flags(skb); | ||
| 1780 | bf->bf_mpdu = skb; | 1797 | bf->bf_mpdu = skb; |
| 1781 | 1798 | ||
| 1782 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, | 1799 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, |
| @@ -1790,22 +1807,6 @@ static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, | |||
| 1790 | goto error; | 1807 | goto error; |
| 1791 | } | 1808 | } |
| 1792 | 1809 | ||
| 1793 | frm_type = get_hw_packet_type(skb); | ||
| 1794 | |||
| 1795 | ds = bf->bf_desc; | ||
| 1796 | ath9k_hw_set_desc_link(ah, ds, 0); | ||
| 1797 | |||
| 1798 | ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER, | ||
| 1799 | fi->keyix, fi->keytype, bf->bf_flags); | ||
| 1800 | |||
| 1801 | ath9k_hw_filltxdesc(ah, ds, | ||
| 1802 | skb->len, /* segment length */ | ||
| 1803 | true, /* first segment */ | ||
| 1804 | true, /* last segment */ | ||
| 1805 | ds, /* first descriptor */ | ||
| 1806 | bf->bf_buf_addr, | ||
| 1807 | txq->axq_qnum); | ||
| 1808 | |||
| 1809 | fi->bf = bf; | 1810 | fi->bf = bf; |
| 1810 | 1811 | ||
| 1811 | return bf; | 1812 | return bf; |
| @@ -1848,16 +1849,9 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb, | |||
| 1848 | 1849 | ||
| 1849 | bf->bf_state.bfs_paprd = txctl->paprd; | 1850 | bf->bf_state.bfs_paprd = txctl->paprd; |
| 1850 | 1851 | ||
| 1851 | if (bf->bf_state.bfs_paprd) | ||
| 1852 | ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc, | ||
| 1853 | bf->bf_state.bfs_paprd); | ||
| 1854 | |||
| 1855 | if (txctl->paprd) | 1852 | if (txctl->paprd) |
| 1856 | bf->bf_state.bfs_paprd_timestamp = jiffies; | 1853 | bf->bf_state.bfs_paprd_timestamp = jiffies; |
| 1857 | 1854 | ||
| 1858 | if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) | ||
| 1859 | ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true); | ||
| 1860 | |||
| 1861 | ath_tx_send_normal(sc, txctl->txq, tid, skb); | 1855 | ath_tx_send_normal(sc, txctl->txq, tid, skb); |
| 1862 | } | 1856 | } |
| 1863 | 1857 | ||
| @@ -1898,15 +1892,17 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, | |||
| 1898 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); | 1892 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); |
| 1899 | } | 1893 | } |
| 1900 | 1894 | ||
| 1901 | /* Add the padding after the header if this is not already done */ | 1895 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) { |
| 1902 | padpos = ath9k_cmn_padpos(hdr->frame_control); | 1896 | /* Add the padding after the header if this is not already done */ |
| 1903 | padsize = padpos & 3; | 1897 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
| 1904 | if (padsize && skb->len > padpos) { | 1898 | padsize = padpos & 3; |
| 1905 | if (skb_headroom(skb) < padsize) | 1899 | if (padsize && skb->len > padpos) { |
| 1906 | return -ENOMEM; | 1900 | if (skb_headroom(skb) < padsize) |
| 1901 | return -ENOMEM; | ||
| 1907 | 1902 | ||
| 1908 | skb_push(skb, padsize); | 1903 | skb_push(skb, padsize); |
| 1909 | memmove(skb->data, skb->data + padsize, padpos); | 1904 | memmove(skb->data, skb->data + padsize, padpos); |
| 1905 | } | ||
| 1910 | } | 1906 | } |
| 1911 | 1907 | ||
| 1912 | if ((vif && vif->type != NL80211_IFTYPE_AP && | 1908 | if ((vif && vif->type != NL80211_IFTYPE_AP && |
| @@ -1952,20 +1948,21 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, | |||
| 1952 | if (tx_flags & ATH_TX_BAR) | 1948 | if (tx_flags & ATH_TX_BAR) |
| 1953 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; | 1949 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; |
| 1954 | 1950 | ||
| 1955 | if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) { | 1951 | if (!(tx_flags & ATH_TX_ERROR)) |
| 1956 | /* Frame was ACKed */ | 1952 | /* Frame was ACKed */ |
| 1957 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | 1953 | tx_info->flags |= IEEE80211_TX_STAT_ACK; |
| 1958 | } | ||
| 1959 | 1954 | ||
| 1960 | padpos = ath9k_cmn_padpos(hdr->frame_control); | 1955 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) { |
| 1961 | padsize = padpos & 3; | 1956 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
| 1962 | if (padsize && skb->len>padpos+padsize) { | 1957 | padsize = padpos & 3; |
| 1963 | /* | 1958 | if (padsize && skb->len>padpos+padsize) { |
| 1964 | * Remove MAC header padding before giving the frame back to | 1959 | /* |
| 1965 | * mac80211. | 1960 | * Remove MAC header padding before giving the frame back to |
| 1966 | */ | 1961 | * mac80211. |
| 1967 | memmove(skb->data + padsize, skb->data, padpos); | 1962 | */ |
| 1968 | skb_pull(skb, padsize); | 1963 | memmove(skb->data + padsize, skb->data, padpos); |
| 1964 | skb_pull(skb, padsize); | ||
| 1965 | } | ||
| 1969 | } | 1966 | } |
| 1970 | 1967 | ||
| 1971 | if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) { | 1968 | if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) { |
| @@ -1999,18 +1996,18 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, | |||
| 1999 | struct ath_tx_status *ts, int txok, int sendbar) | 1996 | struct ath_tx_status *ts, int txok, int sendbar) |
| 2000 | { | 1997 | { |
| 2001 | struct sk_buff *skb = bf->bf_mpdu; | 1998 | struct sk_buff *skb = bf->bf_mpdu; |
| 1999 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | ||
| 2002 | unsigned long flags; | 2000 | unsigned long flags; |
| 2003 | int tx_flags = 0; | 2001 | int tx_flags = 0; |
| 2004 | 2002 | ||
| 2005 | if (sendbar) | 2003 | if (sendbar) |
| 2006 | tx_flags = ATH_TX_BAR; | 2004 | tx_flags = ATH_TX_BAR; |
| 2007 | 2005 | ||
| 2008 | if (!txok) { | 2006 | if (!txok) |
| 2009 | tx_flags |= ATH_TX_ERROR; | 2007 | tx_flags |= ATH_TX_ERROR; |
| 2010 | 2008 | ||
| 2011 | if (bf_isxretried(bf)) | 2009 | if (ts->ts_status & ATH9K_TXERR_FILT) |
| 2012 | tx_flags |= ATH_TX_XRETRY; | 2010 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; |
| 2013 | } | ||
| 2014 | 2011 | ||
| 2015 | dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); | 2012 | dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); |
| 2016 | bf->bf_buf_addr = 0; | 2013 | bf->bf_buf_addr = 0; |
| @@ -2023,7 +2020,7 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, | |||
| 2023 | else | 2020 | else |
| 2024 | complete(&sc->paprd_complete); | 2021 | complete(&sc->paprd_complete); |
| 2025 | } else { | 2022 | } else { |
| 2026 | ath_debug_stat_tx(sc, bf, ts, txq); | 2023 | ath_debug_stat_tx(sc, bf, ts, txq, tx_flags); |
| 2027 | ath_tx_complete(sc, skb, tx_flags, txq); | 2024 | ath_tx_complete(sc, skb, tx_flags, txq); |
| 2028 | } | 2025 | } |
| 2029 | /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't | 2026 | /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't |
| @@ -2041,7 +2038,7 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, | |||
| 2041 | 2038 | ||
| 2042 | static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, | 2039 | static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, |
| 2043 | struct ath_tx_status *ts, int nframes, int nbad, | 2040 | struct ath_tx_status *ts, int nframes, int nbad, |
| 2044 | int txok, bool update_rc) | 2041 | int txok) |
| 2045 | { | 2042 | { |
| 2046 | struct sk_buff *skb = bf->bf_mpdu; | 2043 | struct sk_buff *skb = bf->bf_mpdu; |
| 2047 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | 2044 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
| @@ -2056,9 +2053,7 @@ static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, | |||
| 2056 | tx_rateindex = ts->ts_rateindex; | 2053 | tx_rateindex = ts->ts_rateindex; |
| 2057 | WARN_ON(tx_rateindex >= hw->max_rates); | 2054 | WARN_ON(tx_rateindex >= hw->max_rates); |
| 2058 | 2055 | ||
| 2059 | if (ts->ts_status & ATH9K_TXERR_FILT) | 2056 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { |
| 2060 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | ||
| 2061 | if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) { | ||
| 2062 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU; | 2057 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU; |
| 2063 | 2058 | ||
| 2064 | BUG_ON(nbad > nframes); | 2059 | BUG_ON(nbad > nframes); |
| @@ -2068,7 +2063,7 @@ static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, | |||
| 2068 | } | 2063 | } |
| 2069 | 2064 | ||
| 2070 | if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && | 2065 | if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && |
| 2071 | (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) { | 2066 | (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) { |
| 2072 | /* | 2067 | /* |
| 2073 | * If an underrun error is seen assume it as an excessive | 2068 | * If an underrun error is seen assume it as an excessive |
| 2074 | * retry only if max frame trigger level has been reached | 2069 | * retry only if max frame trigger level has been reached |
| @@ -2081,9 +2076,9 @@ static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, | |||
| 2081 | * successfully by eventually preferring slower rates. | 2076 | * successfully by eventually preferring slower rates. |
| 2082 | * This itself should also alleviate congestion on the bus. | 2077 | * This itself should also alleviate congestion on the bus. |
| 2083 | */ | 2078 | */ |
| 2084 | if (ieee80211_is_data(hdr->frame_control) && | 2079 | if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | |
| 2085 | (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | | 2080 | ATH9K_TX_DELIM_UNDERRUN)) && |
| 2086 | ATH9K_TX_DELIM_UNDERRUN)) && | 2081 | ieee80211_is_data(hdr->frame_control) && |
| 2087 | ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level) | 2082 | ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level) |
| 2088 | tx_info->status.rates[tx_rateindex].count = | 2083 | tx_info->status.rates[tx_rateindex].count = |
| 2089 | hw->max_rate_tries; | 2084 | hw->max_rate_tries; |
| @@ -2114,13 +2109,7 @@ static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq, | |||
| 2114 | spin_unlock_bh(&txq->axq_lock); | 2109 | spin_unlock_bh(&txq->axq_lock); |
| 2115 | 2110 | ||
| 2116 | if (!bf_isampdu(bf)) { | 2111 | if (!bf_isampdu(bf)) { |
| 2117 | /* | 2112 | ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok); |
| 2118 | * This frame is sent out as a single frame. | ||
| 2119 | * Use hardware retry status for this frame. | ||
| 2120 | */ | ||
| 2121 | if (ts->ts_status & ATH9K_TXERR_XRETRY) | ||
| 2122 | bf->bf_state.bf_type |= BUF_XRETRY; | ||
| 2123 | ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok, true); | ||
| 2124 | ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0); | 2113 | ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0); |
| 2125 | } else | 2114 | } else |
| 2126 | ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true); | 2115 | ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true); |
| @@ -2147,6 +2136,9 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) | |||
| 2147 | 2136 | ||
| 2148 | spin_lock_bh(&txq->axq_lock); | 2137 | spin_lock_bh(&txq->axq_lock); |
| 2149 | for (;;) { | 2138 | for (;;) { |
| 2139 | if (work_pending(&sc->hw_reset_work)) | ||
| 2140 | break; | ||
| 2141 | |||
| 2150 | if (list_empty(&txq->axq_q)) { | 2142 | if (list_empty(&txq->axq_q)) { |
| 2151 | txq->axq_link = NULL; | 2143 | txq->axq_link = NULL; |
| 2152 | if (sc->sc_flags & SC_OP_TXAGGR) | 2144 | if (sc->sc_flags & SC_OP_TXAGGR) |
| @@ -2234,9 +2226,7 @@ static void ath_tx_complete_poll_work(struct work_struct *work) | |||
| 2234 | if (needreset) { | 2226 | if (needreset) { |
| 2235 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET, | 2227 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET, |
| 2236 | "tx hung, resetting the chip\n"); | 2228 | "tx hung, resetting the chip\n"); |
| 2237 | spin_lock_bh(&sc->sc_pcu_lock); | 2229 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
| 2238 | ath_reset(sc, true); | ||
| 2239 | spin_unlock_bh(&sc->sc_pcu_lock); | ||
| 2240 | } | 2230 | } |
| 2241 | 2231 | ||
| 2242 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, | 2232 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, |
| @@ -2269,6 +2259,9 @@ void ath_tx_edma_tasklet(struct ath_softc *sc) | |||
| 2269 | int status; | 2259 | int status; |
| 2270 | 2260 | ||
| 2271 | for (;;) { | 2261 | for (;;) { |
| 2262 | if (work_pending(&sc->hw_reset_work)) | ||
| 2263 | break; | ||
| 2264 | |||
| 2272 | status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); | 2265 | status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); |
| 2273 | if (status == -EINPROGRESS) | 2266 | if (status == -EINPROGRESS) |
| 2274 | break; | 2267 | break; |
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h index 8ff706289b5d..f8615cdf1075 100644 --- a/drivers/net/wireless/b43/b43.h +++ b/drivers/net/wireless/b43/b43.h | |||
| @@ -110,6 +110,8 @@ | |||
| 110 | #define B43_MMIO_TSF_CFP_START_LOW 0x604 | 110 | #define B43_MMIO_TSF_CFP_START_LOW 0x604 |
| 111 | #define B43_MMIO_TSF_CFP_START_HIGH 0x606 | 111 | #define B43_MMIO_TSF_CFP_START_HIGH 0x606 |
| 112 | #define B43_MMIO_TSF_CFP_PRETBTT 0x612 | 112 | #define B43_MMIO_TSF_CFP_PRETBTT 0x612 |
| 113 | #define B43_MMIO_TSF_CLK_FRAC_LOW 0x62E | ||
| 114 | #define B43_MMIO_TSF_CLK_FRAC_HIGH 0x630 | ||
| 113 | #define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */ | 115 | #define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */ |
| 114 | #define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */ | 116 | #define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */ |
| 115 | #define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */ | 117 | #define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */ |
diff --git a/drivers/net/wireless/b43/bus.c b/drivers/net/wireless/b43/bus.c index 05f6c7bff6ab..424692df239d 100644 --- a/drivers/net/wireless/b43/bus.c +++ b/drivers/net/wireless/b43/bus.c | |||
| @@ -3,6 +3,8 @@ | |||
| 3 | Broadcom B43 wireless driver | 3 | Broadcom B43 wireless driver |
| 4 | Bus abstraction layer | 4 | Bus abstraction layer |
| 5 | 5 | ||
| 6 | Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com> | ||
| 7 | |||
| 6 | This program is free software; you can redistribute it and/or modify | 8 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by | 9 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 2 of the License, or | 10 | the Free Software Foundation; either version 2 of the License, or |
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c index 172294170df8..24077023d484 100644 --- a/drivers/net/wireless/b43/main.c +++ b/drivers/net/wireless/b43/main.c | |||
| @@ -7,6 +7,7 @@ | |||
| 7 | Copyright (c) 2005-2009 Michael Buesch <m@bues.ch> | 7 | Copyright (c) 2005-2009 Michael Buesch <m@bues.ch> |
| 8 | Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> | 8 | Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> |
| 9 | Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> | 9 | Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> |
| 10 | Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com> | ||
| 10 | 11 | ||
| 11 | SDIO support | 12 | SDIO support |
| 12 | Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es> | 13 | Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es> |
| @@ -64,6 +65,7 @@ MODULE_AUTHOR("Martin Langer"); | |||
| 64 | MODULE_AUTHOR("Stefano Brivio"); | 65 | MODULE_AUTHOR("Stefano Brivio"); |
| 65 | MODULE_AUTHOR("Michael Buesch"); | 66 | MODULE_AUTHOR("Michael Buesch"); |
| 66 | MODULE_AUTHOR("Gábor Stefanik"); | 67 | MODULE_AUTHOR("Gábor Stefanik"); |
| 68 | MODULE_AUTHOR("Rafał Miłecki"); | ||
| 67 | MODULE_LICENSE("GPL"); | 69 | MODULE_LICENSE("GPL"); |
| 68 | 70 | ||
| 69 | MODULE_FIRMWARE("b43/ucode11.fw"); | 71 | MODULE_FIRMWARE("b43/ucode11.fw"); |
| @@ -2953,6 +2955,7 @@ static void b43_rate_memory_init(struct b43_wldev *dev) | |||
| 2953 | case B43_PHYTYPE_N: | 2955 | case B43_PHYTYPE_N: |
| 2954 | case B43_PHYTYPE_LP: | 2956 | case B43_PHYTYPE_LP: |
| 2955 | case B43_PHYTYPE_HT: | 2957 | case B43_PHYTYPE_HT: |
| 2958 | case B43_PHYTYPE_LCN: | ||
| 2956 | b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); | 2959 | b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); |
| 2957 | b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); | 2960 | b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); |
| 2958 | b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); | 2961 | b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); |
diff --git a/drivers/net/wireless/b43/phy_ht.c b/drivers/net/wireless/b43/phy_ht.c index 4d6345e8ee6b..7416c5e9154d 100644 --- a/drivers/net/wireless/b43/phy_ht.c +++ b/drivers/net/wireless/b43/phy_ht.c | |||
| @@ -3,6 +3,8 @@ | |||
| 3 | Broadcom B43 wireless driver | 3 | Broadcom B43 wireless driver |
| 4 | IEEE 802.11n HT-PHY support | 4 | IEEE 802.11n HT-PHY support |
| 5 | 5 | ||
| 6 | Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com> | ||
| 7 | |||
| 6 | This program is free software; you can redistribute it and/or modify | 8 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by | 9 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 2 of the License, or | 10 | the Free Software Foundation; either version 2 of the License, or |
diff --git a/drivers/net/wireless/b43/phy_lcn.c b/drivers/net/wireless/b43/phy_lcn.c index 4b2cd6d24ce9..d1dfeec7bc28 100644 --- a/drivers/net/wireless/b43/phy_lcn.c +++ b/drivers/net/wireless/b43/phy_lcn.c | |||
| @@ -3,6 +3,8 @@ | |||
| 3 | Broadcom B43 wireless driver | 3 | Broadcom B43 wireless driver |
| 4 | IEEE 802.11n LCN-PHY support | 4 | IEEE 802.11n LCN-PHY support |
| 5 | 5 | ||
| 6 | Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com> | ||
| 7 | |||
| 6 | This program is free software; you can redistribute it and/or modify | 8 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by | 9 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 2 of the License, or | 10 | the Free Software Foundation; either version 2 of the License, or |
| @@ -31,24 +33,78 @@ | |||
| 31 | * Radio 2064. | 33 | * Radio 2064. |
| 32 | **************************************************/ | 34 | **************************************************/ |
| 33 | 35 | ||
| 36 | /* wlc_lcnphy_radio_2064_channel_tune_4313 */ | ||
| 37 | static void b43_radio_2064_channel_setup(struct b43_wldev *dev) | ||
| 38 | { | ||
| 39 | u16 save[2]; | ||
| 40 | |||
| 41 | b43_radio_set(dev, 0x09d, 0x4); | ||
| 42 | b43_radio_write(dev, 0x09e, 0xf); | ||
| 43 | |||
| 44 | /* Channel specific values in theory, in practice always the same */ | ||
| 45 | b43_radio_write(dev, 0x02a, 0xb); | ||
| 46 | b43_radio_maskset(dev, 0x030, ~0x3, 0xa); | ||
| 47 | b43_radio_maskset(dev, 0x091, ~0x3, 0); | ||
| 48 | b43_radio_maskset(dev, 0x038, ~0xf, 0x7); | ||
| 49 | b43_radio_maskset(dev, 0x030, ~0xc, 0x8); | ||
| 50 | b43_radio_maskset(dev, 0x05e, ~0xf, 0x8); | ||
| 51 | b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80); | ||
| 52 | b43_radio_write(dev, 0x06c, 0x80); | ||
| 53 | |||
| 54 | save[0] = b43_radio_read(dev, 0x044); | ||
| 55 | save[1] = b43_radio_read(dev, 0x12b); | ||
| 56 | |||
| 57 | b43_radio_set(dev, 0x044, 0x7); | ||
| 58 | b43_radio_set(dev, 0x12b, 0xe); | ||
| 59 | |||
| 60 | /* TODO */ | ||
| 61 | |||
| 62 | b43_radio_write(dev, 0x040, 0xfb); | ||
| 63 | |||
| 64 | b43_radio_write(dev, 0x041, 0x9a); | ||
| 65 | b43_radio_write(dev, 0x042, 0xa3); | ||
| 66 | b43_radio_write(dev, 0x043, 0x0c); | ||
| 67 | |||
| 68 | /* TODO */ | ||
| 69 | |||
| 70 | b43_radio_set(dev, 0x044, 0x0c); | ||
| 71 | udelay(1); | ||
| 72 | |||
| 73 | b43_radio_write(dev, 0x044, save[0]); | ||
| 74 | b43_radio_write(dev, 0x12b, save[1]); | ||
| 75 | |||
| 76 | if (dev->phy.rev == 1) { | ||
| 77 | /* brcmsmac uses outdated 0x3 for 0x038 */ | ||
| 78 | b43_radio_write(dev, 0x038, 0x0); | ||
| 79 | b43_radio_write(dev, 0x091, 0x7); | ||
| 80 | } | ||
| 81 | } | ||
| 82 | |||
| 83 | /* wlc_radio_2064_init */ | ||
| 34 | static void b43_radio_2064_init(struct b43_wldev *dev) | 84 | static void b43_radio_2064_init(struct b43_wldev *dev) |
| 35 | { | 85 | { |
| 36 | b43_radio_write(dev, 0x09c, 0x0020); | 86 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { |
| 37 | b43_radio_write(dev, 0x105, 0x0008); | 87 | b43_radio_write(dev, 0x09c, 0x0020); |
| 88 | b43_radio_write(dev, 0x105, 0x0008); | ||
| 89 | } else { | ||
| 90 | /* TODO */ | ||
| 91 | } | ||
| 38 | b43_radio_write(dev, 0x032, 0x0062); | 92 | b43_radio_write(dev, 0x032, 0x0062); |
| 39 | b43_radio_write(dev, 0x033, 0x0019); | 93 | b43_radio_write(dev, 0x033, 0x0019); |
| 40 | b43_radio_write(dev, 0x090, 0x0010); | 94 | b43_radio_write(dev, 0x090, 0x0010); |
| 41 | b43_radio_write(dev, 0x010, 0x0000); | 95 | b43_radio_write(dev, 0x010, 0x0000); |
| 42 | b43_radio_write(dev, 0x060, 0x007f); | 96 | if (dev->phy.rev == 1) { |
| 43 | b43_radio_write(dev, 0x061, 0x0072); | 97 | b43_radio_write(dev, 0x060, 0x007f); |
| 44 | b43_radio_write(dev, 0x062, 0x007f); | 98 | b43_radio_write(dev, 0x061, 0x0072); |
| 99 | b43_radio_write(dev, 0x062, 0x007f); | ||
| 100 | } | ||
| 45 | b43_radio_write(dev, 0x01d, 0x0002); | 101 | b43_radio_write(dev, 0x01d, 0x0002); |
| 46 | b43_radio_write(dev, 0x01e, 0x0006); | 102 | b43_radio_write(dev, 0x01e, 0x0006); |
| 47 | 103 | ||
| 48 | b43_phy_write(dev, 0x4ea, 0x4688); | 104 | b43_phy_write(dev, 0x4ea, 0x4688); |
| 49 | b43_phy_maskset(dev, 0x4eb, ~0x7, 0x2); | 105 | b43_phy_maskset(dev, 0x4eb, ~0x7, 0x2); |
| 50 | b43_phy_mask(dev, 0x4eb, ~0x01c0); | 106 | b43_phy_mask(dev, 0x4eb, ~0x01c0); |
| 51 | b43_phy_maskset(dev, 0x4eb, 0xff00, 0x19); | 107 | b43_phy_maskset(dev, 0x46a, 0xff00, 0x19); |
| 52 | 108 | ||
| 53 | b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x55), 0); | 109 | b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x55), 0); |
| 54 | 110 | ||
| @@ -80,6 +136,7 @@ static void b43_radio_2064_init(struct b43_wldev *dev) | |||
| 80 | * Various PHY ops | 136 | * Various PHY ops |
| 81 | **************************************************/ | 137 | **************************************************/ |
| 82 | 138 | ||
| 139 | /* wlc_lcnphy_toggle_afe_pwdn */ | ||
| 83 | static void b43_phy_lcn_afe_set_unset(struct b43_wldev *dev) | 140 | static void b43_phy_lcn_afe_set_unset(struct b43_wldev *dev) |
| 84 | { | 141 | { |
| 85 | u16 afe_ctl2 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL2); | 142 | u16 afe_ctl2 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL2); |
| @@ -95,22 +152,17 @@ static void b43_phy_lcn_afe_set_unset(struct b43_wldev *dev) | |||
| 95 | b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1); | 152 | b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1); |
| 96 | } | 153 | } |
| 97 | 154 | ||
| 98 | static void b43_phy_lcn_clean_0x18_table(struct b43_wldev *dev) | 155 | /* wlc_lcnphy_clear_tx_power_offsets */ |
| 99 | { | 156 | static void b43_phy_lcn_clear_tx_power_offsets(struct b43_wldev *dev) |
| 100 | u8 i; | ||
| 101 | |||
| 102 | for (i = 0; i < 0x80; i++) | ||
| 103 | b43_lcntab_write(dev, B43_LCNTAB32(0x18, i), 0x80000); | ||
| 104 | } | ||
| 105 | |||
| 106 | static void b43_phy_lcn_clear_0x07_table(struct b43_wldev *dev) | ||
| 107 | { | 157 | { |
| 108 | u8 i; | 158 | u8 i; |
| 109 | 159 | ||
| 110 | b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x340); | 160 | if (1) { /* FIXME */ |
| 111 | for (i = 0; i < 30; i++) { | 161 | b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x340); |
| 112 | b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0); | 162 | for (i = 0; i < 30; i++) { |
| 113 | b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0); | 163 | b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0); |
| 164 | b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0); | ||
| 165 | } | ||
| 114 | } | 166 | } |
| 115 | 167 | ||
| 116 | b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x80); | 168 | b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x80); |
| @@ -120,6 +172,134 @@ static void b43_phy_lcn_clear_0x07_table(struct b43_wldev *dev) | |||
| 120 | } | 172 | } |
| 121 | } | 173 | } |
| 122 | 174 | ||
| 175 | /* wlc_lcnphy_rev0_baseband_init */ | ||
| 176 | static void b43_phy_lcn_rev0_baseband_init(struct b43_wldev *dev) | ||
| 177 | { | ||
| 178 | b43_radio_write(dev, 0x11c, 0); | ||
| 179 | |||
| 180 | b43_phy_write(dev, 0x43b, 0); | ||
| 181 | b43_phy_write(dev, 0x43c, 0); | ||
| 182 | b43_phy_write(dev, 0x44c, 0); | ||
| 183 | b43_phy_write(dev, 0x4e6, 0); | ||
| 184 | b43_phy_write(dev, 0x4f9, 0); | ||
| 185 | b43_phy_write(dev, 0x4b0, 0); | ||
| 186 | b43_phy_write(dev, 0x938, 0); | ||
| 187 | b43_phy_write(dev, 0x4b0, 0); | ||
| 188 | b43_phy_write(dev, 0x44e, 0); | ||
| 189 | |||
| 190 | b43_phy_set(dev, 0x567, 0x03); | ||
| 191 | |||
| 192 | b43_phy_set(dev, 0x44a, 0x44); | ||
| 193 | b43_phy_write(dev, 0x44a, 0x80); | ||
| 194 | |||
| 195 | if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM)) | ||
| 196 | ; /* TODO */ | ||
| 197 | b43_phy_maskset(dev, 0x634, ~0xff, 0xc); | ||
| 198 | if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM) { | ||
| 199 | b43_phy_maskset(dev, 0x634, ~0xff, 0xa); | ||
| 200 | b43_phy_write(dev, 0x910, 0x1); | ||
| 201 | } | ||
| 202 | |||
| 203 | b43_phy_write(dev, 0x910, 0x1); | ||
| 204 | |||
| 205 | b43_phy_maskset(dev, 0x448, ~0x300, 0x100); | ||
| 206 | b43_phy_maskset(dev, 0x608, ~0xff, 0x17); | ||
| 207 | b43_phy_maskset(dev, 0x604, ~0x7ff, 0x3ea); | ||
| 208 | } | ||
| 209 | |||
| 210 | /* wlc_lcnphy_bu_tweaks */ | ||
| 211 | static void b43_phy_lcn_bu_tweaks(struct b43_wldev *dev) | ||
| 212 | { | ||
| 213 | b43_phy_set(dev, 0x805, 0x1); | ||
| 214 | |||
| 215 | b43_phy_maskset(dev, 0x42f, ~0x7, 0x3); | ||
| 216 | b43_phy_maskset(dev, 0x030, ~0x7, 0x3); | ||
| 217 | |||
| 218 | b43_phy_write(dev, 0x414, 0x1e10); | ||
| 219 | b43_phy_write(dev, 0x415, 0x0640); | ||
| 220 | |||
| 221 | b43_phy_maskset(dev, 0x4df, (u16) ~0xff00, 0xf700); | ||
| 222 | |||
| 223 | b43_phy_set(dev, 0x44a, 0x44); | ||
| 224 | b43_phy_write(dev, 0x44a, 0x80); | ||
| 225 | |||
| 226 | b43_phy_maskset(dev, 0x434, ~0xff, 0xfd); | ||
| 227 | b43_phy_maskset(dev, 0x420, ~0xff, 0x10); | ||
| 228 | |||
| 229 | if (dev->dev->bus_sprom->board_rev >= 0x1204) | ||
| 230 | b43_radio_set(dev, 0x09b, 0xf0); | ||
| 231 | |||
| 232 | b43_phy_write(dev, 0x7d6, 0x0902); | ||
| 233 | |||
| 234 | /* TODO: more ops */ | ||
| 235 | |||
| 236 | if (dev->phy.rev == 1) { | ||
| 237 | /* TODO: more ops */ | ||
| 238 | |||
| 239 | b43_phy_lcn_clear_tx_power_offsets(dev); | ||
| 240 | } | ||
| 241 | } | ||
| 242 | |||
| 243 | /* wlc_lcnphy_vbat_temp_sense_setup */ | ||
| 244 | static void b43_phy_lcn_sense_setup(struct b43_wldev *dev) | ||
| 245 | { | ||
| 246 | u8 i; | ||
| 247 | |||
| 248 | u16 save_radio_regs[6][2] = { | ||
| 249 | { 0x007, 0 }, { 0x0ff, 0 }, { 0x11f, 0 }, { 0x005, 0 }, | ||
| 250 | { 0x025, 0 }, { 0x112, 0 }, | ||
| 251 | }; | ||
| 252 | u16 save_phy_regs[14][2] = { | ||
| 253 | { 0x503, 0 }, { 0x4a4, 0 }, { 0x4d0, 0 }, { 0x4d9, 0 }, | ||
| 254 | { 0x4da, 0 }, { 0x4a6, 0 }, { 0x938, 0 }, { 0x939, 0 }, | ||
| 255 | { 0x4d8, 0 }, { 0x4d0, 0 }, { 0x4d7, 0 }, { 0x4a5, 0 }, | ||
| 256 | { 0x40d, 0 }, { 0x4a2, 0 }, | ||
| 257 | }; | ||
| 258 | u16 save_radio_4a4; | ||
| 259 | |||
| 260 | for (i = 0; i < 6; i++) | ||
| 261 | save_radio_regs[i][1] = b43_radio_read(dev, | ||
| 262 | save_radio_regs[i][0]); | ||
| 263 | for (i = 0; i < 14; i++) | ||
| 264 | save_phy_regs[i][1] = b43_phy_read(dev, save_phy_regs[i][0]); | ||
| 265 | save_radio_4a4 = b43_radio_read(dev, 0x4a4); | ||
| 266 | |||
| 267 | /* TODO: config sth */ | ||
| 268 | |||
| 269 | for (i = 0; i < 6; i++) | ||
| 270 | b43_radio_write(dev, save_radio_regs[i][0], | ||
| 271 | save_radio_regs[i][1]); | ||
| 272 | for (i = 0; i < 14; i++) | ||
| 273 | b43_phy_write(dev, save_phy_regs[i][0], save_phy_regs[i][1]); | ||
| 274 | b43_radio_write(dev, 0x4a4, save_radio_4a4); | ||
| 275 | } | ||
| 276 | |||
| 277 | /************************************************** | ||
| 278 | * Channel switching ops. | ||
| 279 | **************************************************/ | ||
| 280 | |||
| 281 | static int b43_phy_lcn_set_channel(struct b43_wldev *dev, | ||
| 282 | struct ieee80211_channel *channel, | ||
| 283 | enum nl80211_channel_type channel_type) | ||
| 284 | { | ||
| 285 | /* TODO: PLL and PHY ops */ | ||
| 286 | |||
| 287 | b43_phy_set(dev, 0x44a, 0x44); | ||
| 288 | b43_phy_write(dev, 0x44a, 0x80); | ||
| 289 | |||
| 290 | b43_phy_set(dev, 0x44a, 0x44); | ||
| 291 | b43_phy_write(dev, 0x44a, 0x80); | ||
| 292 | |||
| 293 | b43_radio_2064_channel_setup(dev); | ||
| 294 | mdelay(1); | ||
| 295 | |||
| 296 | b43_phy_lcn_afe_set_unset(dev); | ||
| 297 | |||
| 298 | /* TODO */ | ||
| 299 | |||
| 300 | return 0; | ||
| 301 | } | ||
| 302 | |||
| 123 | /************************************************** | 303 | /************************************************** |
| 124 | * Basic PHY ops. | 304 | * Basic PHY ops. |
| 125 | **************************************************/ | 305 | **************************************************/ |
| @@ -153,6 +333,7 @@ static void b43_phy_lcn_op_prepare_structs(struct b43_wldev *dev) | |||
| 153 | memset(phy_lcn, 0, sizeof(*phy_lcn)); | 333 | memset(phy_lcn, 0, sizeof(*phy_lcn)); |
| 154 | } | 334 | } |
| 155 | 335 | ||
| 336 | /* wlc_phy_init_lcnphy */ | ||
| 156 | static int b43_phy_lcn_op_init(struct b43_wldev *dev) | 337 | static int b43_phy_lcn_op_init(struct b43_wldev *dev) |
| 157 | { | 338 | { |
| 158 | b43_phy_set(dev, 0x44a, 0x80); | 339 | b43_phy_set(dev, 0x44a, 0x80); |
| @@ -167,18 +348,17 @@ static int b43_phy_lcn_op_init(struct b43_wldev *dev) | |||
| 167 | b43_phy_maskset(dev, 0x663, 0xFF00, 0x64); | 348 | b43_phy_maskset(dev, 0x663, 0xFF00, 0x64); |
| 168 | 349 | ||
| 169 | b43_phy_lcn_tables_init(dev); | 350 | b43_phy_lcn_tables_init(dev); |
| 170 | /* TODO: various tables ops here */ | ||
| 171 | b43_phy_lcn_clean_0x18_table(dev); | ||
| 172 | 351 | ||
| 173 | /* TODO: some ops here */ | 352 | b43_phy_lcn_rev0_baseband_init(dev); |
| 174 | 353 | b43_phy_lcn_bu_tweaks(dev); | |
| 175 | b43_phy_lcn_clear_0x07_table(dev); | ||
| 176 | 354 | ||
| 177 | if (dev->phy.radio_ver == 0x2064) | 355 | if (dev->phy.radio_ver == 0x2064) |
| 178 | b43_radio_2064_init(dev); | 356 | b43_radio_2064_init(dev); |
| 179 | else | 357 | else |
| 180 | B43_WARN_ON(1); | 358 | B43_WARN_ON(1); |
| 181 | 359 | ||
| 360 | b43_phy_lcn_sense_setup(dev); | ||
| 361 | |||
| 182 | return 0; | 362 | return 0; |
| 183 | } | 363 | } |
| 184 | 364 | ||
| @@ -215,6 +395,22 @@ static void b43_phy_lcn_op_switch_analog(struct b43_wldev *dev, bool on) | |||
| 215 | } | 395 | } |
| 216 | } | 396 | } |
| 217 | 397 | ||
| 398 | static int b43_phy_lcn_op_switch_channel(struct b43_wldev *dev, | ||
| 399 | unsigned int new_channel) | ||
| 400 | { | ||
| 401 | struct ieee80211_channel *channel = dev->wl->hw->conf.channel; | ||
| 402 | enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type; | ||
| 403 | |||
| 404 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | ||
| 405 | if ((new_channel < 1) || (new_channel > 14)) | ||
| 406 | return -EINVAL; | ||
| 407 | } else { | ||
| 408 | return -EINVAL; | ||
| 409 | } | ||
| 410 | |||
| 411 | return b43_phy_lcn_set_channel(dev, channel, channel_type); | ||
| 412 | } | ||
| 413 | |||
| 218 | static unsigned int b43_phy_lcn_op_get_default_chan(struct b43_wldev *dev) | 414 | static unsigned int b43_phy_lcn_op_get_default_chan(struct b43_wldev *dev) |
| 219 | { | 415 | { |
| 220 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | 416 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) |
| @@ -233,6 +429,46 @@ static void b43_phy_lcn_op_adjust_txpower(struct b43_wldev *dev) | |||
| 233 | } | 429 | } |
| 234 | 430 | ||
| 235 | /************************************************** | 431 | /************************************************** |
| 432 | * R/W ops. | ||
| 433 | **************************************************/ | ||
| 434 | |||
| 435 | static u16 b43_phy_lcn_op_read(struct b43_wldev *dev, u16 reg) | ||
| 436 | { | ||
| 437 | b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); | ||
| 438 | return b43_read16(dev, B43_MMIO_PHY_DATA); | ||
| 439 | } | ||
| 440 | |||
| 441 | static void b43_phy_lcn_op_write(struct b43_wldev *dev, u16 reg, u16 value) | ||
| 442 | { | ||
| 443 | b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); | ||
| 444 | b43_write16(dev, B43_MMIO_PHY_DATA, value); | ||
| 445 | } | ||
| 446 | |||
| 447 | static void b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, | ||
| 448 | u16 set) | ||
| 449 | { | ||
| 450 | b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); | ||
| 451 | b43_write16(dev, B43_MMIO_PHY_DATA, | ||
| 452 | (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set); | ||
| 453 | } | ||
| 454 | |||
| 455 | static u16 b43_phy_lcn_op_radio_read(struct b43_wldev *dev, u16 reg) | ||
| 456 | { | ||
| 457 | /* LCN-PHY needs 0x200 for read access */ | ||
| 458 | reg |= 0x200; | ||
| 459 | |||
| 460 | b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg); | ||
| 461 | return b43_read16(dev, B43_MMIO_RADIO24_DATA); | ||
| 462 | } | ||
| 463 | |||
| 464 | static void b43_phy_lcn_op_radio_write(struct b43_wldev *dev, u16 reg, | ||
| 465 | u16 value) | ||
| 466 | { | ||
| 467 | b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg); | ||
| 468 | b43_write16(dev, B43_MMIO_RADIO24_DATA, value); | ||
| 469 | } | ||
| 470 | |||
| 471 | /************************************************** | ||
| 236 | * PHY ops struct. | 472 | * PHY ops struct. |
| 237 | **************************************************/ | 473 | **************************************************/ |
| 238 | 474 | ||
| @@ -241,18 +477,14 @@ const struct b43_phy_operations b43_phyops_lcn = { | |||
| 241 | .free = b43_phy_lcn_op_free, | 477 | .free = b43_phy_lcn_op_free, |
| 242 | .prepare_structs = b43_phy_lcn_op_prepare_structs, | 478 | .prepare_structs = b43_phy_lcn_op_prepare_structs, |
| 243 | .init = b43_phy_lcn_op_init, | 479 | .init = b43_phy_lcn_op_init, |
| 244 | /* | ||
| 245 | .phy_read = b43_phy_lcn_op_read, | 480 | .phy_read = b43_phy_lcn_op_read, |
| 246 | .phy_write = b43_phy_lcn_op_write, | 481 | .phy_write = b43_phy_lcn_op_write, |
| 247 | .phy_maskset = b43_phy_lcn_op_maskset, | 482 | .phy_maskset = b43_phy_lcn_op_maskset, |
| 248 | .radio_read = b43_phy_lcn_op_radio_read, | 483 | .radio_read = b43_phy_lcn_op_radio_read, |
| 249 | .radio_write = b43_phy_lcn_op_radio_write, | 484 | .radio_write = b43_phy_lcn_op_radio_write, |
| 250 | */ | ||
| 251 | .software_rfkill = b43_phy_lcn_op_software_rfkill, | 485 | .software_rfkill = b43_phy_lcn_op_software_rfkill, |
| 252 | .switch_analog = b43_phy_lcn_op_switch_analog, | 486 | .switch_analog = b43_phy_lcn_op_switch_analog, |
| 253 | /* | ||
| 254 | .switch_channel = b43_phy_lcn_op_switch_channel, | 487 | .switch_channel = b43_phy_lcn_op_switch_channel, |
| 255 | */ | ||
| 256 | .get_default_chan = b43_phy_lcn_op_get_default_chan, | 488 | .get_default_chan = b43_phy_lcn_op_get_default_chan, |
| 257 | .recalc_txpower = b43_phy_lcn_op_recalc_txpower, | 489 | .recalc_txpower = b43_phy_lcn_op_recalc_txpower, |
| 258 | .adjust_txpower = b43_phy_lcn_op_adjust_txpower, | 490 | .adjust_txpower = b43_phy_lcn_op_adjust_txpower, |
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c index 2eadadf5f4fc..b17d9b6c33a5 100644 --- a/drivers/net/wireless/b43/phy_n.c +++ b/drivers/net/wireless/b43/phy_n.c | |||
| @@ -4,6 +4,7 @@ | |||
| 4 | IEEE 802.11n PHY support | 4 | IEEE 802.11n PHY support |
| 5 | 5 | ||
| 6 | Copyright (c) 2008 Michael Buesch <m@bues.ch> | 6 | Copyright (c) 2008 Michael Buesch <m@bues.ch> |
| 7 | Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com> | ||
| 7 | 8 | ||
| 8 | This program is free software; you can redistribute it and/or modify | 9 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by | 10 | it under the terms of the GNU General Public License as published by |
| @@ -77,6 +78,7 @@ enum b43_nphy_rssi_type { | |||
| 77 | B43_NPHY_RSSI_TBD, | 78 | B43_NPHY_RSSI_TBD, |
| 78 | }; | 79 | }; |
| 79 | 80 | ||
| 81 | /* TODO: reorder functions */ | ||
| 80 | static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, | 82 | static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, |
| 81 | bool enable); | 83 | bool enable); |
| 82 | static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, | 84 | static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, |
| @@ -87,6 +89,14 @@ static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, | |||
| 87 | u16 value, u8 core, bool off); | 89 | u16 value, u8 core, bool off); |
| 88 | static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, | 90 | static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, |
| 89 | u16 value, u8 core); | 91 | u16 value, u8 core); |
| 92 | static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev); | ||
| 93 | |||
| 94 | static inline bool b43_nphy_ipa(struct b43_wldev *dev) | ||
| 95 | { | ||
| 96 | enum ieee80211_band band = b43_current_band(dev->wl); | ||
| 97 | return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) || | ||
| 98 | (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ)); | ||
| 99 | } | ||
| 90 | 100 | ||
| 91 | void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna) | 101 | void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna) |
| 92 | {//TODO | 102 | {//TODO |
| @@ -248,15 +258,25 @@ static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable) | |||
| 248 | { | 258 | { |
| 249 | struct b43_phy_n *nphy = dev->phy.n; | 259 | struct b43_phy_n *nphy = dev->phy.n; |
| 250 | u8 i; | 260 | u8 i; |
| 251 | u16 tmp; | 261 | u16 bmask, val, tmp; |
| 262 | enum ieee80211_band band = b43_current_band(dev->wl); | ||
| 252 | 263 | ||
| 253 | if (nphy->hang_avoid) | 264 | if (nphy->hang_avoid) |
| 254 | b43_nphy_stay_in_carrier_search(dev, 1); | 265 | b43_nphy_stay_in_carrier_search(dev, 1); |
| 255 | 266 | ||
| 256 | nphy->txpwrctrl = enable; | 267 | nphy->txpwrctrl = enable; |
| 257 | if (!enable) { | 268 | if (!enable) { |
| 258 | if (dev->phy.rev >= 3) | 269 | if (dev->phy.rev >= 3 && |
| 259 | ; /* TODO */ | 270 | (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) & |
| 271 | (B43_NPHY_TXPCTL_CMD_COEFF | | ||
| 272 | B43_NPHY_TXPCTL_CMD_HWPCTLEN | | ||
| 273 | B43_NPHY_TXPCTL_CMD_PCTLEN))) { | ||
| 274 | /* We disable enabled TX pwr ctl, save it's state */ | ||
| 275 | nphy->tx_pwr_idx[0] = b43_phy_read(dev, | ||
| 276 | B43_NPHY_C1_TXPCTL_STAT) & 0x7f; | ||
| 277 | nphy->tx_pwr_idx[1] = b43_phy_read(dev, | ||
| 278 | B43_NPHY_C2_TXPCTL_STAT) & 0x7f; | ||
| 279 | } | ||
| 260 | 280 | ||
| 261 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840); | 281 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840); |
| 262 | for (i = 0; i < 84; i++) | 282 | for (i = 0; i < 84; i++) |
| @@ -285,10 +305,67 @@ static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable) | |||
| 285 | b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, | 305 | b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, |
| 286 | ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A); | 306 | ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A); |
| 287 | 307 | ||
| 288 | if (dev->phy.rev < 2 && 0) | 308 | if (dev->phy.rev < 2 && dev->phy.is_40mhz) |
| 289 | ; /* TODO */ | 309 | b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW); |
| 290 | } else { | 310 | } else { |
| 291 | b43err(dev->wl, "enabling tx pwr ctrl not implemented yet\n"); | 311 | b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, |
| 312 | nphy->adj_pwr_tbl); | ||
| 313 | b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, | ||
| 314 | nphy->adj_pwr_tbl); | ||
| 315 | |||
| 316 | bmask = B43_NPHY_TXPCTL_CMD_COEFF | | ||
| 317 | B43_NPHY_TXPCTL_CMD_HWPCTLEN; | ||
| 318 | /* wl does useless check for "enable" param here */ | ||
| 319 | val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN; | ||
| 320 | if (dev->phy.rev >= 3) { | ||
| 321 | bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN; | ||
| 322 | if (val) | ||
| 323 | val |= B43_NPHY_TXPCTL_CMD_PCTLEN; | ||
| 324 | } | ||
| 325 | b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val); | ||
| 326 | |||
| 327 | if (band == IEEE80211_BAND_5GHZ) { | ||
| 328 | b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, | ||
| 329 | ~B43_NPHY_TXPCTL_CMD_INIT, 0x64); | ||
| 330 | if (dev->phy.rev > 1) | ||
| 331 | b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, | ||
| 332 | ~B43_NPHY_TXPCTL_INIT_PIDXI1, | ||
| 333 | 0x64); | ||
| 334 | } | ||
| 335 | |||
| 336 | if (dev->phy.rev >= 3) { | ||
| 337 | if (nphy->tx_pwr_idx[0] != 128 && | ||
| 338 | nphy->tx_pwr_idx[1] != 128) { | ||
| 339 | /* Recover TX pwr ctl state */ | ||
| 340 | b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, | ||
| 341 | ~B43_NPHY_TXPCTL_CMD_INIT, | ||
| 342 | nphy->tx_pwr_idx[0]); | ||
| 343 | if (dev->phy.rev > 1) | ||
| 344 | b43_phy_maskset(dev, | ||
| 345 | B43_NPHY_TXPCTL_INIT, | ||
| 346 | ~0xff, nphy->tx_pwr_idx[1]); | ||
| 347 | } | ||
| 348 | } | ||
| 349 | |||
| 350 | if (dev->phy.rev >= 3) { | ||
| 351 | b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100); | ||
| 352 | b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100); | ||
| 353 | } else { | ||
| 354 | b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000); | ||
| 355 | } | ||
| 356 | |||
| 357 | if (dev->phy.rev == 2) | ||
| 358 | b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b); | ||
| 359 | else if (dev->phy.rev < 2) | ||
| 360 | b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40); | ||
| 361 | |||
| 362 | if (dev->phy.rev < 2 && dev->phy.is_40mhz) | ||
| 363 | b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW); | ||
| 364 | |||
| 365 | if (b43_nphy_ipa(dev)) { | ||
| 366 | b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4); | ||
| 367 | b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4); | ||
| 368 | } | ||
| 292 | } | 369 | } |
| 293 | 370 | ||
| 294 | if (nphy->hang_avoid) | 371 | if (nphy->hang_avoid) |
| @@ -369,22 +446,23 @@ static void b43_nphy_tx_power_fix(struct b43_wldev *dev) | |||
| 369 | else | 446 | else |
| 370 | b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain); | 447 | b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain); |
| 371 | 448 | ||
| 372 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D10 + i); | 449 | b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain); |
| 373 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, radio_gain); | ||
| 374 | |||
| 375 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57); | ||
| 376 | tmp = b43_phy_read(dev, B43_NPHY_TABLE_DATALO); | ||
| 377 | 450 | ||
| 451 | tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57)); | ||
| 378 | if (i == 0) | 452 | if (i == 0) |
| 379 | tmp = (tmp & 0x00FF) | (bbmult << 8); | 453 | tmp = (tmp & 0x00FF) | (bbmult << 8); |
| 380 | else | 454 | else |
| 381 | tmp = (tmp & 0xFF00) | bbmult; | 455 | tmp = (tmp & 0xFF00) | bbmult; |
| 382 | 456 | b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp); | |
| 383 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57); | 457 | |
| 384 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, tmp); | 458 | if (b43_nphy_ipa(dev)) { |
| 385 | 459 | u32 tmp32; | |
| 386 | if (0) | 460 | u16 reg = (i == 0) ? |
| 387 | ; /* TODO */ | 461 | B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1; |
| 462 | tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i, txpi[i])); | ||
| 463 | b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4); | ||
| 464 | b43_phy_set(dev, reg, 0x4); | ||
| 465 | } | ||
| 388 | } | 466 | } |
| 389 | 467 | ||
| 390 | b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT); | 468 | b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT); |
| @@ -393,6 +471,57 @@ static void b43_nphy_tx_power_fix(struct b43_wldev *dev) | |||
| 393 | b43_nphy_stay_in_carrier_search(dev, 0); | 471 | b43_nphy_stay_in_carrier_search(dev, 0); |
| 394 | } | 472 | } |
| 395 | 473 | ||
| 474 | static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev) | ||
| 475 | { | ||
| 476 | struct b43_phy *phy = &dev->phy; | ||
| 477 | |||
| 478 | const u32 *table = NULL; | ||
| 479 | #if 0 | ||
| 480 | TODO: b43_ntab_papd_pga_gain_delta_ipa_2* | ||
| 481 | u32 rfpwr_offset; | ||
| 482 | u8 pga_gain; | ||
| 483 | int i; | ||
| 484 | #endif | ||
| 485 | |||
| 486 | if (phy->rev >= 3) { | ||
| 487 | if (b43_nphy_ipa(dev)) { | ||
| 488 | table = b43_nphy_get_ipa_gain_table(dev); | ||
| 489 | } else { | ||
| 490 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { | ||
| 491 | if (phy->rev == 3) | ||
| 492 | table = b43_ntab_tx_gain_rev3_5ghz; | ||
| 493 | if (phy->rev == 4) | ||
| 494 | table = b43_ntab_tx_gain_rev4_5ghz; | ||
| 495 | else | ||
| 496 | table = b43_ntab_tx_gain_rev5plus_5ghz; | ||
| 497 | } else { | ||
| 498 | table = b43_ntab_tx_gain_rev3plus_2ghz; | ||
| 499 | } | ||
| 500 | } | ||
| 501 | } else { | ||
| 502 | table = b43_ntab_tx_gain_rev0_1_2; | ||
| 503 | } | ||
| 504 | b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table); | ||
| 505 | b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table); | ||
| 506 | |||
| 507 | if (phy->rev >= 3) { | ||
| 508 | #if 0 | ||
| 509 | nphy->gmval = (table[0] >> 16) & 0x7000; | ||
| 510 | |||
| 511 | for (i = 0; i < 128; i++) { | ||
| 512 | pga_gain = (table[i] >> 24) & 0xF; | ||
| 513 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | ||
| 514 | rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain]; | ||
| 515 | else | ||
| 516 | rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain]; | ||
| 517 | b43_ntab_write(dev, B43_NTAB32(26, 576 + i), | ||
| 518 | rfpwr_offset); | ||
| 519 | b43_ntab_write(dev, B43_NTAB32(27, 576 + i), | ||
| 520 | rfpwr_offset); | ||
| 521 | } | ||
| 522 | #endif | ||
| 523 | } | ||
| 524 | } | ||
| 396 | 525 | ||
| 397 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */ | 526 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */ |
| 398 | static void b43_radio_2055_setup(struct b43_wldev *dev, | 527 | static void b43_radio_2055_setup(struct b43_wldev *dev, |
| @@ -581,14 +710,10 @@ static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable) | |||
| 581 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */ | 710 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */ |
| 582 | static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev) | 711 | static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev) |
| 583 | { | 712 | { |
| 584 | struct b43_phy_n *nphy = dev->phy.n; | ||
| 585 | u16 tmp; | 713 | u16 tmp; |
| 586 | enum ieee80211_band band = b43_current_band(dev->wl); | ||
| 587 | bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) || | ||
| 588 | (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ); | ||
| 589 | 714 | ||
| 590 | if (dev->phy.rev >= 3) { | 715 | if (dev->phy.rev >= 3) { |
| 591 | if (ipa) { | 716 | if (b43_nphy_ipa(dev)) { |
| 592 | tmp = 4; | 717 | tmp = 4; |
| 593 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2, | 718 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2, |
| 594 | (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp); | 719 | (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp); |
| @@ -899,11 +1024,7 @@ static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask) | |||
| 899 | static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev) | 1024 | static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev) |
| 900 | { | 1025 | { |
| 901 | u16 array[4]; | 1026 | u16 array[4]; |
| 902 | int i; | 1027 | b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array); |
| 903 | |||
| 904 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50); | ||
| 905 | for (i = 0; i < 4; i++) | ||
| 906 | array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO); | ||
| 907 | 1028 | ||
| 908 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]); | 1029 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]); |
| 909 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]); | 1030 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]); |
| @@ -1366,180 +1487,220 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev) | |||
| 1366 | } | 1487 | } |
| 1367 | } | 1488 | } |
| 1368 | 1489 | ||
| 1369 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */ | 1490 | static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev) |
| 1370 | static void b43_nphy_workarounds(struct b43_wldev *dev) | ||
| 1371 | { | 1491 | { |
| 1492 | struct b43_phy_n *nphy = dev->phy.n; | ||
| 1372 | struct ssb_sprom *sprom = dev->dev->bus_sprom; | 1493 | struct ssb_sprom *sprom = dev->dev->bus_sprom; |
| 1373 | struct b43_phy *phy = &dev->phy; | ||
| 1374 | struct b43_phy_n *nphy = phy->n; | ||
| 1375 | 1494 | ||
| 1376 | u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 }; | 1495 | /* TX to RX */ |
| 1377 | u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 }; | 1496 | u8 tx2rx_events[9] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F }; |
| 1378 | 1497 | u8 tx2rx_delays[9] = { 8, 4, 2, 2, 4, 4, 6, 1 }; | |
| 1379 | u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; | 1498 | /* RX to TX */ |
| 1380 | u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; | 1499 | u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3, |
| 1500 | 0x1F }; | ||
| 1501 | u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 }; | ||
| 1502 | u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F }; | ||
| 1503 | u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 }; | ||
| 1381 | 1504 | ||
| 1382 | u16 tmp16; | 1505 | u16 tmp16; |
| 1383 | u32 tmp32; | 1506 | u32 tmp32; |
| 1384 | 1507 | ||
| 1385 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) | 1508 | tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); |
| 1386 | b43_nphy_classifier(dev, 1, 0); | 1509 | tmp32 &= 0xffffff; |
| 1387 | else | 1510 | b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); |
| 1388 | b43_nphy_classifier(dev, 1, 1); | 1511 | |
| 1512 | b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); | ||
| 1513 | b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3); | ||
| 1514 | b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); | ||
| 1515 | b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E); | ||
| 1516 | b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD); | ||
| 1517 | b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); | ||
| 1518 | |||
| 1519 | b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C); | ||
| 1520 | b43_phy_write(dev, 0x2AE, 0x000C); | ||
| 1521 | |||
| 1522 | /* TX to RX */ | ||
| 1523 | b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, 9); | ||
| 1524 | |||
| 1525 | /* RX to TX */ | ||
| 1526 | if (b43_nphy_ipa(dev)) | ||
| 1527 | b43_nphy_set_rf_sequence(dev, 1, rx2tx_events_ipa, | ||
| 1528 | rx2tx_delays_ipa, 9); | ||
| 1529 | if (nphy->hw_phyrxchain != 3 && | ||
| 1530 | nphy->hw_phyrxchain != nphy->hw_phytxchain) { | ||
| 1531 | if (b43_nphy_ipa(dev)) { | ||
| 1532 | rx2tx_delays[5] = 59; | ||
| 1533 | rx2tx_delays[6] = 1; | ||
| 1534 | rx2tx_events[7] = 0x1F; | ||
| 1535 | } | ||
| 1536 | b43_nphy_set_rf_sequence(dev, 1, rx2tx_events, rx2tx_delays, 9); | ||
| 1537 | } | ||
| 1389 | 1538 | ||
| 1390 | if (nphy->hang_avoid) | 1539 | tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? |
| 1391 | b43_nphy_stay_in_carrier_search(dev, 1); | 1540 | 0x2 : 0x9C40; |
| 1541 | b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16); | ||
| 1392 | 1542 | ||
| 1393 | b43_phy_set(dev, B43_NPHY_IQFLIP, | 1543 | b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700); |
| 1394 | B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2); | ||
| 1395 | 1544 | ||
| 1396 | if (dev->phy.rev >= 3) { | 1545 | b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D); |
| 1397 | tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); | 1546 | b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D); |
| 1398 | tmp32 &= 0xffffff; | ||
| 1399 | b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); | ||
| 1400 | 1547 | ||
| 1401 | b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); | 1548 | b43_nphy_gain_ctrl_workarounds(dev); |
| 1402 | b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3); | ||
| 1403 | b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); | ||
| 1404 | b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E); | ||
| 1405 | b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD); | ||
| 1406 | b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); | ||
| 1407 | 1549 | ||
| 1408 | b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C); | 1550 | b43_ntab_write(dev, B43_NTAB32(8, 0), 2); |
| 1409 | b43_phy_write(dev, 0x2AE, 0x000C); | 1551 | b43_ntab_write(dev, B43_NTAB32(8, 16), 2); |
| 1410 | 1552 | ||
| 1411 | /* TODO */ | 1553 | /* TODO */ |
| 1412 | 1554 | ||
| 1413 | tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? | 1555 | b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00); |
| 1414 | 0x2 : 0x9C40; | 1556 | b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00); |
| 1415 | b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16); | 1557 | b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06); |
| 1558 | b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06); | ||
| 1559 | b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07); | ||
| 1560 | b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07); | ||
| 1561 | b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88); | ||
| 1562 | b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88); | ||
| 1563 | b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00); | ||
| 1564 | b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00); | ||
| 1565 | |||
| 1566 | /* N PHY WAR TX Chain Update with hw_phytxchain as argument */ | ||
| 1567 | |||
| 1568 | if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR && | ||
| 1569 | b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) || | ||
| 1570 | (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR && | ||
| 1571 | b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) | ||
| 1572 | tmp32 = 0x00088888; | ||
| 1573 | else | ||
| 1574 | tmp32 = 0x88888888; | ||
| 1575 | b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32); | ||
| 1576 | b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32); | ||
| 1577 | b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32); | ||
| 1578 | |||
| 1579 | if (dev->phy.rev == 4 && | ||
| 1580 | b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { | ||
| 1581 | b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC, | ||
| 1582 | 0x70); | ||
| 1583 | b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC, | ||
| 1584 | 0x70); | ||
| 1585 | } | ||
| 1416 | 1586 | ||
| 1417 | b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700); | 1587 | b43_phy_write(dev, 0x224, 0x039C); |
| 1588 | b43_phy_write(dev, 0x225, 0x0357); | ||
| 1589 | b43_phy_write(dev, 0x226, 0x0317); | ||
| 1590 | b43_phy_write(dev, 0x227, 0x02D7); | ||
| 1591 | b43_phy_write(dev, 0x228, 0x039C); | ||
| 1592 | b43_phy_write(dev, 0x229, 0x0357); | ||
| 1593 | b43_phy_write(dev, 0x22A, 0x0317); | ||
| 1594 | b43_phy_write(dev, 0x22B, 0x02D7); | ||
| 1595 | b43_phy_write(dev, 0x22C, 0x039C); | ||
| 1596 | b43_phy_write(dev, 0x22D, 0x0357); | ||
| 1597 | b43_phy_write(dev, 0x22E, 0x0317); | ||
| 1598 | b43_phy_write(dev, 0x22F, 0x02D7); | ||
| 1599 | } | ||
| 1418 | 1600 | ||
| 1419 | b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D); | 1601 | static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev) |
| 1420 | b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D); | 1602 | { |
| 1603 | struct ssb_sprom *sprom = dev->dev->bus_sprom; | ||
| 1604 | struct b43_phy *phy = &dev->phy; | ||
| 1605 | struct b43_phy_n *nphy = phy->n; | ||
| 1421 | 1606 | ||
| 1422 | b43_nphy_gain_ctrl_workarounds(dev); | 1607 | u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 }; |
| 1608 | u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 }; | ||
| 1423 | 1609 | ||
| 1424 | b43_ntab_write(dev, B43_NTAB32(8, 0), 2); | 1610 | u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; |
| 1425 | b43_ntab_write(dev, B43_NTAB32(8, 16), 2); | 1611 | u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; |
| 1426 | 1612 | ||
| 1427 | /* TODO */ | 1613 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ && |
| 1614 | nphy->band5g_pwrgain) { | ||
| 1615 | b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); | ||
| 1616 | b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); | ||
| 1617 | } else { | ||
| 1618 | b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); | ||
| 1619 | b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8); | ||
| 1620 | } | ||
| 1428 | 1621 | ||
| 1429 | b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00); | 1622 | b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A); |
| 1430 | b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00); | 1623 | b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A); |
| 1431 | b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06); | 1624 | b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA); |
| 1432 | b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06); | 1625 | b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA); |
| 1433 | b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07); | ||
| 1434 | b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07); | ||
| 1435 | b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88); | ||
| 1436 | b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88); | ||
| 1437 | b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00); | ||
| 1438 | b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00); | ||
| 1439 | |||
| 1440 | /* N PHY WAR TX Chain Update with hw_phytxchain as argument */ | ||
| 1441 | |||
| 1442 | if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR && | ||
| 1443 | b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) || | ||
| 1444 | (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR && | ||
| 1445 | b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) | ||
| 1446 | tmp32 = 0x00088888; | ||
| 1447 | else | ||
| 1448 | tmp32 = 0x88888888; | ||
| 1449 | b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32); | ||
| 1450 | b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32); | ||
| 1451 | b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32); | ||
| 1452 | |||
| 1453 | if (dev->phy.rev == 4 && | ||
| 1454 | b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { | ||
| 1455 | b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC, | ||
| 1456 | 0x70); | ||
| 1457 | b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC, | ||
| 1458 | 0x70); | ||
| 1459 | } | ||
| 1460 | 1626 | ||
| 1461 | b43_phy_write(dev, 0x224, 0x039C); | 1627 | if (dev->phy.rev < 2) { |
| 1462 | b43_phy_write(dev, 0x225, 0x0357); | 1628 | b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000); |
| 1463 | b43_phy_write(dev, 0x226, 0x0317); | 1629 | b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000); |
| 1464 | b43_phy_write(dev, 0x227, 0x02D7); | 1630 | b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB); |
| 1465 | b43_phy_write(dev, 0x228, 0x039C); | 1631 | b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB); |
| 1466 | b43_phy_write(dev, 0x229, 0x0357); | 1632 | b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800); |
| 1467 | b43_phy_write(dev, 0x22A, 0x0317); | 1633 | b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800); |
| 1468 | b43_phy_write(dev, 0x22B, 0x02D7); | 1634 | } |
| 1469 | b43_phy_write(dev, 0x22C, 0x039C); | ||
| 1470 | b43_phy_write(dev, 0x22D, 0x0357); | ||
| 1471 | b43_phy_write(dev, 0x22E, 0x0317); | ||
| 1472 | b43_phy_write(dev, 0x22F, 0x02D7); | ||
| 1473 | } else { | ||
| 1474 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ && | ||
| 1475 | nphy->band5g_pwrgain) { | ||
| 1476 | b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); | ||
| 1477 | b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); | ||
| 1478 | } else { | ||
| 1479 | b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); | ||
| 1480 | b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8); | ||
| 1481 | } | ||
| 1482 | 1635 | ||
| 1483 | b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A); | 1636 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); |
| 1484 | b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A); | 1637 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); |
| 1485 | b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA); | 1638 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); |
| 1486 | b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA); | 1639 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); |
| 1487 | 1640 | ||
| 1488 | if (dev->phy.rev < 2) { | 1641 | if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD && |
| 1489 | b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000); | 1642 | dev->dev->board_type == 0x8B) { |
| 1490 | b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000); | 1643 | delays1[0] = 0x1; |
| 1491 | b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB); | 1644 | delays1[5] = 0x14; |
| 1492 | b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB); | 1645 | } |
| 1493 | b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800); | 1646 | b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7); |
| 1494 | b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800); | 1647 | b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7); |
| 1495 | } | ||
| 1496 | 1648 | ||
| 1497 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); | 1649 | b43_nphy_gain_ctrl_workarounds(dev); |
| 1498 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); | ||
| 1499 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); | ||
| 1500 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); | ||
| 1501 | 1650 | ||
| 1502 | if (sprom->boardflags2_lo & 0x100 && | 1651 | if (dev->phy.rev < 2) { |
| 1503 | dev->dev->board_type == 0x8B) { | 1652 | if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2) |
| 1504 | delays1[0] = 0x1; | 1653 | b43_hf_write(dev, b43_hf_read(dev) | |
| 1505 | delays1[5] = 0x14; | 1654 | B43_HF_MLADVW); |
| 1506 | } | 1655 | } else if (dev->phy.rev == 2) { |
| 1507 | b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7); | 1656 | b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0); |
| 1508 | b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7); | 1657 | b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0); |
| 1658 | } | ||
| 1509 | 1659 | ||
| 1510 | b43_nphy_gain_ctrl_workarounds(dev); | 1660 | if (dev->phy.rev < 2) |
| 1661 | b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL, | ||
| 1662 | ~B43_NPHY_SCRAM_SIGCTL_SCM); | ||
| 1663 | |||
| 1664 | /* Set phase track alpha and beta */ | ||
| 1665 | b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); | ||
| 1666 | b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); | ||
| 1667 | b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); | ||
| 1668 | b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); | ||
| 1669 | b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); | ||
| 1670 | b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); | ||
| 1671 | |||
| 1672 | b43_phy_mask(dev, B43_NPHY_PIL_DW1, | ||
| 1673 | ~B43_NPHY_PIL_DW_64QAM & 0xFFFF); | ||
| 1674 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); | ||
| 1675 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); | ||
| 1676 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); | ||
| 1677 | |||
| 1678 | if (dev->phy.rev == 2) | ||
| 1679 | b43_phy_set(dev, B43_NPHY_FINERX2_CGC, | ||
| 1680 | B43_NPHY_FINERX2_CGC_DECGC); | ||
| 1681 | } | ||
| 1511 | 1682 | ||
| 1512 | if (dev->phy.rev < 2) { | 1683 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */ |
| 1513 | if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2) | 1684 | static void b43_nphy_workarounds(struct b43_wldev *dev) |
| 1514 | b43_hf_write(dev, b43_hf_read(dev) | | 1685 | { |
| 1515 | B43_HF_MLADVW); | 1686 | struct b43_phy *phy = &dev->phy; |
| 1516 | } else if (dev->phy.rev == 2) { | 1687 | struct b43_phy_n *nphy = phy->n; |
| 1517 | b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0); | ||
| 1518 | b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0); | ||
| 1519 | } | ||
| 1520 | 1688 | ||
| 1521 | if (dev->phy.rev < 2) | 1689 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) |
| 1522 | b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL, | 1690 | b43_nphy_classifier(dev, 1, 0); |
| 1523 | ~B43_NPHY_SCRAM_SIGCTL_SCM); | 1691 | else |
| 1692 | b43_nphy_classifier(dev, 1, 1); | ||
| 1524 | 1693 | ||
| 1525 | /* Set phase track alpha and beta */ | 1694 | if (nphy->hang_avoid) |
| 1526 | b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); | 1695 | b43_nphy_stay_in_carrier_search(dev, 1); |
| 1527 | b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); | ||
| 1528 | b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); | ||
| 1529 | b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); | ||
| 1530 | b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); | ||
| 1531 | b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); | ||
| 1532 | 1696 | ||
| 1533 | b43_phy_mask(dev, B43_NPHY_PIL_DW1, | 1697 | b43_phy_set(dev, B43_NPHY_IQFLIP, |
| 1534 | ~B43_NPHY_PIL_DW_64QAM & 0xFFFF); | 1698 | B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2); |
| 1535 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); | ||
| 1536 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); | ||
| 1537 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); | ||
| 1538 | 1699 | ||
| 1539 | if (dev->phy.rev == 2) | 1700 | if (dev->phy.rev >= 3) |
| 1540 | b43_phy_set(dev, B43_NPHY_FINERX2_CGC, | 1701 | b43_nphy_workarounds_rev3plus(dev); |
| 1541 | B43_NPHY_FINERX2_CGC_DECGC); | 1702 | else |
| 1542 | } | 1703 | b43_nphy_workarounds_rev1_2(dev); |
| 1543 | 1704 | ||
| 1544 | if (nphy->hang_avoid) | 1705 | if (nphy->hang_avoid) |
| 1545 | b43_nphy_stay_in_carrier_search(dev, 0); | 1706 | b43_nphy_stay_in_carrier_search(dev, 0); |
| @@ -2135,7 +2296,6 @@ static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type) | |||
| 2135 | 2296 | ||
| 2136 | static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) | 2297 | static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) |
| 2137 | { | 2298 | { |
| 2138 | struct b43_phy_n *nphy = dev->phy.n; | ||
| 2139 | u8 i; | 2299 | u8 i; |
| 2140 | u16 reg, val; | 2300 | u16 reg, val; |
| 2141 | 2301 | ||
| @@ -2199,10 +2359,7 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) | |||
| 2199 | enum ieee80211_band band = | 2359 | enum ieee80211_band band = |
| 2200 | b43_current_band(dev->wl); | 2360 | b43_current_band(dev->wl); |
| 2201 | 2361 | ||
| 2202 | if ((nphy->ipa2g_on && | 2362 | if (b43_nphy_ipa(dev)) |
| 2203 | band == IEEE80211_BAND_2GHZ) || | ||
| 2204 | (nphy->ipa5g_on && | ||
| 2205 | band == IEEE80211_BAND_5GHZ)) | ||
| 2206 | val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE; | 2363 | val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE; |
| 2207 | else | 2364 | else |
| 2208 | val = 0x11; | 2365 | val = 0x11; |
| @@ -2577,8 +2734,8 @@ static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev) | |||
| 2577 | { | 2734 | { |
| 2578 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | 2735 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { |
| 2579 | if (dev->phy.rev >= 6) { | 2736 | if (dev->phy.rev >= 6) { |
| 2580 | /* TODO If the chip is 47162 | 2737 | if (dev->dev->chip_id == 47162) |
| 2581 | return txpwrctrl_tx_gain_ipa_rev5 */ | 2738 | return txpwrctrl_tx_gain_ipa_rev5; |
| 2582 | return txpwrctrl_tx_gain_ipa_rev6; | 2739 | return txpwrctrl_tx_gain_ipa_rev6; |
| 2583 | } else if (dev->phy.rev >= 5) { | 2740 | } else if (dev->phy.rev >= 5) { |
| 2584 | return txpwrctrl_tx_gain_ipa_rev5; | 2741 | return txpwrctrl_tx_gain_ipa_rev5; |
| @@ -2828,10 +2985,7 @@ static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev) | |||
| 2828 | enum ieee80211_band band = | 2985 | enum ieee80211_band band = |
| 2829 | b43_current_band(dev->wl); | 2986 | b43_current_band(dev->wl); |
| 2830 | 2987 | ||
| 2831 | if ((nphy->ipa2g_on && | 2988 | if (b43_nphy_ipa(dev)) { |
| 2832 | band == IEEE80211_BAND_2GHZ) || | ||
| 2833 | (nphy->ipa5g_on && | ||
| 2834 | band == IEEE80211_BAND_5GHZ)) { | ||
| 2835 | table = b43_nphy_get_ipa_gain_table(dev); | 2989 | table = b43_nphy_get_ipa_gain_table(dev); |
| 2836 | } else { | 2990 | } else { |
| 2837 | if (band == IEEE80211_BAND_5GHZ) { | 2991 | if (band == IEEE80211_BAND_5GHZ) { |
| @@ -3648,7 +3802,7 @@ int b43_phy_initn(struct b43_wldev *dev) | |||
| 3648 | b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); | 3802 | b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); |
| 3649 | b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); | 3803 | b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); |
| 3650 | 3804 | ||
| 3651 | if (sprom->boardflags2_lo & 0x100 || | 3805 | if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD || |
| 3652 | (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && | 3806 | (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && |
| 3653 | dev->dev->board_type == 0x8B)) | 3807 | dev->dev->board_type == 0x8B)) |
| 3654 | b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); | 3808 | b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); |
| @@ -3667,8 +3821,7 @@ int b43_phy_initn(struct b43_wldev *dev) | |||
| 3667 | } | 3821 | } |
| 3668 | 3822 | ||
| 3669 | tmp2 = b43_current_band(dev->wl); | 3823 | tmp2 = b43_current_band(dev->wl); |
| 3670 | if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) || | 3824 | if (b43_nphy_ipa(dev)) { |
| 3671 | (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) { | ||
| 3672 | b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1); | 3825 | b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1); |
| 3673 | b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F, | 3826 | b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F, |
| 3674 | nphy->papd_epsilon_offset[0] << 7); | 3827 | nphy->papd_epsilon_offset[0] << 7); |
| @@ -3706,15 +3859,7 @@ int b43_phy_initn(struct b43_wldev *dev) | |||
| 3706 | b43_nphy_tx_power_fix(dev); | 3859 | b43_nphy_tx_power_fix(dev); |
| 3707 | /* TODO N PHY TX Power Control Idle TSSI */ | 3860 | /* TODO N PHY TX Power Control Idle TSSI */ |
| 3708 | /* TODO N PHY TX Power Control Setup */ | 3861 | /* TODO N PHY TX Power Control Setup */ |
| 3709 | 3862 | b43_nphy_tx_gain_table_upload(dev); | |
| 3710 | if (phy->rev >= 3) { | ||
| 3711 | /* TODO */ | ||
| 3712 | } else { | ||
| 3713 | b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, | ||
| 3714 | b43_ntab_tx_gain_rev0_1_2); | ||
| 3715 | b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, | ||
| 3716 | b43_ntab_tx_gain_rev0_1_2); | ||
| 3717 | } | ||
| 3718 | 3863 | ||
| 3719 | if (nphy->phyrxchain != 3) | 3864 | if (nphy->phyrxchain != 3) |
| 3720 | b43_nphy_set_rx_core_state(dev, nphy->phyrxchain); | 3865 | b43_nphy_set_rx_core_state(dev, nphy->phyrxchain); |
| @@ -3918,6 +4063,10 @@ static void b43_nphy_op_prepare_structs(struct b43_wldev *dev) | |||
| 3918 | nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */ | 4063 | nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */ |
| 3919 | nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */ | 4064 | nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */ |
| 3920 | nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */ | 4065 | nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */ |
| 4066 | /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is | ||
| 4067 | * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */ | ||
| 4068 | nphy->tx_pwr_idx[0] = 128; | ||
| 4069 | nphy->tx_pwr_idx[1] = 128; | ||
| 3921 | } | 4070 | } |
| 3922 | 4071 | ||
| 3923 | static void b43_nphy_op_free(struct b43_wldev *dev) | 4072 | static void b43_nphy_op_free(struct b43_wldev *dev) |
diff --git a/drivers/net/wireless/b43/phy_n.h b/drivers/net/wireless/b43/phy_n.h index e789a89f1047..fbf520285bd1 100644 --- a/drivers/net/wireless/b43/phy_n.h +++ b/drivers/net/wireless/b43/phy_n.h | |||
| @@ -764,6 +764,8 @@ struct b43_phy_n { | |||
| 764 | u8 cal_orig_pwr_idx[2]; | 764 | u8 cal_orig_pwr_idx[2]; |
| 765 | u8 measure_hold; | 765 | u8 measure_hold; |
| 766 | u8 phyrxchain; | 766 | u8 phyrxchain; |
| 767 | u8 hw_phyrxchain; | ||
| 768 | u8 hw_phytxchain; | ||
| 767 | u8 perical; | 769 | u8 perical; |
| 768 | u32 deaf_count; | 770 | u32 deaf_count; |
| 769 | u32 rxcalparams; | 771 | u32 rxcalparams; |
| @@ -783,6 +785,8 @@ struct b43_phy_n { | |||
| 783 | u16 mphase_txcal_bestcoeffs[11]; | 785 | u16 mphase_txcal_bestcoeffs[11]; |
| 784 | 786 | ||
| 785 | bool txpwrctrl; | 787 | bool txpwrctrl; |
| 788 | u8 tx_pwr_idx[2]; | ||
| 789 | u16 adj_pwr_tbl[84]; | ||
| 786 | u16 txcal_bbmult; | 790 | u16 txcal_bbmult; |
| 787 | u16 txiqlocal_bestc[11]; | 791 | u16 txiqlocal_bestc[11]; |
| 788 | bool txiqlocal_coeffsvalid; | 792 | bool txiqlocal_coeffsvalid; |
diff --git a/drivers/net/wireless/b43/radio_2055.c b/drivers/net/wireless/b43/radio_2055.c index 93643f18c2b3..5289a18ddd8c 100644 --- a/drivers/net/wireless/b43/radio_2055.c +++ b/drivers/net/wireless/b43/radio_2055.c | |||
| @@ -4,6 +4,7 @@ | |||
| 4 | IEEE 802.11n PHY and radio device data tables | 4 | IEEE 802.11n PHY and radio device data tables |
| 5 | 5 | ||
| 6 | Copyright (c) 2008 Michael Buesch <m@bues.ch> | 6 | Copyright (c) 2008 Michael Buesch <m@bues.ch> |
| 7 | Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com> | ||
| 7 | 8 | ||
| 8 | This program is free software; you can redistribute it and/or modify | 9 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by | 10 | it under the terms of the GNU General Public License as published by |
diff --git a/drivers/net/wireless/b43/radio_2056.c b/drivers/net/wireless/b43/radio_2056.c index 8890df067029..a01f776ca4de 100644 --- a/drivers/net/wireless/b43/radio_2056.c +++ b/drivers/net/wireless/b43/radio_2056.c | |||
| @@ -3,6 +3,8 @@ | |||
| 3 | Broadcom B43 wireless driver | 3 | Broadcom B43 wireless driver |
| 4 | IEEE 802.11n 2056 radio device data tables | 4 | IEEE 802.11n 2056 radio device data tables |
| 5 | 5 | ||
| 6 | Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com> | ||
| 7 | |||
| 6 | This program is free software; you can redistribute it and/or modify | 8 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by | 9 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 2 of the License, or | 10 | the Free Software Foundation; either version 2 of the License, or |
diff --git a/drivers/net/wireless/b43/radio_2056.h b/drivers/net/wireless/b43/radio_2056.h index d52df6be705a..a7159d8578be 100644 --- a/drivers/net/wireless/b43/radio_2056.h +++ b/drivers/net/wireless/b43/radio_2056.h | |||
| @@ -1,29 +1,3 @@ | |||
| 1 | /* | ||
| 2 | |||
| 3 | Broadcom B43 wireless driver | ||
| 4 | |||
| 5 | Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com> | ||
| 6 | |||
| 7 | Some parts of the code in this file are derived from the brcm80211 | ||
| 8 | driver Copyright (c) 2010 Broadcom Corporation | ||
| 9 | |||
| 10 | This program is free software; you can redistribute it and/or modify | ||
| 11 | it under the terms of the GNU General Public License as published by | ||
| 12 | the Free Software Foundation; either version 2 of the License, or | ||
| 13 | (at your option) any later version. | ||
| 14 | |||
| 15 | This program is distributed in the hope that it will be useful, | ||
| 16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 18 | GNU General Public License for more details. | ||
| 19 | |||
| 20 | You should have received a copy of the GNU General Public License | ||
| 21 | along with this program; see the file COPYING. If not, write to | ||
| 22 | the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, | ||
| 23 | Boston, MA 02110-1301, USA. | ||
| 24 | |||
| 25 | */ | ||
| 26 | |||
| 27 | #ifndef B43_RADIO_2056_H_ | 1 | #ifndef B43_RADIO_2056_H_ |
| 28 | #define B43_RADIO_2056_H_ | 2 | #define B43_RADIO_2056_H_ |
| 29 | 3 | ||
diff --git a/drivers/net/wireless/b43/radio_2059.c b/drivers/net/wireless/b43/radio_2059.c index f029f6e1f5d1..d4ce8a12ff9a 100644 --- a/drivers/net/wireless/b43/radio_2059.c +++ b/drivers/net/wireless/b43/radio_2059.c | |||
| @@ -3,6 +3,8 @@ | |||
| 3 | Broadcom B43 wireless driver | 3 | Broadcom B43 wireless driver |
| 4 | IEEE 802.11n 2059 radio device data tables | 4 | IEEE 802.11n 2059 radio device data tables |
| 5 | 5 | ||
| 6 | Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com> | ||
| 7 | |||
| 6 | This program is free software; you can redistribute it and/or modify | 8 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by | 9 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 2 of the License, or | 10 | the Free Software Foundation; either version 2 of the License, or |
diff --git a/drivers/net/wireless/b43/tables_nphy.c b/drivers/net/wireless/b43/tables_nphy.c index 916f238a71df..7b326f2efdc9 100644 --- a/drivers/net/wireless/b43/tables_nphy.c +++ b/drivers/net/wireless/b43/tables_nphy.c | |||
| @@ -4,6 +4,7 @@ | |||
| 4 | IEEE 802.11n PHY data tables | 4 | IEEE 802.11n PHY data tables |
| 5 | 5 | ||
| 6 | Copyright (c) 2008 Michael Buesch <m@bues.ch> | 6 | Copyright (c) 2008 Michael Buesch <m@bues.ch> |
| 7 | Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com> | ||
| 7 | 8 | ||
| 8 | This program is free software; you can redistribute it and/or modify | 9 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by | 10 | it under the terms of the GNU General Public License as published by |
diff --git a/drivers/net/wireless/b43/tables_phy_ht.c b/drivers/net/wireless/b43/tables_phy_ht.c index 677d217b5fb3..176c49d74ef4 100644 --- a/drivers/net/wireless/b43/tables_phy_ht.c +++ b/drivers/net/wireless/b43/tables_phy_ht.c | |||
| @@ -3,6 +3,8 @@ | |||
| 3 | Broadcom B43 wireless driver | 3 | Broadcom B43 wireless driver |
| 4 | IEEE 802.11n HT-PHY data tables | 4 | IEEE 802.11n HT-PHY data tables |
| 5 | 5 | ||
| 6 | Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com> | ||
| 7 | |||
| 6 | This program is free software; you can redistribute it and/or modify | 8 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by | 9 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 2 of the License, or | 10 | the Free Software Foundation; either version 2 of the License, or |
diff --git a/drivers/net/wireless/b43/tables_phy_lcn.c b/drivers/net/wireless/b43/tables_phy_lcn.c index 0a5842808a78..9d484e2f79bf 100644 --- a/drivers/net/wireless/b43/tables_phy_lcn.c +++ b/drivers/net/wireless/b43/tables_phy_lcn.c | |||
| @@ -3,6 +3,8 @@ | |||
| 3 | Broadcom B43 wireless driver | 3 | Broadcom B43 wireless driver |
| 4 | IEEE 802.11n LCN-PHY data tables | 4 | IEEE 802.11n LCN-PHY data tables |
| 5 | 5 | ||
| 6 | Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com> | ||
| 7 | |||
| 6 | This program is free software; you can redistribute it and/or modify | 8 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by | 9 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 2 of the License, or | 10 | the Free Software Foundation; either version 2 of the License, or |
| @@ -25,6 +27,18 @@ | |||
| 25 | #include "phy_common.h" | 27 | #include "phy_common.h" |
| 26 | #include "phy_lcn.h" | 28 | #include "phy_lcn.h" |
| 27 | 29 | ||
| 30 | struct b43_lcntab_tx_gain_tbl_entry { | ||
| 31 | u8 gm; | ||
| 32 | u8 pga; | ||
| 33 | u8 pad; | ||
| 34 | u8 dac; | ||
| 35 | u8 bb_mult; | ||
| 36 | }; | ||
| 37 | |||
| 38 | /************************************************** | ||
| 39 | * Static tables. | ||
| 40 | **************************************************/ | ||
| 41 | |||
| 28 | static const u16 b43_lcntab_0x02[] = { | 42 | static const u16 b43_lcntab_0x02[] = { |
| 29 | 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, | 43 | 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, |
| 30 | 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, | 44 | 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, |
| @@ -296,6 +310,160 @@ static const u32 b43_lcntab_0x18[] = { | |||
| 296 | }; | 310 | }; |
| 297 | 311 | ||
| 298 | /************************************************** | 312 | /************************************************** |
| 313 | * TX gain. | ||
| 314 | **************************************************/ | ||
| 315 | |||
| 316 | const struct b43_lcntab_tx_gain_tbl_entry | ||
| 317 | b43_lcntab_tx_gain_tbl_2ghz_ext_pa_rev0[B43_LCNTAB_TX_GAIN_SIZE] = { | ||
| 318 | { 0x03, 0x00, 0x1f, 0x0, 0x48 }, | ||
| 319 | { 0x03, 0x00, 0x1f, 0x0, 0x46 }, | ||
| 320 | { 0x03, 0x00, 0x1f, 0x0, 0x44 }, | ||
| 321 | { 0x03, 0x00, 0x1e, 0x0, 0x43 }, | ||
| 322 | { 0x03, 0x00, 0x1d, 0x0, 0x44 }, | ||
| 323 | { 0x03, 0x00, 0x1c, 0x0, 0x44 }, | ||
| 324 | { 0x03, 0x00, 0x1b, 0x0, 0x45 }, | ||
| 325 | { 0x03, 0x00, 0x1a, 0x0, 0x46 }, | ||
| 326 | { 0x03, 0x00, 0x19, 0x0, 0x46 }, | ||
| 327 | { 0x03, 0x00, 0x18, 0x0, 0x47 }, | ||
| 328 | { 0x03, 0x00, 0x17, 0x0, 0x48 }, | ||
| 329 | { 0x03, 0x00, 0x17, 0x0, 0x46 }, | ||
| 330 | { 0x03, 0x00, 0x16, 0x0, 0x47 }, | ||
| 331 | { 0x03, 0x00, 0x15, 0x0, 0x48 }, | ||
| 332 | { 0x03, 0x00, 0x15, 0x0, 0x46 }, | ||
| 333 | { 0x03, 0x00, 0x15, 0x0, 0x44 }, | ||
| 334 | { 0x03, 0x00, 0x15, 0x0, 0x42 }, | ||
| 335 | { 0x03, 0x00, 0x15, 0x0, 0x40 }, | ||
| 336 | { 0x03, 0x00, 0x15, 0x0, 0x3f }, | ||
| 337 | { 0x03, 0x00, 0x14, 0x0, 0x40 }, | ||
| 338 | { 0x03, 0x00, 0x13, 0x0, 0x41 }, | ||
| 339 | { 0x03, 0x00, 0x13, 0x0, 0x40 }, | ||
| 340 | { 0x03, 0x00, 0x12, 0x0, 0x41 }, | ||
| 341 | { 0x03, 0x00, 0x12, 0x0, 0x40 }, | ||
| 342 | { 0x03, 0x00, 0x11, 0x0, 0x41 }, | ||
| 343 | { 0x03, 0x00, 0x11, 0x0, 0x40 }, | ||
| 344 | { 0x03, 0x00, 0x10, 0x0, 0x41 }, | ||
| 345 | { 0x03, 0x00, 0x10, 0x0, 0x40 }, | ||
| 346 | { 0x03, 0x00, 0x10, 0x0, 0x3e }, | ||
| 347 | { 0x03, 0x00, 0x10, 0x0, 0x3c }, | ||
| 348 | { 0x03, 0x00, 0x10, 0x0, 0x3a }, | ||
| 349 | { 0x03, 0x00, 0x0f, 0x0, 0x3d }, | ||
| 350 | { 0x03, 0x00, 0x0f, 0x0, 0x3b }, | ||
| 351 | { 0x03, 0x00, 0x0e, 0x0, 0x3d }, | ||
| 352 | { 0x03, 0x00, 0x0e, 0x0, 0x3c }, | ||
| 353 | { 0x03, 0x00, 0x0e, 0x0, 0x3a }, | ||
| 354 | { 0x03, 0x00, 0x0d, 0x0, 0x3c }, | ||
| 355 | { 0x03, 0x00, 0x0d, 0x0, 0x3b }, | ||
| 356 | { 0x03, 0x00, 0x0c, 0x0, 0x3e }, | ||
| 357 | { 0x03, 0x00, 0x0c, 0x0, 0x3c }, | ||
| 358 | { 0x03, 0x00, 0x0c, 0x0, 0x3a }, | ||
| 359 | { 0x03, 0x00, 0x0b, 0x0, 0x3e }, | ||
| 360 | { 0x03, 0x00, 0x0b, 0x0, 0x3c }, | ||
| 361 | { 0x03, 0x00, 0x0b, 0x0, 0x3b }, | ||
| 362 | { 0x03, 0x00, 0x0b, 0x0, 0x39 }, | ||
| 363 | { 0x03, 0x00, 0x0a, 0x0, 0x3d }, | ||
| 364 | { 0x03, 0x00, 0x0a, 0x0, 0x3b }, | ||
| 365 | { 0x03, 0x00, 0x0a, 0x0, 0x39 }, | ||
| 366 | { 0x03, 0x00, 0x09, 0x0, 0x3e }, | ||
| 367 | { 0x03, 0x00, 0x09, 0x0, 0x3c }, | ||
| 368 | { 0x03, 0x00, 0x09, 0x0, 0x3a }, | ||
| 369 | { 0x03, 0x00, 0x09, 0x0, 0x39 }, | ||
| 370 | { 0x03, 0x00, 0x08, 0x0, 0x3e }, | ||
| 371 | { 0x03, 0x00, 0x08, 0x0, 0x3c }, | ||
| 372 | { 0x03, 0x00, 0x08, 0x0, 0x3a }, | ||
| 373 | { 0x03, 0x00, 0x08, 0x0, 0x39 }, | ||
| 374 | { 0x03, 0x00, 0x08, 0x0, 0x37 }, | ||
| 375 | { 0x03, 0x00, 0x07, 0x0, 0x3d }, | ||
| 376 | { 0x03, 0x00, 0x07, 0x0, 0x3c }, | ||
| 377 | { 0x03, 0x00, 0x07, 0x0, 0x3a }, | ||
| 378 | { 0x03, 0x00, 0x07, 0x0, 0x38 }, | ||
| 379 | { 0x03, 0x00, 0x07, 0x0, 0x37 }, | ||
| 380 | { 0x03, 0x00, 0x06, 0x0, 0x3e }, | ||
| 381 | { 0x03, 0x00, 0x06, 0x0, 0x3c }, | ||
| 382 | { 0x03, 0x00, 0x06, 0x0, 0x3a }, | ||
| 383 | { 0x03, 0x00, 0x06, 0x0, 0x39 }, | ||
| 384 | { 0x03, 0x00, 0x06, 0x0, 0x37 }, | ||
| 385 | { 0x03, 0x00, 0x06, 0x0, 0x36 }, | ||
| 386 | { 0x03, 0x00, 0x06, 0x0, 0x34 }, | ||
| 387 | { 0x03, 0x00, 0x05, 0x0, 0x3d }, | ||
| 388 | { 0x03, 0x00, 0x05, 0x0, 0x3b }, | ||
| 389 | { 0x03, 0x00, 0x05, 0x0, 0x39 }, | ||
| 390 | { 0x03, 0x00, 0x05, 0x0, 0x38 }, | ||
| 391 | { 0x03, 0x00, 0x05, 0x0, 0x36 }, | ||
| 392 | { 0x03, 0x00, 0x05, 0x0, 0x35 }, | ||
| 393 | { 0x03, 0x00, 0x05, 0x0, 0x33 }, | ||
| 394 | { 0x03, 0x00, 0x04, 0x0, 0x3e }, | ||
| 395 | { 0x03, 0x00, 0x04, 0x0, 0x3c }, | ||
| 396 | { 0x03, 0x00, 0x04, 0x0, 0x3a }, | ||
| 397 | { 0x03, 0x00, 0x04, 0x0, 0x39 }, | ||
| 398 | { 0x03, 0x00, 0x04, 0x0, 0x37 }, | ||
| 399 | { 0x03, 0x00, 0x04, 0x0, 0x36 }, | ||
| 400 | { 0x03, 0x00, 0x04, 0x0, 0x34 }, | ||
| 401 | { 0x03, 0x00, 0x04, 0x0, 0x33 }, | ||
| 402 | { 0x03, 0x00, 0x04, 0x0, 0x31 }, | ||
| 403 | { 0x03, 0x00, 0x04, 0x0, 0x30 }, | ||
| 404 | { 0x03, 0x00, 0x04, 0x0, 0x2e }, | ||
| 405 | { 0x03, 0x00, 0x03, 0x0, 0x3c }, | ||
| 406 | { 0x03, 0x00, 0x03, 0x0, 0x3a }, | ||
| 407 | { 0x03, 0x00, 0x03, 0x0, 0x39 }, | ||
| 408 | { 0x03, 0x00, 0x03, 0x0, 0x37 }, | ||
| 409 | { 0x03, 0x00, 0x03, 0x0, 0x36 }, | ||
| 410 | { 0x03, 0x00, 0x03, 0x0, 0x34 }, | ||
| 411 | { 0x03, 0x00, 0x03, 0x0, 0x33 }, | ||
| 412 | { 0x03, 0x00, 0x03, 0x0, 0x31 }, | ||
| 413 | { 0x03, 0x00, 0x03, 0x0, 0x30 }, | ||
| 414 | { 0x03, 0x00, 0x03, 0x0, 0x2e }, | ||
| 415 | { 0x03, 0x00, 0x03, 0x0, 0x2d }, | ||
| 416 | { 0x03, 0x00, 0x03, 0x0, 0x2c }, | ||
| 417 | { 0x03, 0x00, 0x03, 0x0, 0x2b }, | ||
| 418 | { 0x03, 0x00, 0x03, 0x0, 0x29 }, | ||
| 419 | { 0x03, 0x00, 0x02, 0x0, 0x3d }, | ||
| 420 | { 0x03, 0x00, 0x02, 0x0, 0x3b }, | ||
| 421 | { 0x03, 0x00, 0x02, 0x0, 0x39 }, | ||
| 422 | { 0x03, 0x00, 0x02, 0x0, 0x38 }, | ||
| 423 | { 0x03, 0x00, 0x02, 0x0, 0x36 }, | ||
| 424 | { 0x03, 0x00, 0x02, 0x0, 0x35 }, | ||
| 425 | { 0x03, 0x00, 0x02, 0x0, 0x33 }, | ||
| 426 | { 0x03, 0x00, 0x02, 0x0, 0x32 }, | ||
| 427 | { 0x03, 0x00, 0x02, 0x0, 0x30 }, | ||
| 428 | { 0x03, 0x00, 0x02, 0x0, 0x2f }, | ||
| 429 | { 0x03, 0x00, 0x02, 0x0, 0x2e }, | ||
| 430 | { 0x03, 0x00, 0x02, 0x0, 0x2c }, | ||
| 431 | { 0x03, 0x00, 0x02, 0x0, 0x2b }, | ||
| 432 | { 0x03, 0x00, 0x02, 0x0, 0x2a }, | ||
| 433 | { 0x03, 0x00, 0x02, 0x0, 0x29 }, | ||
| 434 | { 0x03, 0x00, 0x02, 0x0, 0x27 }, | ||
| 435 | { 0x03, 0x00, 0x02, 0x0, 0x26 }, | ||
| 436 | { 0x03, 0x00, 0x02, 0x0, 0x25 }, | ||
| 437 | { 0x03, 0x00, 0x02, 0x0, 0x24 }, | ||
| 438 | { 0x03, 0x00, 0x02, 0x0, 0x23 }, | ||
| 439 | { 0x03, 0x00, 0x02, 0x0, 0x22 }, | ||
| 440 | { 0x03, 0x00, 0x02, 0x0, 0x21 }, | ||
| 441 | { 0x03, 0x00, 0x02, 0x0, 0x20 }, | ||
| 442 | { 0x03, 0x00, 0x01, 0x0, 0x3f }, | ||
| 443 | { 0x03, 0x00, 0x01, 0x0, 0x3d }, | ||
| 444 | { 0x03, 0x00, 0x01, 0x0, 0x3b }, | ||
| 445 | { 0x03, 0x00, 0x01, 0x0, 0x39 }, | ||
| 446 | }; | ||
| 447 | |||
| 448 | /************************************************** | ||
| 449 | * SW control. | ||
| 450 | **************************************************/ | ||
| 451 | |||
| 452 | const u16 b43_lcntab_sw_ctl_4313_epa_rev0[] = { | ||
| 453 | 0x0002, 0x0008, 0x0004, 0x0001, 0x0002, 0x0008, | ||
| 454 | 0x0004, 0x0001, 0x0002, 0x0008, 0x0004, 0x0001, | ||
| 455 | 0x0002, 0x0008, 0x0004, 0x0001, 0x0002, 0x0008, | ||
| 456 | 0x0004, 0x0001, 0x0002, 0x0008, 0x0004, 0x0001, | ||
| 457 | 0x0002, 0x0008, 0x0004, 0x0001, 0x0002, 0x0008, | ||
| 458 | 0x0004, 0x0001, 0x0002, 0x0008, 0x0004, 0x0001, | ||
| 459 | 0x0002, 0x0008, 0x0004, 0x0001, 0x0002, 0x0008, | ||
| 460 | 0x0004, 0x0001, 0x0002, 0x0008, 0x0004, 0x0001, | ||
| 461 | 0x0002, 0x0008, 0x0004, 0x0001, 0x0002, 0x0008, | ||
| 462 | 0x0004, 0x0001, 0x0002, 0x0008, 0x0004, 0x0001, | ||
| 463 | 0x0002, 0x0008, 0x0004, 0x0001, | ||
| 464 | }; | ||
| 465 | |||
| 466 | /************************************************** | ||
| 299 | * R/W ops. | 467 | * R/W ops. |
| 300 | **************************************************/ | 468 | **************************************************/ |
| 301 | 469 | ||
| @@ -318,9 +486,8 @@ u32 b43_lcntab_read(struct b43_wldev *dev, u32 offset) | |||
| 318 | break; | 486 | break; |
| 319 | case B43_LCNTAB_32BIT: | 487 | case B43_LCNTAB_32BIT: |
| 320 | b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset); | 488 | b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset); |
| 321 | value = b43_phy_read(dev, B43_PHY_LCN_TABLE_DATAHI); | 489 | value = b43_phy_read(dev, B43_PHY_LCN_TABLE_DATALO); |
| 322 | value <<= 16; | 490 | value |= (b43_phy_read(dev, B43_PHY_LCN_TABLE_DATAHI) << 16); |
| 323 | value |= b43_phy_read(dev, B43_PHY_LCN_TABLE_DATALO); | ||
| 324 | break; | 491 | break; |
| 325 | default: | 492 | default: |
| 326 | B43_WARN_ON(1); | 493 | B43_WARN_ON(1); |
| @@ -357,10 +524,9 @@ void b43_lcntab_read_bulk(struct b43_wldev *dev, u32 offset, | |||
| 357 | break; | 524 | break; |
| 358 | case B43_LCNTAB_32BIT: | 525 | case B43_LCNTAB_32BIT: |
| 359 | *((u32 *)data) = b43_phy_read(dev, | 526 | *((u32 *)data) = b43_phy_read(dev, |
| 360 | B43_PHY_LCN_TABLE_DATAHI); | ||
| 361 | *((u32 *)data) <<= 16; | ||
| 362 | *((u32 *)data) |= b43_phy_read(dev, | ||
| 363 | B43_PHY_LCN_TABLE_DATALO); | 527 | B43_PHY_LCN_TABLE_DATALO); |
| 528 | *((u32 *)data) |= (b43_phy_read(dev, | ||
| 529 | B43_PHY_LCN_TABLE_DATAHI) << 16); | ||
| 364 | data += 4; | 530 | data += 4; |
| 365 | break; | 531 | break; |
| 366 | default: | 532 | default: |
| @@ -447,7 +613,7 @@ void b43_lcntab_write_bulk(struct b43_wldev *dev, u32 offset, | |||
| 447 | #define lcntab_upload(dev, offset, data) do { \ | 613 | #define lcntab_upload(dev, offset, data) do { \ |
| 448 | b43_lcntab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \ | 614 | b43_lcntab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \ |
| 449 | } while (0) | 615 | } while (0) |
| 450 | void b43_phy_lcn_tables_init(struct b43_wldev *dev) | 616 | static void b43_phy_lcn_upload_static_tables(struct b43_wldev *dev) |
| 451 | { | 617 | { |
| 452 | lcntab_upload(dev, B43_LCNTAB16(0x02, 0), b43_lcntab_0x02); | 618 | lcntab_upload(dev, B43_LCNTAB16(0x02, 0), b43_lcntab_0x02); |
| 453 | lcntab_upload(dev, B43_LCNTAB16(0x01, 0), b43_lcntab_0x01); | 619 | lcntab_upload(dev, B43_LCNTAB16(0x01, 0), b43_lcntab_0x01); |
| @@ -464,3 +630,78 @@ void b43_phy_lcn_tables_init(struct b43_wldev *dev) | |||
| 464 | lcntab_upload(dev, B43_LCNTAB16(0x00, 0), b43_lcntab_0x00); | 630 | lcntab_upload(dev, B43_LCNTAB16(0x00, 0), b43_lcntab_0x00); |
| 465 | lcntab_upload(dev, B43_LCNTAB32(0x18, 0), b43_lcntab_0x18); | 631 | lcntab_upload(dev, B43_LCNTAB32(0x18, 0), b43_lcntab_0x18); |
| 466 | } | 632 | } |
| 633 | |||
| 634 | void b43_phy_lcn_load_tx_gain_tab(struct b43_wldev *dev, | ||
| 635 | const struct b43_lcntab_tx_gain_tbl_entry *gain_table) | ||
| 636 | { | ||
| 637 | u32 i; | ||
| 638 | u32 val; | ||
| 639 | |||
| 640 | u16 pa_gain = 0x70; | ||
| 641 | if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM) | ||
| 642 | pa_gain = 0x10; | ||
| 643 | |||
| 644 | for (i = 0; i < B43_LCNTAB_TX_GAIN_SIZE; i++) { | ||
| 645 | val = ((pa_gain << 24) | | ||
| 646 | (gain_table[i].pad << 16) | | ||
| 647 | (gain_table[i].pga << 8) | | ||
| 648 | gain_table[i].gm); | ||
| 649 | b43_lcntab_write(dev, B43_LCNTAB32(0x7, 0xc0 + i), val); | ||
| 650 | |||
| 651 | /* brcmsmac doesn't maskset, we follow newer wl here */ | ||
| 652 | val = b43_lcntab_read(dev, B43_LCNTAB32(0x7, 0x140 + i)); | ||
| 653 | val &= 0x000fffff; | ||
| 654 | val |= ((gain_table[i].dac << 28) | | ||
| 655 | (gain_table[i].bb_mult << 20)); | ||
| 656 | b43_lcntab_write(dev, B43_LCNTAB32(0x7, 0x140 + i), val); | ||
| 657 | } | ||
| 658 | } | ||
| 659 | |||
| 660 | /* Not implemented in brcmsmac, noticed in wl in MMIO dump */ | ||
| 661 | static void b43_phy_lcn_rewrite_tables(struct b43_wldev *dev) | ||
| 662 | { | ||
| 663 | int i; | ||
| 664 | u32 tmp; | ||
| 665 | for (i = 0; i < 128; i++) { | ||
| 666 | tmp = b43_lcntab_read(dev, B43_LCNTAB32(0x7, 0x240 + i)); | ||
| 667 | b43_lcntab_write(dev, B43_LCNTAB32(0x7, 0x240 + i), tmp); | ||
| 668 | } | ||
| 669 | } | ||
| 670 | |||
| 671 | /* wlc_lcnphy_clear_papd_comptable */ | ||
| 672 | static void b43_phy_lcn_clean_papd_comp_table(struct b43_wldev *dev) | ||
| 673 | { | ||
| 674 | u8 i; | ||
| 675 | |||
| 676 | for (i = 0; i < 0x80; i++) | ||
| 677 | b43_lcntab_write(dev, B43_LCNTAB32(0x18, i), 0x80000); | ||
| 678 | } | ||
| 679 | |||
| 680 | /* wlc_lcnphy_tbl_init */ | ||
| 681 | void b43_phy_lcn_tables_init(struct b43_wldev *dev) | ||
| 682 | { | ||
| 683 | struct ssb_sprom *sprom = dev->dev->bus_sprom; | ||
| 684 | |||
| 685 | b43_phy_lcn_upload_static_tables(dev); | ||
| 686 | |||
| 687 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | ||
| 688 | if (sprom->boardflags_lo & B43_BFL_EXTLNA) | ||
| 689 | b43_phy_lcn_load_tx_gain_tab(dev, | ||
| 690 | b43_lcntab_tx_gain_tbl_2ghz_ext_pa_rev0); | ||
| 691 | else | ||
| 692 | b43err(dev->wl, | ||
| 693 | "TX gain table unknown for this card\n"); | ||
| 694 | } | ||
| 695 | |||
| 696 | if (sprom->boardflags_lo & B43_BFL_FEM && | ||
| 697 | !(sprom->boardflags_hi & B43_BFH_FEM_BT)) | ||
| 698 | b43_lcntab_write_bulk(dev, B43_LCNTAB16(0xf, 0), | ||
| 699 | ARRAY_SIZE(b43_lcntab_sw_ctl_4313_epa_rev0), | ||
| 700 | b43_lcntab_sw_ctl_4313_epa_rev0); | ||
| 701 | else | ||
| 702 | b43err(dev->wl, "SW ctl table is unknown for this card\n"); | ||
| 703 | |||
| 704 | /* TODO: various tables ops here */ | ||
| 705 | b43_phy_lcn_rewrite_tables(dev); | ||
| 706 | b43_phy_lcn_clean_papd_comp_table(dev); | ||
| 707 | } | ||
diff --git a/drivers/net/wireless/b43/tables_phy_lcn.h b/drivers/net/wireless/b43/tables_phy_lcn.h index b6471e89c36f..caff9db6831f 100644 --- a/drivers/net/wireless/b43/tables_phy_lcn.h +++ b/drivers/net/wireless/b43/tables_phy_lcn.h | |||
| @@ -10,6 +10,8 @@ | |||
| 10 | #define B43_LCNTAB16(table, offset) (((table) << 10) | (offset) | B43_LCNTAB_16BIT) | 10 | #define B43_LCNTAB16(table, offset) (((table) << 10) | (offset) | B43_LCNTAB_16BIT) |
| 11 | #define B43_LCNTAB32(table, offset) (((table) << 10) | (offset) | B43_LCNTAB_32BIT) | 11 | #define B43_LCNTAB32(table, offset) (((table) << 10) | (offset) | B43_LCNTAB_32BIT) |
| 12 | 12 | ||
| 13 | #define B43_LCNTAB_TX_GAIN_SIZE 128 | ||
| 14 | |||
| 13 | u32 b43_lcntab_read(struct b43_wldev *dev, u32 offset); | 15 | u32 b43_lcntab_read(struct b43_wldev *dev, u32 offset); |
| 14 | void b43_lcntab_read_bulk(struct b43_wldev *dev, u32 offset, | 16 | void b43_lcntab_read_bulk(struct b43_wldev *dev, u32 offset, |
| 15 | unsigned int nr_elements, void *_data); | 17 | unsigned int nr_elements, void *_data); |
diff --git a/drivers/net/wireless/iwlwifi/iwl-2000.c b/drivers/net/wireless/iwlwifi/iwl-2000.c index 764d3104e128..913f2a228527 100644 --- a/drivers/net/wireless/iwlwifi/iwl-2000.c +++ b/drivers/net/wireless/iwlwifi/iwl-2000.c | |||
| @@ -285,6 +285,7 @@ struct iwl_cfg iwl2000_2bg_cfg = { | |||
| 285 | struct iwl_cfg iwl2000_2bgn_d_cfg = { | 285 | struct iwl_cfg iwl2000_2bgn_d_cfg = { |
| 286 | .name = "2000D Series 2x2 BGN", | 286 | .name = "2000D Series 2x2 BGN", |
| 287 | IWL_DEVICE_2000, | 287 | IWL_DEVICE_2000, |
| 288 | .ht_params = &iwl2000_ht_params, | ||
| 288 | }; | 289 | }; |
| 289 | 290 | ||
| 290 | #define IWL_DEVICE_2030 \ | 291 | #define IWL_DEVICE_2030 \ |
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-lib.c b/drivers/net/wireless/iwlwifi/iwl-agn-lib.c index 7c036b9c2b30..13018872f776 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn-lib.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn-lib.c | |||
| @@ -659,7 +659,7 @@ int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control) | |||
| 659 | IWL_SCD_BE_MSK | IWL_SCD_BK_MSK | | 659 | IWL_SCD_BE_MSK | IWL_SCD_BK_MSK | |
| 660 | IWL_SCD_MGMT_MSK; | 660 | IWL_SCD_MGMT_MSK; |
| 661 | if ((flush_control & BIT(IWL_RXON_CTX_PAN)) && | 661 | if ((flush_control & BIT(IWL_RXON_CTX_PAN)) && |
| 662 | (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))) | 662 | (priv->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))) |
| 663 | flush_cmd.fifo_control |= IWL_PAN_SCD_VO_MSK | | 663 | flush_cmd.fifo_control |= IWL_PAN_SCD_VO_MSK | |
| 664 | IWL_PAN_SCD_VI_MSK | IWL_PAN_SCD_BE_MSK | | 664 | IWL_PAN_SCD_VI_MSK | IWL_PAN_SCD_BE_MSK | |
| 665 | IWL_PAN_SCD_BK_MSK | IWL_PAN_SCD_MGMT_MSK | | 665 | IWL_PAN_SCD_BK_MSK | IWL_PAN_SCD_MGMT_MSK | |
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-rxon.c b/drivers/net/wireless/iwlwifi/iwl-agn-rxon.c index 1af276739d87..00e6fc59e459 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn-rxon.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn-rxon.c | |||
| @@ -311,7 +311,7 @@ int iwlagn_set_pan_params(struct iwl_priv *priv) | |||
| 311 | int slot0 = 300, slot1 = 0; | 311 | int slot0 = 300, slot1 = 0; |
| 312 | int ret; | 312 | int ret; |
| 313 | 313 | ||
| 314 | if (priv->valid_contexts == BIT(IWL_RXON_CTX_BSS)) | 314 | if (priv->shrd->valid_contexts == BIT(IWL_RXON_CTX_BSS)) |
| 315 | return 0; | 315 | return 0; |
| 316 | 316 | ||
| 317 | BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2); | 317 | BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2); |
| @@ -456,7 +456,7 @@ int iwlagn_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx) | |||
| 456 | else | 456 | else |
| 457 | ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | 457 | ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
| 458 | 458 | ||
| 459 | iwl_print_rx_config_cmd(priv, ctx); | 459 | iwl_print_rx_config_cmd(priv, ctx->ctxid); |
| 460 | ret = iwl_check_rxon_cmd(priv, ctx); | 460 | ret = iwl_check_rxon_cmd(priv, ctx); |
| 461 | if (ret) { | 461 | if (ret) { |
| 462 | IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n"); | 462 | IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n"); |
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-tt.h b/drivers/net/wireless/iwlwifi/iwl-agn-tt.h index d118ed29bf3f..7282a23e8f1c 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn-tt.h +++ b/drivers/net/wireless/iwlwifi/iwl-agn-tt.h | |||
| @@ -117,7 +117,6 @@ struct iwl_tt_mgmt { | |||
| 117 | u8 iwl_tt_current_power_mode(struct iwl_priv *priv); | 117 | u8 iwl_tt_current_power_mode(struct iwl_priv *priv); |
| 118 | bool iwl_tt_is_low_power_state(struct iwl_priv *priv); | 118 | bool iwl_tt_is_low_power_state(struct iwl_priv *priv); |
| 119 | bool iwl_ht_enabled(struct iwl_priv *priv); | 119 | bool iwl_ht_enabled(struct iwl_priv *priv); |
| 120 | bool iwl_check_for_ct_kill(struct iwl_priv *priv); | ||
| 121 | enum iwl_antenna_ok iwl_tx_ant_restriction(struct iwl_priv *priv); | 120 | enum iwl_antenna_ok iwl_tx_ant_restriction(struct iwl_priv *priv); |
| 122 | enum iwl_antenna_ok iwl_rx_ant_restriction(struct iwl_priv *priv); | 121 | enum iwl_antenna_ok iwl_rx_ant_restriction(struct iwl_priv *priv); |
| 123 | void iwl_tt_enter_ct_kill(struct iwl_priv *priv); | 122 | void iwl_tt_enter_ct_kill(struct iwl_priv *priv); |
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-tx.c b/drivers/net/wireless/iwlwifi/iwl-agn-tx.c index f8a4bcf0a34b..ba5c514c4a43 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn-tx.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn-tx.c | |||
| @@ -741,7 +741,7 @@ void iwlagn_rx_reply_tx(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |||
| 741 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | 741 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
| 742 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); | 742 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
| 743 | int txq_id = SEQ_TO_QUEUE(sequence); | 743 | int txq_id = SEQ_TO_QUEUE(sequence); |
| 744 | int cmd_index = SEQ_TO_INDEX(sequence); | 744 | int cmd_index __maybe_unused = SEQ_TO_INDEX(sequence); |
| 745 | struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; | 745 | struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; |
| 746 | struct ieee80211_hdr *hdr; | 746 | struct ieee80211_hdr *hdr; |
| 747 | u32 status = le16_to_cpu(tx_resp->status.status); | 747 | u32 status = le16_to_cpu(tx_resp->status.status); |
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c b/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c index ddb255a575df..ea31d7674df3 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c | |||
| @@ -114,7 +114,7 @@ static int iwlagn_load_section(struct iwl_priv *priv, const char *name, | |||
| 114 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | 114 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); |
| 115 | 115 | ||
| 116 | IWL_DEBUG_FW(priv, "%s uCode section being loaded...\n", name); | 116 | IWL_DEBUG_FW(priv, "%s uCode section being loaded...\n", name); |
| 117 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | 117 | ret = wait_event_interruptible_timeout(priv->shrd->wait_command_queue, |
| 118 | priv->ucode_write_complete, 5 * HZ); | 118 | priv->ucode_write_complete, 5 * HZ); |
| 119 | if (ret == -ERESTARTSYS) { | 119 | if (ret == -ERESTARTSYS) { |
| 120 | IWL_ERR(priv, "Could not load the %s uCode section due " | 120 | IWL_ERR(priv, "Could not load the %s uCode section due " |
| @@ -349,6 +349,7 @@ int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type) | |||
| 349 | 349 | ||
| 350 | static int iwlagn_alive_notify(struct iwl_priv *priv) | 350 | static int iwlagn_alive_notify(struct iwl_priv *priv) |
| 351 | { | 351 | { |
| 352 | struct iwl_rxon_context *ctx; | ||
| 352 | int ret; | 353 | int ret; |
| 353 | 354 | ||
| 354 | if (!priv->tx_cmd_pool) | 355 | if (!priv->tx_cmd_pool) |
| @@ -361,6 +362,8 @@ static int iwlagn_alive_notify(struct iwl_priv *priv) | |||
| 361 | return -ENOMEM; | 362 | return -ENOMEM; |
| 362 | 363 | ||
| 363 | iwl_trans_tx_start(trans(priv)); | 364 | iwl_trans_tx_start(trans(priv)); |
| 365 | for_each_context(priv, ctx) | ||
| 366 | ctx->last_tx_rejected = false; | ||
| 364 | 367 | ||
| 365 | ret = iwlagn_send_wimax_coex(priv); | 368 | ret = iwlagn_send_wimax_coex(priv); |
| 366 | if (ret) | 369 | if (ret) |
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c index 8113fbe770a3..7f6c58ebbc44 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn.c | |||
| @@ -623,9 +623,9 @@ static void iwl_init_context(struct iwl_priv *priv, u32 ucode_flags) | |||
| 623 | * The default context is always valid, | 623 | * The default context is always valid, |
| 624 | * the PAN context depends on uCode. | 624 | * the PAN context depends on uCode. |
| 625 | */ | 625 | */ |
| 626 | priv->valid_contexts = BIT(IWL_RXON_CTX_BSS); | 626 | priv->shrd->valid_contexts = BIT(IWL_RXON_CTX_BSS); |
| 627 | if (ucode_flags & IWL_UCODE_TLV_FLAGS_PAN) | 627 | if (ucode_flags & IWL_UCODE_TLV_FLAGS_PAN) |
| 628 | priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN); | 628 | priv->shrd->valid_contexts |= BIT(IWL_RXON_CTX_PAN); |
| 629 | 629 | ||
| 630 | for (i = 0; i < NUM_IWL_RXON_CTX; i++) | 630 | for (i = 0; i < NUM_IWL_RXON_CTX; i++) |
| 631 | priv->contexts[i].ctxid = i; | 631 | priv->contexts[i].ctxid = i; |
| @@ -2880,7 +2880,7 @@ static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw, | |||
| 2880 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN]; | 2880 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN]; |
| 2881 | int err = 0; | 2881 | int err = 0; |
| 2882 | 2882 | ||
| 2883 | if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) | 2883 | if (!(priv->shrd->valid_contexts & BIT(IWL_RXON_CTX_PAN))) |
| 2884 | return -EOPNOTSUPP; | 2884 | return -EOPNOTSUPP; |
| 2885 | 2885 | ||
| 2886 | if (!(ctx->interface_modes & BIT(NL80211_IFTYPE_P2P_CLIENT))) | 2886 | if (!(ctx->interface_modes & BIT(NL80211_IFTYPE_P2P_CLIENT))) |
| @@ -2945,7 +2945,7 @@ static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw) | |||
| 2945 | { | 2945 | { |
| 2946 | struct iwl_priv *priv = hw->priv; | 2946 | struct iwl_priv *priv = hw->priv; |
| 2947 | 2947 | ||
| 2948 | if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) | 2948 | if (!(priv->shrd->valid_contexts & BIT(IWL_RXON_CTX_PAN))) |
| 2949 | return -EOPNOTSUPP; | 2949 | return -EOPNOTSUPP; |
| 2950 | 2950 | ||
| 2951 | mutex_lock(&priv->shrd->mutex); | 2951 | mutex_lock(&priv->shrd->mutex); |
| @@ -3032,7 +3032,7 @@ static void iwl_setup_deferred_work(struct iwl_priv *priv) | |||
| 3032 | { | 3032 | { |
| 3033 | priv->shrd->workqueue = create_singlethread_workqueue(DRV_NAME); | 3033 | priv->shrd->workqueue = create_singlethread_workqueue(DRV_NAME); |
| 3034 | 3034 | ||
| 3035 | init_waitqueue_head(&priv->wait_command_queue); | 3035 | init_waitqueue_head(&priv->shrd->wait_command_queue); |
| 3036 | 3036 | ||
| 3037 | INIT_WORK(&priv->restart, iwl_bg_restart); | 3037 | INIT_WORK(&priv->restart, iwl_bg_restart); |
| 3038 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); | 3038 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); |
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.h b/drivers/net/wireless/iwlwifi/iwl-agn.h index a7b4948e43da..4bc1f4669e5a 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn.h +++ b/drivers/net/wireless/iwlwifi/iwl-agn.h | |||
| @@ -98,7 +98,6 @@ int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv, | |||
| 98 | enum iwlagn_ucode_type ucode_type); | 98 | enum iwlagn_ucode_type ucode_type); |
| 99 | 99 | ||
| 100 | /* lib */ | 100 | /* lib */ |
| 101 | int iwlagn_hw_valid_rtc_data_addr(u32 addr); | ||
| 102 | int iwlagn_send_tx_power(struct iwl_priv *priv); | 101 | int iwlagn_send_tx_power(struct iwl_priv *priv); |
| 103 | void iwlagn_temperature(struct iwl_priv *priv); | 102 | void iwlagn_temperature(struct iwl_priv *priv); |
| 104 | u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv); | 103 | u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv); |
| @@ -109,7 +108,6 @@ int iwlagn_send_beacon_cmd(struct iwl_priv *priv); | |||
| 109 | /* rx */ | 108 | /* rx */ |
| 110 | int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band); | 109 | int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band); |
| 111 | void iwl_setup_rx_handlers(struct iwl_priv *priv); | 110 | void iwl_setup_rx_handlers(struct iwl_priv *priv); |
| 112 | void iwl_rx_dispatch(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb); | ||
| 113 | 111 | ||
| 114 | 112 | ||
| 115 | /* tx */ | 113 | /* tx */ |
diff --git a/drivers/net/wireless/iwlwifi/iwl-commands.h b/drivers/net/wireless/iwlwifi/iwl-commands.h index cb06196e0e80..82bfef4730d5 100644 --- a/drivers/net/wireless/iwlwifi/iwl-commands.h +++ b/drivers/net/wireless/iwlwifi/iwl-commands.h | |||
| @@ -3213,12 +3213,7 @@ enum iwl_ucode_calib_cfg { | |||
| 3213 | IWL_CALIB_CFG_LO_IDX | \ | 3213 | IWL_CALIB_CFG_LO_IDX | \ |
| 3214 | IWL_CALIB_CFG_TX_IQ_IDX | \ | 3214 | IWL_CALIB_CFG_TX_IQ_IDX | \ |
| 3215 | IWL_CALIB_CFG_RX_IQ_IDX | \ | 3215 | IWL_CALIB_CFG_RX_IQ_IDX | \ |
| 3216 | IWL_CALIB_CFG_NOISE_IDX | \ | 3216 | IWL_CALIB_CFG_CRYSTAL_IDX) |
| 3217 | IWL_CALIB_CFG_CRYSTAL_IDX | \ | ||
| 3218 | IWL_CALIB_CFG_TEMPERATURE_IDX | \ | ||
| 3219 | IWL_CALIB_CFG_PAPD_IDX | \ | ||
| 3220 | IWL_CALIB_CFG_SENSITIVITY_IDX | \ | ||
| 3221 | IWL_CALIB_CFG_TX_PWR_IDX) | ||
| 3222 | 3217 | ||
| 3223 | #define IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK cpu_to_le32(BIT(0)) | 3218 | #define IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK cpu_to_le32(BIT(0)) |
| 3224 | 3219 | ||
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.c b/drivers/net/wireless/iwlwifi/iwl-core.c index 20dd1a5506ed..9270f990b2dd 100644 --- a/drivers/net/wireless/iwlwifi/iwl-core.c +++ b/drivers/net/wireless/iwlwifi/iwl-core.c | |||
| @@ -817,9 +817,9 @@ void iwl_chswitch_done(struct iwl_priv *priv, bool is_success) | |||
| 817 | } | 817 | } |
| 818 | 818 | ||
| 819 | #ifdef CONFIG_IWLWIFI_DEBUG | 819 | #ifdef CONFIG_IWLWIFI_DEBUG |
| 820 | void iwl_print_rx_config_cmd(struct iwl_priv *priv, | 820 | void iwl_print_rx_config_cmd(struct iwl_priv *priv, u8 ctxid) |
| 821 | struct iwl_rxon_context *ctx) | ||
| 822 | { | 821 | { |
| 822 | struct iwl_rxon_context *ctx = &priv->contexts[ctxid]; | ||
| 823 | struct iwl_rxon_cmd *rxon = &ctx->staging; | 823 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
| 824 | 824 | ||
| 825 | IWL_DEBUG_RADIO(priv, "RX CONFIG:\n"); | 825 | IWL_DEBUG_RADIO(priv, "RX CONFIG:\n"); |
| @@ -868,7 +868,7 @@ void iwlagn_fw_error(struct iwl_priv *priv, bool ondemand) | |||
| 868 | * commands by clearing the ready bit */ | 868 | * commands by clearing the ready bit */ |
| 869 | clear_bit(STATUS_READY, &priv->shrd->status); | 869 | clear_bit(STATUS_READY, &priv->shrd->status); |
| 870 | 870 | ||
| 871 | wake_up_interruptible(&priv->wait_command_queue); | 871 | wake_up_interruptible(&priv->shrd->wait_command_queue); |
| 872 | 872 | ||
| 873 | if (!ondemand) { | 873 | if (!ondemand) { |
| 874 | /* | 874 | /* |
| @@ -1842,7 +1842,7 @@ void iwl_start_tx_ba_trans_ready(struct iwl_priv *priv, | |||
| 1842 | enum iwl_rxon_context_id ctx, | 1842 | enum iwl_rxon_context_id ctx, |
| 1843 | u8 sta_id, u8 tid) | 1843 | u8 sta_id, u8 tid) |
| 1844 | { | 1844 | { |
| 1845 | struct ieee80211_vif *vif = priv->contexts[ctx].vif; | 1845 | struct ieee80211_vif *vif; |
| 1846 | u8 *addr = priv->stations[sta_id].sta.sta.addr; | 1846 | u8 *addr = priv->stations[sta_id].sta.sta.addr; |
| 1847 | 1847 | ||
| 1848 | if (ctx == NUM_IWL_RXON_CTX) | 1848 | if (ctx == NUM_IWL_RXON_CTX) |
| @@ -1865,3 +1865,14 @@ void iwl_stop_tx_ba_trans_ready(struct iwl_priv *priv, | |||
| 1865 | 1865 | ||
| 1866 | ieee80211_stop_tx_ba_cb_irqsafe(vif, addr, tid); | 1866 | ieee80211_stop_tx_ba_cb_irqsafe(vif, addr, tid); |
| 1867 | } | 1867 | } |
| 1868 | |||
| 1869 | void iwl_set_hw_rfkill_state(struct iwl_priv *priv, bool state) | ||
| 1870 | { | ||
| 1871 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, state); | ||
| 1872 | } | ||
| 1873 | |||
| 1874 | void iwl_nic_config(struct iwl_priv *priv) | ||
| 1875 | { | ||
| 1876 | priv->cfg->lib->nic_config(priv); | ||
| 1877 | |||
| 1878 | } | ||
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.h b/drivers/net/wireless/iwlwifi/iwl-core.h index 2ea8a2e0dfbc..56b554c43fde 100644 --- a/drivers/net/wireless/iwlwifi/iwl-core.h +++ b/drivers/net/wireless/iwlwifi/iwl-core.h | |||
| @@ -73,8 +73,6 @@ struct iwl_cmd; | |||
| 73 | 73 | ||
| 74 | #define TIME_UNIT 1024 | 74 | #define TIME_UNIT 1024 |
| 75 | 75 | ||
| 76 | #define IWL_CMD(x) case x: return #x | ||
| 77 | |||
| 78 | struct iwl_lib_ops { | 76 | struct iwl_lib_ops { |
| 79 | /* set hw dependent parameters */ | 77 | /* set hw dependent parameters */ |
| 80 | int (*set_hw_params)(struct iwl_priv *priv); | 78 | int (*set_hw_params)(struct iwl_priv *priv); |
| @@ -271,7 +269,6 @@ int iwl_mac_change_interface(struct ieee80211_hw *hw, | |||
| 271 | #ifdef CONFIG_IWLWIFI_DEBUGFS | 269 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
| 272 | int iwl_alloc_traffic_mem(struct iwl_priv *priv); | 270 | int iwl_alloc_traffic_mem(struct iwl_priv *priv); |
| 273 | void iwl_free_traffic_mem(struct iwl_priv *priv); | 271 | void iwl_free_traffic_mem(struct iwl_priv *priv); |
| 274 | void iwl_reset_traffic_log(struct iwl_priv *priv); | ||
| 275 | void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv, | 272 | void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv, |
| 276 | u16 length, struct ieee80211_hdr *header); | 273 | u16 length, struct ieee80211_hdr *header); |
| 277 | void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv, | 274 | void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv, |
| @@ -360,7 +357,6 @@ int __must_check iwl_scan_initiate(struct iwl_priv *priv, | |||
| 360 | * S e n d i n g H o s t C o m m a n d s * | 357 | * S e n d i n g H o s t C o m m a n d s * |
| 361 | *****************************************************/ | 358 | *****************************************************/ |
| 362 | 359 | ||
| 363 | const char *get_cmd_string(u8 cmd); | ||
| 364 | void iwl_bg_watchdog(unsigned long data); | 360 | void iwl_bg_watchdog(unsigned long data); |
| 365 | u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec, u32 beacon_interval); | 361 | u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec, u32 beacon_interval); |
| 366 | __le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base, | 362 | __le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base, |
| @@ -368,19 +364,6 @@ __le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base, | |||
| 368 | 364 | ||
| 369 | 365 | ||
| 370 | /***************************************************** | 366 | /***************************************************** |
| 371 | * Error Handling Debugging | ||
| 372 | ******************************************************/ | ||
| 373 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
| 374 | void iwl_print_rx_config_cmd(struct iwl_priv *priv, | ||
| 375 | struct iwl_rxon_context *ctx); | ||
| 376 | #else | ||
| 377 | static inline void iwl_print_rx_config_cmd(struct iwl_priv *priv, | ||
| 378 | struct iwl_rxon_context *ctx) | ||
| 379 | { | ||
| 380 | } | ||
| 381 | #endif | ||
| 382 | |||
| 383 | /***************************************************** | ||
| 384 | * GEOS | 367 | * GEOS |
| 385 | ******************************************************/ | 368 | ******************************************************/ |
| 386 | int iwl_init_geos(struct iwl_priv *priv); | 369 | int iwl_init_geos(struct iwl_priv *priv); |
| @@ -389,8 +372,6 @@ void iwl_free_geos(struct iwl_priv *priv); | |||
| 389 | extern void iwl_send_bt_config(struct iwl_priv *priv); | 372 | extern void iwl_send_bt_config(struct iwl_priv *priv); |
| 390 | extern int iwl_send_statistics_request(struct iwl_priv *priv, | 373 | extern int iwl_send_statistics_request(struct iwl_priv *priv, |
| 391 | u8 flags, bool clear); | 374 | u8 flags, bool clear); |
| 392 | void iwl_apm_stop(struct iwl_priv *priv); | ||
| 393 | int iwl_apm_init(struct iwl_priv *priv); | ||
| 394 | 375 | ||
| 395 | int iwl_send_rxon_timing(struct iwl_priv *priv, struct iwl_rxon_context *ctx); | 376 | int iwl_send_rxon_timing(struct iwl_priv *priv, struct iwl_rxon_context *ctx); |
| 396 | 377 | ||
| @@ -408,7 +389,4 @@ static inline bool iwl_advanced_bt_coexist(struct iwl_priv *priv) | |||
| 408 | 389 | ||
| 409 | extern bool bt_siso_mode; | 390 | extern bool bt_siso_mode; |
| 410 | 391 | ||
| 411 | |||
| 412 | void iwlagn_fw_error(struct iwl_priv *priv, bool ondemand); | ||
| 413 | |||
| 414 | #endif /* __iwl_core_h__ */ | 392 | #endif /* __iwl_core_h__ */ |
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h index d6dbb0423045..b9f3267e720c 100644 --- a/drivers/net/wireless/iwlwifi/iwl-csr.h +++ b/drivers/net/wireless/iwlwifi/iwl-csr.h | |||
| @@ -439,4 +439,22 @@ | |||
| 439 | */ | 439 | */ |
| 440 | #define HBUS_TARG_WRPTR (HBUS_BASE+0x060) | 440 | #define HBUS_TARG_WRPTR (HBUS_BASE+0x060) |
| 441 | 441 | ||
| 442 | /********************************************************** | ||
| 443 | * CSR values | ||
| 444 | **********************************************************/ | ||
| 445 | /* | ||
| 446 | * host interrupt timeout value | ||
| 447 | * used with setting interrupt coalescing timer | ||
| 448 | * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit | ||
| 449 | * | ||
| 450 | * default interrupt coalescing timer is 64 x 32 = 2048 usecs | ||
| 451 | * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs | ||
| 452 | */ | ||
| 453 | #define IWL_HOST_INT_TIMEOUT_MAX (0xFF) | ||
| 454 | #define IWL_HOST_INT_TIMEOUT_DEF (0x40) | ||
| 455 | #define IWL_HOST_INT_TIMEOUT_MIN (0x0) | ||
| 456 | #define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF) | ||
| 457 | #define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10) | ||
| 458 | #define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0) | ||
| 459 | |||
| 442 | #endif /* !__iwl_csr_h__ */ | 460 | #endif /* !__iwl_csr_h__ */ |
diff --git a/drivers/net/wireless/iwlwifi/iwl-debugfs.c b/drivers/net/wireless/iwlwifi/iwl-debugfs.c index e320cc10167e..d0c63cfee15c 100644 --- a/drivers/net/wireless/iwlwifi/iwl-debugfs.c +++ b/drivers/net/wireless/iwlwifi/iwl-debugfs.c | |||
| @@ -804,6 +804,89 @@ DEBUGFS_READ_WRITE_FILE_OPS(disable_ht40); | |||
| 804 | DEBUGFS_READ_WRITE_FILE_OPS(sleep_level_override); | 804 | DEBUGFS_READ_WRITE_FILE_OPS(sleep_level_override); |
| 805 | DEBUGFS_READ_FILE_OPS(current_sleep_command); | 805 | DEBUGFS_READ_FILE_OPS(current_sleep_command); |
| 806 | 806 | ||
| 807 | static ssize_t iwl_dbgfs_traffic_log_read(struct file *file, | ||
| 808 | char __user *user_buf, | ||
| 809 | size_t count, loff_t *ppos) | ||
| 810 | { | ||
| 811 | struct iwl_priv *priv = file->private_data; | ||
| 812 | int pos = 0, ofs = 0; | ||
| 813 | int cnt = 0, entry; | ||
| 814 | |||
| 815 | char *buf; | ||
| 816 | int bufsz = ((IWL_TRAFFIC_ENTRIES * IWL_TRAFFIC_ENTRY_SIZE * 64) * 2) + | ||
| 817 | (hw_params(priv).max_txq_num * 32 * 8) + 400; | ||
| 818 | const u8 *ptr; | ||
| 819 | ssize_t ret; | ||
| 820 | |||
| 821 | buf = kzalloc(bufsz, GFP_KERNEL); | ||
| 822 | if (!buf) { | ||
| 823 | IWL_ERR(priv, "Can not allocate buffer\n"); | ||
| 824 | return -ENOMEM; | ||
| 825 | } | ||
| 826 | if (priv->tx_traffic && | ||
| 827 | (iwl_get_debug_level(priv->shrd) & IWL_DL_TX)) { | ||
| 828 | ptr = priv->tx_traffic; | ||
| 829 | pos += scnprintf(buf + pos, bufsz - pos, | ||
| 830 | "Tx Traffic idx: %u\n", priv->tx_traffic_idx); | ||
| 831 | for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) { | ||
| 832 | for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16; | ||
| 833 | entry++, ofs += 16) { | ||
| 834 | pos += scnprintf(buf + pos, bufsz - pos, | ||
| 835 | "0x%.4x ", ofs); | ||
| 836 | hex_dump_to_buffer(ptr + ofs, 16, 16, 2, | ||
| 837 | buf + pos, bufsz - pos, 0); | ||
| 838 | pos += strlen(buf + pos); | ||
| 839 | if (bufsz - pos > 0) | ||
| 840 | buf[pos++] = '\n'; | ||
| 841 | } | ||
| 842 | } | ||
| 843 | } | ||
| 844 | |||
| 845 | if (priv->rx_traffic && | ||
| 846 | (iwl_get_debug_level(priv->shrd) & IWL_DL_RX)) { | ||
| 847 | ptr = priv->rx_traffic; | ||
| 848 | pos += scnprintf(buf + pos, bufsz - pos, | ||
| 849 | "Rx Traffic idx: %u\n", priv->rx_traffic_idx); | ||
| 850 | for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) { | ||
| 851 | for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16; | ||
| 852 | entry++, ofs += 16) { | ||
| 853 | pos += scnprintf(buf + pos, bufsz - pos, | ||
| 854 | "0x%.4x ", ofs); | ||
| 855 | hex_dump_to_buffer(ptr + ofs, 16, 16, 2, | ||
| 856 | buf + pos, bufsz - pos, 0); | ||
| 857 | pos += strlen(buf + pos); | ||
| 858 | if (bufsz - pos > 0) | ||
| 859 | buf[pos++] = '\n'; | ||
| 860 | } | ||
| 861 | } | ||
| 862 | } | ||
| 863 | |||
| 864 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | ||
| 865 | kfree(buf); | ||
| 866 | return ret; | ||
| 867 | } | ||
| 868 | |||
| 869 | static ssize_t iwl_dbgfs_traffic_log_write(struct file *file, | ||
| 870 | const char __user *user_buf, | ||
| 871 | size_t count, loff_t *ppos) | ||
| 872 | { | ||
| 873 | struct iwl_priv *priv = file->private_data; | ||
| 874 | char buf[8]; | ||
| 875 | int buf_size; | ||
| 876 | int traffic_log; | ||
| 877 | |||
| 878 | memset(buf, 0, sizeof(buf)); | ||
| 879 | buf_size = min(count, sizeof(buf) - 1); | ||
| 880 | if (copy_from_user(buf, user_buf, buf_size)) | ||
| 881 | return -EFAULT; | ||
| 882 | if (sscanf(buf, "%d", &traffic_log) != 1) | ||
| 883 | return -EFAULT; | ||
| 884 | if (traffic_log == 0) | ||
| 885 | iwl_reset_traffic_log(priv); | ||
| 886 | |||
| 887 | return count; | ||
| 888 | } | ||
| 889 | |||
| 807 | static const char *fmt_value = " %-30s %10u\n"; | 890 | static const char *fmt_value = " %-30s %10u\n"; |
| 808 | static const char *fmt_hex = " %-30s 0x%02X\n"; | 891 | static const char *fmt_hex = " %-30s 0x%02X\n"; |
| 809 | static const char *fmt_table = " %-30s %10u %10u %10u %10u\n"; | 892 | static const char *fmt_table = " %-30s %10u %10u %10u %10u\n"; |
| @@ -2340,6 +2423,7 @@ static ssize_t iwl_dbgfs_protection_mode_write(struct file *file, | |||
| 2340 | 2423 | ||
| 2341 | DEBUGFS_READ_FILE_OPS(rx_statistics); | 2424 | DEBUGFS_READ_FILE_OPS(rx_statistics); |
| 2342 | DEBUGFS_READ_FILE_OPS(tx_statistics); | 2425 | DEBUGFS_READ_FILE_OPS(tx_statistics); |
| 2426 | DEBUGFS_READ_WRITE_FILE_OPS(traffic_log); | ||
| 2343 | DEBUGFS_READ_FILE_OPS(ucode_rx_stats); | 2427 | DEBUGFS_READ_FILE_OPS(ucode_rx_stats); |
| 2344 | DEBUGFS_READ_FILE_OPS(ucode_tx_stats); | 2428 | DEBUGFS_READ_FILE_OPS(ucode_tx_stats); |
| 2345 | DEBUGFS_READ_FILE_OPS(ucode_general_stats); | 2429 | DEBUGFS_READ_FILE_OPS(ucode_general_stats); |
| @@ -2400,6 +2484,7 @@ int iwl_dbgfs_register(struct iwl_priv *priv, const char *name) | |||
| 2400 | DEBUGFS_ADD_FILE(disable_ht40, dir_data, S_IWUSR | S_IRUSR); | 2484 | DEBUGFS_ADD_FILE(disable_ht40, dir_data, S_IWUSR | S_IRUSR); |
| 2401 | DEBUGFS_ADD_FILE(rx_statistics, dir_debug, S_IRUSR); | 2485 | DEBUGFS_ADD_FILE(rx_statistics, dir_debug, S_IRUSR); |
| 2402 | DEBUGFS_ADD_FILE(tx_statistics, dir_debug, S_IRUSR); | 2486 | DEBUGFS_ADD_FILE(tx_statistics, dir_debug, S_IRUSR); |
| 2487 | DEBUGFS_ADD_FILE(traffic_log, dir_debug, S_IWUSR | S_IRUSR); | ||
| 2403 | DEBUGFS_ADD_FILE(power_save_status, dir_debug, S_IRUSR); | 2488 | DEBUGFS_ADD_FILE(power_save_status, dir_debug, S_IRUSR); |
| 2404 | DEBUGFS_ADD_FILE(clear_ucode_statistics, dir_debug, S_IWUSR); | 2489 | DEBUGFS_ADD_FILE(clear_ucode_statistics, dir_debug, S_IWUSR); |
| 2405 | DEBUGFS_ADD_FILE(clear_traffic_statistics, dir_debug, S_IWUSR); | 2490 | DEBUGFS_ADD_FILE(clear_traffic_statistics, dir_debug, S_IWUSR); |
diff --git a/drivers/net/wireless/iwlwifi/iwl-dev.h b/drivers/net/wireless/iwlwifi/iwl-dev.h index 1e54293532b0..8438a33e17ee 100644 --- a/drivers/net/wireless/iwlwifi/iwl-dev.h +++ b/drivers/net/wireless/iwlwifi/iwl-dev.h | |||
| @@ -32,7 +32,6 @@ | |||
| 32 | #define __iwl_dev_h__ | 32 | #define __iwl_dev_h__ |
| 33 | 33 | ||
| 34 | #include <linux/interrupt.h> | 34 | #include <linux/interrupt.h> |
| 35 | #include <linux/pci.h> /* for struct pci_device_id */ | ||
| 36 | #include <linux/kernel.h> | 35 | #include <linux/kernel.h> |
| 37 | #include <linux/wait.h> | 36 | #include <linux/wait.h> |
| 38 | #include <linux/leds.h> | 37 | #include <linux/leds.h> |
| @@ -89,100 +88,6 @@ struct iwl_tx_queue; | |||
| 89 | #define DEFAULT_SHORT_RETRY_LIMIT 7U | 88 | #define DEFAULT_SHORT_RETRY_LIMIT 7U |
| 90 | #define DEFAULT_LONG_RETRY_LIMIT 4U | 89 | #define DEFAULT_LONG_RETRY_LIMIT 4U |
| 91 | 90 | ||
| 92 | /* defined below */ | ||
| 93 | struct iwl_device_cmd; | ||
| 94 | |||
| 95 | struct iwl_cmd_meta { | ||
| 96 | /* only for SYNC commands, iff the reply skb is wanted */ | ||
| 97 | struct iwl_host_cmd *source; | ||
| 98 | /* | ||
| 99 | * only for ASYNC commands | ||
| 100 | * (which is somewhat stupid -- look at iwl-sta.c for instance | ||
| 101 | * which duplicates a bunch of code because the callback isn't | ||
| 102 | * invoked for SYNC commands, if it were and its result passed | ||
| 103 | * through it would be simpler...) | ||
| 104 | */ | ||
| 105 | void (*callback)(struct iwl_priv *priv, | ||
| 106 | struct iwl_device_cmd *cmd, | ||
| 107 | struct iwl_rx_packet *pkt); | ||
| 108 | |||
| 109 | u32 flags; | ||
| 110 | |||
| 111 | DEFINE_DMA_UNMAP_ADDR(mapping); | ||
| 112 | DEFINE_DMA_UNMAP_LEN(len); | ||
| 113 | }; | ||
| 114 | |||
| 115 | /* | ||
| 116 | * Generic queue structure | ||
| 117 | * | ||
| 118 | * Contains common data for Rx and Tx queues. | ||
| 119 | * | ||
| 120 | * Note the difference between n_bd and n_window: the hardware | ||
| 121 | * always assumes 256 descriptors, so n_bd is always 256 (unless | ||
| 122 | * there might be HW changes in the future). For the normal TX | ||
| 123 | * queues, n_window, which is the size of the software queue data | ||
| 124 | * is also 256; however, for the command queue, n_window is only | ||
| 125 | * 32 since we don't need so many commands pending. Since the HW | ||
| 126 | * still uses 256 BDs for DMA though, n_bd stays 256. As a result, | ||
| 127 | * the software buffers (in the variables @meta, @txb in struct | ||
| 128 | * iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds | ||
| 129 | * in the same struct) have 256. | ||
| 130 | * This means that we end up with the following: | ||
| 131 | * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | | ||
| 132 | * SW entries: | 0 | ... | 31 | | ||
| 133 | * where N is a number between 0 and 7. This means that the SW | ||
| 134 | * data is a window overlayed over the HW queue. | ||
| 135 | */ | ||
| 136 | struct iwl_queue { | ||
| 137 | int n_bd; /* number of BDs in this queue */ | ||
| 138 | int write_ptr; /* 1-st empty entry (index) host_w*/ | ||
| 139 | int read_ptr; /* last used entry (index) host_r*/ | ||
| 140 | /* use for monitoring and recovering the stuck queue */ | ||
| 141 | dma_addr_t dma_addr; /* physical addr for BD's */ | ||
| 142 | int n_window; /* safe queue window */ | ||
| 143 | u32 id; | ||
| 144 | int low_mark; /* low watermark, resume queue if free | ||
| 145 | * space more than this */ | ||
| 146 | int high_mark; /* high watermark, stop queue if free | ||
| 147 | * space less than this */ | ||
| 148 | }; | ||
| 149 | |||
| 150 | /** | ||
| 151 | * struct iwl_tx_queue - Tx Queue for DMA | ||
| 152 | * @q: generic Rx/Tx queue descriptor | ||
| 153 | * @bd: base of circular buffer of TFDs | ||
| 154 | * @cmd: array of command/TX buffer pointers | ||
| 155 | * @meta: array of meta data for each command/tx buffer | ||
| 156 | * @dma_addr_cmd: physical address of cmd/tx buffer array | ||
| 157 | * @txb: array of per-TFD driver data | ||
| 158 | * @time_stamp: time (in jiffies) of last read_ptr change | ||
| 159 | * @need_update: indicates need to update read/write index | ||
| 160 | * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled | ||
| 161 | * @sta_id: valid if sched_retry is set | ||
| 162 | * @tid: valid if sched_retry is set | ||
| 163 | * | ||
| 164 | * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame | ||
| 165 | * descriptors) and required locking structures. | ||
| 166 | */ | ||
| 167 | #define TFD_TX_CMD_SLOTS 256 | ||
| 168 | #define TFD_CMD_SLOTS 32 | ||
| 169 | |||
| 170 | struct iwl_tx_queue { | ||
| 171 | struct iwl_queue q; | ||
| 172 | struct iwl_tfd *tfds; | ||
| 173 | struct iwl_device_cmd **cmd; | ||
| 174 | struct iwl_cmd_meta *meta; | ||
| 175 | struct sk_buff **skbs; | ||
| 176 | unsigned long time_stamp; | ||
| 177 | u8 need_update; | ||
| 178 | u8 sched_retry; | ||
| 179 | u8 active; | ||
| 180 | u8 swq_id; | ||
| 181 | |||
| 182 | u16 sta_id; | ||
| 183 | u16 tid; | ||
| 184 | }; | ||
| 185 | |||
| 186 | #define IWL_NUM_SCAN_RATES (2) | 91 | #define IWL_NUM_SCAN_RATES (2) |
| 187 | 92 | ||
| 188 | /* | 93 | /* |
| @@ -212,21 +117,6 @@ struct iwl_channel_info { | |||
| 212 | u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */ | 117 | u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */ |
| 213 | }; | 118 | }; |
| 214 | 119 | ||
| 215 | #define IWL_TX_FIFO_BK 0 /* shared */ | ||
| 216 | #define IWL_TX_FIFO_BE 1 | ||
| 217 | #define IWL_TX_FIFO_VI 2 /* shared */ | ||
| 218 | #define IWL_TX_FIFO_VO 3 | ||
| 219 | #define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK | ||
| 220 | #define IWL_TX_FIFO_BE_IPAN 4 | ||
| 221 | #define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI | ||
| 222 | #define IWL_TX_FIFO_VO_IPAN 5 | ||
| 223 | /* re-uses the VO FIFO, uCode will properly flush/schedule */ | ||
| 224 | #define IWL_TX_FIFO_AUX 5 | ||
| 225 | #define IWL_TX_FIFO_UNUSED -1 | ||
| 226 | |||
| 227 | /* AUX (TX during scan dwell) queue */ | ||
| 228 | #define IWL_AUX_QUEUE 10 | ||
| 229 | |||
| 230 | /* | 120 | /* |
| 231 | * Minimum number of queues. MAX_NUM is defined in hw specific files. | 121 | * Minimum number of queues. MAX_NUM is defined in hw specific files. |
| 232 | * Set the minimum to accommodate | 122 | * Set the minimum to accommodate |
| @@ -249,70 +139,6 @@ struct iwl_channel_info { | |||
| 249 | #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) | 139 | #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) |
| 250 | #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) | 140 | #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) |
| 251 | 141 | ||
| 252 | |||
| 253 | #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) | ||
| 254 | #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ) | ||
| 255 | #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4) | ||
| 256 | |||
| 257 | enum { | ||
| 258 | CMD_SYNC = 0, | ||
| 259 | CMD_ASYNC = BIT(0), | ||
| 260 | CMD_WANT_SKB = BIT(1), | ||
| 261 | CMD_ON_DEMAND = BIT(2), | ||
| 262 | }; | ||
| 263 | |||
| 264 | #define DEF_CMD_PAYLOAD_SIZE 320 | ||
| 265 | |||
| 266 | /** | ||
| 267 | * struct iwl_device_cmd | ||
| 268 | * | ||
| 269 | * For allocation of the command and tx queues, this establishes the overall | ||
| 270 | * size of the largest command we send to uCode, except for commands that | ||
| 271 | * aren't fully copied and use other TFD space. | ||
| 272 | */ | ||
| 273 | struct iwl_device_cmd { | ||
| 274 | struct iwl_cmd_header hdr; /* uCode API */ | ||
| 275 | union { | ||
| 276 | u32 flags; | ||
| 277 | u8 val8; | ||
| 278 | u16 val16; | ||
| 279 | u32 val32; | ||
| 280 | struct iwl_tx_cmd tx; | ||
| 281 | struct iwl6000_channel_switch_cmd chswitch; | ||
| 282 | u8 payload[DEF_CMD_PAYLOAD_SIZE]; | ||
| 283 | } __packed cmd; | ||
| 284 | } __packed; | ||
| 285 | |||
| 286 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) | ||
| 287 | |||
| 288 | #define IWL_MAX_CMD_TFDS 2 | ||
| 289 | |||
| 290 | enum iwl_hcmd_dataflag { | ||
| 291 | IWL_HCMD_DFL_NOCOPY = BIT(0), | ||
| 292 | }; | ||
| 293 | |||
| 294 | /** | ||
| 295 | * struct iwl_host_cmd - Host command to the uCode | ||
| 296 | * @data: array of chunks that composes the data of the host command | ||
| 297 | * @reply_page: pointer to the page that holds the response to the host command | ||
| 298 | * @callback: | ||
| 299 | * @flags: can be CMD_* note CMD_WANT_SKB is incompatible withe CMD_ASYNC | ||
| 300 | * @len: array of the lenths of the chunks in data | ||
| 301 | * @dataflags: | ||
| 302 | * @id: id of the host command | ||
| 303 | */ | ||
| 304 | struct iwl_host_cmd { | ||
| 305 | const void *data[IWL_MAX_CMD_TFDS]; | ||
| 306 | unsigned long reply_page; | ||
| 307 | void (*callback)(struct iwl_priv *priv, | ||
| 308 | struct iwl_device_cmd *cmd, | ||
| 309 | struct iwl_rx_packet *pkt); | ||
| 310 | u32 flags; | ||
| 311 | u16 len[IWL_MAX_CMD_TFDS]; | ||
| 312 | u8 dataflags[IWL_MAX_CMD_TFDS]; | ||
| 313 | u8 id; | ||
| 314 | }; | ||
| 315 | |||
| 316 | #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 | 142 | #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 |
| 317 | #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 | 143 | #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 |
| 318 | #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 | 144 | #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 |
| @@ -580,9 +406,6 @@ extern const u8 iwl_bcast_addr[ETH_ALEN]; | |||
| 580 | #define IWL_OPERATION_MODE_MIXED 2 | 406 | #define IWL_OPERATION_MODE_MIXED 2 |
| 581 | #define IWL_OPERATION_MODE_20MHZ 3 | 407 | #define IWL_OPERATION_MODE_20MHZ 3 |
| 582 | 408 | ||
| 583 | #define IWL_TX_CRC_SIZE 4 | ||
| 584 | #define IWL_TX_DELIMITER_SIZE 4 | ||
| 585 | |||
| 586 | #define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000 | 409 | #define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000 |
| 587 | 410 | ||
| 588 | /* Sensitivity and chain noise calibration */ | 411 | /* Sensitivity and chain noise calibration */ |
| @@ -706,9 +529,6 @@ struct iwl_chain_noise_data { | |||
| 706 | #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */ | 529 | #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */ |
| 707 | #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ | 530 | #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ |
| 708 | 531 | ||
| 709 | #define IWL_TRAFFIC_ENTRIES (256) | ||
| 710 | #define IWL_TRAFFIC_ENTRY_SIZE (64) | ||
| 711 | |||
| 712 | enum { | 532 | enum { |
| 713 | MEASUREMENT_READY = (1 << 0), | 533 | MEASUREMENT_READY = (1 << 0), |
| 714 | MEASUREMENT_ACTIVE = (1 << 1), | 534 | MEASUREMENT_ACTIVE = (1 << 1), |
| @@ -850,21 +670,6 @@ struct iwl_event_log { | |||
| 850 | }; | 670 | }; |
| 851 | 671 | ||
| 852 | /* | 672 | /* |
| 853 | * host interrupt timeout value | ||
| 854 | * used with setting interrupt coalescing timer | ||
| 855 | * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit | ||
| 856 | * | ||
| 857 | * default interrupt coalescing timer is 64 x 32 = 2048 usecs | ||
| 858 | * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs | ||
| 859 | */ | ||
| 860 | #define IWL_HOST_INT_TIMEOUT_MAX (0xFF) | ||
| 861 | #define IWL_HOST_INT_TIMEOUT_DEF (0x40) | ||
| 862 | #define IWL_HOST_INT_TIMEOUT_MIN (0x0) | ||
| 863 | #define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF) | ||
| 864 | #define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10) | ||
| 865 | #define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0) | ||
| 866 | |||
| 867 | /* | ||
| 868 | * This is the threshold value of plcp error rate per 100mSecs. It is | 673 | * This is the threshold value of plcp error rate per 100mSecs. It is |
| 869 | * used to set and check for the validity of plcp_delta. | 674 | * used to set and check for the validity of plcp_delta. |
| 870 | */ | 675 | */ |
| @@ -1095,9 +900,6 @@ struct iwl_priv { | |||
| 1095 | /*TODO: remove these pointers - use bus(priv) instead */ | 900 | /*TODO: remove these pointers - use bus(priv) instead */ |
| 1096 | struct iwl_bus *bus; /* bus specific data */ | 901 | struct iwl_bus *bus; /* bus specific data */ |
| 1097 | 902 | ||
| 1098 | /* microcode/device supports multiple contexts */ | ||
| 1099 | u8 valid_contexts; | ||
| 1100 | |||
| 1101 | /* max number of station keys */ | 903 | /* max number of station keys */ |
| 1102 | u8 sta_key_max_num; | 904 | u8 sta_key_max_num; |
| 1103 | 905 | ||
| @@ -1142,8 +944,6 @@ struct iwl_priv { | |||
| 1142 | /* Rate scaling data */ | 944 | /* Rate scaling data */ |
| 1143 | u8 retry_rate; | 945 | u8 retry_rate; |
| 1144 | 946 | ||
| 1145 | wait_queue_head_t wait_command_queue; | ||
| 1146 | |||
| 1147 | int activity_timer_active; | 947 | int activity_timer_active; |
| 1148 | 948 | ||
| 1149 | /* counts mgmt, ctl, and data packets */ | 949 | /* counts mgmt, ctl, and data packets */ |
| @@ -1327,7 +1127,7 @@ iwl_rxon_ctx_from_vif(struct ieee80211_vif *vif) | |||
| 1327 | #define for_each_context(priv, ctx) \ | 1127 | #define for_each_context(priv, ctx) \ |
| 1328 | for (ctx = &priv->contexts[IWL_RXON_CTX_BSS]; \ | 1128 | for (ctx = &priv->contexts[IWL_RXON_CTX_BSS]; \ |
| 1329 | ctx < &priv->contexts[NUM_IWL_RXON_CTX]; ctx++) \ | 1129 | ctx < &priv->contexts[NUM_IWL_RXON_CTX]; ctx++) \ |
| 1330 | if (priv->valid_contexts & BIT(ctx->ctxid)) | 1130 | if (priv->shrd->valid_contexts & BIT(ctx->ctxid)) |
| 1331 | 1131 | ||
| 1332 | static inline int iwl_is_associated_ctx(struct iwl_rxon_context *ctx) | 1132 | static inline int iwl_is_associated_ctx(struct iwl_rxon_context *ctx) |
| 1333 | { | 1133 | { |
diff --git a/drivers/net/wireless/iwlwifi/iwl-helpers.h b/drivers/net/wireless/iwlwifi/iwl-helpers.h index d3feac9e45b4..968fc66e3506 100644 --- a/drivers/net/wireless/iwlwifi/iwl-helpers.h +++ b/drivers/net/wireless/iwlwifi/iwl-helpers.h | |||
| @@ -35,35 +35,12 @@ | |||
| 35 | 35 | ||
| 36 | #include "iwl-io.h" | 36 | #include "iwl-io.h" |
| 37 | 37 | ||
| 38 | #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) | ||
| 39 | |||
| 40 | |||
| 41 | static inline struct ieee80211_conf *ieee80211_get_hw_conf( | 38 | static inline struct ieee80211_conf *ieee80211_get_hw_conf( |
| 42 | struct ieee80211_hw *hw) | 39 | struct ieee80211_hw *hw) |
| 43 | { | 40 | { |
| 44 | return &hw->conf; | 41 | return &hw->conf; |
| 45 | } | 42 | } |
| 46 | 43 | ||
| 47 | /** | ||
| 48 | * iwl_queue_inc_wrap - increment queue index, wrap back to beginning | ||
| 49 | * @index -- current index | ||
| 50 | * @n_bd -- total number of entries in queue (must be power of 2) | ||
| 51 | */ | ||
| 52 | static inline int iwl_queue_inc_wrap(int index, int n_bd) | ||
| 53 | { | ||
| 54 | return ++index & (n_bd - 1); | ||
| 55 | } | ||
| 56 | |||
| 57 | /** | ||
| 58 | * iwl_queue_dec_wrap - decrement queue index, wrap back to end | ||
| 59 | * @index -- current index | ||
| 60 | * @n_bd -- total number of entries in queue (must be power of 2) | ||
| 61 | */ | ||
| 62 | static inline int iwl_queue_dec_wrap(int index, int n_bd) | ||
| 63 | { | ||
| 64 | return --index & (n_bd - 1); | ||
| 65 | } | ||
| 66 | |||
| 67 | static inline void iwl_enable_rfkill_int(struct iwl_priv *priv) | 44 | static inline void iwl_enable_rfkill_int(struct iwl_priv *priv) |
| 68 | { | 45 | { |
| 69 | IWL_DEBUG_ISR(priv, "Enabling rfkill interrupt\n"); | 46 | IWL_DEBUG_ISR(priv, "Enabling rfkill interrupt\n"); |
diff --git a/drivers/net/wireless/iwlwifi/iwl-pci.c b/drivers/net/wireless/iwlwifi/iwl-pci.c index e41f53e5c307..78a3f8dfe680 100644 --- a/drivers/net/wireless/iwlwifi/iwl-pci.c +++ b/drivers/net/wireless/iwlwifi/iwl-pci.c | |||
| @@ -483,9 +483,13 @@ out_no_pci: | |||
| 483 | return err; | 483 | return err; |
| 484 | } | 484 | } |
| 485 | 485 | ||
| 486 | static void iwl_pci_down(struct iwl_bus *bus) | 486 | static void __devexit iwl_pci_remove(struct pci_dev *pdev) |
| 487 | { | 487 | { |
| 488 | struct iwl_pci_bus *pci_bus = (struct iwl_pci_bus *) bus->bus_specific; | 488 | struct iwl_shared *shrd = pci_get_drvdata(pdev); |
| 489 | struct iwl_bus *bus = shrd->bus; | ||
| 490 | struct iwl_pci_bus *pci_bus = IWL_BUS_GET_PCI_BUS(bus); | ||
| 491 | |||
| 492 | iwl_remove(shrd->priv); | ||
| 489 | 493 | ||
| 490 | pci_disable_msi(pci_bus->pci_dev); | 494 | pci_disable_msi(pci_bus->pci_dev); |
| 491 | pci_iounmap(pci_bus->pci_dev, pci_bus->hw_base); | 495 | pci_iounmap(pci_bus->pci_dev, pci_bus->hw_base); |
| @@ -496,16 +500,6 @@ static void iwl_pci_down(struct iwl_bus *bus) | |||
| 496 | kfree(bus); | 500 | kfree(bus); |
| 497 | } | 501 | } |
| 498 | 502 | ||
| 499 | static void __devexit iwl_pci_remove(struct pci_dev *pdev) | ||
| 500 | { | ||
| 501 | struct iwl_shared *shrd = pci_get_drvdata(pdev); | ||
| 502 | struct iwl_bus *bus = shrd->bus; | ||
| 503 | |||
| 504 | iwl_remove(shrd->priv); | ||
| 505 | |||
| 506 | iwl_pci_down(bus); | ||
| 507 | } | ||
| 508 | |||
| 509 | #ifdef CONFIG_PM_SLEEP | 503 | #ifdef CONFIG_PM_SLEEP |
| 510 | 504 | ||
| 511 | static int iwl_pci_suspend(struct device *device) | 505 | static int iwl_pci_suspend(struct device *device) |
diff --git a/drivers/net/wireless/iwlwifi/iwl-rx.c b/drivers/net/wireless/iwlwifi/iwl-rx.c index 8572548dd4a2..c7e6a746c3ea 100644 --- a/drivers/net/wireless/iwlwifi/iwl-rx.c +++ b/drivers/net/wireless/iwlwifi/iwl-rx.c | |||
| @@ -42,6 +42,87 @@ | |||
| 42 | #include "iwl-agn.h" | 42 | #include "iwl-agn.h" |
| 43 | #include "iwl-shared.h" | 43 | #include "iwl-shared.h" |
| 44 | 44 | ||
| 45 | const char *get_cmd_string(u8 cmd) | ||
| 46 | { | ||
| 47 | switch (cmd) { | ||
| 48 | IWL_CMD(REPLY_ALIVE); | ||
| 49 | IWL_CMD(REPLY_ERROR); | ||
| 50 | IWL_CMD(REPLY_RXON); | ||
| 51 | IWL_CMD(REPLY_RXON_ASSOC); | ||
| 52 | IWL_CMD(REPLY_QOS_PARAM); | ||
| 53 | IWL_CMD(REPLY_RXON_TIMING); | ||
| 54 | IWL_CMD(REPLY_ADD_STA); | ||
| 55 | IWL_CMD(REPLY_REMOVE_STA); | ||
| 56 | IWL_CMD(REPLY_REMOVE_ALL_STA); | ||
| 57 | IWL_CMD(REPLY_TXFIFO_FLUSH); | ||
| 58 | IWL_CMD(REPLY_WEPKEY); | ||
| 59 | IWL_CMD(REPLY_TX); | ||
| 60 | IWL_CMD(REPLY_LEDS_CMD); | ||
| 61 | IWL_CMD(REPLY_TX_LINK_QUALITY_CMD); | ||
| 62 | IWL_CMD(COEX_PRIORITY_TABLE_CMD); | ||
| 63 | IWL_CMD(COEX_MEDIUM_NOTIFICATION); | ||
| 64 | IWL_CMD(COEX_EVENT_CMD); | ||
| 65 | IWL_CMD(REPLY_QUIET_CMD); | ||
| 66 | IWL_CMD(REPLY_CHANNEL_SWITCH); | ||
| 67 | IWL_CMD(CHANNEL_SWITCH_NOTIFICATION); | ||
| 68 | IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD); | ||
| 69 | IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION); | ||
| 70 | IWL_CMD(POWER_TABLE_CMD); | ||
| 71 | IWL_CMD(PM_SLEEP_NOTIFICATION); | ||
| 72 | IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC); | ||
| 73 | IWL_CMD(REPLY_SCAN_CMD); | ||
| 74 | IWL_CMD(REPLY_SCAN_ABORT_CMD); | ||
| 75 | IWL_CMD(SCAN_START_NOTIFICATION); | ||
| 76 | IWL_CMD(SCAN_RESULTS_NOTIFICATION); | ||
| 77 | IWL_CMD(SCAN_COMPLETE_NOTIFICATION); | ||
| 78 | IWL_CMD(BEACON_NOTIFICATION); | ||
| 79 | IWL_CMD(REPLY_TX_BEACON); | ||
| 80 | IWL_CMD(WHO_IS_AWAKE_NOTIFICATION); | ||
| 81 | IWL_CMD(QUIET_NOTIFICATION); | ||
| 82 | IWL_CMD(REPLY_TX_PWR_TABLE_CMD); | ||
| 83 | IWL_CMD(MEASURE_ABORT_NOTIFICATION); | ||
| 84 | IWL_CMD(REPLY_BT_CONFIG); | ||
| 85 | IWL_CMD(REPLY_STATISTICS_CMD); | ||
| 86 | IWL_CMD(STATISTICS_NOTIFICATION); | ||
| 87 | IWL_CMD(REPLY_CARD_STATE_CMD); | ||
| 88 | IWL_CMD(CARD_STATE_NOTIFICATION); | ||
| 89 | IWL_CMD(MISSED_BEACONS_NOTIFICATION); | ||
| 90 | IWL_CMD(REPLY_CT_KILL_CONFIG_CMD); | ||
| 91 | IWL_CMD(SENSITIVITY_CMD); | ||
| 92 | IWL_CMD(REPLY_PHY_CALIBRATION_CMD); | ||
| 93 | IWL_CMD(REPLY_RX_PHY_CMD); | ||
| 94 | IWL_CMD(REPLY_RX_MPDU_CMD); | ||
| 95 | IWL_CMD(REPLY_RX); | ||
| 96 | IWL_CMD(REPLY_COMPRESSED_BA); | ||
| 97 | IWL_CMD(CALIBRATION_CFG_CMD); | ||
| 98 | IWL_CMD(CALIBRATION_RES_NOTIFICATION); | ||
| 99 | IWL_CMD(CALIBRATION_COMPLETE_NOTIFICATION); | ||
| 100 | IWL_CMD(REPLY_TX_POWER_DBM_CMD); | ||
| 101 | IWL_CMD(TEMPERATURE_NOTIFICATION); | ||
| 102 | IWL_CMD(TX_ANT_CONFIGURATION_CMD); | ||
| 103 | IWL_CMD(REPLY_BT_COEX_PROFILE_NOTIF); | ||
| 104 | IWL_CMD(REPLY_BT_COEX_PRIO_TABLE); | ||
| 105 | IWL_CMD(REPLY_BT_COEX_PROT_ENV); | ||
| 106 | IWL_CMD(REPLY_WIPAN_PARAMS); | ||
| 107 | IWL_CMD(REPLY_WIPAN_RXON); | ||
| 108 | IWL_CMD(REPLY_WIPAN_RXON_TIMING); | ||
| 109 | IWL_CMD(REPLY_WIPAN_RXON_ASSOC); | ||
| 110 | IWL_CMD(REPLY_WIPAN_QOS_PARAM); | ||
| 111 | IWL_CMD(REPLY_WIPAN_WEPKEY); | ||
| 112 | IWL_CMD(REPLY_WIPAN_P2P_CHANNEL_SWITCH); | ||
| 113 | IWL_CMD(REPLY_WIPAN_NOA_NOTIFICATION); | ||
| 114 | IWL_CMD(REPLY_WIPAN_DEACTIVATION_COMPLETE); | ||
| 115 | IWL_CMD(REPLY_WOWLAN_PATTERNS); | ||
| 116 | IWL_CMD(REPLY_WOWLAN_WAKEUP_FILTER); | ||
| 117 | IWL_CMD(REPLY_WOWLAN_TSC_RSC_PARAMS); | ||
| 118 | IWL_CMD(REPLY_WOWLAN_TKIP_PARAMS); | ||
| 119 | IWL_CMD(REPLY_WOWLAN_KEK_KCK_MATERIAL); | ||
| 120 | IWL_CMD(REPLY_WOWLAN_GET_STATUS); | ||
| 121 | default: | ||
| 122 | return "UNKNOWN"; | ||
| 123 | |||
| 124 | } | ||
| 125 | } | ||
| 45 | 126 | ||
| 46 | /****************************************************************************** | 127 | /****************************************************************************** |
| 47 | * | 128 | * |
| @@ -563,7 +644,7 @@ static void iwl_rx_card_state_notif(struct iwl_priv *priv, | |||
| 563 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, | 644 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, |
| 564 | test_bit(STATUS_RF_KILL_HW, &priv->shrd->status)); | 645 | test_bit(STATUS_RF_KILL_HW, &priv->shrd->status)); |
| 565 | else | 646 | else |
| 566 | wake_up_interruptible(&priv->wait_command_queue); | 647 | wake_up_interruptible(&priv->shrd->wait_command_queue); |
| 567 | } | 648 | } |
| 568 | 649 | ||
| 569 | static void iwl_rx_missed_beacon_notif(struct iwl_priv *priv, | 650 | static void iwl_rx_missed_beacon_notif(struct iwl_priv *priv, |
diff --git a/drivers/net/wireless/iwlwifi/iwl-shared.h b/drivers/net/wireless/iwlwifi/iwl-shared.h index 8b8cd54a32e0..d987bee5e6ce 100644 --- a/drivers/net/wireless/iwlwifi/iwl-shared.h +++ b/drivers/net/wireless/iwlwifi/iwl-shared.h | |||
| @@ -67,6 +67,7 @@ | |||
| 67 | #include <linux/spinlock.h> | 67 | #include <linux/spinlock.h> |
| 68 | #include <linux/mutex.h> | 68 | #include <linux/mutex.h> |
| 69 | #include <linux/gfp.h> | 69 | #include <linux/gfp.h> |
| 70 | #include <linux/mm.h> /* for page_address */ | ||
| 70 | #include <net/mac80211.h> | 71 | #include <net/mac80211.h> |
| 71 | 72 | ||
| 72 | #include "iwl-commands.h" | 73 | #include "iwl-commands.h" |
| @@ -212,6 +213,7 @@ struct iwl_tid_data { | |||
| 212 | * @ucode_owner: IWL_OWNERSHIP_* | 213 | * @ucode_owner: IWL_OWNERSHIP_* |
| 213 | * @cmd_queue: command queue number | 214 | * @cmd_queue: command queue number |
| 214 | * @status: STATUS_* | 215 | * @status: STATUS_* |
| 216 | * @valid_contexts: microcode/device supports multiple contexts | ||
| 215 | * @bus: pointer to the bus layer data | 217 | * @bus: pointer to the bus layer data |
| 216 | * @priv: pointer to the upper layer data | 218 | * @priv: pointer to the upper layer data |
| 217 | * @hw_params: see struct iwl_hw_params | 219 | * @hw_params: see struct iwl_hw_params |
| @@ -232,6 +234,7 @@ struct iwl_shared { | |||
| 232 | u8 cmd_queue; | 234 | u8 cmd_queue; |
| 233 | unsigned long status; | 235 | unsigned long status; |
| 234 | bool wowlan; | 236 | bool wowlan; |
| 237 | u8 valid_contexts; | ||
| 235 | 238 | ||
| 236 | struct iwl_bus *bus; | 239 | struct iwl_bus *bus; |
| 237 | struct iwl_priv *priv; | 240 | struct iwl_priv *priv; |
| @@ -250,6 +253,8 @@ struct iwl_shared { | |||
| 250 | struct ieee80211_hw *hw; | 253 | struct ieee80211_hw *hw; |
| 251 | 254 | ||
| 252 | struct iwl_tid_data tid_data[IWLAGN_STATION_COUNT][IWL_MAX_TID_COUNT]; | 255 | struct iwl_tid_data tid_data[IWLAGN_STATION_COUNT][IWL_MAX_TID_COUNT]; |
| 256 | |||
| 257 | wait_queue_head_t wait_command_queue; | ||
| 253 | }; | 258 | }; |
| 254 | 259 | ||
| 255 | /*Whatever _m is (iwl_trans, iwl_priv, iwl_bus, these macros will work */ | 260 | /*Whatever _m is (iwl_trans, iwl_priv, iwl_bus, these macros will work */ |
| @@ -285,6 +290,26 @@ static inline void iwl_free_pages(struct iwl_shared *shrd, unsigned long page) | |||
| 285 | free_pages(page, shrd->hw_params.rx_page_order); | 290 | free_pages(page, shrd->hw_params.rx_page_order); |
| 286 | } | 291 | } |
| 287 | 292 | ||
| 293 | /** | ||
| 294 | * iwl_queue_inc_wrap - increment queue index, wrap back to beginning | ||
| 295 | * @index -- current index | ||
| 296 | * @n_bd -- total number of entries in queue (must be power of 2) | ||
| 297 | */ | ||
| 298 | static inline int iwl_queue_inc_wrap(int index, int n_bd) | ||
| 299 | { | ||
| 300 | return ++index & (n_bd - 1); | ||
| 301 | } | ||
| 302 | |||
| 303 | /** | ||
| 304 | * iwl_queue_dec_wrap - decrement queue index, wrap back to end | ||
| 305 | * @index -- current index | ||
| 306 | * @n_bd -- total number of entries in queue (must be power of 2) | ||
| 307 | */ | ||
| 308 | static inline int iwl_queue_dec_wrap(int index, int n_bd) | ||
| 309 | { | ||
| 310 | return --index & (n_bd - 1); | ||
| 311 | } | ||
| 312 | |||
| 288 | struct iwl_rx_mem_buffer { | 313 | struct iwl_rx_mem_buffer { |
| 289 | dma_addr_t page_dma; | 314 | dma_addr_t page_dma; |
| 290 | struct page *page; | 315 | struct page *page; |
| @@ -355,12 +380,39 @@ int iwl_probe(struct iwl_bus *bus, const struct iwl_trans_ops *trans_ops, | |||
| 355 | struct iwl_cfg *cfg); | 380 | struct iwl_cfg *cfg); |
| 356 | void __devexit iwl_remove(struct iwl_priv * priv); | 381 | void __devexit iwl_remove(struct iwl_priv * priv); |
| 357 | 382 | ||
| 383 | void iwl_rx_dispatch(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb); | ||
| 384 | int iwlagn_hw_valid_rtc_data_addr(u32 addr); | ||
| 358 | void iwl_start_tx_ba_trans_ready(struct iwl_priv *priv, | 385 | void iwl_start_tx_ba_trans_ready(struct iwl_priv *priv, |
| 359 | enum iwl_rxon_context_id ctx, | 386 | enum iwl_rxon_context_id ctx, |
| 360 | u8 sta_id, u8 tid); | 387 | u8 sta_id, u8 tid); |
| 361 | void iwl_stop_tx_ba_trans_ready(struct iwl_priv *priv, | 388 | void iwl_stop_tx_ba_trans_ready(struct iwl_priv *priv, |
| 362 | enum iwl_rxon_context_id ctx, | 389 | enum iwl_rxon_context_id ctx, |
| 363 | u8 sta_id, u8 tid); | 390 | u8 sta_id, u8 tid); |
| 391 | void iwl_set_hw_rfkill_state(struct iwl_priv *priv, bool state); | ||
| 392 | void iwl_nic_config(struct iwl_priv *priv); | ||
| 393 | void iwl_apm_stop(struct iwl_priv *priv); | ||
| 394 | int iwl_apm_init(struct iwl_priv *priv); | ||
| 395 | void iwlagn_fw_error(struct iwl_priv *priv, bool ondemand); | ||
| 396 | const char *get_cmd_string(u8 cmd); | ||
| 397 | bool iwl_check_for_ct_kill(struct iwl_priv *priv); | ||
| 398 | |||
| 399 | #ifdef CONFIG_IWLWIFI_DEBUGFS | ||
| 400 | void iwl_reset_traffic_log(struct iwl_priv *priv); | ||
| 401 | #endif /* CONFIG_IWLWIFI_DEBUGFS */ | ||
| 402 | |||
| 403 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
| 404 | void iwl_print_rx_config_cmd(struct iwl_priv *priv, u8 ctxid); | ||
| 405 | #else | ||
| 406 | static inline void iwl_print_rx_config_cmd(struct iwl_priv *priv, u8 ctxid) | ||
| 407 | { | ||
| 408 | } | ||
| 409 | #endif | ||
| 410 | |||
| 411 | #define IWL_CMD(x) case x: return #x | ||
| 412 | #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) | ||
| 413 | |||
| 414 | #define IWL_TRAFFIC_ENTRIES (256) | ||
| 415 | #define IWL_TRAFFIC_ENTRY_SIZE (64) | ||
| 364 | 416 | ||
| 365 | /***************************************************** | 417 | /***************************************************** |
| 366 | * DRIVER STATUS FUNCTIONS | 418 | * DRIVER STATUS FUNCTIONS |
diff --git a/drivers/net/wireless/iwlwifi/iwl-sta.c b/drivers/net/wireless/iwlwifi/iwl-sta.c index 26b2bd4db6b4..e24135e7d37d 100644 --- a/drivers/net/wireless/iwlwifi/iwl-sta.c +++ b/drivers/net/wireless/iwlwifi/iwl-sta.c | |||
| @@ -123,14 +123,14 @@ static int iwl_process_add_sta_resp(struct iwl_priv *priv, | |||
| 123 | return ret; | 123 | return ret; |
| 124 | } | 124 | } |
| 125 | 125 | ||
| 126 | static void iwl_add_sta_callback(struct iwl_priv *priv, | 126 | static void iwl_add_sta_callback(struct iwl_shared *shrd, |
| 127 | struct iwl_device_cmd *cmd, | 127 | struct iwl_device_cmd *cmd, |
| 128 | struct iwl_rx_packet *pkt) | 128 | struct iwl_rx_packet *pkt) |
| 129 | { | 129 | { |
| 130 | struct iwl_addsta_cmd *addsta = | 130 | struct iwl_addsta_cmd *addsta = |
| 131 | (struct iwl_addsta_cmd *)cmd->cmd.payload; | 131 | (struct iwl_addsta_cmd *)cmd->cmd.payload; |
| 132 | 132 | ||
| 133 | iwl_process_add_sta_resp(priv, addsta, pkt, false); | 133 | iwl_process_add_sta_resp(shrd->priv, addsta, pkt, false); |
| 134 | 134 | ||
| 135 | } | 135 | } |
| 136 | 136 | ||
diff --git a/drivers/net/wireless/iwlwifi/iwl-sv-open.c b/drivers/net/wireless/iwlwifi/iwl-sv-open.c index 848fc18befc2..3335d31daf89 100644 --- a/drivers/net/wireless/iwlwifi/iwl-sv-open.c +++ b/drivers/net/wireless/iwlwifi/iwl-sv-open.c | |||
| @@ -63,6 +63,7 @@ | |||
| 63 | #include <linux/init.h> | 63 | #include <linux/init.h> |
| 64 | #include <linux/kernel.h> | 64 | #include <linux/kernel.h> |
| 65 | #include <linux/module.h> | 65 | #include <linux/module.h> |
| 66 | #include <linux/dma-mapping.h> | ||
| 66 | #include <net/net_namespace.h> | 67 | #include <net/net_namespace.h> |
| 67 | #include <linux/netdevice.h> | 68 | #include <linux/netdevice.h> |
| 68 | #include <net/cfg80211.h> | 69 | #include <net/cfg80211.h> |
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans-int-pcie.h b/drivers/net/wireless/iwlwifi/iwl-trans-int-pcie.h index ec4e73737681..8047e955a27b 100644 --- a/drivers/net/wireless/iwlwifi/iwl-trans-int-pcie.h +++ b/drivers/net/wireless/iwlwifi/iwl-trans-int-pcie.h | |||
| @@ -32,6 +32,7 @@ | |||
| 32 | #include <linux/spinlock.h> | 32 | #include <linux/spinlock.h> |
| 33 | #include <linux/interrupt.h> | 33 | #include <linux/interrupt.h> |
| 34 | #include <linux/skbuff.h> | 34 | #include <linux/skbuff.h> |
| 35 | #include <linux/pci.h> | ||
| 35 | 36 | ||
| 36 | #include "iwl-fh.h" | 37 | #include "iwl-fh.h" |
| 37 | #include "iwl-csr.h" | 38 | #include "iwl-csr.h" |
| @@ -114,6 +115,97 @@ struct iwl_dma_ptr { | |||
| 114 | */ | 115 | */ |
| 115 | #define IWL_IPAN_MCAST_QUEUE 8 | 116 | #define IWL_IPAN_MCAST_QUEUE 8 |
| 116 | 117 | ||
| 118 | struct iwl_cmd_meta { | ||
| 119 | /* only for SYNC commands, iff the reply skb is wanted */ | ||
| 120 | struct iwl_host_cmd *source; | ||
| 121 | /* | ||
| 122 | * only for ASYNC commands | ||
| 123 | * (which is somewhat stupid -- look at iwl-sta.c for instance | ||
| 124 | * which duplicates a bunch of code because the callback isn't | ||
| 125 | * invoked for SYNC commands, if it were and its result passed | ||
| 126 | * through it would be simpler...) | ||
| 127 | */ | ||
| 128 | void (*callback)(struct iwl_shared *shrd, | ||
| 129 | struct iwl_device_cmd *cmd, | ||
| 130 | struct iwl_rx_packet *pkt); | ||
| 131 | |||
| 132 | u32 flags; | ||
| 133 | |||
| 134 | DEFINE_DMA_UNMAP_ADDR(mapping); | ||
| 135 | DEFINE_DMA_UNMAP_LEN(len); | ||
| 136 | }; | ||
| 137 | |||
| 138 | /* | ||
| 139 | * Generic queue structure | ||
| 140 | * | ||
| 141 | * Contains common data for Rx and Tx queues. | ||
| 142 | * | ||
| 143 | * Note the difference between n_bd and n_window: the hardware | ||
| 144 | * always assumes 256 descriptors, so n_bd is always 256 (unless | ||
| 145 | * there might be HW changes in the future). For the normal TX | ||
| 146 | * queues, n_window, which is the size of the software queue data | ||
| 147 | * is also 256; however, for the command queue, n_window is only | ||
| 148 | * 32 since we don't need so many commands pending. Since the HW | ||
| 149 | * still uses 256 BDs for DMA though, n_bd stays 256. As a result, | ||
| 150 | * the software buffers (in the variables @meta, @txb in struct | ||
| 151 | * iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds | ||
| 152 | * in the same struct) have 256. | ||
| 153 | * This means that we end up with the following: | ||
| 154 | * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | | ||
| 155 | * SW entries: | 0 | ... | 31 | | ||
| 156 | * where N is a number between 0 and 7. This means that the SW | ||
| 157 | * data is a window overlayed over the HW queue. | ||
| 158 | */ | ||
| 159 | struct iwl_queue { | ||
| 160 | int n_bd; /* number of BDs in this queue */ | ||
| 161 | int write_ptr; /* 1-st empty entry (index) host_w*/ | ||
| 162 | int read_ptr; /* last used entry (index) host_r*/ | ||
| 163 | /* use for monitoring and recovering the stuck queue */ | ||
| 164 | dma_addr_t dma_addr; /* physical addr for BD's */ | ||
| 165 | int n_window; /* safe queue window */ | ||
| 166 | u32 id; | ||
| 167 | int low_mark; /* low watermark, resume queue if free | ||
| 168 | * space more than this */ | ||
| 169 | int high_mark; /* high watermark, stop queue if free | ||
| 170 | * space less than this */ | ||
| 171 | }; | ||
| 172 | |||
| 173 | /** | ||
| 174 | * struct iwl_tx_queue - Tx Queue for DMA | ||
| 175 | * @q: generic Rx/Tx queue descriptor | ||
| 176 | * @bd: base of circular buffer of TFDs | ||
| 177 | * @cmd: array of command/TX buffer pointers | ||
| 178 | * @meta: array of meta data for each command/tx buffer | ||
| 179 | * @dma_addr_cmd: physical address of cmd/tx buffer array | ||
| 180 | * @txb: array of per-TFD driver data | ||
| 181 | * @time_stamp: time (in jiffies) of last read_ptr change | ||
| 182 | * @need_update: indicates need to update read/write index | ||
| 183 | * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled | ||
| 184 | * @sta_id: valid if sched_retry is set | ||
| 185 | * @tid: valid if sched_retry is set | ||
| 186 | * | ||
| 187 | * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame | ||
| 188 | * descriptors) and required locking structures. | ||
| 189 | */ | ||
| 190 | #define TFD_TX_CMD_SLOTS 256 | ||
| 191 | #define TFD_CMD_SLOTS 32 | ||
| 192 | |||
| 193 | struct iwl_tx_queue { | ||
| 194 | struct iwl_queue q; | ||
| 195 | struct iwl_tfd *tfds; | ||
| 196 | struct iwl_device_cmd **cmd; | ||
| 197 | struct iwl_cmd_meta *meta; | ||
| 198 | struct sk_buff **skbs; | ||
| 199 | unsigned long time_stamp; | ||
| 200 | u8 need_update; | ||
| 201 | u8 sched_retry; | ||
| 202 | u8 active; | ||
| 203 | u8 swq_id; | ||
| 204 | |||
| 205 | u16 sta_id; | ||
| 206 | u16 tid; | ||
| 207 | }; | ||
| 208 | |||
| 117 | /** | 209 | /** |
| 118 | * struct iwl_trans_pcie - PCIe transport specific data | 210 | * struct iwl_trans_pcie - PCIe transport specific data |
| 119 | * @rxq: all the RX queue data | 211 | * @rxq: all the RX queue data |
| @@ -195,7 +287,8 @@ int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id); | |||
| 195 | int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); | 287 | int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); |
| 196 | int __must_check iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id, | 288 | int __must_check iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id, |
| 197 | u32 flags, u16 len, const void *data); | 289 | u32 flags, u16 len, const void *data); |
| 198 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb); | 290 | void iwl_tx_cmd_complete(struct iwl_trans *trans, |
| 291 | struct iwl_rx_mem_buffer *rxb); | ||
| 199 | void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans, | 292 | void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
| 200 | struct iwl_tx_queue *txq, | 293 | struct iwl_tx_queue *txq, |
| 201 | u16 byte_cnt); | 294 | u16 byte_cnt); |
| @@ -343,4 +436,19 @@ static inline u8 get_cmd_index(struct iwl_queue *q, u32 index) | |||
| 343 | return index & (q->n_window - 1); | 436 | return index & (q->n_window - 1); |
| 344 | } | 437 | } |
| 345 | 438 | ||
| 439 | #define IWL_TX_FIFO_BK 0 /* shared */ | ||
| 440 | #define IWL_TX_FIFO_BE 1 | ||
| 441 | #define IWL_TX_FIFO_VI 2 /* shared */ | ||
| 442 | #define IWL_TX_FIFO_VO 3 | ||
| 443 | #define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK | ||
| 444 | #define IWL_TX_FIFO_BE_IPAN 4 | ||
| 445 | #define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI | ||
| 446 | #define IWL_TX_FIFO_VO_IPAN 5 | ||
| 447 | /* re-uses the VO FIFO, uCode will properly flush/schedule */ | ||
| 448 | #define IWL_TX_FIFO_AUX 5 | ||
| 449 | #define IWL_TX_FIFO_UNUSED -1 | ||
| 450 | |||
| 451 | /* AUX (TX during scan dwell) queue */ | ||
| 452 | #define IWL_AUX_QUEUE 10 | ||
| 453 | |||
| 346 | #endif /* __iwl_trans_int_pcie_h__ */ | 454 | #endif /* __iwl_trans_int_pcie_h__ */ |
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c b/drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c index 2d0ddb8d422d..126e5a4cc401 100644 --- a/drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c +++ b/drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c | |||
| @@ -30,8 +30,7 @@ | |||
| 30 | #include <linux/wait.h> | 30 | #include <linux/wait.h> |
| 31 | #include <linux/gfp.h> | 31 | #include <linux/gfp.h> |
| 32 | 32 | ||
| 33 | #include "iwl-dev.h" | 33 | /*TODO: Remove include to iwl-core.h*/ |
| 34 | #include "iwl-agn.h" | ||
| 35 | #include "iwl-core.h" | 34 | #include "iwl-core.h" |
| 36 | #include "iwl-io.h" | 35 | #include "iwl-io.h" |
| 37 | #include "iwl-helpers.h" | 36 | #include "iwl-helpers.h" |
| @@ -453,7 +452,7 @@ static void iwl_rx_handle(struct iwl_trans *trans) | |||
| 453 | * iwl_trans_send_cmd() | 452 | * iwl_trans_send_cmd() |
| 454 | * as we reclaim the driver command queue */ | 453 | * as we reclaim the driver command queue */ |
| 455 | if (rxb->page) | 454 | if (rxb->page) |
| 456 | iwl_tx_cmd_complete(priv(trans), rxb); | 455 | iwl_tx_cmd_complete(trans, rxb); |
| 457 | else | 456 | else |
| 458 | IWL_WARN(trans, "Claim null rxb?\n"); | 457 | IWL_WARN(trans, "Claim null rxb?\n"); |
| 459 | } | 458 | } |
| @@ -646,7 +645,7 @@ static void iwl_irq_handle_error(struct iwl_trans *trans) | |||
| 646 | */ | 645 | */ |
| 647 | clear_bit(STATUS_READY, &trans->shrd->status); | 646 | clear_bit(STATUS_READY, &trans->shrd->status); |
| 648 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); | 647 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
| 649 | wake_up_interruptible(&priv->wait_command_queue); | 648 | wake_up_interruptible(&priv->shrd->wait_command_queue); |
| 650 | IWL_ERR(trans, "RF is used by WiMAX\n"); | 649 | IWL_ERR(trans, "RF is used by WiMAX\n"); |
| 651 | return; | 650 | return; |
| 652 | } | 651 | } |
| @@ -660,8 +659,7 @@ static void iwl_irq_handle_error(struct iwl_trans *trans) | |||
| 660 | iwl_dump_nic_event_log(trans, false, NULL, false); | 659 | iwl_dump_nic_event_log(trans, false, NULL, false); |
| 661 | #ifdef CONFIG_IWLWIFI_DEBUG | 660 | #ifdef CONFIG_IWLWIFI_DEBUG |
| 662 | if (iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) | 661 | if (iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) |
| 663 | iwl_print_rx_config_cmd(priv, | 662 | iwl_print_rx_config_cmd(priv(trans), IWL_RXON_CTX_BSS); |
| 664 | &priv->contexts[IWL_RXON_CTX_BSS]); | ||
| 665 | #endif | 663 | #endif |
| 666 | 664 | ||
| 667 | iwlagn_fw_error(priv, false); | 665 | iwlagn_fw_error(priv, false); |
| @@ -705,18 +703,18 @@ static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx, | |||
| 705 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | 703 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); |
| 706 | 704 | ||
| 707 | /* Make sure device is powered up for SRAM reads */ | 705 | /* Make sure device is powered up for SRAM reads */ |
| 708 | spin_lock_irqsave(&bus(priv)->reg_lock, reg_flags); | 706 | spin_lock_irqsave(&bus(trans)->reg_lock, reg_flags); |
| 709 | iwl_grab_nic_access(bus(priv)); | 707 | iwl_grab_nic_access(bus(trans)); |
| 710 | 708 | ||
| 711 | /* Set starting address; reads will auto-increment */ | 709 | /* Set starting address; reads will auto-increment */ |
| 712 | iwl_write32(bus(priv), HBUS_TARG_MEM_RADDR, ptr); | 710 | iwl_write32(bus(trans), HBUS_TARG_MEM_RADDR, ptr); |
| 713 | rmb(); | 711 | rmb(); |
| 714 | 712 | ||
| 715 | /* "time" is actually "data" for mode 0 (no timestamp). | 713 | /* "time" is actually "data" for mode 0 (no timestamp). |
| 716 | * place event id # at far right for easier visual parsing. */ | 714 | * place event id # at far right for easier visual parsing. */ |
| 717 | for (i = 0; i < num_events; i++) { | 715 | for (i = 0; i < num_events; i++) { |
| 718 | ev = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT); | 716 | ev = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT); |
| 719 | time = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT); | 717 | time = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT); |
| 720 | if (mode == 0) { | 718 | if (mode == 0) { |
| 721 | /* data, ev */ | 719 | /* data, ev */ |
| 722 | if (bufsz) { | 720 | if (bufsz) { |
| @@ -730,7 +728,7 @@ static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx, | |||
| 730 | time, ev); | 728 | time, ev); |
| 731 | } | 729 | } |
| 732 | } else { | 730 | } else { |
| 733 | data = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT); | 731 | data = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT); |
| 734 | if (bufsz) { | 732 | if (bufsz) { |
| 735 | pos += scnprintf(*buf + pos, bufsz - pos, | 733 | pos += scnprintf(*buf + pos, bufsz - pos, |
| 736 | "EVT_LOGT:%010u:0x%08x:%04u\n", | 734 | "EVT_LOGT:%010u:0x%08x:%04u\n", |
| @@ -745,8 +743,8 @@ static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx, | |||
| 745 | } | 743 | } |
| 746 | 744 | ||
| 747 | /* Allow device to power down */ | 745 | /* Allow device to power down */ |
| 748 | iwl_release_nic_access(bus(priv)); | 746 | iwl_release_nic_access(bus(trans)); |
| 749 | spin_unlock_irqrestore(&bus(priv)->reg_lock, reg_flags); | 747 | spin_unlock_irqrestore(&bus(trans)->reg_lock, reg_flags); |
| 750 | return pos; | 748 | return pos; |
| 751 | } | 749 | } |
| 752 | 750 | ||
| @@ -823,10 +821,10 @@ int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log, | |||
| 823 | } | 821 | } |
| 824 | 822 | ||
| 825 | /* event log header */ | 823 | /* event log header */ |
| 826 | capacity = iwl_read_targ_mem(bus(priv), base); | 824 | capacity = iwl_read_targ_mem(bus(trans), base); |
| 827 | mode = iwl_read_targ_mem(bus(priv), base + (1 * sizeof(u32))); | 825 | mode = iwl_read_targ_mem(bus(trans), base + (1 * sizeof(u32))); |
| 828 | num_wraps = iwl_read_targ_mem(bus(priv), base + (2 * sizeof(u32))); | 826 | num_wraps = iwl_read_targ_mem(bus(trans), base + (2 * sizeof(u32))); |
| 829 | next_entry = iwl_read_targ_mem(bus(priv), base + (3 * sizeof(u32))); | 827 | next_entry = iwl_read_targ_mem(bus(trans), base + (3 * sizeof(u32))); |
| 830 | 828 | ||
| 831 | if (capacity > logsize) { | 829 | if (capacity > logsize) { |
| 832 | IWL_ERR(trans, "Log capacity %d is bogus, limit to %d " | 830 | IWL_ERR(trans, "Log capacity %d is bogus, limit to %d " |
| @@ -848,9 +846,6 @@ int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log, | |||
| 848 | return pos; | 846 | return pos; |
| 849 | } | 847 | } |
| 850 | 848 | ||
| 851 | /* enable/disable bt channel inhibition */ | ||
| 852 | priv->bt_ch_announce = iwlagn_mod_params.bt_ch_announce; | ||
| 853 | |||
| 854 | #ifdef CONFIG_IWLWIFI_DEBUG | 849 | #ifdef CONFIG_IWLWIFI_DEBUG |
| 855 | if (!(iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) && !full_log) | 850 | if (!(iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) && !full_log) |
| 856 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) | 851 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) |
| @@ -908,8 +903,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans) | |||
| 908 | u32 inta_mask; | 903 | u32 inta_mask; |
| 909 | #endif | 904 | #endif |
| 910 | 905 | ||
| 911 | struct iwl_trans_pcie *trans_pcie = | 906 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 912 | IWL_TRANS_GET_PCIE_TRANS(trans); | ||
| 913 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; | 907 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
| 914 | 908 | ||
| 915 | 909 | ||
| @@ -1003,8 +997,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans) | |||
| 1003 | else | 997 | else |
| 1004 | clear_bit(STATUS_RF_KILL_HW, | 998 | clear_bit(STATUS_RF_KILL_HW, |
| 1005 | &trans->shrd->status); | 999 | &trans->shrd->status); |
| 1006 | wiphy_rfkill_set_hw_state(priv(trans)->hw->wiphy, | 1000 | iwl_set_hw_rfkill_state(priv(trans), hw_rf_kill); |
| 1007 | hw_rf_kill); | ||
| 1008 | } | 1001 | } |
| 1009 | 1002 | ||
| 1010 | handled |= CSR_INT_BIT_RF_KILL; | 1003 | handled |= CSR_INT_BIT_RF_KILL; |
| @@ -1093,7 +1086,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans) | |||
| 1093 | handled |= CSR_INT_BIT_FH_TX; | 1086 | handled |= CSR_INT_BIT_FH_TX; |
| 1094 | /* Wake up uCode load routine, now that load is complete */ | 1087 | /* Wake up uCode load routine, now that load is complete */ |
| 1095 | priv(trans)->ucode_write_complete = 1; | 1088 | priv(trans)->ucode_write_complete = 1; |
| 1096 | wake_up_interruptible(&priv(trans)->wait_command_queue); | 1089 | wake_up_interruptible(&trans->shrd->wait_command_queue); |
| 1097 | } | 1090 | } |
| 1098 | 1091 | ||
| 1099 | if (inta & ~handled) { | 1092 | if (inta & ~handled) { |
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c b/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c index 5dd6a6d1dfd7..ca686dbf5893 100644 --- a/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c +++ b/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c | |||
| @@ -30,13 +30,19 @@ | |||
| 30 | #include <linux/slab.h> | 30 | #include <linux/slab.h> |
| 31 | #include <linux/sched.h> | 31 | #include <linux/sched.h> |
| 32 | 32 | ||
| 33 | #include "iwl-agn.h" | 33 | /* TODO: remove include to iwl-dev.h */ |
| 34 | #include "iwl-dev.h" | 34 | #include "iwl-dev.h" |
| 35 | #include "iwl-core.h" | 35 | #include "iwl-debug.h" |
| 36 | #include "iwl-csr.h" | ||
| 37 | #include "iwl-prph.h" | ||
| 36 | #include "iwl-io.h" | 38 | #include "iwl-io.h" |
| 39 | #include "iwl-agn-hw.h" | ||
| 37 | #include "iwl-helpers.h" | 40 | #include "iwl-helpers.h" |
| 38 | #include "iwl-trans-int-pcie.h" | 41 | #include "iwl-trans-int-pcie.h" |
| 39 | 42 | ||
| 43 | #define IWL_TX_CRC_SIZE 4 | ||
| 44 | #define IWL_TX_DELIMITER_SIZE 4 | ||
| 45 | |||
| 40 | /** | 46 | /** |
| 41 | * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | 47 | * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array |
| 42 | */ | 48 | */ |
| @@ -535,8 +541,7 @@ int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans, | |||
| 535 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | 541 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 536 | struct iwl_tid_data *tid_data; | 542 | struct iwl_tid_data *tid_data; |
| 537 | unsigned long flags; | 543 | unsigned long flags; |
| 538 | u16 txq_id; | 544 | int txq_id; |
| 539 | struct iwl_priv *priv = priv(trans); | ||
| 540 | 545 | ||
| 541 | txq_id = iwlagn_txq_ctx_activate_free(trans); | 546 | txq_id = iwlagn_txq_ctx_activate_free(trans); |
| 542 | if (txq_id == -1) { | 547 | if (txq_id == -1) { |
| @@ -560,7 +565,7 @@ int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans, | |||
| 560 | "queue\n", tid_data->tfds_in_queue); | 565 | "queue\n", tid_data->tfds_in_queue); |
| 561 | tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA; | 566 | tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA; |
| 562 | } | 567 | } |
| 563 | spin_unlock_irqrestore(&priv->shrd->sta_lock, flags); | 568 | spin_unlock_irqrestore(&trans->shrd->sta_lock, flags); |
| 564 | 569 | ||
| 565 | return 0; | 570 | return 0; |
| 566 | } | 571 | } |
| @@ -856,16 +861,16 @@ static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) | |||
| 856 | * need to be reclaimed. As result, some free space forms. If there is | 861 | * need to be reclaimed. As result, some free space forms. If there is |
| 857 | * enough free space (> low mark), wake the stack that feeds us. | 862 | * enough free space (> low mark), wake the stack that feeds us. |
| 858 | */ | 863 | */ |
| 859 | static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx) | 864 | static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id, |
| 865 | int idx) | ||
| 860 | { | 866 | { |
| 861 | struct iwl_trans_pcie *trans_pcie = | 867 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 862 | IWL_TRANS_GET_PCIE_TRANS(trans(priv)); | ||
| 863 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | 868 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; |
| 864 | struct iwl_queue *q = &txq->q; | 869 | struct iwl_queue *q = &txq->q; |
| 865 | int nfreed = 0; | 870 | int nfreed = 0; |
| 866 | 871 | ||
| 867 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { | 872 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
| 868 | IWL_ERR(priv, "%s: Read index for DMA queue txq id (%d), " | 873 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " |
| 869 | "index %d is out of range [0-%d] %d %d.\n", __func__, | 874 | "index %d is out of range [0-%d] %d %d.\n", __func__, |
| 870 | txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr); | 875 | txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr); |
| 871 | return; | 876 | return; |
| @@ -875,9 +880,9 @@ static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx) | |||
| 875 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | 880 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { |
| 876 | 881 | ||
| 877 | if (nfreed++ > 0) { | 882 | if (nfreed++ > 0) { |
| 878 | IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx, | 883 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx, |
| 879 | q->write_ptr, q->read_ptr); | 884 | q->write_ptr, q->read_ptr); |
| 880 | iwlagn_fw_error(priv, false); | 885 | iwlagn_fw_error(priv(trans), false); |
| 881 | } | 886 | } |
| 882 | 887 | ||
| 883 | } | 888 | } |
| @@ -891,7 +896,7 @@ static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx) | |||
| 891 | * will be executed. The attached skb (if present) will only be freed | 896 | * will be executed. The attached skb (if present) will only be freed |
| 892 | * if the callback returns 1 | 897 | * if the callback returns 1 |
| 893 | */ | 898 | */ |
| 894 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | 899 | void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_mem_buffer *rxb) |
| 895 | { | 900 | { |
| 896 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | 901 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
| 897 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); | 902 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
| @@ -900,7 +905,6 @@ void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |||
| 900 | int cmd_index; | 905 | int cmd_index; |
| 901 | struct iwl_device_cmd *cmd; | 906 | struct iwl_device_cmd *cmd; |
| 902 | struct iwl_cmd_meta *meta; | 907 | struct iwl_cmd_meta *meta; |
| 903 | struct iwl_trans *trans = trans(priv); | ||
| 904 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | 908 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 905 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue]; | 909 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue]; |
| 906 | unsigned long flags; | 910 | unsigned long flags; |
| @@ -913,7 +917,7 @@ void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |||
| 913 | txq_id, trans->shrd->cmd_queue, sequence, | 917 | txq_id, trans->shrd->cmd_queue, sequence, |
| 914 | trans_pcie->txq[trans->shrd->cmd_queue].q.read_ptr, | 918 | trans_pcie->txq[trans->shrd->cmd_queue].q.read_ptr, |
| 915 | trans_pcie->txq[trans->shrd->cmd_queue].q.write_ptr)) { | 919 | trans_pcie->txq[trans->shrd->cmd_queue].q.write_ptr)) { |
| 916 | iwl_print_hex_error(priv, pkt, 32); | 920 | iwl_print_hex_error(trans, pkt, 32); |
| 917 | return; | 921 | return; |
| 918 | } | 922 | } |
| 919 | 923 | ||
| @@ -929,17 +933,17 @@ void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |||
| 929 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); | 933 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); |
| 930 | rxb->page = NULL; | 934 | rxb->page = NULL; |
| 931 | } else if (meta->callback) | 935 | } else if (meta->callback) |
| 932 | meta->callback(priv, cmd, pkt); | 936 | meta->callback(trans->shrd, cmd, pkt); |
| 933 | 937 | ||
| 934 | spin_lock_irqsave(&trans->hcmd_lock, flags); | 938 | spin_lock_irqsave(&trans->hcmd_lock, flags); |
| 935 | 939 | ||
| 936 | iwl_hcmd_queue_reclaim(priv, txq_id, index); | 940 | iwl_hcmd_queue_reclaim(trans, txq_id, index); |
| 937 | 941 | ||
| 938 | if (!(meta->flags & CMD_ASYNC)) { | 942 | if (!(meta->flags & CMD_ASYNC)) { |
| 939 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); | 943 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
| 940 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", | 944 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
| 941 | get_cmd_string(cmd->hdr.cmd)); | 945 | get_cmd_string(cmd->hdr.cmd)); |
| 942 | wake_up_interruptible(&priv->wait_command_queue); | 946 | wake_up_interruptible(&trans->shrd->wait_command_queue); |
| 943 | } | 947 | } |
| 944 | 948 | ||
| 945 | meta->flags = 0; | 949 | meta->flags = 0; |
| @@ -947,96 +951,14 @@ void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |||
| 947 | spin_unlock_irqrestore(&trans->hcmd_lock, flags); | 951 | spin_unlock_irqrestore(&trans->hcmd_lock, flags); |
| 948 | } | 952 | } |
| 949 | 953 | ||
| 950 | const char *get_cmd_string(u8 cmd) | ||
| 951 | { | ||
| 952 | switch (cmd) { | ||
| 953 | IWL_CMD(REPLY_ALIVE); | ||
| 954 | IWL_CMD(REPLY_ERROR); | ||
| 955 | IWL_CMD(REPLY_RXON); | ||
| 956 | IWL_CMD(REPLY_RXON_ASSOC); | ||
| 957 | IWL_CMD(REPLY_QOS_PARAM); | ||
| 958 | IWL_CMD(REPLY_RXON_TIMING); | ||
| 959 | IWL_CMD(REPLY_ADD_STA); | ||
| 960 | IWL_CMD(REPLY_REMOVE_STA); | ||
| 961 | IWL_CMD(REPLY_REMOVE_ALL_STA); | ||
| 962 | IWL_CMD(REPLY_TXFIFO_FLUSH); | ||
| 963 | IWL_CMD(REPLY_WEPKEY); | ||
| 964 | IWL_CMD(REPLY_TX); | ||
| 965 | IWL_CMD(REPLY_LEDS_CMD); | ||
| 966 | IWL_CMD(REPLY_TX_LINK_QUALITY_CMD); | ||
| 967 | IWL_CMD(COEX_PRIORITY_TABLE_CMD); | ||
| 968 | IWL_CMD(COEX_MEDIUM_NOTIFICATION); | ||
| 969 | IWL_CMD(COEX_EVENT_CMD); | ||
| 970 | IWL_CMD(REPLY_QUIET_CMD); | ||
| 971 | IWL_CMD(REPLY_CHANNEL_SWITCH); | ||
| 972 | IWL_CMD(CHANNEL_SWITCH_NOTIFICATION); | ||
| 973 | IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD); | ||
| 974 | IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION); | ||
| 975 | IWL_CMD(POWER_TABLE_CMD); | ||
| 976 | IWL_CMD(PM_SLEEP_NOTIFICATION); | ||
| 977 | IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC); | ||
| 978 | IWL_CMD(REPLY_SCAN_CMD); | ||
| 979 | IWL_CMD(REPLY_SCAN_ABORT_CMD); | ||
| 980 | IWL_CMD(SCAN_START_NOTIFICATION); | ||
| 981 | IWL_CMD(SCAN_RESULTS_NOTIFICATION); | ||
| 982 | IWL_CMD(SCAN_COMPLETE_NOTIFICATION); | ||
| 983 | IWL_CMD(BEACON_NOTIFICATION); | ||
| 984 | IWL_CMD(REPLY_TX_BEACON); | ||
| 985 | IWL_CMD(WHO_IS_AWAKE_NOTIFICATION); | ||
| 986 | IWL_CMD(QUIET_NOTIFICATION); | ||
| 987 | IWL_CMD(REPLY_TX_PWR_TABLE_CMD); | ||
| 988 | IWL_CMD(MEASURE_ABORT_NOTIFICATION); | ||
| 989 | IWL_CMD(REPLY_BT_CONFIG); | ||
| 990 | IWL_CMD(REPLY_STATISTICS_CMD); | ||
| 991 | IWL_CMD(STATISTICS_NOTIFICATION); | ||
| 992 | IWL_CMD(REPLY_CARD_STATE_CMD); | ||
| 993 | IWL_CMD(CARD_STATE_NOTIFICATION); | ||
| 994 | IWL_CMD(MISSED_BEACONS_NOTIFICATION); | ||
| 995 | IWL_CMD(REPLY_CT_KILL_CONFIG_CMD); | ||
| 996 | IWL_CMD(SENSITIVITY_CMD); | ||
| 997 | IWL_CMD(REPLY_PHY_CALIBRATION_CMD); | ||
| 998 | IWL_CMD(REPLY_RX_PHY_CMD); | ||
| 999 | IWL_CMD(REPLY_RX_MPDU_CMD); | ||
| 1000 | IWL_CMD(REPLY_RX); | ||
| 1001 | IWL_CMD(REPLY_COMPRESSED_BA); | ||
| 1002 | IWL_CMD(CALIBRATION_CFG_CMD); | ||
| 1003 | IWL_CMD(CALIBRATION_RES_NOTIFICATION); | ||
| 1004 | IWL_CMD(CALIBRATION_COMPLETE_NOTIFICATION); | ||
| 1005 | IWL_CMD(REPLY_TX_POWER_DBM_CMD); | ||
| 1006 | IWL_CMD(TEMPERATURE_NOTIFICATION); | ||
| 1007 | IWL_CMD(TX_ANT_CONFIGURATION_CMD); | ||
| 1008 | IWL_CMD(REPLY_BT_COEX_PROFILE_NOTIF); | ||
| 1009 | IWL_CMD(REPLY_BT_COEX_PRIO_TABLE); | ||
| 1010 | IWL_CMD(REPLY_BT_COEX_PROT_ENV); | ||
| 1011 | IWL_CMD(REPLY_WIPAN_PARAMS); | ||
| 1012 | IWL_CMD(REPLY_WIPAN_RXON); | ||
| 1013 | IWL_CMD(REPLY_WIPAN_RXON_TIMING); | ||
| 1014 | IWL_CMD(REPLY_WIPAN_RXON_ASSOC); | ||
| 1015 | IWL_CMD(REPLY_WIPAN_QOS_PARAM); | ||
| 1016 | IWL_CMD(REPLY_WIPAN_WEPKEY); | ||
| 1017 | IWL_CMD(REPLY_WIPAN_P2P_CHANNEL_SWITCH); | ||
| 1018 | IWL_CMD(REPLY_WIPAN_NOA_NOTIFICATION); | ||
| 1019 | IWL_CMD(REPLY_WIPAN_DEACTIVATION_COMPLETE); | ||
| 1020 | IWL_CMD(REPLY_WOWLAN_PATTERNS); | ||
| 1021 | IWL_CMD(REPLY_WOWLAN_WAKEUP_FILTER); | ||
| 1022 | IWL_CMD(REPLY_WOWLAN_TSC_RSC_PARAMS); | ||
| 1023 | IWL_CMD(REPLY_WOWLAN_TKIP_PARAMS); | ||
| 1024 | IWL_CMD(REPLY_WOWLAN_KEK_KCK_MATERIAL); | ||
| 1025 | IWL_CMD(REPLY_WOWLAN_GET_STATUS); | ||
| 1026 | default: | ||
| 1027 | return "UNKNOWN"; | ||
| 1028 | |||
| 1029 | } | ||
| 1030 | } | ||
| 1031 | |||
| 1032 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) | 954 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
| 1033 | 955 | ||
| 1034 | static void iwl_generic_cmd_callback(struct iwl_priv *priv, | 956 | static void iwl_generic_cmd_callback(struct iwl_shared *shrd, |
| 1035 | struct iwl_device_cmd *cmd, | 957 | struct iwl_device_cmd *cmd, |
| 1036 | struct iwl_rx_packet *pkt) | 958 | struct iwl_rx_packet *pkt) |
| 1037 | { | 959 | { |
| 1038 | if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) { | 960 | if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) { |
| 1039 | IWL_ERR(priv, "Bad return from %s (0x%08X)\n", | 961 | IWL_ERR(shrd->trans, "Bad return from %s (0x%08X)\n", |
| 1040 | get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); | 962 | get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); |
| 1041 | return; | 963 | return; |
| 1042 | } | 964 | } |
| @@ -1045,11 +967,11 @@ static void iwl_generic_cmd_callback(struct iwl_priv *priv, | |||
| 1045 | switch (cmd->hdr.cmd) { | 967 | switch (cmd->hdr.cmd) { |
| 1046 | case REPLY_TX_LINK_QUALITY_CMD: | 968 | case REPLY_TX_LINK_QUALITY_CMD: |
| 1047 | case SENSITIVITY_CMD: | 969 | case SENSITIVITY_CMD: |
| 1048 | IWL_DEBUG_HC_DUMP(priv, "back from %s (0x%08X)\n", | 970 | IWL_DEBUG_HC_DUMP(shrd->trans, "back from %s (0x%08X)\n", |
| 1049 | get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); | 971 | get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); |
| 1050 | break; | 972 | break; |
| 1051 | default: | 973 | default: |
| 1052 | IWL_DEBUG_HC(priv, "back from %s (0x%08X)\n", | 974 | IWL_DEBUG_HC(shrd->trans, "back from %s (0x%08X)\n", |
| 1053 | get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); | 975 | get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); |
| 1054 | } | 976 | } |
| 1055 | #endif | 977 | #endif |
| @@ -1107,7 +1029,7 @@ static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd) | |||
| 1107 | return ret; | 1029 | return ret; |
| 1108 | } | 1030 | } |
| 1109 | 1031 | ||
| 1110 | ret = wait_event_interruptible_timeout(priv(trans)->wait_command_queue, | 1032 | ret = wait_event_interruptible_timeout(trans->shrd->wait_command_queue, |
| 1111 | !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status), | 1033 | !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status), |
| 1112 | HOST_COMPLETE_TIMEOUT); | 1034 | HOST_COMPLETE_TIMEOUT); |
| 1113 | if (!ret) { | 1035 | if (!ret) { |
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans.c b/drivers/net/wireless/iwlwifi/iwl-trans.c index cec13adb018e..b2e89077c684 100644 --- a/drivers/net/wireless/iwlwifi/iwl-trans.c +++ b/drivers/net/wireless/iwlwifi/iwl-trans.c | |||
| @@ -65,14 +65,13 @@ | |||
| 65 | #include <linux/bitops.h> | 65 | #include <linux/bitops.h> |
| 66 | #include <linux/gfp.h> | 66 | #include <linux/gfp.h> |
| 67 | 67 | ||
| 68 | #include "iwl-dev.h" | ||
| 69 | #include "iwl-trans.h" | 68 | #include "iwl-trans.h" |
| 70 | #include "iwl-core.h" | ||
| 71 | #include "iwl-helpers.h" | ||
| 72 | #include "iwl-trans-int-pcie.h" | 69 | #include "iwl-trans-int-pcie.h" |
| 73 | /*TODO remove uneeded includes when the transport layer tx_free will be here */ | 70 | #include "iwl-csr.h" |
| 74 | #include "iwl-agn.h" | 71 | #include "iwl-prph.h" |
| 75 | #include "iwl-shared.h" | 72 | #include "iwl-shared.h" |
| 73 | #include "iwl-eeprom.h" | ||
| 74 | #include "iwl-agn-hw.h" | ||
| 76 | 75 | ||
| 77 | static int iwl_trans_rx_alloc(struct iwl_trans *trans) | 76 | static int iwl_trans_rx_alloc(struct iwl_trans *trans) |
| 78 | { | 77 | { |
| @@ -604,9 +603,8 @@ error: | |||
| 604 | return ret; | 603 | return ret; |
| 605 | } | 604 | } |
| 606 | 605 | ||
| 607 | static void iwl_set_pwr_vmain(struct iwl_priv *priv) | 606 | static void iwl_set_pwr_vmain(struct iwl_trans *trans) |
| 608 | { | 607 | { |
| 609 | struct iwl_trans *trans = trans(priv); | ||
| 610 | /* | 608 | /* |
| 611 | * (for documentation purposes) | 609 | * (for documentation purposes) |
| 612 | * to set power to V_AUX, do: | 610 | * to set power to V_AUX, do: |
| @@ -625,11 +623,10 @@ static void iwl_set_pwr_vmain(struct iwl_priv *priv) | |||
| 625 | static int iwl_nic_init(struct iwl_trans *trans) | 623 | static int iwl_nic_init(struct iwl_trans *trans) |
| 626 | { | 624 | { |
| 627 | unsigned long flags; | 625 | unsigned long flags; |
| 628 | struct iwl_priv *priv = priv(trans); | ||
| 629 | 626 | ||
| 630 | /* nic_init */ | 627 | /* nic_init */ |
| 631 | spin_lock_irqsave(&trans->shrd->lock, flags); | 628 | spin_lock_irqsave(&trans->shrd->lock, flags); |
| 632 | iwl_apm_init(priv); | 629 | iwl_apm_init(priv(trans)); |
| 633 | 630 | ||
| 634 | /* Set interrupt coalescing calibration timer to default (512 usecs) */ | 631 | /* Set interrupt coalescing calibration timer to default (512 usecs) */ |
| 635 | iwl_write8(bus(trans), CSR_INT_COALESCING, | 632 | iwl_write8(bus(trans), CSR_INT_COALESCING, |
| @@ -637,9 +634,9 @@ static int iwl_nic_init(struct iwl_trans *trans) | |||
| 637 | 634 | ||
| 638 | spin_unlock_irqrestore(&trans->shrd->lock, flags); | 635 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
| 639 | 636 | ||
| 640 | iwl_set_pwr_vmain(priv); | 637 | iwl_set_pwr_vmain(trans); |
| 641 | 638 | ||
| 642 | priv->cfg->lib->nic_config(priv); | 639 | iwl_nic_config(priv(trans)); |
| 643 | 640 | ||
| 644 | /* Allocate the RX queue, or reset if it is already allocated */ | 641 | /* Allocate the RX queue, or reset if it is already allocated */ |
| 645 | iwl_rx_init(trans); | 642 | iwl_rx_init(trans); |
| @@ -764,7 +761,6 @@ static const u8 iwlagn_pan_ac_to_queue[] = { | |||
| 764 | static int iwl_trans_pcie_start_device(struct iwl_trans *trans) | 761 | static int iwl_trans_pcie_start_device(struct iwl_trans *trans) |
| 765 | { | 762 | { |
| 766 | int ret; | 763 | int ret; |
| 767 | struct iwl_priv *priv = priv(trans); | ||
| 768 | struct iwl_trans_pcie *trans_pcie = | 764 | struct iwl_trans_pcie *trans_pcie = |
| 769 | IWL_TRANS_GET_PCIE_TRANS(trans); | 765 | IWL_TRANS_GET_PCIE_TRANS(trans); |
| 770 | 766 | ||
| @@ -792,7 +788,7 @@ static int iwl_trans_pcie_start_device(struct iwl_trans *trans) | |||
| 792 | set_bit(STATUS_RF_KILL_HW, &trans->shrd->status); | 788 | set_bit(STATUS_RF_KILL_HW, &trans->shrd->status); |
| 793 | 789 | ||
| 794 | if (iwl_is_rfkill(trans->shrd)) { | 790 | if (iwl_is_rfkill(trans->shrd)) { |
| 795 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, true); | 791 | iwl_set_hw_rfkill_state(priv(trans), true); |
| 796 | iwl_enable_interrupts(trans); | 792 | iwl_enable_interrupts(trans); |
| 797 | return -ERFKILL; | 793 | return -ERFKILL; |
| 798 | } | 794 | } |
| @@ -833,8 +829,6 @@ static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask) | |||
| 833 | static void iwl_trans_pcie_tx_start(struct iwl_trans *trans) | 829 | static void iwl_trans_pcie_tx_start(struct iwl_trans *trans) |
| 834 | { | 830 | { |
| 835 | const struct queue_to_fifo_ac *queue_to_fifo; | 831 | const struct queue_to_fifo_ac *queue_to_fifo; |
| 836 | struct iwl_rxon_context *ctx; | ||
| 837 | struct iwl_priv *priv = priv(trans); | ||
| 838 | struct iwl_trans_pcie *trans_pcie = | 832 | struct iwl_trans_pcie *trans_pcie = |
| 839 | IWL_TRANS_GET_PCIE_TRANS(trans); | 833 | IWL_TRANS_GET_PCIE_TRANS(trans); |
| 840 | u32 a; | 834 | u32 a; |
| @@ -902,7 +896,7 @@ static void iwl_trans_pcie_tx_start(struct iwl_trans *trans) | |||
| 902 | iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7)); | 896 | iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7)); |
| 903 | 897 | ||
| 904 | /* map queues to FIFOs */ | 898 | /* map queues to FIFOs */ |
| 905 | if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)) | 899 | if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS)) |
| 906 | queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo; | 900 | queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo; |
| 907 | else | 901 | else |
| 908 | queue_to_fifo = iwlagn_default_queue_to_tx_fifo; | 902 | queue_to_fifo = iwlagn_default_queue_to_tx_fifo; |
| @@ -914,8 +908,6 @@ static void iwl_trans_pcie_tx_start(struct iwl_trans *trans) | |||
| 914 | sizeof(trans_pcie->queue_stopped)); | 908 | sizeof(trans_pcie->queue_stopped)); |
| 915 | for (i = 0; i < 4; i++) | 909 | for (i = 0; i < 4; i++) |
| 916 | atomic_set(&trans_pcie->queue_stop_count[i], 0); | 910 | atomic_set(&trans_pcie->queue_stop_count[i], 0); |
| 917 | for_each_context(priv, ctx) | ||
| 918 | ctx->last_tx_rejected = false; | ||
| 919 | 911 | ||
| 920 | /* reset to 0 to enable all the queue first */ | 912 | /* reset to 0 to enable all the queue first */ |
| 921 | trans_pcie->txq_ctx_active_msk = 0; | 913 | trans_pcie->txq_ctx_active_msk = 0; |
| @@ -1397,7 +1389,7 @@ static int iwl_trans_pcie_resume(struct iwl_trans *trans) | |||
| 1397 | else | 1389 | else |
| 1398 | clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status); | 1390 | clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status); |
| 1399 | 1391 | ||
| 1400 | wiphy_rfkill_set_hw_state(priv(trans)->hw->wiphy, hw_rfkill); | 1392 | iwl_set_hw_rfkill_state(priv(trans), hw_rfkill); |
| 1401 | 1393 | ||
| 1402 | return 0; | 1394 | return 0; |
| 1403 | } | 1395 | } |
| @@ -1505,12 +1497,144 @@ static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt) | |||
| 1505 | if (time_after(jiffies, timeout)) { | 1497 | if (time_after(jiffies, timeout)) { |
| 1506 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id, | 1498 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id, |
| 1507 | hw_params(trans).wd_timeout); | 1499 | hw_params(trans).wd_timeout); |
| 1500 | IWL_ERR(trans, "Current read_ptr %d write_ptr %d\n", | ||
| 1501 | q->read_ptr, q->write_ptr); | ||
| 1508 | return 1; | 1502 | return 1; |
| 1509 | } | 1503 | } |
| 1510 | 1504 | ||
| 1511 | return 0; | 1505 | return 0; |
| 1512 | } | 1506 | } |
| 1513 | 1507 | ||
| 1508 | static const char *get_fh_string(int cmd) | ||
| 1509 | { | ||
| 1510 | switch (cmd) { | ||
| 1511 | IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG); | ||
| 1512 | IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG); | ||
| 1513 | IWL_CMD(FH_RSCSR_CHNL0_WPTR); | ||
| 1514 | IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG); | ||
| 1515 | IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG); | ||
| 1516 | IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG); | ||
| 1517 | IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); | ||
| 1518 | IWL_CMD(FH_TSSR_TX_STATUS_REG); | ||
| 1519 | IWL_CMD(FH_TSSR_TX_ERROR_REG); | ||
| 1520 | default: | ||
| 1521 | return "UNKNOWN"; | ||
| 1522 | } | ||
| 1523 | } | ||
| 1524 | |||
| 1525 | int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display) | ||
| 1526 | { | ||
| 1527 | int i; | ||
| 1528 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
| 1529 | int pos = 0; | ||
| 1530 | size_t bufsz = 0; | ||
| 1531 | #endif | ||
| 1532 | static const u32 fh_tbl[] = { | ||
| 1533 | FH_RSCSR_CHNL0_STTS_WPTR_REG, | ||
| 1534 | FH_RSCSR_CHNL0_RBDCB_BASE_REG, | ||
| 1535 | FH_RSCSR_CHNL0_WPTR, | ||
| 1536 | FH_MEM_RCSR_CHNL0_CONFIG_REG, | ||
| 1537 | FH_MEM_RSSR_SHARED_CTRL_REG, | ||
| 1538 | FH_MEM_RSSR_RX_STATUS_REG, | ||
| 1539 | FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, | ||
| 1540 | FH_TSSR_TX_STATUS_REG, | ||
| 1541 | FH_TSSR_TX_ERROR_REG | ||
| 1542 | }; | ||
| 1543 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
| 1544 | if (display) { | ||
| 1545 | bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; | ||
| 1546 | *buf = kmalloc(bufsz, GFP_KERNEL); | ||
| 1547 | if (!*buf) | ||
| 1548 | return -ENOMEM; | ||
| 1549 | pos += scnprintf(*buf + pos, bufsz - pos, | ||
| 1550 | "FH register values:\n"); | ||
| 1551 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { | ||
| 1552 | pos += scnprintf(*buf + pos, bufsz - pos, | ||
| 1553 | " %34s: 0X%08x\n", | ||
| 1554 | get_fh_string(fh_tbl[i]), | ||
| 1555 | iwl_read_direct32(bus(trans), fh_tbl[i])); | ||
| 1556 | } | ||
| 1557 | return pos; | ||
| 1558 | } | ||
| 1559 | #endif | ||
| 1560 | IWL_ERR(trans, "FH register values:\n"); | ||
| 1561 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { | ||
| 1562 | IWL_ERR(trans, " %34s: 0X%08x\n", | ||
| 1563 | get_fh_string(fh_tbl[i]), | ||
| 1564 | iwl_read_direct32(bus(trans), fh_tbl[i])); | ||
| 1565 | } | ||
| 1566 | return 0; | ||
| 1567 | } | ||
| 1568 | |||
| 1569 | static const char *get_csr_string(int cmd) | ||
| 1570 | { | ||
| 1571 | switch (cmd) { | ||
| 1572 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | ||
| 1573 | IWL_CMD(CSR_INT_COALESCING); | ||
| 1574 | IWL_CMD(CSR_INT); | ||
| 1575 | IWL_CMD(CSR_INT_MASK); | ||
| 1576 | IWL_CMD(CSR_FH_INT_STATUS); | ||
| 1577 | IWL_CMD(CSR_GPIO_IN); | ||
| 1578 | IWL_CMD(CSR_RESET); | ||
| 1579 | IWL_CMD(CSR_GP_CNTRL); | ||
| 1580 | IWL_CMD(CSR_HW_REV); | ||
| 1581 | IWL_CMD(CSR_EEPROM_REG); | ||
| 1582 | IWL_CMD(CSR_EEPROM_GP); | ||
| 1583 | IWL_CMD(CSR_OTP_GP_REG); | ||
| 1584 | IWL_CMD(CSR_GIO_REG); | ||
| 1585 | IWL_CMD(CSR_GP_UCODE_REG); | ||
| 1586 | IWL_CMD(CSR_GP_DRIVER_REG); | ||
| 1587 | IWL_CMD(CSR_UCODE_DRV_GP1); | ||
| 1588 | IWL_CMD(CSR_UCODE_DRV_GP2); | ||
| 1589 | IWL_CMD(CSR_LED_REG); | ||
| 1590 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | ||
| 1591 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | ||
| 1592 | IWL_CMD(CSR_ANA_PLL_CFG); | ||
| 1593 | IWL_CMD(CSR_HW_REV_WA_REG); | ||
| 1594 | IWL_CMD(CSR_DBG_HPET_MEM_REG); | ||
| 1595 | default: | ||
| 1596 | return "UNKNOWN"; | ||
| 1597 | } | ||
| 1598 | } | ||
| 1599 | |||
| 1600 | void iwl_dump_csr(struct iwl_trans *trans) | ||
| 1601 | { | ||
| 1602 | int i; | ||
| 1603 | static const u32 csr_tbl[] = { | ||
| 1604 | CSR_HW_IF_CONFIG_REG, | ||
| 1605 | CSR_INT_COALESCING, | ||
| 1606 | CSR_INT, | ||
| 1607 | CSR_INT_MASK, | ||
| 1608 | CSR_FH_INT_STATUS, | ||
| 1609 | CSR_GPIO_IN, | ||
| 1610 | CSR_RESET, | ||
| 1611 | CSR_GP_CNTRL, | ||
| 1612 | CSR_HW_REV, | ||
| 1613 | CSR_EEPROM_REG, | ||
| 1614 | CSR_EEPROM_GP, | ||
| 1615 | CSR_OTP_GP_REG, | ||
| 1616 | CSR_GIO_REG, | ||
| 1617 | CSR_GP_UCODE_REG, | ||
| 1618 | CSR_GP_DRIVER_REG, | ||
| 1619 | CSR_UCODE_DRV_GP1, | ||
| 1620 | CSR_UCODE_DRV_GP2, | ||
| 1621 | CSR_LED_REG, | ||
| 1622 | CSR_DRAM_INT_TBL_REG, | ||
| 1623 | CSR_GIO_CHICKEN_BITS, | ||
| 1624 | CSR_ANA_PLL_CFG, | ||
| 1625 | CSR_HW_REV_WA_REG, | ||
| 1626 | CSR_DBG_HPET_MEM_REG | ||
| 1627 | }; | ||
| 1628 | IWL_ERR(trans, "CSR values:\n"); | ||
| 1629 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | ||
| 1630 | "CSR_INT_PERIODIC_REG)\n"); | ||
| 1631 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | ||
| 1632 | IWL_ERR(trans, " %25s: 0X%08x\n", | ||
| 1633 | get_csr_string(csr_tbl[i]), | ||
| 1634 | iwl_read32(bus(trans), csr_tbl[i])); | ||
| 1635 | } | ||
| 1636 | } | ||
| 1637 | |||
| 1514 | #ifdef CONFIG_IWLWIFI_DEBUGFS | 1638 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
| 1515 | /* create and remove of files */ | 1639 | /* create and remove of files */ |
| 1516 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | 1640 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ |
| @@ -1563,118 +1687,12 @@ static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |||
| 1563 | .llseek = generic_file_llseek, \ | 1687 | .llseek = generic_file_llseek, \ |
| 1564 | }; | 1688 | }; |
| 1565 | 1689 | ||
| 1566 | static ssize_t iwl_dbgfs_traffic_log_read(struct file *file, | ||
| 1567 | char __user *user_buf, | ||
| 1568 | size_t count, loff_t *ppos) | ||
| 1569 | { | ||
| 1570 | struct iwl_trans *trans = file->private_data; | ||
| 1571 | struct iwl_priv *priv = priv(trans); | ||
| 1572 | int pos = 0, ofs = 0; | ||
| 1573 | int cnt = 0, entry; | ||
| 1574 | struct iwl_trans_pcie *trans_pcie = | ||
| 1575 | IWL_TRANS_GET_PCIE_TRANS(trans); | ||
| 1576 | struct iwl_tx_queue *txq; | ||
| 1577 | struct iwl_queue *q; | ||
| 1578 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | ||
| 1579 | char *buf; | ||
| 1580 | int bufsz = ((IWL_TRAFFIC_ENTRIES * IWL_TRAFFIC_ENTRY_SIZE * 64) * 2) + | ||
| 1581 | (hw_params(trans).max_txq_num * 32 * 8) + 400; | ||
| 1582 | const u8 *ptr; | ||
| 1583 | ssize_t ret; | ||
| 1584 | |||
| 1585 | if (!trans_pcie->txq) { | ||
| 1586 | IWL_ERR(trans, "txq not ready\n"); | ||
| 1587 | return -EAGAIN; | ||
| 1588 | } | ||
| 1589 | buf = kzalloc(bufsz, GFP_KERNEL); | ||
| 1590 | if (!buf) { | ||
| 1591 | IWL_ERR(trans, "Can not allocate buffer\n"); | ||
| 1592 | return -ENOMEM; | ||
| 1593 | } | ||
| 1594 | pos += scnprintf(buf + pos, bufsz - pos, "Tx Queue\n"); | ||
| 1595 | for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) { | ||
| 1596 | txq = &trans_pcie->txq[cnt]; | ||
| 1597 | q = &txq->q; | ||
| 1598 | pos += scnprintf(buf + pos, bufsz - pos, | ||
| 1599 | "q[%d]: read_ptr: %u, write_ptr: %u\n", | ||
| 1600 | cnt, q->read_ptr, q->write_ptr); | ||
| 1601 | } | ||
| 1602 | if (priv->tx_traffic && | ||
| 1603 | (iwl_get_debug_level(trans->shrd) & IWL_DL_TX)) { | ||
| 1604 | ptr = priv->tx_traffic; | ||
| 1605 | pos += scnprintf(buf + pos, bufsz - pos, | ||
| 1606 | "Tx Traffic idx: %u\n", priv->tx_traffic_idx); | ||
| 1607 | for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) { | ||
| 1608 | for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16; | ||
| 1609 | entry++, ofs += 16) { | ||
| 1610 | pos += scnprintf(buf + pos, bufsz - pos, | ||
| 1611 | "0x%.4x ", ofs); | ||
| 1612 | hex_dump_to_buffer(ptr + ofs, 16, 16, 2, | ||
| 1613 | buf + pos, bufsz - pos, 0); | ||
| 1614 | pos += strlen(buf + pos); | ||
| 1615 | if (bufsz - pos > 0) | ||
| 1616 | buf[pos++] = '\n'; | ||
| 1617 | } | ||
| 1618 | } | ||
| 1619 | } | ||
| 1620 | |||
| 1621 | pos += scnprintf(buf + pos, bufsz - pos, "Rx Queue\n"); | ||
| 1622 | pos += scnprintf(buf + pos, bufsz - pos, | ||
| 1623 | "read: %u, write: %u\n", | ||
| 1624 | rxq->read, rxq->write); | ||
| 1625 | |||
| 1626 | if (priv->rx_traffic && | ||
| 1627 | (iwl_get_debug_level(trans->shrd) & IWL_DL_RX)) { | ||
| 1628 | ptr = priv->rx_traffic; | ||
| 1629 | pos += scnprintf(buf + pos, bufsz - pos, | ||
| 1630 | "Rx Traffic idx: %u\n", priv->rx_traffic_idx); | ||
| 1631 | for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) { | ||
| 1632 | for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16; | ||
| 1633 | entry++, ofs += 16) { | ||
| 1634 | pos += scnprintf(buf + pos, bufsz - pos, | ||
| 1635 | "0x%.4x ", ofs); | ||
| 1636 | hex_dump_to_buffer(ptr + ofs, 16, 16, 2, | ||
| 1637 | buf + pos, bufsz - pos, 0); | ||
| 1638 | pos += strlen(buf + pos); | ||
| 1639 | if (bufsz - pos > 0) | ||
| 1640 | buf[pos++] = '\n'; | ||
| 1641 | } | ||
| 1642 | } | ||
| 1643 | } | ||
| 1644 | |||
| 1645 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | ||
| 1646 | kfree(buf); | ||
| 1647 | return ret; | ||
| 1648 | } | ||
| 1649 | |||
| 1650 | static ssize_t iwl_dbgfs_traffic_log_write(struct file *file, | ||
| 1651 | const char __user *user_buf, | ||
| 1652 | size_t count, loff_t *ppos) | ||
| 1653 | { | ||
| 1654 | struct iwl_trans *trans = file->private_data; | ||
| 1655 | char buf[8]; | ||
| 1656 | int buf_size; | ||
| 1657 | int traffic_log; | ||
| 1658 | |||
| 1659 | memset(buf, 0, sizeof(buf)); | ||
| 1660 | buf_size = min(count, sizeof(buf) - 1); | ||
| 1661 | if (copy_from_user(buf, user_buf, buf_size)) | ||
| 1662 | return -EFAULT; | ||
| 1663 | if (sscanf(buf, "%d", &traffic_log) != 1) | ||
| 1664 | return -EFAULT; | ||
| 1665 | if (traffic_log == 0) | ||
| 1666 | iwl_reset_traffic_log(priv(trans)); | ||
| 1667 | |||
| 1668 | return count; | ||
| 1669 | } | ||
| 1670 | |||
| 1671 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, | 1690 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
| 1672 | char __user *user_buf, | 1691 | char __user *user_buf, |
| 1673 | size_t count, loff_t *ppos) | 1692 | size_t count, loff_t *ppos) |
| 1674 | { | 1693 | { |
| 1675 | struct iwl_trans *trans = file->private_data; | 1694 | struct iwl_trans *trans = file->private_data; |
| 1676 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | 1695 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1677 | struct iwl_priv *priv = priv(trans); | ||
| 1678 | struct iwl_tx_queue *txq; | 1696 | struct iwl_tx_queue *txq; |
| 1679 | struct iwl_queue *q; | 1697 | struct iwl_queue *q; |
| 1680 | char *buf; | 1698 | char *buf; |
| @@ -1684,7 +1702,7 @@ static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, | |||
| 1684 | const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num; | 1702 | const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num; |
| 1685 | 1703 | ||
| 1686 | if (!trans_pcie->txq) { | 1704 | if (!trans_pcie->txq) { |
| 1687 | IWL_ERR(priv, "txq not ready\n"); | 1705 | IWL_ERR(trans, "txq not ready\n"); |
| 1688 | return -EAGAIN; | 1706 | return -EAGAIN; |
| 1689 | } | 1707 | } |
| 1690 | buf = kzalloc(bufsz, GFP_KERNEL); | 1708 | buf = kzalloc(bufsz, GFP_KERNEL); |
| @@ -1864,75 +1882,6 @@ static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |||
| 1864 | return count; | 1882 | return count; |
| 1865 | } | 1883 | } |
| 1866 | 1884 | ||
| 1867 | static const char *get_csr_string(int cmd) | ||
| 1868 | { | ||
| 1869 | switch (cmd) { | ||
| 1870 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | ||
| 1871 | IWL_CMD(CSR_INT_COALESCING); | ||
| 1872 | IWL_CMD(CSR_INT); | ||
| 1873 | IWL_CMD(CSR_INT_MASK); | ||
| 1874 | IWL_CMD(CSR_FH_INT_STATUS); | ||
| 1875 | IWL_CMD(CSR_GPIO_IN); | ||
| 1876 | IWL_CMD(CSR_RESET); | ||
| 1877 | IWL_CMD(CSR_GP_CNTRL); | ||
| 1878 | IWL_CMD(CSR_HW_REV); | ||
| 1879 | IWL_CMD(CSR_EEPROM_REG); | ||
| 1880 | IWL_CMD(CSR_EEPROM_GP); | ||
| 1881 | IWL_CMD(CSR_OTP_GP_REG); | ||
| 1882 | IWL_CMD(CSR_GIO_REG); | ||
| 1883 | IWL_CMD(CSR_GP_UCODE_REG); | ||
| 1884 | IWL_CMD(CSR_GP_DRIVER_REG); | ||
| 1885 | IWL_CMD(CSR_UCODE_DRV_GP1); | ||
| 1886 | IWL_CMD(CSR_UCODE_DRV_GP2); | ||
| 1887 | IWL_CMD(CSR_LED_REG); | ||
| 1888 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | ||
| 1889 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | ||
| 1890 | IWL_CMD(CSR_ANA_PLL_CFG); | ||
| 1891 | IWL_CMD(CSR_HW_REV_WA_REG); | ||
| 1892 | IWL_CMD(CSR_DBG_HPET_MEM_REG); | ||
| 1893 | default: | ||
| 1894 | return "UNKNOWN"; | ||
| 1895 | } | ||
| 1896 | } | ||
| 1897 | |||
| 1898 | void iwl_dump_csr(struct iwl_trans *trans) | ||
| 1899 | { | ||
| 1900 | int i; | ||
| 1901 | static const u32 csr_tbl[] = { | ||
| 1902 | CSR_HW_IF_CONFIG_REG, | ||
| 1903 | CSR_INT_COALESCING, | ||
| 1904 | CSR_INT, | ||
| 1905 | CSR_INT_MASK, | ||
| 1906 | CSR_FH_INT_STATUS, | ||
| 1907 | CSR_GPIO_IN, | ||
| 1908 | CSR_RESET, | ||
| 1909 | CSR_GP_CNTRL, | ||
| 1910 | CSR_HW_REV, | ||
| 1911 | CSR_EEPROM_REG, | ||
| 1912 | CSR_EEPROM_GP, | ||
| 1913 | CSR_OTP_GP_REG, | ||
| 1914 | CSR_GIO_REG, | ||
| 1915 | CSR_GP_UCODE_REG, | ||
| 1916 | CSR_GP_DRIVER_REG, | ||
| 1917 | CSR_UCODE_DRV_GP1, | ||
| 1918 | CSR_UCODE_DRV_GP2, | ||
| 1919 | CSR_LED_REG, | ||
| 1920 | CSR_DRAM_INT_TBL_REG, | ||
| 1921 | CSR_GIO_CHICKEN_BITS, | ||
| 1922 | CSR_ANA_PLL_CFG, | ||
| 1923 | CSR_HW_REV_WA_REG, | ||
| 1924 | CSR_DBG_HPET_MEM_REG | ||
| 1925 | }; | ||
| 1926 | IWL_ERR(trans, "CSR values:\n"); | ||
| 1927 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | ||
| 1928 | "CSR_INT_PERIODIC_REG)\n"); | ||
| 1929 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | ||
| 1930 | IWL_ERR(trans, " %25s: 0X%08x\n", | ||
| 1931 | get_csr_string(csr_tbl[i]), | ||
| 1932 | iwl_read32(bus(trans), csr_tbl[i])); | ||
| 1933 | } | ||
| 1934 | } | ||
| 1935 | |||
| 1936 | static ssize_t iwl_dbgfs_csr_write(struct file *file, | 1885 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
| 1937 | const char __user *user_buf, | 1886 | const char __user *user_buf, |
| 1938 | size_t count, loff_t *ppos) | 1887 | size_t count, loff_t *ppos) |
| @@ -1954,67 +1903,6 @@ static ssize_t iwl_dbgfs_csr_write(struct file *file, | |||
| 1954 | return count; | 1903 | return count; |
| 1955 | } | 1904 | } |
| 1956 | 1905 | ||
| 1957 | static const char *get_fh_string(int cmd) | ||
| 1958 | { | ||
| 1959 | switch (cmd) { | ||
| 1960 | IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG); | ||
| 1961 | IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG); | ||
| 1962 | IWL_CMD(FH_RSCSR_CHNL0_WPTR); | ||
| 1963 | IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG); | ||
| 1964 | IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG); | ||
| 1965 | IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG); | ||
| 1966 | IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); | ||
| 1967 | IWL_CMD(FH_TSSR_TX_STATUS_REG); | ||
| 1968 | IWL_CMD(FH_TSSR_TX_ERROR_REG); | ||
| 1969 | default: | ||
| 1970 | return "UNKNOWN"; | ||
| 1971 | } | ||
| 1972 | } | ||
| 1973 | |||
| 1974 | int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display) | ||
| 1975 | { | ||
| 1976 | int i; | ||
| 1977 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
| 1978 | int pos = 0; | ||
| 1979 | size_t bufsz = 0; | ||
| 1980 | #endif | ||
| 1981 | static const u32 fh_tbl[] = { | ||
| 1982 | FH_RSCSR_CHNL0_STTS_WPTR_REG, | ||
| 1983 | FH_RSCSR_CHNL0_RBDCB_BASE_REG, | ||
| 1984 | FH_RSCSR_CHNL0_WPTR, | ||
| 1985 | FH_MEM_RCSR_CHNL0_CONFIG_REG, | ||
| 1986 | FH_MEM_RSSR_SHARED_CTRL_REG, | ||
| 1987 | FH_MEM_RSSR_RX_STATUS_REG, | ||
| 1988 | FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, | ||
| 1989 | FH_TSSR_TX_STATUS_REG, | ||
| 1990 | FH_TSSR_TX_ERROR_REG | ||
| 1991 | }; | ||
| 1992 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
| 1993 | if (display) { | ||
| 1994 | bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; | ||
| 1995 | *buf = kmalloc(bufsz, GFP_KERNEL); | ||
| 1996 | if (!*buf) | ||
| 1997 | return -ENOMEM; | ||
| 1998 | pos += scnprintf(*buf + pos, bufsz - pos, | ||
| 1999 | "FH register values:\n"); | ||
| 2000 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { | ||
| 2001 | pos += scnprintf(*buf + pos, bufsz - pos, | ||
| 2002 | " %34s: 0X%08x\n", | ||
| 2003 | get_fh_string(fh_tbl[i]), | ||
| 2004 | iwl_read_direct32(bus(trans), fh_tbl[i])); | ||
| 2005 | } | ||
| 2006 | return pos; | ||
| 2007 | } | ||
| 2008 | #endif | ||
| 2009 | IWL_ERR(trans, "FH register values:\n"); | ||
| 2010 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { | ||
| 2011 | IWL_ERR(trans, " %34s: 0X%08x\n", | ||
| 2012 | get_fh_string(fh_tbl[i]), | ||
| 2013 | iwl_read_direct32(bus(trans), fh_tbl[i])); | ||
| 2014 | } | ||
| 2015 | return 0; | ||
| 2016 | } | ||
| 2017 | |||
| 2018 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, | 1906 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
| 2019 | char __user *user_buf, | 1907 | char __user *user_buf, |
| 2020 | size_t count, loff_t *ppos) | 1908 | size_t count, loff_t *ppos) |
| @@ -2034,7 +1922,6 @@ static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, | |||
| 2034 | return ret; | 1922 | return ret; |
| 2035 | } | 1923 | } |
| 2036 | 1924 | ||
| 2037 | DEBUGFS_READ_WRITE_FILE_OPS(traffic_log); | ||
| 2038 | DEBUGFS_READ_WRITE_FILE_OPS(log_event); | 1925 | DEBUGFS_READ_WRITE_FILE_OPS(log_event); |
| 2039 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); | 1926 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
| 2040 | DEBUGFS_READ_FILE_OPS(fh_reg); | 1927 | DEBUGFS_READ_FILE_OPS(fh_reg); |
| @@ -2049,7 +1936,6 @@ DEBUGFS_WRITE_FILE_OPS(csr); | |||
| 2049 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | 1936 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, |
| 2050 | struct dentry *dir) | 1937 | struct dentry *dir) |
| 2051 | { | 1938 | { |
| 2052 | DEBUGFS_ADD_FILE(traffic_log, dir, S_IWUSR | S_IRUSR); | ||
| 2053 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); | 1939 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
| 2054 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | 1940 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); |
| 2055 | DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR); | 1941 | DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR); |
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans.h b/drivers/net/wireless/iwlwifi/iwl-trans.h index 7a2daa886dfd..71a6fb05356a 100644 --- a/drivers/net/wireless/iwlwifi/iwl-trans.h +++ b/drivers/net/wireless/iwlwifi/iwl-trans.h | |||
| @@ -73,10 +73,70 @@ | |||
| 73 | * layer */ | 73 | * layer */ |
| 74 | 74 | ||
| 75 | struct iwl_priv; | 75 | struct iwl_priv; |
| 76 | struct iwl_rxon_context; | ||
| 77 | struct iwl_host_cmd; | ||
| 78 | struct iwl_shared; | 76 | struct iwl_shared; |
| 79 | struct iwl_device_cmd; | 77 | |
| 78 | #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) | ||
| 79 | #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ) | ||
| 80 | #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4) | ||
| 81 | |||
| 82 | enum { | ||
| 83 | CMD_SYNC = 0, | ||
| 84 | CMD_ASYNC = BIT(0), | ||
| 85 | CMD_WANT_SKB = BIT(1), | ||
| 86 | CMD_ON_DEMAND = BIT(2), | ||
| 87 | }; | ||
| 88 | |||
| 89 | #define DEF_CMD_PAYLOAD_SIZE 320 | ||
| 90 | |||
| 91 | /** | ||
| 92 | * struct iwl_device_cmd | ||
| 93 | * | ||
| 94 | * For allocation of the command and tx queues, this establishes the overall | ||
| 95 | * size of the largest command we send to uCode, except for commands that | ||
| 96 | * aren't fully copied and use other TFD space. | ||
| 97 | */ | ||
| 98 | struct iwl_device_cmd { | ||
| 99 | struct iwl_cmd_header hdr; /* uCode API */ | ||
| 100 | union { | ||
| 101 | u32 flags; | ||
| 102 | u8 val8; | ||
| 103 | u16 val16; | ||
| 104 | u32 val32; | ||
| 105 | struct iwl_tx_cmd tx; | ||
| 106 | struct iwl6000_channel_switch_cmd chswitch; | ||
| 107 | u8 payload[DEF_CMD_PAYLOAD_SIZE]; | ||
| 108 | } __packed cmd; | ||
| 109 | } __packed; | ||
| 110 | |||
| 111 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) | ||
| 112 | |||
| 113 | #define IWL_MAX_CMD_TFDS 2 | ||
| 114 | |||
| 115 | enum iwl_hcmd_dataflag { | ||
| 116 | IWL_HCMD_DFL_NOCOPY = BIT(0), | ||
| 117 | }; | ||
| 118 | |||
| 119 | /** | ||
| 120 | * struct iwl_host_cmd - Host command to the uCode | ||
| 121 | * @data: array of chunks that composes the data of the host command | ||
| 122 | * @reply_page: pointer to the page that holds the response to the host command | ||
| 123 | * @callback: | ||
| 124 | * @flags: can be CMD_* note CMD_WANT_SKB is incompatible withe CMD_ASYNC | ||
| 125 | * @len: array of the lenths of the chunks in data | ||
| 126 | * @dataflags: | ||
| 127 | * @id: id of the host command | ||
| 128 | */ | ||
| 129 | struct iwl_host_cmd { | ||
| 130 | const void *data[IWL_MAX_CMD_TFDS]; | ||
| 131 | unsigned long reply_page; | ||
| 132 | void (*callback)(struct iwl_shared *shrd, | ||
| 133 | struct iwl_device_cmd *cmd, | ||
| 134 | struct iwl_rx_packet *pkt); | ||
| 135 | u32 flags; | ||
| 136 | u16 len[IWL_MAX_CMD_TFDS]; | ||
| 137 | u8 dataflags[IWL_MAX_CMD_TFDS]; | ||
| 138 | u8 id; | ||
| 139 | }; | ||
| 80 | 140 | ||
| 81 | /** | 141 | /** |
| 82 | * struct iwl_trans_ops - transport specific operations | 142 | * struct iwl_trans_ops - transport specific operations |
diff --git a/drivers/net/wireless/libertas/if_usb.c b/drivers/net/wireless/libertas/if_usb.c index 0c846f5a646a..8147f1e2a0b0 100644 --- a/drivers/net/wireless/libertas/if_usb.c +++ b/drivers/net/wireless/libertas/if_usb.c | |||
| @@ -973,6 +973,23 @@ static const struct { | |||
| 973 | { MODEL_8682, "libertas/usb8682.bin" } | 973 | { MODEL_8682, "libertas/usb8682.bin" } |
| 974 | }; | 974 | }; |
| 975 | 975 | ||
| 976 | #ifdef CONFIG_OLPC | ||
| 977 | |||
| 978 | static int try_olpc_fw(struct if_usb_card *cardp) | ||
| 979 | { | ||
| 980 | int retval = -ENOENT; | ||
| 981 | |||
| 982 | /* try the OLPC firmware first; fall back to fw_table list */ | ||
| 983 | if (machine_is_olpc() && cardp->model == MODEL_8388) | ||
| 984 | retval = request_firmware(&cardp->fw, | ||
| 985 | "libertas/usb8388_olpc.bin", &cardp->udev->dev); | ||
| 986 | return retval; | ||
| 987 | } | ||
| 988 | |||
| 989 | #else | ||
| 990 | static int try_olpc_fw(struct if_usb_card *cardp) { return -ENOENT; } | ||
| 991 | #endif /* !CONFIG_OLPC */ | ||
| 992 | |||
| 976 | static int get_fw(struct if_usb_card *cardp, const char *fwname) | 993 | static int get_fw(struct if_usb_card *cardp, const char *fwname) |
| 977 | { | 994 | { |
| 978 | int i; | 995 | int i; |
| @@ -981,6 +998,10 @@ static int get_fw(struct if_usb_card *cardp, const char *fwname) | |||
| 981 | if (fwname) | 998 | if (fwname) |
| 982 | return request_firmware(&cardp->fw, fwname, &cardp->udev->dev); | 999 | return request_firmware(&cardp->fw, fwname, &cardp->udev->dev); |
| 983 | 1000 | ||
| 1001 | /* Handle OLPC firmware */ | ||
| 1002 | if (try_olpc_fw(cardp) == 0) | ||
| 1003 | return 0; | ||
| 1004 | |||
| 984 | /* Otherwise search for firmware to use */ | 1005 | /* Otherwise search for firmware to use */ |
| 985 | for (i = 0; i < ARRAY_SIZE(fw_table); i++) { | 1006 | for (i = 0; i < ARRAY_SIZE(fw_table); i++) { |
| 986 | if (fw_table[i].model != cardp->model) | 1007 | if (fw_table[i].model != cardp->model) |
diff --git a/drivers/net/wireless/mwifiex/join.c b/drivers/net/wireless/mwifiex/join.c index 5cdad92277fa..62b4c2938608 100644 --- a/drivers/net/wireless/mwifiex/join.c +++ b/drivers/net/wireless/mwifiex/join.c | |||
| @@ -147,13 +147,12 @@ static int mwifiex_get_common_rates(struct mwifiex_private *priv, u8 *rate1, | |||
| 147 | u8 *ptr = rate1, *tmp; | 147 | u8 *ptr = rate1, *tmp; |
| 148 | u32 i, j; | 148 | u32 i, j; |
| 149 | 149 | ||
| 150 | tmp = kmalloc(rate1_size, GFP_KERNEL); | 150 | tmp = kmemdup(rate1, rate1_size, GFP_KERNEL); |
| 151 | if (!tmp) { | 151 | if (!tmp) { |
| 152 | dev_err(priv->adapter->dev, "failed to alloc tmp buf\n"); | 152 | dev_err(priv->adapter->dev, "failed to alloc tmp buf\n"); |
| 153 | return -ENOMEM; | 153 | return -ENOMEM; |
| 154 | } | 154 | } |
| 155 | 155 | ||
| 156 | memcpy(tmp, rate1, rate1_size); | ||
| 157 | memset(rate1, 0, rate1_size); | 156 | memset(rate1, 0, rate1_size); |
| 158 | 157 | ||
| 159 | for (i = 0; rate2[i] && i < rate2_size; i++) { | 158 | for (i = 0; rate2[i] && i < rate2_size; i++) { |
diff --git a/drivers/net/wireless/mwifiex/scan.c b/drivers/net/wireless/mwifiex/scan.c index 37ca2f90ad63..8d8588db1cd9 100644 --- a/drivers/net/wireless/mwifiex/scan.c +++ b/drivers/net/wireless/mwifiex/scan.c | |||
| @@ -1479,12 +1479,12 @@ mwifiex_update_curr_bss_params(struct mwifiex_private *priv, | |||
| 1479 | dev_err(priv->adapter->dev, " failed to alloc bss_desc\n"); | 1479 | dev_err(priv->adapter->dev, " failed to alloc bss_desc\n"); |
| 1480 | return -ENOMEM; | 1480 | return -ENOMEM; |
| 1481 | } | 1481 | } |
| 1482 | beacon_ie = kzalloc(ie_len, GFP_KERNEL); | 1482 | |
| 1483 | beacon_ie = kmemdup(ie_buf, ie_len, GFP_KERNEL); | ||
| 1483 | if (!beacon_ie) { | 1484 | if (!beacon_ie) { |
| 1484 | dev_err(priv->adapter->dev, " failed to alloc beacon_ie\n"); | 1485 | dev_err(priv->adapter->dev, " failed to alloc beacon_ie\n"); |
| 1485 | return -ENOMEM; | 1486 | return -ENOMEM; |
| 1486 | } | 1487 | } |
| 1487 | memcpy(beacon_ie, ie_buf, ie_len); | ||
| 1488 | 1488 | ||
| 1489 | ret = mwifiex_fill_new_bss_desc(priv, bssid, rssi, beacon_ie, | 1489 | ret = mwifiex_fill_new_bss_desc(priv, bssid, rssi, beacon_ie, |
| 1490 | ie_len, beacon_period, | 1490 | ie_len, beacon_period, |
| @@ -1986,7 +1986,7 @@ mwifiex_save_curr_bcn(struct mwifiex_private *priv) | |||
| 1986 | priv->curr_bcn_size = curr_bss->beacon_buf_size; | 1986 | priv->curr_bcn_size = curr_bss->beacon_buf_size; |
| 1987 | 1987 | ||
| 1988 | kfree(priv->curr_bcn_buf); | 1988 | kfree(priv->curr_bcn_buf); |
| 1989 | priv->curr_bcn_buf = kzalloc(curr_bss->beacon_buf_size, | 1989 | priv->curr_bcn_buf = kmalloc(curr_bss->beacon_buf_size, |
| 1990 | GFP_KERNEL); | 1990 | GFP_KERNEL); |
| 1991 | if (!priv->curr_bcn_buf) { | 1991 | if (!priv->curr_bcn_buf) { |
| 1992 | dev_err(priv->adapter->dev, | 1992 | dev_err(priv->adapter->dev, |
diff --git a/drivers/net/wireless/mwifiex/sta_ioctl.c b/drivers/net/wireless/mwifiex/sta_ioctl.c index 3fca219bcfb6..eb569fa9adba 100644 --- a/drivers/net/wireless/mwifiex/sta_ioctl.c +++ b/drivers/net/wireless/mwifiex/sta_ioctl.c | |||
| @@ -199,13 +199,14 @@ int mwifiex_bss_start(struct mwifiex_private *priv, struct cfg80211_bss *bss, | |||
| 199 | dev_err(priv->adapter->dev, " failed to alloc bss_desc\n"); | 199 | dev_err(priv->adapter->dev, " failed to alloc bss_desc\n"); |
| 200 | return -ENOMEM; | 200 | return -ENOMEM; |
| 201 | } | 201 | } |
| 202 | beacon_ie = kzalloc(bss->len_beacon_ies, GFP_KERNEL); | 202 | |
| 203 | beacon_ie = kmemdup(bss->information_elements, | ||
| 204 | bss->len_beacon_ies, GFP_KERNEL); | ||
| 203 | if (!beacon_ie) { | 205 | if (!beacon_ie) { |
| 204 | dev_err(priv->adapter->dev, " failed to alloc bss_desc\n"); | 206 | dev_err(priv->adapter->dev, " failed to alloc beacon_ie\n"); |
| 205 | return -ENOMEM; | 207 | return -ENOMEM; |
| 206 | } | 208 | } |
| 207 | memcpy(beacon_ie, bss->information_elements, | 209 | |
| 208 | bss->len_beacon_ies); | ||
| 209 | ret = mwifiex_fill_new_bss_desc(priv, bss->bssid, bss->signal, | 210 | ret = mwifiex_fill_new_bss_desc(priv, bss->bssid, bss->signal, |
| 210 | beacon_ie, bss->len_beacon_ies, | 211 | beacon_ie, bss->len_beacon_ies, |
| 211 | bss->beacon_interval, | 212 | bss->beacon_interval, |
diff --git a/drivers/net/wireless/mwl8k.c b/drivers/net/wireless/mwl8k.c index 771280a47ea7..ea1395aafa39 100644 --- a/drivers/net/wireless/mwl8k.c +++ b/drivers/net/wireless/mwl8k.c | |||
| @@ -5501,6 +5501,14 @@ static int mwl8k_firmware_load_success(struct mwl8k_priv *priv) | |||
| 5501 | 5501 | ||
| 5502 | /* Set rssi values to dBm */ | 5502 | /* Set rssi values to dBm */ |
| 5503 | hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_HAS_RATE_CONTROL; | 5503 | hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_HAS_RATE_CONTROL; |
| 5504 | |||
| 5505 | /* | ||
| 5506 | * Ask mac80211 to not to trigger PS mode | ||
| 5507 | * based on PM bit of incoming frames. | ||
| 5508 | */ | ||
| 5509 | if (priv->ap_fw) | ||
| 5510 | hw->flags |= IEEE80211_HW_AP_LINK_PS; | ||
| 5511 | |||
| 5504 | hw->vif_data_size = sizeof(struct mwl8k_vif); | 5512 | hw->vif_data_size = sizeof(struct mwl8k_vif); |
| 5505 | hw->sta_data_size = sizeof(struct mwl8k_sta); | 5513 | hw->sta_data_size = sizeof(struct mwl8k_sta); |
| 5506 | 5514 | ||
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h index c69a7d71f4ca..4778620347c4 100644 --- a/drivers/net/wireless/rt2x00/rt2800.h +++ b/drivers/net/wireless/rt2x00/rt2800.h | |||
| @@ -664,6 +664,9 @@ | |||
| 664 | 664 | ||
| 665 | /* | 665 | /* |
| 666 | * LED_CFG: LED control | 666 | * LED_CFG: LED control |
| 667 | * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1) | ||
| 668 | * OFF_PERIOD: LED inactive time (ms) during TX (only used for LED mode 1) | ||
| 669 | * SLOW_BLINK_PERIOD: LED blink interval in seconds (only used for LED mode 2) | ||
| 667 | * color LED's: | 670 | * color LED's: |
| 668 | * 0: off | 671 | * 0: off |
| 669 | * 1: blinking upon TX2 | 672 | * 1: blinking upon TX2 |
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c index ef67f6786a84..a5ddb39ca4a0 100644 --- a/drivers/net/wireless/rt2x00/rt2800lib.c +++ b/drivers/net/wireless/rt2x00/rt2800lib.c | |||
| @@ -493,7 +493,7 @@ void rt2800_write_tx_data(struct queue_entry *entry, | |||
| 493 | rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); | 493 | rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); |
| 494 | rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, | 494 | rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, |
| 495 | test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? | 495 | test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? |
| 496 | txdesc->key_idx : 0xff); | 496 | txdesc->key_idx : txdesc->u.ht.wcid); |
| 497 | rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, | 497 | rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, |
| 498 | txdesc->length); | 498 | txdesc->length); |
| 499 | rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); | 499 | rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); |
| @@ -601,7 +601,7 @@ void rt2800_process_rxwi(struct queue_entry *entry, | |||
| 601 | } | 601 | } |
| 602 | EXPORT_SYMBOL_GPL(rt2800_process_rxwi); | 602 | EXPORT_SYMBOL_GPL(rt2800_process_rxwi); |
| 603 | 603 | ||
| 604 | void rt2800_txdone_entry(struct queue_entry *entry, u32 status) | 604 | void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi) |
| 605 | { | 605 | { |
| 606 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | 606 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
| 607 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | 607 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
| @@ -609,13 +609,11 @@ void rt2800_txdone_entry(struct queue_entry *entry, u32 status) | |||
| 609 | u32 word; | 609 | u32 word; |
| 610 | u16 mcs, real_mcs; | 610 | u16 mcs, real_mcs; |
| 611 | int aggr, ampdu; | 611 | int aggr, ampdu; |
| 612 | __le32 *txwi; | ||
| 613 | 612 | ||
| 614 | /* | 613 | /* |
| 615 | * Obtain the status about this packet. | 614 | * Obtain the status about this packet. |
| 616 | */ | 615 | */ |
| 617 | txdesc.flags = 0; | 616 | txdesc.flags = 0; |
| 618 | txwi = rt2800_drv_get_txwi(entry); | ||
| 619 | rt2x00_desc_read(txwi, 0, &word); | 617 | rt2x00_desc_read(txwi, 0, &word); |
| 620 | 618 | ||
| 621 | mcs = rt2x00_get_field32(word, TXWI_W0_MCS); | 619 | mcs = rt2x00_get_field32(word, TXWI_W0_MCS); |
| @@ -899,28 +897,12 @@ static void rt2800_brightness_set(struct led_classdev *led_cdev, | |||
| 899 | } | 897 | } |
| 900 | } | 898 | } |
| 901 | 899 | ||
| 902 | static int rt2800_blink_set(struct led_classdev *led_cdev, | ||
| 903 | unsigned long *delay_on, unsigned long *delay_off) | ||
| 904 | { | ||
| 905 | struct rt2x00_led *led = | ||
| 906 | container_of(led_cdev, struct rt2x00_led, led_dev); | ||
| 907 | u32 reg; | ||
| 908 | |||
| 909 | rt2800_register_read(led->rt2x00dev, LED_CFG, ®); | ||
| 910 | rt2x00_set_field32(®, LED_CFG_ON_PERIOD, *delay_on); | ||
| 911 | rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, *delay_off); | ||
| 912 | rt2800_register_write(led->rt2x00dev, LED_CFG, reg); | ||
| 913 | |||
| 914 | return 0; | ||
| 915 | } | ||
| 916 | |||
| 917 | static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, | 900 | static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, |
| 918 | struct rt2x00_led *led, enum led_type type) | 901 | struct rt2x00_led *led, enum led_type type) |
| 919 | { | 902 | { |
| 920 | led->rt2x00dev = rt2x00dev; | 903 | led->rt2x00dev = rt2x00dev; |
| 921 | led->type = type; | 904 | led->type = type; |
| 922 | led->led_dev.brightness_set = rt2800_brightness_set; | 905 | led->led_dev.brightness_set = rt2800_brightness_set; |
| 923 | led->led_dev.blink_set = rt2800_blink_set; | ||
| 924 | led->flags = LED_INITIALIZED; | 906 | led->flags = LED_INITIALIZED; |
| 925 | } | 907 | } |
| 926 | #endif /* CONFIG_RT2X00_LIB_LEDS */ | 908 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
| @@ -928,11 +910,51 @@ static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, | |||
| 928 | /* | 910 | /* |
| 929 | * Configuration handlers. | 911 | * Configuration handlers. |
| 930 | */ | 912 | */ |
| 931 | static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev, | 913 | static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, |
| 932 | struct rt2x00lib_crypto *crypto, | 914 | const u8 *address, |
| 933 | struct ieee80211_key_conf *key) | 915 | int wcid) |
| 934 | { | 916 | { |
| 935 | struct mac_wcid_entry wcid_entry; | 917 | struct mac_wcid_entry wcid_entry; |
| 918 | u32 offset; | ||
| 919 | |||
| 920 | offset = MAC_WCID_ENTRY(wcid); | ||
| 921 | |||
| 922 | memset(&wcid_entry, 0xff, sizeof(wcid_entry)); | ||
| 923 | if (address) | ||
| 924 | memcpy(wcid_entry.mac, address, ETH_ALEN); | ||
| 925 | |||
| 926 | rt2800_register_multiwrite(rt2x00dev, offset, | ||
| 927 | &wcid_entry, sizeof(wcid_entry)); | ||
| 928 | } | ||
| 929 | |||
| 930 | static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) | ||
| 931 | { | ||
| 932 | u32 offset; | ||
| 933 | offset = MAC_WCID_ATTR_ENTRY(wcid); | ||
| 934 | rt2800_register_write(rt2x00dev, offset, 0); | ||
| 935 | } | ||
| 936 | |||
| 937 | static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, | ||
| 938 | int wcid, u32 bssidx) | ||
| 939 | { | ||
| 940 | u32 offset = MAC_WCID_ATTR_ENTRY(wcid); | ||
| 941 | u32 reg; | ||
| 942 | |||
| 943 | /* | ||
| 944 | * The BSS Idx numbers is split in a main value of 3 bits, | ||
| 945 | * and a extended field for adding one additional bit to the value. | ||
| 946 | */ | ||
| 947 | rt2800_register_read(rt2x00dev, offset, ®); | ||
| 948 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); | ||
| 949 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, | ||
| 950 | (bssidx & 0x8) >> 3); | ||
| 951 | rt2800_register_write(rt2x00dev, offset, reg); | ||
| 952 | } | ||
| 953 | |||
| 954 | static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, | ||
| 955 | struct rt2x00lib_crypto *crypto, | ||
| 956 | struct ieee80211_key_conf *key) | ||
| 957 | { | ||
| 936 | struct mac_iveiv_entry iveiv_entry; | 958 | struct mac_iveiv_entry iveiv_entry; |
| 937 | u32 offset; | 959 | u32 offset; |
| 938 | u32 reg; | 960 | u32 reg; |
| @@ -952,14 +974,16 @@ static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev, | |||
| 952 | (crypto->cipher & 0x7)); | 974 | (crypto->cipher & 0x7)); |
| 953 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, | 975 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, |
| 954 | (crypto->cipher & 0x8) >> 3); | 976 | (crypto->cipher & 0x8) >> 3); |
| 955 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, | ||
| 956 | (crypto->bssidx & 0x7)); | ||
| 957 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, | ||
| 958 | (crypto->bssidx & 0x8) >> 3); | ||
| 959 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); | 977 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); |
| 960 | rt2800_register_write(rt2x00dev, offset, reg); | 978 | rt2800_register_write(rt2x00dev, offset, reg); |
| 961 | } else { | 979 | } else { |
| 962 | rt2800_register_write(rt2x00dev, offset, 0); | 980 | /* Delete the cipher without touching the bssidx */ |
| 981 | rt2800_register_read(rt2x00dev, offset, ®); | ||
| 982 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); | ||
| 983 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); | ||
| 984 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); | ||
| 985 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); | ||
| 986 | rt2800_register_write(rt2x00dev, offset, reg); | ||
| 963 | } | 987 | } |
| 964 | 988 | ||
| 965 | offset = MAC_IVEIV_ENTRY(key->hw_key_idx); | 989 | offset = MAC_IVEIV_ENTRY(key->hw_key_idx); |
| @@ -972,14 +996,6 @@ static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev, | |||
| 972 | iveiv_entry.iv[3] |= key->keyidx << 6; | 996 | iveiv_entry.iv[3] |= key->keyidx << 6; |
| 973 | rt2800_register_multiwrite(rt2x00dev, offset, | 997 | rt2800_register_multiwrite(rt2x00dev, offset, |
| 974 | &iveiv_entry, sizeof(iveiv_entry)); | 998 | &iveiv_entry, sizeof(iveiv_entry)); |
| 975 | |||
| 976 | offset = MAC_WCID_ENTRY(key->hw_key_idx); | ||
| 977 | |||
| 978 | memset(&wcid_entry, 0, sizeof(wcid_entry)); | ||
| 979 | if (crypto->cmd == SET_KEY) | ||
| 980 | memcpy(wcid_entry.mac, crypto->address, ETH_ALEN); | ||
| 981 | rt2800_register_multiwrite(rt2x00dev, offset, | ||
| 982 | &wcid_entry, sizeof(wcid_entry)); | ||
| 983 | } | 999 | } |
| 984 | 1000 | ||
| 985 | int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, | 1001 | int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, |
| @@ -1026,20 +1042,24 @@ int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, | |||
| 1026 | /* | 1042 | /* |
| 1027 | * Update WCID information | 1043 | * Update WCID information |
| 1028 | */ | 1044 | */ |
| 1029 | rt2800_config_wcid_attr(rt2x00dev, crypto, key); | 1045 | rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); |
| 1046 | rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, | ||
| 1047 | crypto->bssidx); | ||
| 1048 | rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); | ||
| 1030 | 1049 | ||
| 1031 | return 0; | 1050 | return 0; |
| 1032 | } | 1051 | } |
| 1033 | EXPORT_SYMBOL_GPL(rt2800_config_shared_key); | 1052 | EXPORT_SYMBOL_GPL(rt2800_config_shared_key); |
| 1034 | 1053 | ||
| 1035 | static inline int rt2800_find_pairwise_keyslot(struct rt2x00_dev *rt2x00dev) | 1054 | static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev) |
| 1036 | { | 1055 | { |
| 1056 | struct mac_wcid_entry wcid_entry; | ||
| 1037 | int idx; | 1057 | int idx; |
| 1038 | u32 offset, reg; | 1058 | u32 offset; |
| 1039 | 1059 | ||
| 1040 | /* | 1060 | /* |
| 1041 | * Search for the first free pairwise key entry and return the | 1061 | * Search for the first free WCID entry and return the corresponding |
| 1042 | * corresponding index. | 1062 | * index. |
| 1043 | * | 1063 | * |
| 1044 | * Make sure the WCID starts _after_ the last possible shared key | 1064 | * Make sure the WCID starts _after_ the last possible shared key |
| 1045 | * entry (>32). | 1065 | * entry (>32). |
| @@ -1049,11 +1069,17 @@ static inline int rt2800_find_pairwise_keyslot(struct rt2x00_dev *rt2x00dev) | |||
| 1049 | * first 222 entries. | 1069 | * first 222 entries. |
| 1050 | */ | 1070 | */ |
| 1051 | for (idx = 33; idx <= 222; idx++) { | 1071 | for (idx = 33; idx <= 222; idx++) { |
| 1052 | offset = MAC_WCID_ATTR_ENTRY(idx); | 1072 | offset = MAC_WCID_ENTRY(idx); |
| 1053 | rt2800_register_read(rt2x00dev, offset, ®); | 1073 | rt2800_register_multiread(rt2x00dev, offset, &wcid_entry, |
| 1054 | if (!reg) | 1074 | sizeof(wcid_entry)); |
| 1075 | if (is_broadcast_ether_addr(wcid_entry.mac)) | ||
| 1055 | return idx; | 1076 | return idx; |
| 1056 | } | 1077 | } |
| 1078 | |||
| 1079 | /* | ||
| 1080 | * Use -1 to indicate that we don't have any more space in the WCID | ||
| 1081 | * table. | ||
| 1082 | */ | ||
| 1057 | return -1; | 1083 | return -1; |
| 1058 | } | 1084 | } |
| 1059 | 1085 | ||
| @@ -1063,13 +1089,15 @@ int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, | |||
| 1063 | { | 1089 | { |
| 1064 | struct hw_key_entry key_entry; | 1090 | struct hw_key_entry key_entry; |
| 1065 | u32 offset; | 1091 | u32 offset; |
| 1066 | int idx; | ||
| 1067 | 1092 | ||
| 1068 | if (crypto->cmd == SET_KEY) { | 1093 | if (crypto->cmd == SET_KEY) { |
| 1069 | idx = rt2800_find_pairwise_keyslot(rt2x00dev); | 1094 | /* |
| 1070 | if (idx < 0) | 1095 | * Allow key configuration only for STAs that are |
| 1096 | * known by the hw. | ||
| 1097 | */ | ||
| 1098 | if (crypto->wcid < 0) | ||
| 1071 | return -ENOSPC; | 1099 | return -ENOSPC; |
| 1072 | key->hw_key_idx = idx; | 1100 | key->hw_key_idx = crypto->wcid; |
| 1073 | 1101 | ||
| 1074 | memcpy(key_entry.key, crypto->key, | 1102 | memcpy(key_entry.key, crypto->key, |
| 1075 | sizeof(key_entry.key)); | 1103 | sizeof(key_entry.key)); |
| @@ -1086,12 +1114,59 @@ int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, | |||
| 1086 | /* | 1114 | /* |
| 1087 | * Update WCID information | 1115 | * Update WCID information |
| 1088 | */ | 1116 | */ |
| 1089 | rt2800_config_wcid_attr(rt2x00dev, crypto, key); | 1117 | rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); |
| 1090 | 1118 | ||
| 1091 | return 0; | 1119 | return 0; |
| 1092 | } | 1120 | } |
| 1093 | EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); | 1121 | EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); |
| 1094 | 1122 | ||
| 1123 | int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif, | ||
| 1124 | struct ieee80211_sta *sta) | ||
| 1125 | { | ||
| 1126 | int wcid; | ||
| 1127 | struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); | ||
| 1128 | |||
| 1129 | /* | ||
| 1130 | * Find next free WCID. | ||
| 1131 | */ | ||
| 1132 | wcid = rt2800_find_wcid(rt2x00dev); | ||
| 1133 | |||
| 1134 | /* | ||
| 1135 | * Store selected wcid even if it is invalid so that we can | ||
| 1136 | * later decide if the STA is uploaded into the hw. | ||
| 1137 | */ | ||
| 1138 | sta_priv->wcid = wcid; | ||
| 1139 | |||
| 1140 | /* | ||
| 1141 | * No space left in the device, however, we can still communicate | ||
| 1142 | * with the STA -> No error. | ||
| 1143 | */ | ||
| 1144 | if (wcid < 0) | ||
| 1145 | return 0; | ||
| 1146 | |||
| 1147 | /* | ||
| 1148 | * Clean up WCID attributes and write STA address to the device. | ||
| 1149 | */ | ||
| 1150 | rt2800_delete_wcid_attr(rt2x00dev, wcid); | ||
| 1151 | rt2800_config_wcid(rt2x00dev, sta->addr, wcid); | ||
| 1152 | rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, | ||
| 1153 | rt2x00lib_get_bssidx(rt2x00dev, vif)); | ||
| 1154 | return 0; | ||
| 1155 | } | ||
| 1156 | EXPORT_SYMBOL_GPL(rt2800_sta_add); | ||
| 1157 | |||
| 1158 | int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid) | ||
| 1159 | { | ||
| 1160 | /* | ||
| 1161 | * Remove WCID entry, no need to clean the attributes as they will | ||
| 1162 | * get renewed when the WCID is reused. | ||
| 1163 | */ | ||
| 1164 | rt2800_config_wcid(rt2x00dev, NULL, wcid); | ||
| 1165 | |||
| 1166 | return 0; | ||
| 1167 | } | ||
| 1168 | EXPORT_SYMBOL_GPL(rt2800_sta_remove); | ||
| 1169 | |||
| 1095 | void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, | 1170 | void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, |
| 1096 | const unsigned int filter_flags) | 1171 | const unsigned int filter_flags) |
| 1097 | { | 1172 | { |
| @@ -2771,11 +2846,8 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) | |||
| 2771 | SHARED_KEY_MODE_ENTRY(i), 0); | 2846 | SHARED_KEY_MODE_ENTRY(i), 0); |
| 2772 | 2847 | ||
| 2773 | for (i = 0; i < 256; i++) { | 2848 | for (i = 0; i < 256; i++) { |
| 2774 | static const u32 wcid[2] = { 0xffffffff, 0x00ffffff }; | 2849 | rt2800_config_wcid(rt2x00dev, NULL, i); |
| 2775 | rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i), | 2850 | rt2800_delete_wcid_attr(rt2x00dev, i); |
| 2776 | wcid, sizeof(wcid)); | ||
| 2777 | |||
| 2778 | rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 0); | ||
| 2779 | rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); | 2851 | rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); |
| 2780 | } | 2852 | } |
| 2781 | 2853 | ||
| @@ -4409,8 +4481,19 @@ int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |||
| 4409 | struct ieee80211_sta *sta, u16 tid, u16 *ssn, | 4481 | struct ieee80211_sta *sta, u16 tid, u16 *ssn, |
| 4410 | u8 buf_size) | 4482 | u8 buf_size) |
| 4411 | { | 4483 | { |
| 4484 | struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; | ||
| 4412 | int ret = 0; | 4485 | int ret = 0; |
| 4413 | 4486 | ||
| 4487 | /* | ||
| 4488 | * Don't allow aggregation for stations the hardware isn't aware | ||
| 4489 | * of because tx status reports for frames to an unknown station | ||
| 4490 | * always contain wcid=255 and thus we can't distinguish between | ||
| 4491 | * multiple stations which leads to unwanted situations when the | ||
| 4492 | * hw reorders frames due to aggregation. | ||
| 4493 | */ | ||
| 4494 | if (sta_priv->wcid < 0) | ||
| 4495 | return 1; | ||
| 4496 | |||
| 4414 | switch (action) { | 4497 | switch (action) { |
| 4415 | case IEEE80211_AMPDU_RX_START: | 4498 | case IEEE80211_AMPDU_RX_START: |
| 4416 | case IEEE80211_AMPDU_RX_STOP: | 4499 | case IEEE80211_AMPDU_RX_STOP: |
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.h b/drivers/net/wireless/rt2x00/rt2800lib.h index 69deb3148ae7..7a2511f6785c 100644 --- a/drivers/net/wireless/rt2x00/rt2800lib.h +++ b/drivers/net/wireless/rt2x00/rt2800lib.h | |||
| @@ -152,7 +152,7 @@ void rt2800_write_tx_data(struct queue_entry *entry, | |||
| 152 | struct txentry_desc *txdesc); | 152 | struct txentry_desc *txdesc); |
| 153 | void rt2800_process_rxwi(struct queue_entry *entry, struct rxdone_entry_desc *txdesc); | 153 | void rt2800_process_rxwi(struct queue_entry *entry, struct rxdone_entry_desc *txdesc); |
| 154 | 154 | ||
| 155 | void rt2800_txdone_entry(struct queue_entry *entry, u32 status); | 155 | void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32* txwi); |
| 156 | 156 | ||
| 157 | void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc); | 157 | void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc); |
| 158 | void rt2800_clear_beacon(struct queue_entry *entry); | 158 | void rt2800_clear_beacon(struct queue_entry *entry); |
| @@ -166,6 +166,9 @@ int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, | |||
| 166 | int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, | 166 | int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, |
| 167 | struct rt2x00lib_crypto *crypto, | 167 | struct rt2x00lib_crypto *crypto, |
| 168 | struct ieee80211_key_conf *key); | 168 | struct ieee80211_key_conf *key); |
| 169 | int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif, | ||
| 170 | struct ieee80211_sta *sta); | ||
| 171 | int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid); | ||
| 169 | void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, | 172 | void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, |
| 170 | const unsigned int filter_flags); | 173 | const unsigned int filter_flags); |
| 171 | void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, | 174 | void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, |
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c index cabf249aa55b..da48c8ac27bd 100644 --- a/drivers/net/wireless/rt2x00/rt2800pci.c +++ b/drivers/net/wireless/rt2x00/rt2800pci.c | |||
| @@ -619,11 +619,11 @@ static void rt2800pci_write_tx_desc(struct queue_entry *entry, | |||
| 619 | /* | 619 | /* |
| 620 | * Initialize TX descriptor | 620 | * Initialize TX descriptor |
| 621 | */ | 621 | */ |
| 622 | rt2x00_desc_read(txd, 0, &word); | 622 | word = 0; |
| 623 | rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma); | 623 | rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma); |
| 624 | rt2x00_desc_write(txd, 0, word); | 624 | rt2x00_desc_write(txd, 0, word); |
| 625 | 625 | ||
| 626 | rt2x00_desc_read(txd, 1, &word); | 626 | word = 0; |
| 627 | rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len); | 627 | rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len); |
| 628 | rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, | 628 | rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, |
| 629 | !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); | 629 | !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); |
| @@ -634,12 +634,12 @@ static void rt2800pci_write_tx_desc(struct queue_entry *entry, | |||
| 634 | rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0); | 634 | rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0); |
| 635 | rt2x00_desc_write(txd, 1, word); | 635 | rt2x00_desc_write(txd, 1, word); |
| 636 | 636 | ||
| 637 | rt2x00_desc_read(txd, 2, &word); | 637 | word = 0; |
| 638 | rt2x00_set_field32(&word, TXD_W2_SD_PTR1, | 638 | rt2x00_set_field32(&word, TXD_W2_SD_PTR1, |
| 639 | skbdesc->skb_dma + TXWI_DESC_SIZE); | 639 | skbdesc->skb_dma + TXWI_DESC_SIZE); |
| 640 | rt2x00_desc_write(txd, 2, word); | 640 | rt2x00_desc_write(txd, 2, word); |
| 641 | 641 | ||
| 642 | rt2x00_desc_read(txd, 3, &word); | 642 | word = 0; |
| 643 | rt2x00_set_field32(&word, TXD_W3_WIV, | 643 | rt2x00_set_field32(&word, TXD_W3_WIV, |
| 644 | !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags)); | 644 | !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags)); |
| 645 | rt2x00_set_field32(&word, TXD_W3_QSEL, 2); | 645 | rt2x00_set_field32(&word, TXD_W3_QSEL, 2); |
| @@ -760,7 +760,7 @@ static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev) | |||
| 760 | } | 760 | } |
| 761 | 761 | ||
| 762 | entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); | 762 | entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); |
| 763 | rt2800_txdone_entry(entry, status); | 763 | rt2800_txdone_entry(entry, status, rt2800pci_get_txwi(entry)); |
| 764 | 764 | ||
| 765 | if (--max_tx_done == 0) | 765 | if (--max_tx_done == 0) |
| 766 | break; | 766 | break; |
| @@ -1015,6 +1015,8 @@ static const struct ieee80211_ops rt2800pci_mac80211_ops = { | |||
| 1015 | .get_stats = rt2x00mac_get_stats, | 1015 | .get_stats = rt2x00mac_get_stats, |
| 1016 | .get_tkip_seq = rt2800_get_tkip_seq, | 1016 | .get_tkip_seq = rt2800_get_tkip_seq, |
| 1017 | .set_rts_threshold = rt2800_set_rts_threshold, | 1017 | .set_rts_threshold = rt2800_set_rts_threshold, |
| 1018 | .sta_add = rt2x00mac_sta_add, | ||
| 1019 | .sta_remove = rt2x00mac_sta_remove, | ||
| 1018 | .bss_info_changed = rt2x00mac_bss_info_changed, | 1020 | .bss_info_changed = rt2x00mac_bss_info_changed, |
| 1019 | .conf_tx = rt2800_conf_tx, | 1021 | .conf_tx = rt2800_conf_tx, |
| 1020 | .get_tsf = rt2800_get_tsf, | 1022 | .get_tsf = rt2800_get_tsf, |
| @@ -1076,6 +1078,8 @@ static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = { | |||
| 1076 | .config_erp = rt2800_config_erp, | 1078 | .config_erp = rt2800_config_erp, |
| 1077 | .config_ant = rt2800_config_ant, | 1079 | .config_ant = rt2800_config_ant, |
| 1078 | .config = rt2800_config, | 1080 | .config = rt2800_config, |
| 1081 | .sta_add = rt2800_sta_add, | ||
| 1082 | .sta_remove = rt2800_sta_remove, | ||
| 1079 | }; | 1083 | }; |
| 1080 | 1084 | ||
| 1081 | static const struct data_queue_desc rt2800pci_queue_rx = { | 1085 | static const struct data_queue_desc rt2800pci_queue_rx = { |
| @@ -1153,6 +1157,7 @@ static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = { | |||
| 1153 | #endif | 1157 | #endif |
| 1154 | #ifdef CONFIG_RT2800PCI_RT53XX | 1158 | #ifdef CONFIG_RT2800PCI_RT53XX |
| 1155 | { PCI_DEVICE(0x1814, 0x5390) }, | 1159 | { PCI_DEVICE(0x1814, 0x5390) }, |
| 1160 | { PCI_DEVICE(0x1814, 0x539a) }, | ||
| 1156 | { PCI_DEVICE(0x1814, 0x539f) }, | 1161 | { PCI_DEVICE(0x1814, 0x539f) }, |
| 1157 | #endif | 1162 | #endif |
| 1158 | { 0, } | 1163 | { 0, } |
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c index 939563162fb3..677b5ababbdd 100644 --- a/drivers/net/wireless/rt2x00/rt2800usb.c +++ b/drivers/net/wireless/rt2x00/rt2800usb.c | |||
| @@ -534,7 +534,8 @@ static void rt2800usb_txdone(struct rt2x00_dev *rt2x00dev) | |||
| 534 | if (!entry || rt2x00queue_empty(queue)) | 534 | if (!entry || rt2x00queue_empty(queue)) |
| 535 | break; | 535 | break; |
| 536 | 536 | ||
| 537 | rt2800_txdone_entry(entry, reg); | 537 | rt2800_txdone_entry(entry, reg, |
| 538 | rt2800usb_get_txwi(entry)); | ||
| 538 | } | 539 | } |
| 539 | } | 540 | } |
| 540 | 541 | ||
| @@ -749,6 +750,8 @@ static const struct ieee80211_ops rt2800usb_mac80211_ops = { | |||
| 749 | .get_stats = rt2x00mac_get_stats, | 750 | .get_stats = rt2x00mac_get_stats, |
| 750 | .get_tkip_seq = rt2800_get_tkip_seq, | 751 | .get_tkip_seq = rt2800_get_tkip_seq, |
| 751 | .set_rts_threshold = rt2800_set_rts_threshold, | 752 | .set_rts_threshold = rt2800_set_rts_threshold, |
| 753 | .sta_add = rt2x00mac_sta_add, | ||
| 754 | .sta_remove = rt2x00mac_sta_remove, | ||
| 752 | .bss_info_changed = rt2x00mac_bss_info_changed, | 755 | .bss_info_changed = rt2x00mac_bss_info_changed, |
| 753 | .conf_tx = rt2800_conf_tx, | 756 | .conf_tx = rt2800_conf_tx, |
| 754 | .get_tsf = rt2800_get_tsf, | 757 | .get_tsf = rt2800_get_tsf, |
| @@ -806,6 +809,8 @@ static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = { | |||
| 806 | .config_erp = rt2800_config_erp, | 809 | .config_erp = rt2800_config_erp, |
| 807 | .config_ant = rt2800_config_ant, | 810 | .config_ant = rt2800_config_ant, |
| 808 | .config = rt2800_config, | 811 | .config = rt2800_config, |
| 812 | .sta_add = rt2800_sta_add, | ||
| 813 | .sta_remove = rt2800_sta_remove, | ||
| 809 | }; | 814 | }; |
| 810 | 815 | ||
| 811 | static const struct data_queue_desc rt2800usb_queue_rx = { | 816 | static const struct data_queue_desc rt2800usb_queue_rx = { |
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h index f82bfeb79ebb..cbf8eb334e96 100644 --- a/drivers/net/wireless/rt2x00/rt2x00.h +++ b/drivers/net/wireless/rt2x00/rt2x00.h | |||
| @@ -478,6 +478,8 @@ struct rt2x00lib_crypto { | |||
| 478 | u8 key[16]; | 478 | u8 key[16]; |
| 479 | u8 tx_mic[8]; | 479 | u8 tx_mic[8]; |
| 480 | u8 rx_mic[8]; | 480 | u8 rx_mic[8]; |
| 481 | |||
| 482 | int wcid; | ||
| 481 | }; | 483 | }; |
| 482 | 484 | ||
| 483 | /* | 485 | /* |
| @@ -512,6 +514,19 @@ struct rt2x00intf_conf { | |||
| 512 | }; | 514 | }; |
| 513 | 515 | ||
| 514 | /* | 516 | /* |
| 517 | * Private structure for storing STA details | ||
| 518 | * wcid: Wireless Client ID | ||
| 519 | */ | ||
| 520 | struct rt2x00_sta { | ||
| 521 | int wcid; | ||
| 522 | }; | ||
| 523 | |||
| 524 | static inline struct rt2x00_sta* sta_to_rt2x00_sta(struct ieee80211_sta *sta) | ||
| 525 | { | ||
| 526 | return (struct rt2x00_sta *)sta->drv_priv; | ||
| 527 | } | ||
| 528 | |||
| 529 | /* | ||
| 515 | * rt2x00lib callback functions. | 530 | * rt2x00lib callback functions. |
| 516 | */ | 531 | */ |
| 517 | struct rt2x00lib_ops { | 532 | struct rt2x00lib_ops { |
| @@ -620,6 +635,11 @@ struct rt2x00lib_ops { | |||
| 620 | void (*config) (struct rt2x00_dev *rt2x00dev, | 635 | void (*config) (struct rt2x00_dev *rt2x00dev, |
| 621 | struct rt2x00lib_conf *libconf, | 636 | struct rt2x00lib_conf *libconf, |
| 622 | const unsigned int changed_flags); | 637 | const unsigned int changed_flags); |
| 638 | int (*sta_add) (struct rt2x00_dev *rt2x00dev, | ||
| 639 | struct ieee80211_vif *vif, | ||
| 640 | struct ieee80211_sta *sta); | ||
| 641 | int (*sta_remove) (struct rt2x00_dev *rt2x00dev, | ||
| 642 | int wcid); | ||
| 623 | }; | 643 | }; |
| 624 | 644 | ||
| 625 | /* | 645 | /* |
| @@ -1226,6 +1246,12 @@ static inline void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev, | |||
| 1226 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | 1246 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
| 1227 | 1247 | ||
| 1228 | /* | 1248 | /* |
| 1249 | * Utility functions. | ||
| 1250 | */ | ||
| 1251 | u32 rt2x00lib_get_bssidx(struct rt2x00_dev *rt2x00dev, | ||
| 1252 | struct ieee80211_vif *vif); | ||
| 1253 | |||
| 1254 | /* | ||
| 1229 | * Interrupt context handlers. | 1255 | * Interrupt context handlers. |
| 1230 | */ | 1256 | */ |
| 1231 | void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev); | 1257 | void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev); |
| @@ -1261,6 +1287,10 @@ int rt2x00mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, | |||
| 1261 | #else | 1287 | #else |
| 1262 | #define rt2x00mac_set_key NULL | 1288 | #define rt2x00mac_set_key NULL |
| 1263 | #endif /* CONFIG_RT2X00_LIB_CRYPTO */ | 1289 | #endif /* CONFIG_RT2X00_LIB_CRYPTO */ |
| 1290 | int rt2x00mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | ||
| 1291 | struct ieee80211_sta *sta); | ||
| 1292 | int rt2x00mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | ||
| 1293 | struct ieee80211_sta *sta); | ||
| 1264 | void rt2x00mac_sw_scan_start(struct ieee80211_hw *hw); | 1294 | void rt2x00mac_sw_scan_start(struct ieee80211_hw *hw); |
| 1265 | void rt2x00mac_sw_scan_complete(struct ieee80211_hw *hw); | 1295 | void rt2x00mac_sw_scan_complete(struct ieee80211_hw *hw); |
| 1266 | int rt2x00mac_get_stats(struct ieee80211_hw *hw, | 1296 | int rt2x00mac_get_stats(struct ieee80211_hw *hw, |
diff --git a/drivers/net/wireless/rt2x00/rt2x00dev.c b/drivers/net/wireless/rt2x00/rt2x00dev.c index 92ff6a72a2bb..e1fb2a8569be 100644 --- a/drivers/net/wireless/rt2x00/rt2x00dev.c +++ b/drivers/net/wireless/rt2x00/rt2x00dev.c | |||
| @@ -33,6 +33,22 @@ | |||
| 33 | #include "rt2x00lib.h" | 33 | #include "rt2x00lib.h" |
| 34 | 34 | ||
| 35 | /* | 35 | /* |
| 36 | * Utility functions. | ||
| 37 | */ | ||
| 38 | u32 rt2x00lib_get_bssidx(struct rt2x00_dev *rt2x00dev, | ||
| 39 | struct ieee80211_vif *vif) | ||
| 40 | { | ||
| 41 | /* | ||
| 42 | * When in STA mode, bssidx is always 0 otherwise local_address[5] | ||
| 43 | * contains the bss number, see BSS_ID_MASK comments for details. | ||
| 44 | */ | ||
| 45 | if (rt2x00dev->intf_sta_count) | ||
| 46 | return 0; | ||
| 47 | return vif->addr[5] & (rt2x00dev->ops->max_ap_intf - 1); | ||
| 48 | } | ||
| 49 | EXPORT_SYMBOL_GPL(rt2x00lib_get_bssidx); | ||
| 50 | |||
| 51 | /* | ||
| 36 | * Radio control handlers. | 52 | * Radio control handlers. |
| 37 | */ | 53 | */ |
| 38 | int rt2x00lib_enable_radio(struct rt2x00_dev *rt2x00dev) | 54 | int rt2x00lib_enable_radio(struct rt2x00_dev *rt2x00dev) |
| @@ -915,6 +931,11 @@ static int rt2x00lib_probe_hw(struct rt2x00_dev *rt2x00dev) | |||
| 915 | rt2x00dev->hw->extra_tx_headroom += RT2X00_ALIGN_SIZE; | 931 | rt2x00dev->hw->extra_tx_headroom += RT2X00_ALIGN_SIZE; |
| 916 | 932 | ||
| 917 | /* | 933 | /* |
| 934 | * Tell mac80211 about the size of our private STA structure. | ||
| 935 | */ | ||
| 936 | rt2x00dev->hw->sta_data_size = sizeof(struct rt2x00_sta); | ||
| 937 | |||
| 938 | /* | ||
| 918 | * Allocate tx status FIFO for driver use. | 939 | * Allocate tx status FIFO for driver use. |
| 919 | */ | 940 | */ |
| 920 | if (test_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags)) { | 941 | if (test_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags)) { |
diff --git a/drivers/net/wireless/rt2x00/rt2x00mac.c b/drivers/net/wireless/rt2x00/rt2x00mac.c index 4ccf23805973..cef1c878c37e 100644 --- a/drivers/net/wireless/rt2x00/rt2x00mac.c +++ b/drivers/net/wireless/rt2x00/rt2x00mac.c | |||
| @@ -494,6 +494,7 @@ int rt2x00mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, | |||
| 494 | struct rt2x00lib_crypto crypto; | 494 | struct rt2x00lib_crypto crypto; |
| 495 | static const u8 bcast_addr[ETH_ALEN] = | 495 | static const u8 bcast_addr[ETH_ALEN] = |
| 496 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }; | 496 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }; |
| 497 | struct rt2x00_sta *sta_priv = NULL; | ||
| 497 | 498 | ||
| 498 | if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags)) | 499 | if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags)) |
| 499 | return 0; | 500 | return 0; |
| @@ -504,24 +505,18 @@ int rt2x00mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, | |||
| 504 | 505 | ||
| 505 | memset(&crypto, 0, sizeof(crypto)); | 506 | memset(&crypto, 0, sizeof(crypto)); |
| 506 | 507 | ||
| 507 | /* | 508 | crypto.bssidx = rt2x00lib_get_bssidx(rt2x00dev, vif); |
| 508 | * When in STA mode, bssidx is always 0 otherwise local_address[5] | ||
| 509 | * contains the bss number, see BSS_ID_MASK comments for details. | ||
| 510 | */ | ||
| 511 | if (rt2x00dev->intf_sta_count) | ||
| 512 | crypto.bssidx = 0; | ||
| 513 | else | ||
| 514 | crypto.bssidx = vif->addr[5] & (rt2x00dev->ops->max_ap_intf - 1); | ||
| 515 | |||
| 516 | crypto.cipher = rt2x00crypto_key_to_cipher(key); | 509 | crypto.cipher = rt2x00crypto_key_to_cipher(key); |
| 517 | if (crypto.cipher == CIPHER_NONE) | 510 | if (crypto.cipher == CIPHER_NONE) |
| 518 | return -EOPNOTSUPP; | 511 | return -EOPNOTSUPP; |
| 519 | 512 | ||
| 520 | crypto.cmd = cmd; | 513 | crypto.cmd = cmd; |
| 521 | 514 | ||
| 522 | if (sta) | 515 | if (sta) { |
| 523 | crypto.address = sta->addr; | 516 | crypto.address = sta->addr; |
| 524 | else | 517 | sta_priv = sta_to_rt2x00_sta(sta); |
| 518 | crypto.wcid = sta_priv->wcid; | ||
| 519 | } else | ||
| 525 | crypto.address = bcast_addr; | 520 | crypto.address = bcast_addr; |
| 526 | 521 | ||
| 527 | if (crypto.cipher == CIPHER_TKIP) | 522 | if (crypto.cipher == CIPHER_TKIP) |
| @@ -560,6 +555,39 @@ int rt2x00mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, | |||
| 560 | EXPORT_SYMBOL_GPL(rt2x00mac_set_key); | 555 | EXPORT_SYMBOL_GPL(rt2x00mac_set_key); |
| 561 | #endif /* CONFIG_RT2X00_LIB_CRYPTO */ | 556 | #endif /* CONFIG_RT2X00_LIB_CRYPTO */ |
| 562 | 557 | ||
| 558 | int rt2x00mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | ||
| 559 | struct ieee80211_sta *sta) | ||
| 560 | { | ||
| 561 | struct rt2x00_dev *rt2x00dev = hw->priv; | ||
| 562 | struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); | ||
| 563 | |||
| 564 | /* | ||
| 565 | * If there's no space left in the device table store | ||
| 566 | * -1 as wcid but tell mac80211 everything went ok. | ||
| 567 | */ | ||
| 568 | if (rt2x00dev->ops->lib->sta_add(rt2x00dev, vif, sta)) | ||
| 569 | sta_priv->wcid = -1; | ||
| 570 | |||
| 571 | return 0; | ||
| 572 | } | ||
| 573 | EXPORT_SYMBOL_GPL(rt2x00mac_sta_add); | ||
| 574 | |||
| 575 | int rt2x00mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | ||
| 576 | struct ieee80211_sta *sta) | ||
| 577 | { | ||
| 578 | struct rt2x00_dev *rt2x00dev = hw->priv; | ||
| 579 | struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); | ||
| 580 | |||
| 581 | /* | ||
| 582 | * If we never sent the STA to the device no need to clean it up. | ||
| 583 | */ | ||
| 584 | if (sta_priv->wcid < 0) | ||
| 585 | return 0; | ||
| 586 | |||
| 587 | return rt2x00dev->ops->lib->sta_remove(rt2x00dev, sta_priv->wcid); | ||
| 588 | } | ||
| 589 | EXPORT_SYMBOL_GPL(rt2x00mac_sta_remove); | ||
| 590 | |||
| 563 | void rt2x00mac_sw_scan_start(struct ieee80211_hw *hw) | 591 | void rt2x00mac_sw_scan_start(struct ieee80211_hw *hw) |
| 564 | { | 592 | { |
| 565 | struct rt2x00_dev *rt2x00dev = hw->priv; | 593 | struct rt2x00_dev *rt2x00dev = hw->priv; |
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.c b/drivers/net/wireless/rt2x00/rt2x00queue.c index 29edb9fbe6f1..5adfb3eab9cd 100644 --- a/drivers/net/wireless/rt2x00/rt2x00queue.c +++ b/drivers/net/wireless/rt2x00/rt2x00queue.c | |||
| @@ -310,11 +310,16 @@ static void rt2x00queue_create_tx_descriptor_ht(struct rt2x00_dev *rt2x00dev, | |||
| 310 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | 310 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
| 311 | struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; | 311 | struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; |
| 312 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | 312 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
| 313 | struct rt2x00_sta *sta_priv = NULL; | ||
| 313 | 314 | ||
| 314 | if (tx_info->control.sta) | 315 | if (tx_info->control.sta) { |
| 315 | txdesc->u.ht.mpdu_density = | 316 | txdesc->u.ht.mpdu_density = |
| 316 | tx_info->control.sta->ht_cap.ampdu_density; | 317 | tx_info->control.sta->ht_cap.ampdu_density; |
| 317 | 318 | ||
| 319 | sta_priv = sta_to_rt2x00_sta(tx_info->control.sta); | ||
| 320 | txdesc->u.ht.wcid = sta_priv->wcid; | ||
| 321 | } | ||
| 322 | |||
| 318 | txdesc->u.ht.ba_size = 7; /* FIXME: What value is needed? */ | 323 | txdesc->u.ht.ba_size = 7; /* FIXME: What value is needed? */ |
| 319 | 324 | ||
| 320 | /* | 325 | /* |
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.h b/drivers/net/wireless/rt2x00/rt2x00queue.h index f2100f4ddcff..349008d1fb28 100644 --- a/drivers/net/wireless/rt2x00/rt2x00queue.h +++ b/drivers/net/wireless/rt2x00/rt2x00queue.h | |||
| @@ -288,8 +288,8 @@ enum txentry_desc_flags { | |||
| 288 | * @signal: PLCP signal. | 288 | * @signal: PLCP signal. |
| 289 | * @service: PLCP service. | 289 | * @service: PLCP service. |
| 290 | * @msc: MCS. | 290 | * @msc: MCS. |
| 291 | * @stbc: STBC. | 291 | * @stbc: Use Space Time Block Coding (only available for MCS rates < 8). |
| 292 | * @ba_size: BA size. | 292 | * @ba_size: Size of the recepients RX reorder buffer - 1. |
| 293 | * @rate_mode: Rate mode (See @enum rate_modulation). | 293 | * @rate_mode: Rate mode (See @enum rate_modulation). |
| 294 | * @mpdu_density: MDPU density. | 294 | * @mpdu_density: MDPU density. |
| 295 | * @retry_limit: Max number of retries. | 295 | * @retry_limit: Max number of retries. |
| @@ -321,6 +321,7 @@ struct txentry_desc { | |||
| 321 | u8 ba_size; | 321 | u8 ba_size; |
| 322 | u8 mpdu_density; | 322 | u8 mpdu_density; |
| 323 | enum txop txop; | 323 | enum txop txop; |
| 324 | int wcid; | ||
| 324 | } ht; | 325 | } ht; |
| 325 | } u; | 326 | } u; |
| 326 | 327 | ||
diff --git a/drivers/net/wireless/wl12xx/boot.c b/drivers/net/wireless/wl12xx/boot.c index cc70422c0575..6d5664bfc37d 100644 --- a/drivers/net/wireless/wl12xx/boot.c +++ b/drivers/net/wireless/wl12xx/boot.c | |||
| @@ -294,9 +294,7 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl) | |||
| 294 | */ | 294 | */ |
| 295 | if (wl->nvs_len == sizeof(struct wl1271_nvs_file) || | 295 | if (wl->nvs_len == sizeof(struct wl1271_nvs_file) || |
| 296 | wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) { | 296 | wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) { |
| 297 | /* for now 11a is unsupported in AP mode */ | 297 | if (nvs->general_params.dual_mode_select) |
| 298 | if (wl->bss_type != BSS_TYPE_AP_BSS && | ||
| 299 | nvs->general_params.dual_mode_select) | ||
| 300 | wl->enable_11a = true; | 298 | wl->enable_11a = true; |
| 301 | } | 299 | } |
| 302 | 300 | ||
diff --git a/drivers/net/wireless/wl12xx/main.c b/drivers/net/wireless/wl12xx/main.c index 82f4408e89ad..bde84027ab7f 100644 --- a/drivers/net/wireless/wl12xx/main.c +++ b/drivers/net/wireless/wl12xx/main.c | |||
| @@ -236,7 +236,7 @@ static struct conf_drv_settings default_conf = { | |||
| 236 | .ps_poll_recovery_period = 700, | 236 | .ps_poll_recovery_period = 700, |
| 237 | .bet_enable = CONF_BET_MODE_ENABLE, | 237 | .bet_enable = CONF_BET_MODE_ENABLE, |
| 238 | .bet_max_consecutive = 50, | 238 | .bet_max_consecutive = 50, |
| 239 | .psm_entry_retries = 5, | 239 | .psm_entry_retries = 8, |
| 240 | .psm_exit_retries = 16, | 240 | .psm_exit_retries = 16, |
| 241 | .psm_entry_nullfunc_retries = 3, | 241 | .psm_entry_nullfunc_retries = 3, |
| 242 | .psm_entry_hangover_period = 1, | 242 | .psm_entry_hangover_period = 1, |
| @@ -2064,6 +2064,7 @@ deinit: | |||
| 2064 | wl->session_counter = 0; | 2064 | wl->session_counter = 0; |
| 2065 | wl->rate_set = CONF_TX_RATE_MASK_BASIC; | 2065 | wl->rate_set = CONF_TX_RATE_MASK_BASIC; |
| 2066 | wl->vif = NULL; | 2066 | wl->vif = NULL; |
| 2067 | wl->tx_spare_blocks = TX_HW_BLOCK_SPARE_DEFAULT; | ||
| 2067 | wl1271_free_ap_keys(wl); | 2068 | wl1271_free_ap_keys(wl); |
| 2068 | memset(wl->ap_hlid_map, 0, sizeof(wl->ap_hlid_map)); | 2069 | memset(wl->ap_hlid_map, 0, sizeof(wl->ap_hlid_map)); |
| 2069 | wl->ap_fw_ps_map = 0; | 2070 | wl->ap_fw_ps_map = 0; |
| @@ -2199,10 +2200,14 @@ out: | |||
| 2199 | 2200 | ||
| 2200 | static void wl1271_set_band_rate(struct wl1271 *wl) | 2201 | static void wl1271_set_band_rate(struct wl1271 *wl) |
| 2201 | { | 2202 | { |
| 2202 | if (wl->band == IEEE80211_BAND_2GHZ) | 2203 | if (wl->band == IEEE80211_BAND_2GHZ) { |
| 2203 | wl->basic_rate_set = wl->conf.tx.basic_rate; | 2204 | wl->basic_rate_set = wl->conf.tx.basic_rate; |
| 2204 | else | 2205 | wl->rate_set = wl->conf.tx.basic_rate; |
| 2206 | } else { | ||
| 2205 | wl->basic_rate_set = wl->conf.tx.basic_rate_5; | 2207 | wl->basic_rate_set = wl->conf.tx.basic_rate_5; |
| 2208 | wl->rate_set = wl->conf.tx.basic_rate_5; | ||
| 2209 | } | ||
| 2210 | |||
| 2206 | } | 2211 | } |
| 2207 | 2212 | ||
| 2208 | static bool wl12xx_is_roc(struct wl1271 *wl) | 2213 | static bool wl12xx_is_roc(struct wl1271 *wl) |
| @@ -2653,6 +2658,17 @@ static int wl1271_set_key(struct wl1271 *wl, u16 action, u8 id, u8 key_type, | |||
| 2653 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff | 2658 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff |
| 2654 | }; | 2659 | }; |
| 2655 | 2660 | ||
| 2661 | /* | ||
| 2662 | * A STA set to GEM cipher requires 2 tx spare blocks. | ||
| 2663 | * Return to default value when GEM cipher key is removed | ||
| 2664 | */ | ||
| 2665 | if (key_type == KEY_GEM) { | ||
| 2666 | if (action == KEY_ADD_OR_REPLACE) | ||
| 2667 | wl->tx_spare_blocks = 2; | ||
| 2668 | else if (action == KEY_REMOVE) | ||
| 2669 | wl->tx_spare_blocks = TX_HW_BLOCK_SPARE_DEFAULT; | ||
| 2670 | } | ||
| 2671 | |||
| 2656 | addr = sta ? sta->addr : bcast_addr; | 2672 | addr = sta ? sta->addr : bcast_addr; |
| 2657 | 2673 | ||
| 2658 | if (is_zero_ether_addr(addr)) { | 2674 | if (is_zero_ether_addr(addr)) { |
| @@ -3345,19 +3361,6 @@ sta_not_found: | |||
| 3345 | ret = wl1271_acx_conn_monit_params(wl, true); | 3361 | ret = wl1271_acx_conn_monit_params(wl, true); |
| 3346 | if (ret < 0) | 3362 | if (ret < 0) |
| 3347 | goto out; | 3363 | goto out; |
| 3348 | |||
| 3349 | /* If we want to go in PSM but we're not there yet */ | ||
| 3350 | if (test_bit(WL1271_FLAG_PSM_REQUESTED, &wl->flags) && | ||
| 3351 | !test_bit(WL1271_FLAG_PSM, &wl->flags)) { | ||
| 3352 | enum wl1271_cmd_ps_mode mode; | ||
| 3353 | |||
| 3354 | mode = STATION_POWER_SAVE_MODE; | ||
| 3355 | ret = wl1271_ps_set_mode(wl, mode, | ||
| 3356 | wl->basic_rate, | ||
| 3357 | true); | ||
| 3358 | if (ret < 0) | ||
| 3359 | goto out; | ||
| 3360 | } | ||
| 3361 | } else { | 3364 | } else { |
| 3362 | /* use defaults when not associated */ | 3365 | /* use defaults when not associated */ |
| 3363 | bool was_assoc = | 3366 | bool was_assoc = |
| @@ -3501,6 +3504,19 @@ sta_not_found: | |||
| 3501 | if (ret < 0) | 3504 | if (ret < 0) |
| 3502 | goto out; | 3505 | goto out; |
| 3503 | } | 3506 | } |
| 3507 | |||
| 3508 | /* If we want to go in PSM but we're not there yet */ | ||
| 3509 | if (test_bit(WL1271_FLAG_PSM_REQUESTED, &wl->flags) && | ||
| 3510 | !test_bit(WL1271_FLAG_PSM, &wl->flags)) { | ||
| 3511 | enum wl1271_cmd_ps_mode mode; | ||
| 3512 | |||
| 3513 | mode = STATION_POWER_SAVE_MODE; | ||
| 3514 | ret = wl1271_ps_set_mode(wl, mode, | ||
| 3515 | wl->basic_rate, | ||
| 3516 | true); | ||
| 3517 | if (ret < 0) | ||
| 3518 | goto out; | ||
| 3519 | } | ||
| 3504 | } | 3520 | } |
| 3505 | 3521 | ||
| 3506 | /* Handle new association with HT. Do this after join. */ | 3522 | /* Handle new association with HT. Do this after join. */ |
| @@ -4475,6 +4491,7 @@ int wl1271_init_ieee80211(struct wl1271 *wl) | |||
| 4475 | wl->hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | | 4491 | wl->hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | |
| 4476 | BIT(NL80211_IFTYPE_ADHOC) | BIT(NL80211_IFTYPE_AP); | 4492 | BIT(NL80211_IFTYPE_ADHOC) | BIT(NL80211_IFTYPE_AP); |
| 4477 | wl->hw->wiphy->max_scan_ssids = 1; | 4493 | wl->hw->wiphy->max_scan_ssids = 1; |
| 4494 | wl->hw->wiphy->max_sched_scan_ssids = 8; | ||
| 4478 | /* | 4495 | /* |
| 4479 | * Maximum length of elements in scanning probe request templates | 4496 | * Maximum length of elements in scanning probe request templates |
| 4480 | * should be the maximum length possible for a template, without | 4497 | * should be the maximum length possible for a template, without |
| @@ -4599,6 +4616,7 @@ struct ieee80211_hw *wl1271_alloc_hw(void) | |||
| 4599 | wl->sched_scanning = false; | 4616 | wl->sched_scanning = false; |
| 4600 | wl->tx_security_seq = 0; | 4617 | wl->tx_security_seq = 0; |
| 4601 | wl->tx_security_last_seq_lsb = 0; | 4618 | wl->tx_security_last_seq_lsb = 0; |
| 4619 | wl->tx_spare_blocks = TX_HW_BLOCK_SPARE_DEFAULT; | ||
| 4602 | wl->role_id = WL12XX_INVALID_ROLE_ID; | 4620 | wl->role_id = WL12XX_INVALID_ROLE_ID; |
| 4603 | wl->system_hlid = WL12XX_SYSTEM_HLID; | 4621 | wl->system_hlid = WL12XX_SYSTEM_HLID; |
| 4604 | wl->sta_hlid = WL12XX_INVALID_LINK_ID; | 4622 | wl->sta_hlid = WL12XX_INVALID_LINK_ID; |
diff --git a/drivers/net/wireless/wl12xx/scan.c b/drivers/net/wireless/wl12xx/scan.c index 7229eaa89018..af4ad2353f59 100644 --- a/drivers/net/wireless/wl12xx/scan.c +++ b/drivers/net/wireless/wl12xx/scan.c | |||
| @@ -473,6 +473,51 @@ wl1271_scan_sched_scan_channels(struct wl1271 *wl, | |||
| 473 | cfg->passive[2] || cfg->active[2]; | 473 | cfg->passive[2] || cfg->active[2]; |
| 474 | } | 474 | } |
| 475 | 475 | ||
| 476 | /* Returns 0 if no wildcard is used, 1 if wildcard is used or a | ||
| 477 | * negative value on error */ | ||
| 478 | static int | ||
| 479 | wl12xx_scan_sched_scan_ssid_list(struct wl1271 *wl, | ||
| 480 | struct cfg80211_sched_scan_request *req) | ||
| 481 | { | ||
| 482 | struct wl1271_cmd_sched_scan_ssid_list *cmd = NULL; | ||
| 483 | struct cfg80211_ssid *ssid = req->ssids; | ||
| 484 | int ret, wildcard = 0; | ||
| 485 | |||
| 486 | wl1271_debug(DEBUG_CMD, "cmd sched scan ssid list"); | ||
| 487 | |||
| 488 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | ||
| 489 | if (!cmd) | ||
| 490 | return -ENOMEM; | ||
| 491 | |||
| 492 | while ((cmd->n_ssids < req->n_ssids) && ssid) { | ||
| 493 | if (ssid->ssid_len == 0) { | ||
| 494 | wildcard = 1; | ||
| 495 | cmd->ssids[cmd->n_ssids].type = SCAN_SSID_TYPE_PUBLIC; | ||
| 496 | } else { | ||
| 497 | cmd->ssids[cmd->n_ssids].type = SCAN_SSID_TYPE_HIDDEN; | ||
| 498 | } | ||
| 499 | cmd->ssids[cmd->n_ssids].len = ssid->ssid_len; | ||
| 500 | memcpy(cmd->ssids[cmd->n_ssids].ssid, ssid->ssid, | ||
| 501 | ssid->ssid_len); | ||
| 502 | ssid++; | ||
| 503 | cmd->n_ssids++; | ||
| 504 | } | ||
| 505 | |||
| 506 | wl1271_dump(DEBUG_SCAN, "SSID_LIST: ", cmd, sizeof(*cmd)); | ||
| 507 | |||
| 508 | ret = wl1271_cmd_send(wl, CMD_CONNECTION_SCAN_SSID_CFG, cmd, | ||
| 509 | sizeof(*cmd), 0); | ||
| 510 | if (ret < 0) { | ||
| 511 | wl1271_error("cmd sched scan ssid list failed"); | ||
| 512 | goto out; | ||
| 513 | } | ||
| 514 | |||
| 515 | ret = wildcard; | ||
| 516 | out: | ||
| 517 | kfree(cmd); | ||
| 518 | return ret; | ||
| 519 | } | ||
| 520 | |||
| 476 | int wl1271_scan_sched_scan_config(struct wl1271 *wl, | 521 | int wl1271_scan_sched_scan_config(struct wl1271 *wl, |
| 477 | struct cfg80211_sched_scan_request *req, | 522 | struct cfg80211_sched_scan_request *req, |
| 478 | struct ieee80211_sched_scan_ies *ies) | 523 | struct ieee80211_sched_scan_ies *ies) |
| @@ -504,14 +549,21 @@ int wl1271_scan_sched_scan_config(struct wl1271 *wl, | |||
| 504 | for (i = 0; i < SCAN_MAX_CYCLE_INTERVALS; i++) | 549 | for (i = 0; i < SCAN_MAX_CYCLE_INTERVALS; i++) |
| 505 | cfg->intervals[i] = cpu_to_le32(req->interval); | 550 | cfg->intervals[i] = cpu_to_le32(req->interval); |
| 506 | 551 | ||
| 507 | if (!force_passive && req->ssids[0].ssid_len && req->ssids[0].ssid) { | 552 | cfg->ssid_len = 0; |
| 508 | cfg->filter_type = SCAN_SSID_FILTER_SPECIFIC; | 553 | if (req->n_ssids == 0) { |
| 509 | cfg->ssid_len = req->ssids[0].ssid_len; | 554 | wl1271_debug(DEBUG_SCAN, "using SCAN_SSID_FILTER_ANY"); |
| 510 | memcpy(cfg->ssid, req->ssids[0].ssid, | ||
| 511 | req->ssids[0].ssid_len); | ||
| 512 | } else { | ||
| 513 | cfg->filter_type = SCAN_SSID_FILTER_ANY; | 555 | cfg->filter_type = SCAN_SSID_FILTER_ANY; |
| 514 | cfg->ssid_len = 0; | 556 | } else { |
| 557 | ret = wl12xx_scan_sched_scan_ssid_list(wl, req); | ||
| 558 | if (ret < 0) | ||
| 559 | goto out; | ||
| 560 | if (ret) { | ||
| 561 | wl1271_debug(DEBUG_SCAN, "using SCAN_SSID_FILTER_DISABLED"); | ||
| 562 | cfg->filter_type = SCAN_SSID_FILTER_DISABLED; | ||
| 563 | } else { | ||
| 564 | wl1271_debug(DEBUG_SCAN, "using SCAN_SSID_FILTER_LIST"); | ||
| 565 | cfg->filter_type = SCAN_SSID_FILTER_LIST; | ||
| 566 | } | ||
| 515 | } | 567 | } |
| 516 | 568 | ||
| 517 | if (!wl1271_scan_sched_scan_channels(wl, req, cfg)) { | 569 | if (!wl1271_scan_sched_scan_channels(wl, req, cfg)) { |
diff --git a/drivers/net/wireless/wl12xx/tx.c b/drivers/net/wireless/wl12xx/tx.c index 0f1578577b1a..08227e69616b 100644 --- a/drivers/net/wireless/wl12xx/tx.c +++ b/drivers/net/wireless/wl12xx/tx.c | |||
| @@ -204,9 +204,7 @@ static int wl1271_tx_allocate(struct wl1271 *wl, struct sk_buff *skb, u32 extra, | |||
| 204 | u32 len; | 204 | u32 len; |
| 205 | u32 total_blocks; | 205 | u32 total_blocks; |
| 206 | int id, ret = -EBUSY, ac; | 206 | int id, ret = -EBUSY, ac; |
| 207 | 207 | u32 spare_blocks = wl->tx_spare_blocks; | |
| 208 | /* we use 1 spare block */ | ||
| 209 | u32 spare_blocks = 1; | ||
| 210 | 208 | ||
| 211 | if (buf_offset + total_len > WL1271_AGGR_BUFFER_SIZE) | 209 | if (buf_offset + total_len > WL1271_AGGR_BUFFER_SIZE) |
| 212 | return -EAGAIN; | 210 | return -EAGAIN; |
| @@ -220,6 +218,10 @@ static int wl1271_tx_allocate(struct wl1271 *wl, struct sk_buff *skb, u32 extra, | |||
| 220 | in the firmware */ | 218 | in the firmware */ |
| 221 | len = wl12xx_calc_packet_alignment(wl, total_len); | 219 | len = wl12xx_calc_packet_alignment(wl, total_len); |
| 222 | 220 | ||
| 221 | /* in case of a dummy packet, use default amount of spare mem blocks */ | ||
| 222 | if (unlikely(wl12xx_is_dummy_packet(wl, skb))) | ||
| 223 | spare_blocks = TX_HW_BLOCK_SPARE_DEFAULT; | ||
| 224 | |||
| 223 | total_blocks = (len + TX_HW_BLOCK_SIZE - 1) / TX_HW_BLOCK_SIZE + | 225 | total_blocks = (len + TX_HW_BLOCK_SIZE - 1) / TX_HW_BLOCK_SIZE + |
| 224 | spare_blocks; | 226 | spare_blocks; |
| 225 | 227 | ||
diff --git a/drivers/net/wireless/wl12xx/tx.h b/drivers/net/wireless/wl12xx/tx.h index 7da35c0e411b..6519be4b2c38 100644 --- a/drivers/net/wireless/wl12xx/tx.h +++ b/drivers/net/wireless/wl12xx/tx.h | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #ifndef __TX_H__ | 25 | #ifndef __TX_H__ |
| 26 | #define __TX_H__ | 26 | #define __TX_H__ |
| 27 | 27 | ||
| 28 | #define TX_HW_BLOCK_SPARE_DEFAULT 1 | ||
| 28 | #define TX_HW_BLOCK_SIZE 252 | 29 | #define TX_HW_BLOCK_SIZE 252 |
| 29 | 30 | ||
| 30 | #define TX_HW_MGMT_PKT_LIFETIME_TU 2000 | 31 | #define TX_HW_MGMT_PKT_LIFETIME_TU 2000 |
diff --git a/drivers/net/wireless/wl12xx/wl12xx.h b/drivers/net/wireless/wl12xx/wl12xx.h index 61a7c2163ea2..fb2753c46300 100644 --- a/drivers/net/wireless/wl12xx/wl12xx.h +++ b/drivers/net/wireless/wl12xx/wl12xx.h | |||
| @@ -425,6 +425,9 @@ struct wl1271 { | |||
| 425 | u32 tx_allocated_blocks; | 425 | u32 tx_allocated_blocks; |
| 426 | u32 tx_results_count; | 426 | u32 tx_results_count; |
| 427 | 427 | ||
| 428 | /* amount of spare TX blocks to use */ | ||
| 429 | u32 tx_spare_blocks; | ||
| 430 | |||
| 428 | /* Accounting for allocated / available Tx packets in HW */ | 431 | /* Accounting for allocated / available Tx packets in HW */ |
| 429 | u32 tx_pkts_freed[NUM_TX_QUEUES]; | 432 | u32 tx_pkts_freed[NUM_TX_QUEUES]; |
| 430 | u32 tx_allocated_pkts[NUM_TX_QUEUES]; | 433 | u32 tx_allocated_pkts[NUM_TX_QUEUES]; |
diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h index 37f95f2e10f9..72f3933938c0 100644 --- a/include/linux/ieee80211.h +++ b/include/linux/ieee80211.h | |||
| @@ -130,6 +130,8 @@ | |||
| 130 | #define IEEE80211_QOS_CTL_ACK_POLICY_BLOCKACK 0x0060 | 130 | #define IEEE80211_QOS_CTL_ACK_POLICY_BLOCKACK 0x0060 |
| 131 | /* A-MSDU 802.11n */ | 131 | /* A-MSDU 802.11n */ |
| 132 | #define IEEE80211_QOS_CTL_A_MSDU_PRESENT 0x0080 | 132 | #define IEEE80211_QOS_CTL_A_MSDU_PRESENT 0x0080 |
| 133 | /* Mesh Control 802.11s */ | ||
| 134 | #define IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT 0x0100 | ||
| 133 | 135 | ||
| 134 | /* U-APSD queue for WMM IEs sent by AP */ | 136 | /* U-APSD queue for WMM IEs sent by AP */ |
| 135 | #define IEEE80211_WMM_IE_AP_QOSINFO_UAPSD (1<<7) | 137 | #define IEEE80211_WMM_IE_AP_QOSINFO_UAPSD (1<<7) |
diff --git a/include/linux/nl80211.h b/include/linux/nl80211.h index 0343504082a8..f17307590e61 100644 --- a/include/linux/nl80211.h +++ b/include/linux/nl80211.h | |||
| @@ -769,6 +769,8 @@ enum nl80211_commands { | |||
| 769 | * that can be added to a scan request | 769 | * that can be added to a scan request |
| 770 | * @NL80211_ATTR_MAX_SCHED_SCAN_IE_LEN: maximum length of information | 770 | * @NL80211_ATTR_MAX_SCHED_SCAN_IE_LEN: maximum length of information |
| 771 | * elements that can be added to a scheduled scan request | 771 | * elements that can be added to a scheduled scan request |
| 772 | * @NL80211_ATTR_MAX_MATCH_SETS: maximum number of sets that can be | ||
| 773 | * used with @NL80211_ATTR_SCHED_SCAN_MATCH, a wiphy attribute. | ||
| 772 | * | 774 | * |
| 773 | * @NL80211_ATTR_SCAN_FREQUENCIES: nested attribute with frequencies (in MHz) | 775 | * @NL80211_ATTR_SCAN_FREQUENCIES: nested attribute with frequencies (in MHz) |
| 774 | * @NL80211_ATTR_SCAN_SSIDS: nested attribute with SSIDs, leave out for passive | 776 | * @NL80211_ATTR_SCAN_SSIDS: nested attribute with SSIDs, leave out for passive |
| @@ -1011,6 +1013,24 @@ enum nl80211_commands { | |||
| 1011 | 1013 | ||
| 1012 | * @NL80211_ATTR_SCHED_SCAN_INTERVAL: Interval between scheduled scan | 1014 | * @NL80211_ATTR_SCHED_SCAN_INTERVAL: Interval between scheduled scan |
| 1013 | * cycles, in msecs. | 1015 | * cycles, in msecs. |
| 1016 | |||
| 1017 | * @NL80211_ATTR_SCHED_SCAN_MATCH: Nested attribute with one or more | ||
| 1018 | * sets of attributes to match during scheduled scans. Only BSSs | ||
| 1019 | * that match any of the sets will be reported. These are | ||
| 1020 | * pass-thru filter rules. | ||
| 1021 | * For a match to succeed, the BSS must match all attributes of a | ||
| 1022 | * set. Since not every hardware supports matching all types of | ||
| 1023 | * attributes, there is no guarantee that the reported BSSs are | ||
| 1024 | * fully complying with the match sets and userspace needs to be | ||
| 1025 | * able to ignore them by itself. | ||
| 1026 | * Thus, the implementation is somewhat hardware-dependent, but | ||
| 1027 | * this is only an optimization and the userspace application | ||
| 1028 | * needs to handle all the non-filtered results anyway. | ||
| 1029 | * If the match attributes don't make sense when combined with | ||
| 1030 | * the values passed in @NL80211_ATTR_SCAN_SSIDS (eg. if an SSID | ||
| 1031 | * is included in the probe request, but the match attributes | ||
| 1032 | * will never let it go through), -EINVAL may be returned. | ||
| 1033 | * If ommited, no filtering is done. | ||
| 1014 | * | 1034 | * |
| 1015 | * @NL80211_ATTR_INTERFACE_COMBINATIONS: Nested attribute listing the supported | 1035 | * @NL80211_ATTR_INTERFACE_COMBINATIONS: Nested attribute listing the supported |
| 1016 | * interface combinations. In each nested item, it contains attributes | 1036 | * interface combinations. In each nested item, it contains attributes |
| @@ -1044,6 +1064,11 @@ enum nl80211_commands { | |||
| 1044 | * | 1064 | * |
| 1045 | * @NL80211_ATTR_STA_WME: Nested attribute containing the wme configuration | 1065 | * @NL80211_ATTR_STA_WME: Nested attribute containing the wme configuration |
| 1046 | * of the station, see &enum nl80211_sta_wme_attr. | 1066 | * of the station, see &enum nl80211_sta_wme_attr. |
| 1067 | * @NL80211_ATTR_SUPPORT_AP_UAPSD: the device supports uapsd when working | ||
| 1068 | * as AP. | ||
| 1069 | * | ||
| 1070 | * @NL80211_ATTR_ROAM_SUPPORT: Indicates whether the firmware is capable of | ||
| 1071 | * roaming to another AP in the same ESS if the signal lever is low. | ||
| 1047 | * | 1072 | * |
| 1048 | * @NL80211_ATTR_MAX: highest attribute number currently defined | 1073 | * @NL80211_ATTR_MAX: highest attribute number currently defined |
| 1049 | * @__NL80211_ATTR_AFTER_LAST: internal use | 1074 | * @__NL80211_ATTR_AFTER_LAST: internal use |
| @@ -1256,6 +1281,12 @@ enum nl80211_attrs { | |||
| 1256 | NL80211_ATTR_IE_ASSOC_RESP, | 1281 | NL80211_ATTR_IE_ASSOC_RESP, |
| 1257 | 1282 | ||
| 1258 | NL80211_ATTR_STA_WME, | 1283 | NL80211_ATTR_STA_WME, |
| 1284 | NL80211_ATTR_SUPPORT_AP_UAPSD, | ||
| 1285 | |||
| 1286 | NL80211_ATTR_ROAM_SUPPORT, | ||
| 1287 | |||
| 1288 | NL80211_ATTR_SCHED_SCAN_MATCH, | ||
| 1289 | NL80211_ATTR_MAX_MATCH_SETS, | ||
| 1259 | 1290 | ||
| 1260 | /* add attributes here, update the policy in nl80211.c */ | 1291 | /* add attributes here, update the policy in nl80211.c */ |
| 1261 | 1292 | ||
| @@ -1716,6 +1747,26 @@ enum nl80211_reg_rule_attr { | |||
| 1716 | }; | 1747 | }; |
| 1717 | 1748 | ||
| 1718 | /** | 1749 | /** |
| 1750 | * enum nl80211_sched_scan_match_attr - scheduled scan match attributes | ||
| 1751 | * @__NL80211_SCHED_SCAN_MATCH_ATTR_INVALID: attribute number 0 is reserved | ||
| 1752 | * @NL80211_SCHED_SCAN_MATCH_ATTR_SSID: SSID to be used for matching, | ||
| 1753 | * only report BSS with matching SSID. | ||
| 1754 | * @NL80211_SCHED_SCAN_MATCH_ATTR_MAX: highest scheduled scan filter | ||
| 1755 | * attribute number currently defined | ||
| 1756 | * @__NL80211_SCHED_SCAN_MATCH_ATTR_AFTER_LAST: internal use | ||
| 1757 | */ | ||
| 1758 | enum nl80211_sched_scan_match_attr { | ||
| 1759 | __NL80211_SCHED_SCAN_MATCH_ATTR_INVALID, | ||
| 1760 | |||
| 1761 | NL80211_ATTR_SCHED_SCAN_MATCH_SSID, | ||
| 1762 | |||
| 1763 | /* keep last */ | ||
| 1764 | __NL80211_SCHED_SCAN_MATCH_ATTR_AFTER_LAST, | ||
| 1765 | NL80211_SCHED_SCAN_MATCH_ATTR_MAX = | ||
| 1766 | __NL80211_SCHED_SCAN_MATCH_ATTR_AFTER_LAST - 1 | ||
| 1767 | }; | ||
| 1768 | |||
| 1769 | /** | ||
| 1719 | * enum nl80211_reg_rule_flags - regulatory rule flags | 1770 | * enum nl80211_reg_rule_flags - regulatory rule flags |
| 1720 | * | 1771 | * |
| 1721 | * @NL80211_RRF_NO_OFDM: OFDM modulation not allowed | 1772 | * @NL80211_RRF_NO_OFDM: OFDM modulation not allowed |
| @@ -2490,8 +2541,10 @@ enum nl80211_hidden_ssid { | |||
| 2490 | /** | 2541 | /** |
| 2491 | * enum nl80211_sta_wme_attr - station WME attributes | 2542 | * enum nl80211_sta_wme_attr - station WME attributes |
| 2492 | * @__NL80211_STA_WME_INVALID: invalid number for nested attribute | 2543 | * @__NL80211_STA_WME_INVALID: invalid number for nested attribute |
| 2493 | * @NL80211_STA_WME_QUEUES: bitmap of uapsd queues. | 2544 | * @NL80211_STA_WME_UAPSD_QUEUES: bitmap of uapsd queues. the format |
| 2494 | * @NL80211_STA_WME_MAX_SP: max service period. | 2545 | * is the same as the AC bitmap in the QoS info field. |
| 2546 | * @NL80211_STA_WME_MAX_SP: max service period. the format is the same | ||
| 2547 | * as the MAX_SP field in the QoS info field (but already shifted down). | ||
| 2495 | * @__NL80211_STA_WME_AFTER_LAST: internal | 2548 | * @__NL80211_STA_WME_AFTER_LAST: internal |
| 2496 | * @NL80211_STA_WME_MAX: highest station WME attribute | 2549 | * @NL80211_STA_WME_MAX: highest station WME attribute |
| 2497 | */ | 2550 | */ |
diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index 8623217f84d0..f10ed7b4a714 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h | |||
| @@ -25,7 +25,7 @@ struct ssb_sprom { | |||
| 25 | u8 et1phyaddr; /* MII address for enet1 */ | 25 | u8 et1phyaddr; /* MII address for enet1 */ |
| 26 | u8 et0mdcport; /* MDIO for enet0 */ | 26 | u8 et0mdcport; /* MDIO for enet0 */ |
| 27 | u8 et1mdcport; /* MDIO for enet1 */ | 27 | u8 et1mdcport; /* MDIO for enet1 */ |
| 28 | u8 board_rev; /* Board revision number from SPROM. */ | 28 | u16 board_rev; /* Board revision number from SPROM. */ |
| 29 | u8 country_code; /* Country Code */ | 29 | u8 country_code; /* Country Code */ |
| 30 | u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */ | 30 | u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */ |
| 31 | u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */ | 31 | u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */ |
diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h index eb2659aefd97..b42136a61f3a 100644 --- a/include/net/cfg80211.h +++ b/include/net/cfg80211.h | |||
| @@ -441,6 +441,10 @@ enum plink_actions { | |||
| 441 | * @plink_action: plink action to take | 441 | * @plink_action: plink action to take |
| 442 | * @plink_state: set the peer link state for a station | 442 | * @plink_state: set the peer link state for a station |
| 443 | * @ht_capa: HT capabilities of station | 443 | * @ht_capa: HT capabilities of station |
| 444 | * @uapsd_queues: bitmap of queues configured for uapsd. same format | ||
| 445 | * as the AC bitmap in the QoS info field | ||
| 446 | * @max_sp: max Service Period. same format as the MAX_SP in the | ||
| 447 | * QoS info field (but already shifted down) | ||
| 444 | */ | 448 | */ |
| 445 | struct station_parameters { | 449 | struct station_parameters { |
| 446 | u8 *supported_rates; | 450 | u8 *supported_rates; |
| @@ -876,6 +880,15 @@ struct cfg80211_scan_request { | |||
| 876 | }; | 880 | }; |
| 877 | 881 | ||
| 878 | /** | 882 | /** |
| 883 | * struct cfg80211_match_set - sets of attributes to match | ||
| 884 | * | ||
| 885 | * @ssid: SSID to be matched | ||
| 886 | */ | ||
| 887 | struct cfg80211_match_set { | ||
| 888 | struct cfg80211_ssid ssid; | ||
| 889 | }; | ||
| 890 | |||
| 891 | /** | ||
| 879 | * struct cfg80211_sched_scan_request - scheduled scan request description | 892 | * struct cfg80211_sched_scan_request - scheduled scan request description |
| 880 | * | 893 | * |
| 881 | * @ssids: SSIDs to scan for (passed in the probe_reqs in active scans) | 894 | * @ssids: SSIDs to scan for (passed in the probe_reqs in active scans) |
| @@ -884,6 +897,11 @@ struct cfg80211_scan_request { | |||
| 884 | * @interval: interval between each scheduled scan cycle | 897 | * @interval: interval between each scheduled scan cycle |
| 885 | * @ie: optional information element(s) to add into Probe Request or %NULL | 898 | * @ie: optional information element(s) to add into Probe Request or %NULL |
| 886 | * @ie_len: length of ie in octets | 899 | * @ie_len: length of ie in octets |
| 900 | * @match_sets: sets of parameters to be matched for a scan result | ||
| 901 | * entry to be considered valid and to be passed to the host | ||
| 902 | * (others are filtered out). | ||
| 903 | * If ommited, all results are passed. | ||
| 904 | * @n_match_sets: number of match sets | ||
| 887 | * @wiphy: the wiphy this was for | 905 | * @wiphy: the wiphy this was for |
| 888 | * @dev: the interface | 906 | * @dev: the interface |
| 889 | * @channels: channels to scan | 907 | * @channels: channels to scan |
| @@ -895,6 +913,8 @@ struct cfg80211_sched_scan_request { | |||
| 895 | u32 interval; | 913 | u32 interval; |
| 896 | const u8 *ie; | 914 | const u8 *ie; |
| 897 | size_t ie_len; | 915 | size_t ie_len; |
| 916 | struct cfg80211_match_set *match_sets; | ||
| 917 | int n_match_sets; | ||
| 898 | 918 | ||
| 899 | /* internal */ | 919 | /* internal */ |
| 900 | struct wiphy *wiphy; | 920 | struct wiphy *wiphy; |
| @@ -1619,6 +1639,9 @@ struct cfg80211_ops { | |||
| 1619 | * @WIPHY_FLAG_MESH_AUTH: The device supports mesh authentication by routing | 1639 | * @WIPHY_FLAG_MESH_AUTH: The device supports mesh authentication by routing |
| 1620 | * auth frames to userspace. See @NL80211_MESH_SETUP_USERSPACE_AUTH. | 1640 | * auth frames to userspace. See @NL80211_MESH_SETUP_USERSPACE_AUTH. |
| 1621 | * @WIPHY_FLAG_SUPPORTS_SCHED_SCAN: The device supports scheduled scans. | 1641 | * @WIPHY_FLAG_SUPPORTS_SCHED_SCAN: The device supports scheduled scans. |
| 1642 | * @WIPHY_FLAG_SUPPORTS_FW_ROAM: The device supports roaming feature in the | ||
| 1643 | * firmware. | ||
| 1644 | * @WIPHY_FLAG_AP_UAPSD: The device supports uapsd on AP. | ||
| 1622 | */ | 1645 | */ |
| 1623 | enum wiphy_flags { | 1646 | enum wiphy_flags { |
| 1624 | WIPHY_FLAG_CUSTOM_REGULATORY = BIT(0), | 1647 | WIPHY_FLAG_CUSTOM_REGULATORY = BIT(0), |
| @@ -1633,6 +1656,8 @@ enum wiphy_flags { | |||
| 1633 | WIPHY_FLAG_MESH_AUTH = BIT(10), | 1656 | WIPHY_FLAG_MESH_AUTH = BIT(10), |
| 1634 | WIPHY_FLAG_SUPPORTS_SCHED_SCAN = BIT(11), | 1657 | WIPHY_FLAG_SUPPORTS_SCHED_SCAN = BIT(11), |
| 1635 | WIPHY_FLAG_ENFORCE_COMBINATIONS = BIT(12), | 1658 | WIPHY_FLAG_ENFORCE_COMBINATIONS = BIT(12), |
| 1659 | WIPHY_FLAG_SUPPORTS_FW_ROAM = BIT(13), | ||
| 1660 | WIPHY_FLAG_AP_UAPSD = BIT(14), | ||
| 1636 | }; | 1661 | }; |
| 1637 | 1662 | ||
| 1638 | /** | 1663 | /** |
| @@ -1789,6 +1814,8 @@ struct wiphy_wowlan_support { | |||
| 1789 | * by default for perm_addr. In this case, the mask should be set to | 1814 | * by default for perm_addr. In this case, the mask should be set to |
| 1790 | * all-zeroes. In this case it is assumed that the device can handle | 1815 | * all-zeroes. In this case it is assumed that the device can handle |
| 1791 | * the same number of arbitrary MAC addresses. | 1816 | * the same number of arbitrary MAC addresses. |
| 1817 | * @registered: protects ->resume and ->suspend sysfs callbacks against | ||
| 1818 | * unregister hardware | ||
| 1792 | * @debugfsdir: debugfs directory used for this wiphy, will be renamed | 1819 | * @debugfsdir: debugfs directory used for this wiphy, will be renamed |
| 1793 | * automatically on wiphy renames | 1820 | * automatically on wiphy renames |
| 1794 | * @dev: (virtual) struct device for this wiphy | 1821 | * @dev: (virtual) struct device for this wiphy |
| @@ -1809,6 +1836,9 @@ struct wiphy_wowlan_support { | |||
| 1809 | * any given scan | 1836 | * any given scan |
| 1810 | * @max_sched_scan_ssids: maximum number of SSIDs the device can scan | 1837 | * @max_sched_scan_ssids: maximum number of SSIDs the device can scan |
| 1811 | * for in any given scheduled scan | 1838 | * for in any given scheduled scan |
| 1839 | * @max_match_sets: maximum number of match sets the device can handle | ||
| 1840 | * when performing a scheduled scan, 0 if filtering is not | ||
| 1841 | * supported. | ||
| 1812 | * @max_scan_ie_len: maximum length of user-controlled IEs device can | 1842 | * @max_scan_ie_len: maximum length of user-controlled IEs device can |
| 1813 | * add to probe request frames transmitted during a scan, must not | 1843 | * add to probe request frames transmitted during a scan, must not |
| 1814 | * include fixed IEs like supported rates | 1844 | * include fixed IEs like supported rates |
| @@ -1866,6 +1896,7 @@ struct wiphy { | |||
| 1866 | int bss_priv_size; | 1896 | int bss_priv_size; |
| 1867 | u8 max_scan_ssids; | 1897 | u8 max_scan_ssids; |
| 1868 | u8 max_sched_scan_ssids; | 1898 | u8 max_sched_scan_ssids; |
| 1899 | u8 max_match_sets; | ||
| 1869 | u16 max_scan_ie_len; | 1900 | u16 max_scan_ie_len; |
| 1870 | u16 max_sched_scan_ie_len; | 1901 | u16 max_sched_scan_ie_len; |
| 1871 | 1902 | ||
diff --git a/include/net/mac80211.h b/include/net/mac80211.h index 2e752df57510..9edba09547e4 100644 --- a/include/net/mac80211.h +++ b/include/net/mac80211.h | |||
| @@ -164,6 +164,7 @@ struct ieee80211_low_level_stats { | |||
| 164 | * @BSS_CHANGED_QOS: QoS for this association was enabled/disabled. Note | 164 | * @BSS_CHANGED_QOS: QoS for this association was enabled/disabled. Note |
| 165 | * that it is only ever disabled for station mode. | 165 | * that it is only ever disabled for station mode. |
| 166 | * @BSS_CHANGED_IDLE: Idle changed for this BSS/interface. | 166 | * @BSS_CHANGED_IDLE: Idle changed for this BSS/interface. |
| 167 | * @BSS_CHANGED_SSID: SSID changed for this BSS (AP mode) | ||
| 167 | */ | 168 | */ |
| 168 | enum ieee80211_bss_change { | 169 | enum ieee80211_bss_change { |
| 169 | BSS_CHANGED_ASSOC = 1<<0, | 170 | BSS_CHANGED_ASSOC = 1<<0, |
| @@ -181,6 +182,7 @@ enum ieee80211_bss_change { | |||
| 181 | BSS_CHANGED_ARP_FILTER = 1<<12, | 182 | BSS_CHANGED_ARP_FILTER = 1<<12, |
| 182 | BSS_CHANGED_QOS = 1<<13, | 183 | BSS_CHANGED_QOS = 1<<13, |
| 183 | BSS_CHANGED_IDLE = 1<<14, | 184 | BSS_CHANGED_IDLE = 1<<14, |
| 185 | BSS_CHANGED_SSID = 1<<15, | ||
| 184 | 186 | ||
| 185 | /* when adding here, make sure to change ieee80211_reconfig */ | 187 | /* when adding here, make sure to change ieee80211_reconfig */ |
| 186 | }; | 188 | }; |
| @@ -254,6 +256,9 @@ enum ieee80211_rssi_event { | |||
| 254 | * @idle: This interface is idle. There's also a global idle flag in the | 256 | * @idle: This interface is idle. There's also a global idle flag in the |
| 255 | * hardware config which may be more appropriate depending on what | 257 | * hardware config which may be more appropriate depending on what |
| 256 | * your driver/device needs to do. | 258 | * your driver/device needs to do. |
| 259 | * @ssid: The SSID of the current vif. Only valid in AP-mode. | ||
| 260 | * @ssid_len: Length of SSID given in @ssid. | ||
| 261 | * @hidden_ssid: The SSID of the current vif is hidden. Only valid in AP-mode. | ||
| 257 | */ | 262 | */ |
| 258 | struct ieee80211_bss_conf { | 263 | struct ieee80211_bss_conf { |
| 259 | const u8 *bssid; | 264 | const u8 *bssid; |
| @@ -280,6 +285,9 @@ struct ieee80211_bss_conf { | |||
| 280 | bool arp_filter_enabled; | 285 | bool arp_filter_enabled; |
| 281 | bool qos; | 286 | bool qos; |
| 282 | bool idle; | 287 | bool idle; |
| 288 | u8 ssid[IEEE80211_MAX_SSID_LEN]; | ||
| 289 | size_t ssid_len; | ||
| 290 | bool hidden_ssid; | ||
| 283 | }; | 291 | }; |
| 284 | 292 | ||
| 285 | /** | 293 | /** |
| @@ -947,6 +955,9 @@ enum set_key_cmd { | |||
| 947 | * @wme: indicates whether the STA supports WME. Only valid during AP-mode. | 955 | * @wme: indicates whether the STA supports WME. Only valid during AP-mode. |
| 948 | * @drv_priv: data area for driver use, will always be aligned to | 956 | * @drv_priv: data area for driver use, will always be aligned to |
| 949 | * sizeof(void *), size is determined in hw information. | 957 | * sizeof(void *), size is determined in hw information. |
| 958 | * @uapsd_queues: bitmap of queues configured for uapsd. Only valid | ||
| 959 | * if wme is supported. | ||
| 960 | * @max_sp: max Service Period. Only valid if wme is supported. | ||
| 950 | */ | 961 | */ |
| 951 | struct ieee80211_sta { | 962 | struct ieee80211_sta { |
| 952 | u32 supp_rates[IEEE80211_NUM_BANDS]; | 963 | u32 supp_rates[IEEE80211_NUM_BANDS]; |
| @@ -1096,6 +1107,10 @@ enum sta_notify_cmd { | |||
| 1096 | * stations based on the PM bit of incoming frames. | 1107 | * stations based on the PM bit of incoming frames. |
| 1097 | * Use ieee80211_start_ps()/ieee8021_end_ps() to manually configure | 1108 | * Use ieee80211_start_ps()/ieee8021_end_ps() to manually configure |
| 1098 | * the PS mode of connected stations. | 1109 | * the PS mode of connected stations. |
| 1110 | * | ||
| 1111 | * @IEEE80211_HW_TX_AMPDU_SETUP_IN_HW: The device handles TX A-MPDU session | ||
| 1112 | * setup strictly in HW. mac80211 should not attempt to do this in | ||
| 1113 | * software. | ||
| 1099 | */ | 1114 | */ |
| 1100 | enum ieee80211_hw_flags { | 1115 | enum ieee80211_hw_flags { |
| 1101 | IEEE80211_HW_HAS_RATE_CONTROL = 1<<0, | 1116 | IEEE80211_HW_HAS_RATE_CONTROL = 1<<0, |
| @@ -1121,6 +1136,7 @@ enum ieee80211_hw_flags { | |||
| 1121 | IEEE80211_HW_SUPPORTS_CQM_RSSI = 1<<20, | 1136 | IEEE80211_HW_SUPPORTS_CQM_RSSI = 1<<20, |
| 1122 | IEEE80211_HW_SUPPORTS_PER_STA_GTK = 1<<21, | 1137 | IEEE80211_HW_SUPPORTS_PER_STA_GTK = 1<<21, |
| 1123 | IEEE80211_HW_AP_LINK_PS = 1<<22, | 1138 | IEEE80211_HW_AP_LINK_PS = 1<<22, |
| 1139 | IEEE80211_HW_TX_AMPDU_SETUP_IN_HW = 1<<23, | ||
| 1124 | }; | 1140 | }; |
| 1125 | 1141 | ||
| 1126 | /** | 1142 | /** |
| @@ -3220,6 +3236,19 @@ void ieee80211_remain_on_channel_expired(struct ieee80211_hw *hw); | |||
| 3220 | void ieee80211_stop_rx_ba_session(struct ieee80211_vif *vif, u16 ba_rx_bitmap, | 3236 | void ieee80211_stop_rx_ba_session(struct ieee80211_vif *vif, u16 ba_rx_bitmap, |
| 3221 | const u8 *addr); | 3237 | const u8 *addr); |
| 3222 | 3238 | ||
| 3239 | /** | ||
| 3240 | * ieee80211_send_bar - send a BlockAckReq frame | ||
| 3241 | * | ||
| 3242 | * can be used to flush pending frames from the peer's aggregation reorder | ||
| 3243 | * buffer. | ||
| 3244 | * | ||
| 3245 | * @vif: &struct ieee80211_vif pointer from the add_interface callback. | ||
| 3246 | * @ra: the peer's destination address | ||
| 3247 | * @tid: the TID of the aggregation session | ||
| 3248 | * @ssn: the new starting sequence number for the receiver | ||
| 3249 | */ | ||
| 3250 | void ieee80211_send_bar(struct ieee80211_vif *vif, u8 *ra, u16 tid, u16 ssn); | ||
| 3251 | |||
| 3223 | /* Rate control API */ | 3252 | /* Rate control API */ |
| 3224 | 3253 | ||
| 3225 | /** | 3254 | /** |
diff --git a/net/mac80211/agg-rx.c b/net/mac80211/agg-rx.c index 9b5bd8cafc20..7c366dfe8da9 100644 --- a/net/mac80211/agg-rx.c +++ b/net/mac80211/agg-rx.c | |||
| @@ -167,12 +167,8 @@ static void ieee80211_send_addba_resp(struct ieee80211_sub_if_data *sdata, u8 *d | |||
| 167 | u16 capab; | 167 | u16 capab; |
| 168 | 168 | ||
| 169 | skb = dev_alloc_skb(sizeof(*mgmt) + local->hw.extra_tx_headroom); | 169 | skb = dev_alloc_skb(sizeof(*mgmt) + local->hw.extra_tx_headroom); |
| 170 | 170 | if (!skb) | |
| 171 | if (!skb) { | ||
| 172 | printk(KERN_DEBUG "%s: failed to allocate buffer " | ||
| 173 | "for addba resp frame\n", sdata->name); | ||
| 174 | return; | 171 | return; |
| 175 | } | ||
| 176 | 172 | ||
| 177 | skb_reserve(skb, local->hw.extra_tx_headroom); | 173 | skb_reserve(skb, local->hw.extra_tx_headroom); |
| 178 | mgmt = (struct ieee80211_mgmt *) skb_put(skb, 24); | 174 | mgmt = (struct ieee80211_mgmt *) skb_put(skb, 24); |
| @@ -279,14 +275,8 @@ void ieee80211_process_addba_request(struct ieee80211_local *local, | |||
| 279 | 275 | ||
| 280 | /* prepare A-MPDU MLME for Rx aggregation */ | 276 | /* prepare A-MPDU MLME for Rx aggregation */ |
| 281 | tid_agg_rx = kmalloc(sizeof(struct tid_ampdu_rx), GFP_KERNEL); | 277 | tid_agg_rx = kmalloc(sizeof(struct tid_ampdu_rx), GFP_KERNEL); |
| 282 | if (!tid_agg_rx) { | 278 | if (!tid_agg_rx) |
| 283 | #ifdef CONFIG_MAC80211_HT_DEBUG | ||
| 284 | if (net_ratelimit()) | ||
| 285 | printk(KERN_ERR "allocate rx mlme to tid %d failed\n", | ||
| 286 | tid); | ||
| 287 | #endif | ||
| 288 | goto end; | 279 | goto end; |
| 289 | } | ||
| 290 | 280 | ||
| 291 | spin_lock_init(&tid_agg_rx->reorder_lock); | 281 | spin_lock_init(&tid_agg_rx->reorder_lock); |
| 292 | 282 | ||
| @@ -306,11 +296,6 @@ void ieee80211_process_addba_request(struct ieee80211_local *local, | |||
| 306 | tid_agg_rx->reorder_time = | 296 | tid_agg_rx->reorder_time = |
| 307 | kcalloc(buf_size, sizeof(unsigned long), GFP_KERNEL); | 297 | kcalloc(buf_size, sizeof(unsigned long), GFP_KERNEL); |
| 308 | if (!tid_agg_rx->reorder_buf || !tid_agg_rx->reorder_time) { | 298 | if (!tid_agg_rx->reorder_buf || !tid_agg_rx->reorder_time) { |
| 309 | #ifdef CONFIG_MAC80211_HT_DEBUG | ||
| 310 | if (net_ratelimit()) | ||
| 311 | printk(KERN_ERR "can not allocate reordering buffer " | ||
| 312 | "to tid %d\n", tid); | ||
| 313 | #endif | ||
| 314 | kfree(tid_agg_rx->reorder_buf); | 299 | kfree(tid_agg_rx->reorder_buf); |
| 315 | kfree(tid_agg_rx->reorder_time); | 300 | kfree(tid_agg_rx->reorder_time); |
| 316 | kfree(tid_agg_rx); | 301 | kfree(tid_agg_rx); |
diff --git a/net/mac80211/agg-tx.c b/net/mac80211/agg-tx.c index 018108d1a2fd..3cef5a7281cb 100644 --- a/net/mac80211/agg-tx.c +++ b/net/mac80211/agg-tx.c | |||
| @@ -68,11 +68,9 @@ static void ieee80211_send_addba_request(struct ieee80211_sub_if_data *sdata, | |||
| 68 | 68 | ||
| 69 | skb = dev_alloc_skb(sizeof(*mgmt) + local->hw.extra_tx_headroom); | 69 | skb = dev_alloc_skb(sizeof(*mgmt) + local->hw.extra_tx_headroom); |
| 70 | 70 | ||
| 71 | if (!skb) { | 71 | if (!skb) |
| 72 | printk(KERN_ERR "%s: failed to allocate buffer " | ||
| 73 | "for addba request frame\n", sdata->name); | ||
| 74 | return; | 72 | return; |
| 75 | } | 73 | |
| 76 | skb_reserve(skb, local->hw.extra_tx_headroom); | 74 | skb_reserve(skb, local->hw.extra_tx_headroom); |
| 77 | mgmt = (struct ieee80211_mgmt *) skb_put(skb, 24); | 75 | mgmt = (struct ieee80211_mgmt *) skb_put(skb, 24); |
| 78 | memset(mgmt, 0, 24); | 76 | memset(mgmt, 0, 24); |
| @@ -106,19 +104,18 @@ static void ieee80211_send_addba_request(struct ieee80211_sub_if_data *sdata, | |||
| 106 | ieee80211_tx_skb(sdata, skb); | 104 | ieee80211_tx_skb(sdata, skb); |
| 107 | } | 105 | } |
| 108 | 106 | ||
| 109 | void ieee80211_send_bar(struct ieee80211_sub_if_data *sdata, u8 *ra, u16 tid, u16 ssn) | 107 | void ieee80211_send_bar(struct ieee80211_vif *vif, u8 *ra, u16 tid, u16 ssn) |
| 110 | { | 108 | { |
| 109 | struct ieee80211_sub_if_data *sdata = vif_to_sdata(vif); | ||
| 111 | struct ieee80211_local *local = sdata->local; | 110 | struct ieee80211_local *local = sdata->local; |
| 112 | struct sk_buff *skb; | 111 | struct sk_buff *skb; |
| 113 | struct ieee80211_bar *bar; | 112 | struct ieee80211_bar *bar; |
| 114 | u16 bar_control = 0; | 113 | u16 bar_control = 0; |
| 115 | 114 | ||
| 116 | skb = dev_alloc_skb(sizeof(*bar) + local->hw.extra_tx_headroom); | 115 | skb = dev_alloc_skb(sizeof(*bar) + local->hw.extra_tx_headroom); |
| 117 | if (!skb) { | 116 | if (!skb) |
| 118 | printk(KERN_ERR "%s: failed to allocate buffer for " | ||
| 119 | "bar frame\n", sdata->name); | ||
| 120 | return; | 117 | return; |
| 121 | } | 118 | |
| 122 | skb_reserve(skb, local->hw.extra_tx_headroom); | 119 | skb_reserve(skb, local->hw.extra_tx_headroom); |
| 123 | bar = (struct ieee80211_bar *)skb_put(skb, sizeof(*bar)); | 120 | bar = (struct ieee80211_bar *)skb_put(skb, sizeof(*bar)); |
| 124 | memset(bar, 0, sizeof(*bar)); | 121 | memset(bar, 0, sizeof(*bar)); |
| @@ -135,6 +132,7 @@ void ieee80211_send_bar(struct ieee80211_sub_if_data *sdata, u8 *ra, u16 tid, u1 | |||
| 135 | IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_INTFL_DONT_ENCRYPT; | 132 | IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_INTFL_DONT_ENCRYPT; |
| 136 | ieee80211_tx_skb(sdata, skb); | 133 | ieee80211_tx_skb(sdata, skb); |
| 137 | } | 134 | } |
| 135 | EXPORT_SYMBOL(ieee80211_send_bar); | ||
| 138 | 136 | ||
| 139 | void ieee80211_assign_tid_tx(struct sta_info *sta, int tid, | 137 | void ieee80211_assign_tid_tx(struct sta_info *sta, int tid, |
| 140 | struct tid_ampdu_tx *tid_tx) | 138 | struct tid_ampdu_tx *tid_tx) |
| @@ -364,7 +362,8 @@ int ieee80211_start_tx_ba_session(struct ieee80211_sta *pubsta, u16 tid, | |||
| 364 | return -EINVAL; | 362 | return -EINVAL; |
| 365 | 363 | ||
| 366 | if ((tid >= STA_TID_NUM) || | 364 | if ((tid >= STA_TID_NUM) || |
| 367 | !(local->hw.flags & IEEE80211_HW_AMPDU_AGGREGATION)) | 365 | !(local->hw.flags & IEEE80211_HW_AMPDU_AGGREGATION) || |
| 366 | (local->hw.flags & IEEE80211_HW_TX_AMPDU_SETUP_IN_HW)) | ||
| 368 | return -EINVAL; | 367 | return -EINVAL; |
| 369 | 368 | ||
| 370 | #ifdef CONFIG_MAC80211_HT_DEBUG | 369 | #ifdef CONFIG_MAC80211_HT_DEBUG |
| @@ -413,11 +412,6 @@ int ieee80211_start_tx_ba_session(struct ieee80211_sta *pubsta, u16 tid, | |||
| 413 | /* prepare A-MPDU MLME for Tx aggregation */ | 412 | /* prepare A-MPDU MLME for Tx aggregation */ |
| 414 | tid_tx = kzalloc(sizeof(struct tid_ampdu_tx), GFP_ATOMIC); | 413 | tid_tx = kzalloc(sizeof(struct tid_ampdu_tx), GFP_ATOMIC); |
| 415 | if (!tid_tx) { | 414 | if (!tid_tx) { |
| 416 | #ifdef CONFIG_MAC80211_HT_DEBUG | ||
| 417 | if (net_ratelimit()) | ||
| 418 | printk(KERN_ERR "allocate tx mlme to tid %d failed\n", | ||
| 419 | tid); | ||
| 420 | #endif | ||
| 421 | ret = -ENOMEM; | 415 | ret = -ENOMEM; |
| 422 | goto err_unlock_sta; | 416 | goto err_unlock_sta; |
| 423 | } | 417 | } |
| @@ -574,14 +568,9 @@ void ieee80211_start_tx_ba_cb_irqsafe(struct ieee80211_vif *vif, | |||
| 574 | struct ieee80211_ra_tid *ra_tid; | 568 | struct ieee80211_ra_tid *ra_tid; |
| 575 | struct sk_buff *skb = dev_alloc_skb(0); | 569 | struct sk_buff *skb = dev_alloc_skb(0); |
| 576 | 570 | ||
| 577 | if (unlikely(!skb)) { | 571 | if (unlikely(!skb)) |
| 578 | #ifdef CONFIG_MAC80211_HT_DEBUG | ||
| 579 | if (net_ratelimit()) | ||
| 580 | printk(KERN_WARNING "%s: Not enough memory, " | ||
| 581 | "dropping start BA session", sdata->name); | ||
| 582 | #endif | ||
| 583 | return; | 572 | return; |
| 584 | } | 573 | |
| 585 | ra_tid = (struct ieee80211_ra_tid *) &skb->cb; | 574 | ra_tid = (struct ieee80211_ra_tid *) &skb->cb; |
| 586 | memcpy(&ra_tid->ra, ra, ETH_ALEN); | 575 | memcpy(&ra_tid->ra, ra, ETH_ALEN); |
| 587 | ra_tid->tid = tid; | 576 | ra_tid->tid = tid; |
| @@ -727,14 +716,9 @@ void ieee80211_stop_tx_ba_cb_irqsafe(struct ieee80211_vif *vif, | |||
| 727 | struct ieee80211_ra_tid *ra_tid; | 716 | struct ieee80211_ra_tid *ra_tid; |
| 728 | struct sk_buff *skb = dev_alloc_skb(0); | 717 | struct sk_buff *skb = dev_alloc_skb(0); |
| 729 | 718 | ||
| 730 | if (unlikely(!skb)) { | 719 | if (unlikely(!skb)) |
| 731 | #ifdef CONFIG_MAC80211_HT_DEBUG | ||
| 732 | if (net_ratelimit()) | ||
| 733 | printk(KERN_WARNING "%s: Not enough memory, " | ||
| 734 | "dropping stop BA session", sdata->name); | ||
| 735 | #endif | ||
| 736 | return; | 720 | return; |
| 737 | } | 721 | |
| 738 | ra_tid = (struct ieee80211_ra_tid *) &skb->cb; | 722 | ra_tid = (struct ieee80211_ra_tid *) &skb->cb; |
| 739 | memcpy(&ra_tid->ra, ra, ETH_ALEN); | 723 | memcpy(&ra_tid->ra, ra, ETH_ALEN); |
| 740 | ra_tid->tid = tid; | 724 | ra_tid->tid = tid; |
diff --git a/net/mac80211/cfg.c b/net/mac80211/cfg.c index 4baa03b1c251..567e3e54685a 100644 --- a/net/mac80211/cfg.c +++ b/net/mac80211/cfg.c | |||
| @@ -455,6 +455,20 @@ static int ieee80211_get_station(struct wiphy *wiphy, struct net_device *dev, | |||
| 455 | return ret; | 455 | return ret; |
| 456 | } | 456 | } |
| 457 | 457 | ||
| 458 | static void ieee80211_config_ap_ssid(struct ieee80211_sub_if_data *sdata, | ||
| 459 | struct beacon_parameters *params) | ||
| 460 | { | ||
| 461 | struct ieee80211_bss_conf *bss_conf = &sdata->vif.bss_conf; | ||
| 462 | |||
| 463 | bss_conf->ssid_len = params->ssid_len; | ||
| 464 | |||
| 465 | if (params->ssid_len) | ||
| 466 | memcpy(bss_conf->ssid, params->ssid, params->ssid_len); | ||
| 467 | |||
| 468 | bss_conf->hidden_ssid = | ||
| 469 | (params->hidden_ssid != NL80211_HIDDEN_SSID_NOT_IN_USE); | ||
| 470 | } | ||
| 471 | |||
| 458 | /* | 472 | /* |
| 459 | * This handles both adding a beacon and setting new beacon info | 473 | * This handles both adding a beacon and setting new beacon info |
| 460 | */ | 474 | */ |
| @@ -548,8 +562,11 @@ static int ieee80211_config_beacon(struct ieee80211_sub_if_data *sdata, | |||
| 548 | 562 | ||
| 549 | kfree(old); | 563 | kfree(old); |
| 550 | 564 | ||
| 565 | ieee80211_config_ap_ssid(sdata, params); | ||
| 566 | |||
| 551 | ieee80211_bss_info_change_notify(sdata, BSS_CHANGED_BEACON_ENABLED | | 567 | ieee80211_bss_info_change_notify(sdata, BSS_CHANGED_BEACON_ENABLED | |
| 552 | BSS_CHANGED_BEACON); | 568 | BSS_CHANGED_BEACON | |
| 569 | BSS_CHANGED_SSID); | ||
| 553 | return 0; | 570 | return 0; |
| 554 | } | 571 | } |
| 555 | 572 | ||
| @@ -921,7 +938,7 @@ static int ieee80211_del_mpath(struct wiphy *wiphy, struct net_device *dev, | |||
| 921 | if (dst) | 938 | if (dst) |
| 922 | return mesh_path_del(dst, sdata); | 939 | return mesh_path_del(dst, sdata); |
| 923 | 940 | ||
| 924 | mesh_path_flush(sdata); | 941 | mesh_path_flush_by_iface(sdata); |
| 925 | return 0; | 942 | return 0; |
| 926 | } | 943 | } |
| 927 | 944 | ||
diff --git a/net/mac80211/debugfs.c b/net/mac80211/debugfs.c index 267ed45ef6a2..c9141168fd43 100644 --- a/net/mac80211/debugfs.c +++ b/net/mac80211/debugfs.c | |||
| @@ -297,6 +297,9 @@ static ssize_t hwflags_read(struct file *file, char __user *user_buf, | |||
| 297 | char *buf = kzalloc(mxln, GFP_KERNEL); | 297 | char *buf = kzalloc(mxln, GFP_KERNEL); |
| 298 | int sf = 0; /* how many written so far */ | 298 | int sf = 0; /* how many written so far */ |
| 299 | 299 | ||
| 300 | if (!buf) | ||
| 301 | return 0; | ||
| 302 | |||
| 300 | sf += snprintf(buf, mxln - sf, "0x%x\n", local->hw.flags); | 303 | sf += snprintf(buf, mxln - sf, "0x%x\n", local->hw.flags); |
| 301 | if (local->hw.flags & IEEE80211_HW_HAS_RATE_CONTROL) | 304 | if (local->hw.flags & IEEE80211_HW_HAS_RATE_CONTROL) |
| 302 | sf += snprintf(buf + sf, mxln - sf, "HAS_RATE_CONTROL\n"); | 305 | sf += snprintf(buf + sf, mxln - sf, "HAS_RATE_CONTROL\n"); |
| @@ -347,6 +350,8 @@ static ssize_t hwflags_read(struct file *file, char __user *user_buf, | |||
| 347 | sf += snprintf(buf + sf, mxln - sf, "SUPPORTS_PER_STA_GTK\n"); | 350 | sf += snprintf(buf + sf, mxln - sf, "SUPPORTS_PER_STA_GTK\n"); |
| 348 | if (local->hw.flags & IEEE80211_HW_AP_LINK_PS) | 351 | if (local->hw.flags & IEEE80211_HW_AP_LINK_PS) |
| 349 | sf += snprintf(buf + sf, mxln - sf, "AP_LINK_PS\n"); | 352 | sf += snprintf(buf + sf, mxln - sf, "AP_LINK_PS\n"); |
| 353 | if (local->hw.flags & IEEE80211_HW_TX_AMPDU_SETUP_IN_HW) | ||
| 354 | sf += snprintf(buf + sf, mxln - sf, "TX_AMPDU_SETUP_IN_HW\n"); | ||
| 350 | 355 | ||
| 351 | rv = simple_read_from_buffer(user_buf, count, ppos, buf, strlen(buf)); | 356 | rv = simple_read_from_buffer(user_buf, count, ppos, buf, strlen(buf)); |
| 352 | kfree(buf); | 357 | kfree(buf); |
diff --git a/net/mac80211/debugfs_netdev.c b/net/mac80211/debugfs_netdev.c index 6e8eab7919e2..dd0462917518 100644 --- a/net/mac80211/debugfs_netdev.c +++ b/net/mac80211/debugfs_netdev.c | |||
| @@ -340,6 +340,8 @@ IEEE80211_IF_FILE(fwded_mcast, u.mesh.mshstats.fwded_mcast, DEC); | |||
| 340 | IEEE80211_IF_FILE(fwded_unicast, u.mesh.mshstats.fwded_unicast, DEC); | 340 | IEEE80211_IF_FILE(fwded_unicast, u.mesh.mshstats.fwded_unicast, DEC); |
| 341 | IEEE80211_IF_FILE(fwded_frames, u.mesh.mshstats.fwded_frames, DEC); | 341 | IEEE80211_IF_FILE(fwded_frames, u.mesh.mshstats.fwded_frames, DEC); |
| 342 | IEEE80211_IF_FILE(dropped_frames_ttl, u.mesh.mshstats.dropped_frames_ttl, DEC); | 342 | IEEE80211_IF_FILE(dropped_frames_ttl, u.mesh.mshstats.dropped_frames_ttl, DEC); |
| 343 | IEEE80211_IF_FILE(dropped_frames_congestion, | ||
| 344 | u.mesh.mshstats.dropped_frames_congestion, DEC); | ||
| 343 | IEEE80211_IF_FILE(dropped_frames_no_route, | 345 | IEEE80211_IF_FILE(dropped_frames_no_route, |
| 344 | u.mesh.mshstats.dropped_frames_no_route, DEC); | 346 | u.mesh.mshstats.dropped_frames_no_route, DEC); |
| 345 | IEEE80211_IF_FILE(estab_plinks, u.mesh.mshstats.estab_plinks, ATOMIC); | 347 | IEEE80211_IF_FILE(estab_plinks, u.mesh.mshstats.estab_plinks, ATOMIC); |
| @@ -463,6 +465,7 @@ static void add_mesh_stats(struct ieee80211_sub_if_data *sdata) | |||
| 463 | MESHSTATS_ADD(fwded_frames); | 465 | MESHSTATS_ADD(fwded_frames); |
| 464 | MESHSTATS_ADD(dropped_frames_ttl); | 466 | MESHSTATS_ADD(dropped_frames_ttl); |
| 465 | MESHSTATS_ADD(dropped_frames_no_route); | 467 | MESHSTATS_ADD(dropped_frames_no_route); |
| 468 | MESHSTATS_ADD(dropped_frames_congestion); | ||
| 466 | MESHSTATS_ADD(estab_plinks); | 469 | MESHSTATS_ADD(estab_plinks); |
| 467 | #undef MESHSTATS_ADD | 470 | #undef MESHSTATS_ADD |
| 468 | } | 471 | } |
diff --git a/net/mac80211/ht.c b/net/mac80211/ht.c index 7cfc286946c0..2b9b52c69569 100644 --- a/net/mac80211/ht.c +++ b/net/mac80211/ht.c | |||
| @@ -186,12 +186,8 @@ void ieee80211_send_delba(struct ieee80211_sub_if_data *sdata, | |||
| 186 | u16 params; | 186 | u16 params; |
| 187 | 187 | ||
| 188 | skb = dev_alloc_skb(sizeof(*mgmt) + local->hw.extra_tx_headroom); | 188 | skb = dev_alloc_skb(sizeof(*mgmt) + local->hw.extra_tx_headroom); |
| 189 | 189 | if (!skb) | |
| 190 | if (!skb) { | ||
| 191 | printk(KERN_ERR "%s: failed to allocate buffer " | ||
| 192 | "for delba frame\n", sdata->name); | ||
| 193 | return; | 190 | return; |
| 194 | } | ||
| 195 | 191 | ||
| 196 | skb_reserve(skb, local->hw.extra_tx_headroom); | 192 | skb_reserve(skb, local->hw.extra_tx_headroom); |
| 197 | mgmt = (struct ieee80211_mgmt *) skb_put(skb, 24); | 193 | mgmt = (struct ieee80211_mgmt *) skb_put(skb, 24); |
diff --git a/net/mac80211/ieee80211_i.h b/net/mac80211/ieee80211_i.h index c204cee1189c..21186e280ceb 100644 --- a/net/mac80211/ieee80211_i.h +++ b/net/mac80211/ieee80211_i.h | |||
| @@ -261,6 +261,7 @@ struct mesh_stats { | |||
| 261 | __u32 fwded_frames; /* Mesh total forwarded frames */ | 261 | __u32 fwded_frames; /* Mesh total forwarded frames */ |
| 262 | __u32 dropped_frames_ttl; /* Not transmitted since mesh_ttl == 0*/ | 262 | __u32 dropped_frames_ttl; /* Not transmitted since mesh_ttl == 0*/ |
| 263 | __u32 dropped_frames_no_route; /* Not transmitted, no route found */ | 263 | __u32 dropped_frames_no_route; /* Not transmitted, no route found */ |
| 264 | __u32 dropped_frames_congestion;/* Not forwarded due to congestion */ | ||
| 264 | atomic_t estab_plinks; | 265 | atomic_t estab_plinks; |
| 265 | }; | 266 | }; |
| 266 | 267 | ||
| @@ -670,6 +671,7 @@ enum queue_stop_reason { | |||
| 670 | IEEE80211_QUEUE_STOP_REASON_AGGREGATION, | 671 | IEEE80211_QUEUE_STOP_REASON_AGGREGATION, |
| 671 | IEEE80211_QUEUE_STOP_REASON_SUSPEND, | 672 | IEEE80211_QUEUE_STOP_REASON_SUSPEND, |
| 672 | IEEE80211_QUEUE_STOP_REASON_SKB_ADD, | 673 | IEEE80211_QUEUE_STOP_REASON_SKB_ADD, |
| 674 | IEEE80211_QUEUE_STOP_REASON_CHTYPE_CHANGE, | ||
| 673 | }; | 675 | }; |
| 674 | 676 | ||
| 675 | #ifdef CONFIG_MAC80211_LEDS | 677 | #ifdef CONFIG_MAC80211_LEDS |
| @@ -1186,7 +1188,6 @@ struct ieee80211_tx_status_rtap_hdr { | |||
| 1186 | void ieee80211_ht_cap_ie_to_sta_ht_cap(struct ieee80211_supported_band *sband, | 1188 | void ieee80211_ht_cap_ie_to_sta_ht_cap(struct ieee80211_supported_band *sband, |
| 1187 | struct ieee80211_ht_cap *ht_cap_ie, | 1189 | struct ieee80211_ht_cap *ht_cap_ie, |
| 1188 | struct ieee80211_sta_ht_cap *ht_cap); | 1190 | struct ieee80211_sta_ht_cap *ht_cap); |
| 1189 | void ieee80211_send_bar(struct ieee80211_sub_if_data *sdata, u8 *ra, u16 tid, u16 ssn); | ||
| 1190 | void ieee80211_send_delba(struct ieee80211_sub_if_data *sdata, | 1191 | void ieee80211_send_delba(struct ieee80211_sub_if_data *sdata, |
| 1191 | const u8 *da, u16 tid, | 1192 | const u8 *da, u16 tid, |
| 1192 | u16 initiator, u16 reason_code); | 1193 | u16 initiator, u16 reason_code); |
diff --git a/net/mac80211/iface.c b/net/mac80211/iface.c index d10dc4df60b6..a33c58f5137c 100644 --- a/net/mac80211/iface.c +++ b/net/mac80211/iface.c | |||
| @@ -1214,6 +1214,9 @@ void ieee80211_if_remove(struct ieee80211_sub_if_data *sdata) | |||
| 1214 | list_del_rcu(&sdata->list); | 1214 | list_del_rcu(&sdata->list); |
| 1215 | mutex_unlock(&sdata->local->iflist_mtx); | 1215 | mutex_unlock(&sdata->local->iflist_mtx); |
| 1216 | 1216 | ||
| 1217 | if (ieee80211_vif_is_mesh(&sdata->vif)) | ||
| 1218 | mesh_path_flush_by_iface(sdata); | ||
| 1219 | |||
| 1217 | synchronize_rcu(); | 1220 | synchronize_rcu(); |
| 1218 | unregister_netdevice(sdata->dev); | 1221 | unregister_netdevice(sdata->dev); |
| 1219 | } | 1222 | } |
| @@ -1233,6 +1236,9 @@ void ieee80211_remove_interfaces(struct ieee80211_local *local) | |||
| 1233 | list_for_each_entry_safe(sdata, tmp, &local->interfaces, list) { | 1236 | list_for_each_entry_safe(sdata, tmp, &local->interfaces, list) { |
| 1234 | list_del(&sdata->list); | 1237 | list_del(&sdata->list); |
| 1235 | 1238 | ||
| 1239 | if (ieee80211_vif_is_mesh(&sdata->vif)) | ||
| 1240 | mesh_path_flush_by_iface(sdata); | ||
| 1241 | |||
| 1236 | unregister_netdevice_queue(sdata->dev, &unreg_list); | 1242 | unregister_netdevice_queue(sdata->dev, &unreg_list); |
| 1237 | } | 1243 | } |
| 1238 | mutex_unlock(&local->iflist_mtx); | 1244 | mutex_unlock(&local->iflist_mtx); |
diff --git a/net/mac80211/mesh.c b/net/mac80211/mesh.c index 28ab510e621a..a4225ae69681 100644 --- a/net/mac80211/mesh.c +++ b/net/mac80211/mesh.c | |||
| @@ -200,10 +200,9 @@ int mesh_rmc_check(u8 *sa, struct ieee80211s_hdr *mesh_hdr, | |||
| 200 | } | 200 | } |
| 201 | 201 | ||
| 202 | p = kmem_cache_alloc(rm_cache, GFP_ATOMIC); | 202 | p = kmem_cache_alloc(rm_cache, GFP_ATOMIC); |
| 203 | if (!p) { | 203 | if (!p) |
| 204 | printk(KERN_DEBUG "o11s: could not allocate RMC entry\n"); | ||
| 205 | return 0; | 204 | return 0; |
| 206 | } | 205 | |
| 207 | p->seqnum = seqnum; | 206 | p->seqnum = seqnum; |
| 208 | p->exp_time = jiffies + RMC_TIMEOUT; | 207 | p->exp_time = jiffies + RMC_TIMEOUT; |
| 209 | memcpy(p->sa, sa, ETH_ALEN); | 208 | memcpy(p->sa, sa, ETH_ALEN); |
| @@ -464,8 +463,7 @@ int ieee80211_fill_mesh_addresses(struct ieee80211_hdr *hdr, __le16 *fc, | |||
| 464 | memcpy(hdr->addr3, meshsa, ETH_ALEN); | 463 | memcpy(hdr->addr3, meshsa, ETH_ALEN); |
| 465 | return 24; | 464 | return 24; |
| 466 | } else { | 465 | } else { |
| 467 | *fc |= cpu_to_le16(IEEE80211_FCTL_FROMDS | | 466 | *fc |= cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS); |
| 468 | IEEE80211_FCTL_TODS); | ||
| 469 | /* RA TA DA SA */ | 467 | /* RA TA DA SA */ |
| 470 | memset(hdr->addr1, 0, ETH_ALEN); /* RA is resolved later */ | 468 | memset(hdr->addr1, 0, ETH_ALEN); /* RA is resolved later */ |
| 471 | memcpy(hdr->addr2, meshsa, ETH_ALEN); | 469 | memcpy(hdr->addr2, meshsa, ETH_ALEN); |
diff --git a/net/mac80211/mesh.h b/net/mac80211/mesh.h index 20272072171f..7118e8e8855c 100644 --- a/net/mac80211/mesh.h +++ b/net/mac80211/mesh.h | |||
| @@ -80,7 +80,9 @@ enum mesh_deferred_task_flags { | |||
| 80 | * retry | 80 | * retry |
| 81 | * @discovery_retries: number of discovery retries | 81 | * @discovery_retries: number of discovery retries |
| 82 | * @flags: mesh path flags, as specified on &enum mesh_path_flags | 82 | * @flags: mesh path flags, as specified on &enum mesh_path_flags |
| 83 | * @state_lock: mesh path state lock | 83 | * @state_lock: mesh path state lock used to protect changes to the |
| 84 | * mpath itself. No need to take this lock when adding or removing | ||
| 85 | * an mpath to a hash bucket on a path table. | ||
| 84 | * @is_gate: the destination station of this path is a mesh gate | 86 | * @is_gate: the destination station of this path is a mesh gate |
| 85 | * | 87 | * |
| 86 | * | 88 | * |
| @@ -238,7 +240,6 @@ struct mesh_path *mesh_path_lookup_by_idx(int idx, | |||
| 238 | struct ieee80211_sub_if_data *sdata); | 240 | struct ieee80211_sub_if_data *sdata); |
| 239 | void mesh_path_fix_nexthop(struct mesh_path *mpath, struct sta_info *next_hop); | 241 | void mesh_path_fix_nexthop(struct mesh_path *mpath, struct sta_info *next_hop); |
| 240 | void mesh_path_expire(struct ieee80211_sub_if_data *sdata); | 242 | void mesh_path_expire(struct ieee80211_sub_if_data *sdata); |
| 241 | void mesh_path_flush(struct ieee80211_sub_if_data *sdata); | ||
| 242 | void mesh_rx_path_sel_frame(struct ieee80211_sub_if_data *sdata, | 243 | void mesh_rx_path_sel_frame(struct ieee80211_sub_if_data *sdata, |
| 243 | struct ieee80211_mgmt *mgmt, size_t len); | 244 | struct ieee80211_mgmt *mgmt, size_t len); |
| 244 | int mesh_path_add(u8 *dst, struct ieee80211_sub_if_data *sdata); | 245 | int mesh_path_add(u8 *dst, struct ieee80211_sub_if_data *sdata); |
| @@ -275,6 +276,7 @@ void mesh_pathtbl_unregister(void); | |||
| 275 | int mesh_path_del(u8 *addr, struct ieee80211_sub_if_data *sdata); | 276 | int mesh_path_del(u8 *addr, struct ieee80211_sub_if_data *sdata); |
| 276 | void mesh_path_timer(unsigned long data); | 277 | void mesh_path_timer(unsigned long data); |
| 277 | void mesh_path_flush_by_nexthop(struct sta_info *sta); | 278 | void mesh_path_flush_by_nexthop(struct sta_info *sta); |
| 279 | void mesh_path_flush_by_iface(struct ieee80211_sub_if_data *sdata); | ||
| 278 | void mesh_path_discard_frame(struct sk_buff *skb, | 280 | void mesh_path_discard_frame(struct sk_buff *skb, |
| 279 | struct ieee80211_sub_if_data *sdata); | 281 | struct ieee80211_sub_if_data *sdata); |
| 280 | void mesh_path_quiesce(struct ieee80211_sub_if_data *sdata); | 282 | void mesh_path_quiesce(struct ieee80211_sub_if_data *sdata); |
diff --git a/net/mac80211/mesh_hwmp.c b/net/mac80211/mesh_hwmp.c index fd4f76a3e139..6df7913d7ca4 100644 --- a/net/mac80211/mesh_hwmp.c +++ b/net/mac80211/mesh_hwmp.c | |||
| @@ -8,6 +8,7 @@ | |||
| 8 | */ | 8 | */ |
| 9 | 9 | ||
| 10 | #include <linux/slab.h> | 10 | #include <linux/slab.h> |
| 11 | #include "wme.h" | ||
| 11 | #include "mesh.h" | 12 | #include "mesh.h" |
| 12 | 13 | ||
| 13 | #ifdef CONFIG_MAC80211_VERBOSE_MHWMP_DEBUG | 14 | #ifdef CONFIG_MAC80211_VERBOSE_MHWMP_DEBUG |
| @@ -202,6 +203,26 @@ static int mesh_path_sel_frame_tx(enum mpath_frame_type action, u8 flags, | |||
| 202 | return 0; | 203 | return 0; |
| 203 | } | 204 | } |
| 204 | 205 | ||
| 206 | |||
| 207 | /* Headroom is not adjusted. Caller should ensure that skb has sufficient | ||
| 208 | * headroom in case the frame is encrypted. */ | ||
| 209 | static void prepare_frame_for_deferred_tx(struct ieee80211_sub_if_data *sdata, | ||
| 210 | struct sk_buff *skb) | ||
| 211 | { | ||
| 212 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | ||
| 213 | |||
| 214 | skb_set_mac_header(skb, 0); | ||
| 215 | skb_set_network_header(skb, 0); | ||
| 216 | skb_set_transport_header(skb, 0); | ||
| 217 | |||
| 218 | /* Send all internal mgmt frames on VO. Accordingly set TID to 7. */ | ||
| 219 | skb_set_queue_mapping(skb, IEEE80211_AC_VO); | ||
| 220 | skb->priority = 7; | ||
| 221 | |||
| 222 | info->control.vif = &sdata->vif; | ||
| 223 | ieee80211_set_qos_hdr(sdata, skb); | ||
| 224 | } | ||
| 225 | |||
| 205 | /** | 226 | /** |
| 206 | * mesh_send_path error - Sends a PERR mesh management frame | 227 | * mesh_send_path error - Sends a PERR mesh management frame |
| 207 | * | 228 | * |
| @@ -209,6 +230,10 @@ static int mesh_path_sel_frame_tx(enum mpath_frame_type action, u8 flags, | |||
| 209 | * @target_sn: SN of the broken destination | 230 | * @target_sn: SN of the broken destination |
| 210 | * @target_rcode: reason code for this PERR | 231 | * @target_rcode: reason code for this PERR |
| 211 | * @ra: node this frame is addressed to | 232 | * @ra: node this frame is addressed to |
| 233 | * | ||
| 234 | * Note: This function may be called with driver locks taken that the driver | ||
| 235 | * also acquires in the TX path. To avoid a deadlock we don't transmit the | ||
| 236 | * frame directly but add it to the pending queue instead. | ||
| 212 | */ | 237 | */ |
| 213 | int mesh_path_error_tx(u8 ttl, u8 *target, __le32 target_sn, | 238 | int mesh_path_error_tx(u8 ttl, u8 *target, __le32 target_sn, |
| 214 | __le16 target_rcode, const u8 *ra, | 239 | __le16 target_rcode, const u8 *ra, |
| @@ -222,7 +247,7 @@ int mesh_path_error_tx(u8 ttl, u8 *target, __le32 target_sn, | |||
| 222 | 247 | ||
| 223 | if (!skb) | 248 | if (!skb) |
| 224 | return -1; | 249 | return -1; |
| 225 | skb_reserve(skb, local->hw.extra_tx_headroom); | 250 | skb_reserve(skb, local->tx_headroom + local->hw.extra_tx_headroom); |
| 226 | /* 25 is the size of the common mgmt part (24) plus the size of the | 251 | /* 25 is the size of the common mgmt part (24) plus the size of the |
| 227 | * common action part (1) | 252 | * common action part (1) |
| 228 | */ | 253 | */ |
| @@ -263,7 +288,9 @@ int mesh_path_error_tx(u8 ttl, u8 *target, __le32 target_sn, | |||
| 263 | pos += 4; | 288 | pos += 4; |
| 264 | memcpy(pos, &target_rcode, 2); | 289 | memcpy(pos, &target_rcode, 2); |
| 265 | 290 | ||
| 266 | ieee80211_tx_skb(sdata, skb); | 291 | /* see note in function header */ |
| 292 | prepare_frame_for_deferred_tx(sdata, skb); | ||
| 293 | ieee80211_add_pending_skb(local, skb); | ||
| 267 | return 0; | 294 | return 0; |
| 268 | } | 295 | } |
| 269 | 296 | ||
diff --git a/net/mac80211/mesh_pathtbl.c b/net/mac80211/mesh_pathtbl.c index f97d17cb073c..7f54c5042235 100644 --- a/net/mac80211/mesh_pathtbl.c +++ b/net/mac80211/mesh_pathtbl.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <linux/spinlock.h> | 14 | #include <linux/spinlock.h> |
| 15 | #include <linux/string.h> | 15 | #include <linux/string.h> |
| 16 | #include <net/mac80211.h> | 16 | #include <net/mac80211.h> |
| 17 | #include "wme.h" | ||
| 17 | #include "ieee80211_i.h" | 18 | #include "ieee80211_i.h" |
| 18 | #include "mesh.h" | 19 | #include "mesh.h" |
| 19 | 20 | ||
| @@ -48,8 +49,10 @@ static struct mesh_table __rcu *mpp_paths; /* Store paths for MPP&MAP */ | |||
| 48 | int mesh_paths_generation; | 49 | int mesh_paths_generation; |
| 49 | 50 | ||
| 50 | /* This lock will have the grow table function as writer and add / delete nodes | 51 | /* This lock will have the grow table function as writer and add / delete nodes |
| 51 | * as readers. When reading the table (i.e. doing lookups) we are well protected | 52 | * as readers. RCU provides sufficient protection only when reading the table |
| 52 | * by RCU | 53 | * (i.e. doing lookups). Adding or adding or removing nodes requires we take |
| 54 | * the read lock or we risk operating on an old table. The write lock is only | ||
| 55 | * needed when modifying the number of buckets a table. | ||
| 53 | */ | 56 | */ |
| 54 | static DEFINE_RWLOCK(pathtbl_resize_lock); | 57 | static DEFINE_RWLOCK(pathtbl_resize_lock); |
| 55 | 58 | ||
| @@ -210,6 +213,7 @@ void mesh_path_assign_nexthop(struct mesh_path *mpath, struct sta_info *sta) | |||
| 210 | struct ieee80211_hdr *hdr; | 213 | struct ieee80211_hdr *hdr; |
| 211 | struct sk_buff_head tmpq; | 214 | struct sk_buff_head tmpq; |
| 212 | unsigned long flags; | 215 | unsigned long flags; |
| 216 | struct ieee80211_sub_if_data *sdata = mpath->sdata; | ||
| 213 | 217 | ||
| 214 | rcu_assign_pointer(mpath->next_hop, sta); | 218 | rcu_assign_pointer(mpath->next_hop, sta); |
| 215 | 219 | ||
| @@ -220,6 +224,8 @@ void mesh_path_assign_nexthop(struct mesh_path *mpath, struct sta_info *sta) | |||
| 220 | while ((skb = __skb_dequeue(&mpath->frame_queue)) != NULL) { | 224 | while ((skb = __skb_dequeue(&mpath->frame_queue)) != NULL) { |
| 221 | hdr = (struct ieee80211_hdr *) skb->data; | 225 | hdr = (struct ieee80211_hdr *) skb->data; |
| 222 | memcpy(hdr->addr1, sta->sta.addr, ETH_ALEN); | 226 | memcpy(hdr->addr1, sta->sta.addr, ETH_ALEN); |
| 227 | skb_set_queue_mapping(skb, ieee80211_select_queue(sdata, skb)); | ||
| 228 | ieee80211_set_qos_hdr(sdata, skb); | ||
| 223 | __skb_queue_tail(&tmpq, skb); | 229 | __skb_queue_tail(&tmpq, skb); |
| 224 | } | 230 | } |
| 225 | 231 | ||
| @@ -333,25 +339,14 @@ static void mesh_path_move_to_queue(struct mesh_path *gate_mpath, | |||
| 333 | } | 339 | } |
| 334 | 340 | ||
| 335 | 341 | ||
| 336 | /** | 342 | static struct mesh_path *path_lookup(struct mesh_table *tbl, u8 *dst, |
| 337 | * mesh_path_lookup - look up a path in the mesh path table | 343 | struct ieee80211_sub_if_data *sdata) |
| 338 | * @dst: hardware address (ETH_ALEN length) of destination | ||
| 339 | * @sdata: local subif | ||
| 340 | * | ||
| 341 | * Returns: pointer to the mesh path structure, or NULL if not found | ||
| 342 | * | ||
| 343 | * Locking: must be called within a read rcu section. | ||
| 344 | */ | ||
| 345 | struct mesh_path *mesh_path_lookup(u8 *dst, struct ieee80211_sub_if_data *sdata) | ||
| 346 | { | 344 | { |
| 347 | struct mesh_path *mpath; | 345 | struct mesh_path *mpath; |
| 348 | struct hlist_node *n; | 346 | struct hlist_node *n; |
| 349 | struct hlist_head *bucket; | 347 | struct hlist_head *bucket; |
| 350 | struct mesh_table *tbl; | ||
| 351 | struct mpath_node *node; | 348 | struct mpath_node *node; |
| 352 | 349 | ||
| 353 | tbl = rcu_dereference(mesh_paths); | ||
| 354 | |||
| 355 | bucket = &tbl->hash_buckets[mesh_table_hash(dst, sdata, tbl)]; | 350 | bucket = &tbl->hash_buckets[mesh_table_hash(dst, sdata, tbl)]; |
| 356 | hlist_for_each_entry_rcu(node, n, bucket, list) { | 351 | hlist_for_each_entry_rcu(node, n, bucket, list) { |
| 357 | mpath = node->mpath; | 352 | mpath = node->mpath; |
| @@ -359,8 +354,7 @@ struct mesh_path *mesh_path_lookup(u8 *dst, struct ieee80211_sub_if_data *sdata) | |||
| 359 | memcmp(dst, mpath->dst, ETH_ALEN) == 0) { | 354 | memcmp(dst, mpath->dst, ETH_ALEN) == 0) { |
| 360 | if (MPATH_EXPIRED(mpath)) { | 355 | if (MPATH_EXPIRED(mpath)) { |
| 361 | spin_lock_bh(&mpath->state_lock); | 356 | spin_lock_bh(&mpath->state_lock); |
| 362 | if (MPATH_EXPIRED(mpath)) | 357 | mpath->flags &= ~MESH_PATH_ACTIVE; |
| 363 | mpath->flags &= ~MESH_PATH_ACTIVE; | ||
| 364 | spin_unlock_bh(&mpath->state_lock); | 358 | spin_unlock_bh(&mpath->state_lock); |
| 365 | } | 359 | } |
| 366 | return mpath; | 360 | return mpath; |
| @@ -369,31 +363,23 @@ struct mesh_path *mesh_path_lookup(u8 *dst, struct ieee80211_sub_if_data *sdata) | |||
| 369 | return NULL; | 363 | return NULL; |
| 370 | } | 364 | } |
| 371 | 365 | ||
| 372 | struct mesh_path *mpp_path_lookup(u8 *dst, struct ieee80211_sub_if_data *sdata) | 366 | /** |
| 367 | * mesh_path_lookup - look up a path in the mesh path table | ||
| 368 | * @dst: hardware address (ETH_ALEN length) of destination | ||
| 369 | * @sdata: local subif | ||
| 370 | * | ||
| 371 | * Returns: pointer to the mesh path structure, or NULL if not found | ||
| 372 | * | ||
| 373 | * Locking: must be called within a read rcu section. | ||
| 374 | */ | ||
| 375 | struct mesh_path *mesh_path_lookup(u8 *dst, struct ieee80211_sub_if_data *sdata) | ||
| 373 | { | 376 | { |
| 374 | struct mesh_path *mpath; | 377 | return path_lookup(rcu_dereference(mesh_paths), dst, sdata); |
| 375 | struct hlist_node *n; | 378 | } |
| 376 | struct hlist_head *bucket; | ||
| 377 | struct mesh_table *tbl; | ||
| 378 | struct mpath_node *node; | ||
| 379 | |||
| 380 | tbl = rcu_dereference(mpp_paths); | ||
| 381 | 379 | ||
| 382 | bucket = &tbl->hash_buckets[mesh_table_hash(dst, sdata, tbl)]; | 380 | struct mesh_path *mpp_path_lookup(u8 *dst, struct ieee80211_sub_if_data *sdata) |
| 383 | hlist_for_each_entry_rcu(node, n, bucket, list) { | 381 | { |
| 384 | mpath = node->mpath; | 382 | return path_lookup(rcu_dereference(mpp_paths), dst, sdata); |
| 385 | if (mpath->sdata == sdata && | ||
| 386 | memcmp(dst, mpath->dst, ETH_ALEN) == 0) { | ||
| 387 | if (MPATH_EXPIRED(mpath)) { | ||
| 388 | spin_lock_bh(&mpath->state_lock); | ||
| 389 | if (MPATH_EXPIRED(mpath)) | ||
| 390 | mpath->flags &= ~MESH_PATH_ACTIVE; | ||
| 391 | spin_unlock_bh(&mpath->state_lock); | ||
| 392 | } | ||
| 393 | return mpath; | ||
| 394 | } | ||
| 395 | } | ||
| 396 | return NULL; | ||
| 397 | } | 383 | } |
| 398 | 384 | ||
| 399 | 385 | ||
| @@ -420,8 +406,7 @@ struct mesh_path *mesh_path_lookup_by_idx(int idx, struct ieee80211_sub_if_data | |||
| 420 | if (j++ == idx) { | 406 | if (j++ == idx) { |
| 421 | if (MPATH_EXPIRED(node->mpath)) { | 407 | if (MPATH_EXPIRED(node->mpath)) { |
| 422 | spin_lock_bh(&node->mpath->state_lock); | 408 | spin_lock_bh(&node->mpath->state_lock); |
| 423 | if (MPATH_EXPIRED(node->mpath)) | 409 | node->mpath->flags &= ~MESH_PATH_ACTIVE; |
| 424 | node->mpath->flags &= ~MESH_PATH_ACTIVE; | ||
| 425 | spin_unlock_bh(&node->mpath->state_lock); | 410 | spin_unlock_bh(&node->mpath->state_lock); |
| 426 | } | 411 | } |
| 427 | return node->mpath; | 412 | return node->mpath; |
| @@ -776,22 +761,47 @@ void mesh_plink_broken(struct sta_info *sta) | |||
| 776 | tbl = rcu_dereference(mesh_paths); | 761 | tbl = rcu_dereference(mesh_paths); |
| 777 | for_each_mesh_entry(tbl, p, node, i) { | 762 | for_each_mesh_entry(tbl, p, node, i) { |
| 778 | mpath = node->mpath; | 763 | mpath = node->mpath; |
| 779 | spin_lock_bh(&mpath->state_lock); | ||
| 780 | if (rcu_dereference(mpath->next_hop) == sta && | 764 | if (rcu_dereference(mpath->next_hop) == sta && |
| 781 | mpath->flags & MESH_PATH_ACTIVE && | 765 | mpath->flags & MESH_PATH_ACTIVE && |
| 782 | !(mpath->flags & MESH_PATH_FIXED)) { | 766 | !(mpath->flags & MESH_PATH_FIXED)) { |
| 767 | spin_lock_bh(&mpath->state_lock); | ||
| 783 | mpath->flags &= ~MESH_PATH_ACTIVE; | 768 | mpath->flags &= ~MESH_PATH_ACTIVE; |
| 784 | ++mpath->sn; | 769 | ++mpath->sn; |
| 785 | spin_unlock_bh(&mpath->state_lock); | 770 | spin_unlock_bh(&mpath->state_lock); |
| 786 | mesh_path_error_tx(sdata->u.mesh.mshcfg.element_ttl, | 771 | mesh_path_error_tx(sdata->u.mesh.mshcfg.element_ttl, |
| 787 | mpath->dst, cpu_to_le32(mpath->sn), | 772 | mpath->dst, cpu_to_le32(mpath->sn), |
| 788 | reason, bcast, sdata); | 773 | reason, bcast, sdata); |
| 789 | } else | 774 | } |
| 790 | spin_unlock_bh(&mpath->state_lock); | ||
| 791 | } | 775 | } |
| 792 | rcu_read_unlock(); | 776 | rcu_read_unlock(); |
| 793 | } | 777 | } |
| 794 | 778 | ||
| 779 | static void mesh_path_node_reclaim(struct rcu_head *rp) | ||
| 780 | { | ||
| 781 | struct mpath_node *node = container_of(rp, struct mpath_node, rcu); | ||
| 782 | struct ieee80211_sub_if_data *sdata = node->mpath->sdata; | ||
| 783 | |||
| 784 | del_timer_sync(&node->mpath->timer); | ||
| 785 | atomic_dec(&sdata->u.mesh.mpaths); | ||
| 786 | kfree(node->mpath); | ||
| 787 | kfree(node); | ||
| 788 | } | ||
| 789 | |||
| 790 | /* needs to be called with the corresponding hashwlock taken */ | ||
| 791 | static void __mesh_path_del(struct mesh_table *tbl, struct mpath_node *node) | ||
| 792 | { | ||
| 793 | struct mesh_path *mpath; | ||
| 794 | mpath = node->mpath; | ||
| 795 | spin_lock(&mpath->state_lock); | ||
| 796 | mpath->flags |= MESH_PATH_RESOLVING; | ||
| 797 | if (mpath->is_gate) | ||
| 798 | mesh_gate_del(tbl, mpath); | ||
| 799 | hlist_del_rcu(&node->list); | ||
| 800 | call_rcu(&node->rcu, mesh_path_node_reclaim); | ||
| 801 | spin_unlock(&mpath->state_lock); | ||
| 802 | atomic_dec(&tbl->entries); | ||
| 803 | } | ||
| 804 | |||
| 795 | /** | 805 | /** |
| 796 | * mesh_path_flush_by_nexthop - Deletes mesh paths if their next hop matches | 806 | * mesh_path_flush_by_nexthop - Deletes mesh paths if their next hop matches |
| 797 | * | 807 | * |
| @@ -812,42 +822,59 @@ void mesh_path_flush_by_nexthop(struct sta_info *sta) | |||
| 812 | int i; | 822 | int i; |
| 813 | 823 | ||
| 814 | rcu_read_lock(); | 824 | rcu_read_lock(); |
| 815 | tbl = rcu_dereference(mesh_paths); | 825 | read_lock_bh(&pathtbl_resize_lock); |
| 826 | tbl = resize_dereference_mesh_paths(); | ||
| 816 | for_each_mesh_entry(tbl, p, node, i) { | 827 | for_each_mesh_entry(tbl, p, node, i) { |
| 817 | mpath = node->mpath; | 828 | mpath = node->mpath; |
| 818 | if (rcu_dereference(mpath->next_hop) == sta) | 829 | if (rcu_dereference(mpath->next_hop) == sta) { |
| 819 | mesh_path_del(mpath->dst, mpath->sdata); | 830 | spin_lock_bh(&tbl->hashwlock[i]); |
| 831 | __mesh_path_del(tbl, node); | ||
| 832 | spin_unlock_bh(&tbl->hashwlock[i]); | ||
| 833 | } | ||
| 820 | } | 834 | } |
| 835 | read_unlock_bh(&pathtbl_resize_lock); | ||
| 821 | rcu_read_unlock(); | 836 | rcu_read_unlock(); |
| 822 | } | 837 | } |
| 823 | 838 | ||
| 824 | void mesh_path_flush(struct ieee80211_sub_if_data *sdata) | 839 | static void table_flush_by_iface(struct mesh_table *tbl, |
| 840 | struct ieee80211_sub_if_data *sdata) | ||
| 825 | { | 841 | { |
| 826 | struct mesh_table *tbl; | ||
| 827 | struct mesh_path *mpath; | 842 | struct mesh_path *mpath; |
| 828 | struct mpath_node *node; | 843 | struct mpath_node *node; |
| 829 | struct hlist_node *p; | 844 | struct hlist_node *p; |
| 830 | int i; | 845 | int i; |
| 831 | 846 | ||
| 832 | rcu_read_lock(); | 847 | WARN_ON(!rcu_read_lock_held()); |
| 833 | tbl = rcu_dereference(mesh_paths); | ||
| 834 | for_each_mesh_entry(tbl, p, node, i) { | 848 | for_each_mesh_entry(tbl, p, node, i) { |
| 835 | mpath = node->mpath; | 849 | mpath = node->mpath; |
| 836 | if (mpath->sdata == sdata) | 850 | if (mpath->sdata != sdata) |
| 837 | mesh_path_del(mpath->dst, mpath->sdata); | 851 | continue; |
| 852 | spin_lock_bh(&tbl->hashwlock[i]); | ||
| 853 | __mesh_path_del(tbl, node); | ||
| 854 | spin_unlock_bh(&tbl->hashwlock[i]); | ||
| 838 | } | 855 | } |
| 839 | rcu_read_unlock(); | ||
| 840 | } | 856 | } |
| 841 | 857 | ||
| 842 | static void mesh_path_node_reclaim(struct rcu_head *rp) | 858 | /** |
| 859 | * mesh_path_flush_by_iface - Deletes all mesh paths associated with a given iface | ||
| 860 | * | ||
| 861 | * This function deletes both mesh paths as well as mesh portal paths. | ||
| 862 | * | ||
| 863 | * @sdata - interface data to match | ||
| 864 | * | ||
| 865 | */ | ||
| 866 | void mesh_path_flush_by_iface(struct ieee80211_sub_if_data *sdata) | ||
| 843 | { | 867 | { |
| 844 | struct mpath_node *node = container_of(rp, struct mpath_node, rcu); | 868 | struct mesh_table *tbl; |
| 845 | struct ieee80211_sub_if_data *sdata = node->mpath->sdata; | ||
| 846 | 869 | ||
| 847 | del_timer_sync(&node->mpath->timer); | 870 | rcu_read_lock(); |
| 848 | atomic_dec(&sdata->u.mesh.mpaths); | 871 | read_lock_bh(&pathtbl_resize_lock); |
| 849 | kfree(node->mpath); | 872 | tbl = resize_dereference_mesh_paths(); |
| 850 | kfree(node); | 873 | table_flush_by_iface(tbl, sdata); |
| 874 | tbl = resize_dereference_mpp_paths(); | ||
| 875 | table_flush_by_iface(tbl, sdata); | ||
| 876 | read_unlock_bh(&pathtbl_resize_lock); | ||
| 877 | rcu_read_unlock(); | ||
| 851 | } | 878 | } |
| 852 | 879 | ||
| 853 | /** | 880 | /** |
| @@ -878,14 +905,7 @@ int mesh_path_del(u8 *addr, struct ieee80211_sub_if_data *sdata) | |||
| 878 | mpath = node->mpath; | 905 | mpath = node->mpath; |
| 879 | if (mpath->sdata == sdata && | 906 | if (mpath->sdata == sdata && |
| 880 | memcmp(addr, mpath->dst, ETH_ALEN) == 0) { | 907 | memcmp(addr, mpath->dst, ETH_ALEN) == 0) { |
| 881 | spin_lock_bh(&mpath->state_lock); | 908 | __mesh_path_del(tbl, node); |
| 882 | if (mpath->is_gate) | ||
| 883 | mesh_gate_del(tbl, mpath); | ||
| 884 | mpath->flags |= MESH_PATH_RESOLVING; | ||
| 885 | hlist_del_rcu(&node->list); | ||
| 886 | call_rcu(&node->rcu, mesh_path_node_reclaim); | ||
| 887 | atomic_dec(&tbl->entries); | ||
| 888 | spin_unlock_bh(&mpath->state_lock); | ||
| 889 | goto enddel; | 909 | goto enddel; |
| 890 | } | 910 | } |
| 891 | } | 911 | } |
| @@ -991,9 +1011,14 @@ void mesh_path_discard_frame(struct sk_buff *skb, | |||
| 991 | 1011 | ||
| 992 | da = hdr->addr3; | 1012 | da = hdr->addr3; |
| 993 | ra = hdr->addr1; | 1013 | ra = hdr->addr1; |
| 1014 | rcu_read_lock(); | ||
| 994 | mpath = mesh_path_lookup(da, sdata); | 1015 | mpath = mesh_path_lookup(da, sdata); |
| 995 | if (mpath) | 1016 | if (mpath) { |
| 1017 | spin_lock_bh(&mpath->state_lock); | ||
| 996 | sn = ++mpath->sn; | 1018 | sn = ++mpath->sn; |
| 1019 | spin_unlock_bh(&mpath->state_lock); | ||
| 1020 | } | ||
| 1021 | rcu_read_unlock(); | ||
| 997 | mesh_path_error_tx(sdata->u.mesh.mshcfg.element_ttl, skb->data, | 1022 | mesh_path_error_tx(sdata->u.mesh.mshcfg.element_ttl, skb->data, |
| 998 | cpu_to_le32(sn), reason, ra, sdata); | 1023 | cpu_to_le32(sn), reason, ra, sdata); |
| 999 | } | 1024 | } |
| @@ -1074,6 +1099,7 @@ static int mesh_path_node_copy(struct hlist_node *p, struct mesh_table *newtbl) | |||
| 1074 | int mesh_pathtbl_init(void) | 1099 | int mesh_pathtbl_init(void) |
| 1075 | { | 1100 | { |
| 1076 | struct mesh_table *tbl_path, *tbl_mpp; | 1101 | struct mesh_table *tbl_path, *tbl_mpp; |
| 1102 | int ret; | ||
| 1077 | 1103 | ||
| 1078 | tbl_path = mesh_table_alloc(INIT_PATHS_SIZE_ORDER); | 1104 | tbl_path = mesh_table_alloc(INIT_PATHS_SIZE_ORDER); |
| 1079 | if (!tbl_path) | 1105 | if (!tbl_path) |
| @@ -1082,18 +1108,26 @@ int mesh_pathtbl_init(void) | |||
| 1082 | tbl_path->copy_node = &mesh_path_node_copy; | 1108 | tbl_path->copy_node = &mesh_path_node_copy; |
| 1083 | tbl_path->mean_chain_len = MEAN_CHAIN_LEN; | 1109 | tbl_path->mean_chain_len = MEAN_CHAIN_LEN; |
| 1084 | tbl_path->known_gates = kzalloc(sizeof(struct hlist_head), GFP_ATOMIC); | 1110 | tbl_path->known_gates = kzalloc(sizeof(struct hlist_head), GFP_ATOMIC); |
| 1111 | if (!tbl_path->known_gates) { | ||
| 1112 | ret = -ENOMEM; | ||
| 1113 | goto free_path; | ||
| 1114 | } | ||
| 1085 | INIT_HLIST_HEAD(tbl_path->known_gates); | 1115 | INIT_HLIST_HEAD(tbl_path->known_gates); |
| 1086 | 1116 | ||
| 1087 | 1117 | ||
| 1088 | tbl_mpp = mesh_table_alloc(INIT_PATHS_SIZE_ORDER); | 1118 | tbl_mpp = mesh_table_alloc(INIT_PATHS_SIZE_ORDER); |
| 1089 | if (!tbl_mpp) { | 1119 | if (!tbl_mpp) { |
| 1090 | mesh_table_free(tbl_path, true); | 1120 | ret = -ENOMEM; |
| 1091 | return -ENOMEM; | 1121 | goto free_path; |
| 1092 | } | 1122 | } |
| 1093 | tbl_mpp->free_node = &mesh_path_node_free; | 1123 | tbl_mpp->free_node = &mesh_path_node_free; |
| 1094 | tbl_mpp->copy_node = &mesh_path_node_copy; | 1124 | tbl_mpp->copy_node = &mesh_path_node_copy; |
| 1095 | tbl_mpp->mean_chain_len = MEAN_CHAIN_LEN; | 1125 | tbl_mpp->mean_chain_len = MEAN_CHAIN_LEN; |
| 1096 | tbl_mpp->known_gates = kzalloc(sizeof(struct hlist_head), GFP_ATOMIC); | 1126 | tbl_mpp->known_gates = kzalloc(sizeof(struct hlist_head), GFP_ATOMIC); |
| 1127 | if (!tbl_mpp->known_gates) { | ||
| 1128 | ret = -ENOMEM; | ||
| 1129 | goto free_mpp; | ||
| 1130 | } | ||
| 1097 | INIT_HLIST_HEAD(tbl_mpp->known_gates); | 1131 | INIT_HLIST_HEAD(tbl_mpp->known_gates); |
| 1098 | 1132 | ||
| 1099 | /* Need no locking since this is during init */ | 1133 | /* Need no locking since this is during init */ |
| @@ -1101,6 +1135,12 @@ int mesh_pathtbl_init(void) | |||
| 1101 | RCU_INIT_POINTER(mpp_paths, tbl_mpp); | 1135 | RCU_INIT_POINTER(mpp_paths, tbl_mpp); |
| 1102 | 1136 | ||
| 1103 | return 0; | 1137 | return 0; |
| 1138 | |||
| 1139 | free_mpp: | ||
| 1140 | mesh_table_free(tbl_mpp, true); | ||
| 1141 | free_path: | ||
| 1142 | mesh_table_free(tbl_path, true); | ||
| 1143 | return ret; | ||
| 1104 | } | 1144 | } |
| 1105 | 1145 | ||
| 1106 | void mesh_path_expire(struct ieee80211_sub_if_data *sdata) | 1146 | void mesh_path_expire(struct ieee80211_sub_if_data *sdata) |
| @@ -1117,14 +1157,10 @@ void mesh_path_expire(struct ieee80211_sub_if_data *sdata) | |||
| 1117 | if (node->mpath->sdata != sdata) | 1157 | if (node->mpath->sdata != sdata) |
| 1118 | continue; | 1158 | continue; |
| 1119 | mpath = node->mpath; | 1159 | mpath = node->mpath; |
| 1120 | spin_lock_bh(&mpath->state_lock); | ||
| 1121 | if ((!(mpath->flags & MESH_PATH_RESOLVING)) && | 1160 | if ((!(mpath->flags & MESH_PATH_RESOLVING)) && |
| 1122 | (!(mpath->flags & MESH_PATH_FIXED)) && | 1161 | (!(mpath->flags & MESH_PATH_FIXED)) && |
| 1123 | time_after(jiffies, mpath->exp_time + MESH_PATH_EXPIRE)) { | 1162 | time_after(jiffies, mpath->exp_time + MESH_PATH_EXPIRE)) |
| 1124 | spin_unlock_bh(&mpath->state_lock); | ||
| 1125 | mesh_path_del(mpath->dst, mpath->sdata); | 1163 | mesh_path_del(mpath->dst, mpath->sdata); |
| 1126 | } else | ||
| 1127 | spin_unlock_bh(&mpath->state_lock); | ||
| 1128 | } | 1164 | } |
| 1129 | rcu_read_unlock(); | 1165 | rcu_read_unlock(); |
| 1130 | } | 1166 | } |
diff --git a/net/mac80211/mesh_plink.c b/net/mac80211/mesh_plink.c index 1a00d0f701c3..4396906175ae 100644 --- a/net/mac80211/mesh_plink.c +++ b/net/mac80211/mesh_plink.c | |||
| @@ -88,7 +88,7 @@ static struct sta_info *mesh_plink_alloc(struct ieee80211_sub_if_data *sdata, | |||
| 88 | if (!sta) | 88 | if (!sta) |
| 89 | return NULL; | 89 | return NULL; |
| 90 | 90 | ||
| 91 | sta->flags = WLAN_STA_AUTHORIZED | WLAN_STA_AUTH; | 91 | sta->flags = WLAN_STA_AUTHORIZED | WLAN_STA_AUTH | WLAN_STA_WME; |
| 92 | sta->sta.supp_rates[local->hw.conf.channel->band] = rates; | 92 | sta->sta.supp_rates[local->hw.conf.channel->band] = rates; |
| 93 | rate_control_rate_init(sta); | 93 | rate_control_rate_init(sta); |
| 94 | 94 | ||
diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c index 60a6f273cd30..2f92ae2f9706 100644 --- a/net/mac80211/mlme.c +++ b/net/mac80211/mlme.c | |||
| @@ -271,11 +271,9 @@ static void ieee80211_send_deauth_disassoc(struct ieee80211_sub_if_data *sdata, | |||
| 271 | struct ieee80211_mgmt *mgmt; | 271 | struct ieee80211_mgmt *mgmt; |
| 272 | 272 | ||
| 273 | skb = dev_alloc_skb(local->hw.extra_tx_headroom + sizeof(*mgmt)); | 273 | skb = dev_alloc_skb(local->hw.extra_tx_headroom + sizeof(*mgmt)); |
| 274 | if (!skb) { | 274 | if (!skb) |
| 275 | printk(KERN_DEBUG "%s: failed to allocate buffer for " | ||
| 276 | "deauth/disassoc frame\n", sdata->name); | ||
| 277 | return; | 275 | return; |
| 278 | } | 276 | |
| 279 | skb_reserve(skb, local->hw.extra_tx_headroom); | 277 | skb_reserve(skb, local->hw.extra_tx_headroom); |
| 280 | 278 | ||
| 281 | mgmt = (struct ieee80211_mgmt *) skb_put(skb, 24); | 279 | mgmt = (struct ieee80211_mgmt *) skb_put(skb, 24); |
| @@ -354,11 +352,9 @@ static void ieee80211_send_4addr_nullfunc(struct ieee80211_local *local, | |||
| 354 | return; | 352 | return; |
| 355 | 353 | ||
| 356 | skb = dev_alloc_skb(local->hw.extra_tx_headroom + 30); | 354 | skb = dev_alloc_skb(local->hw.extra_tx_headroom + 30); |
| 357 | if (!skb) { | 355 | if (!skb) |
| 358 | printk(KERN_DEBUG "%s: failed to allocate buffer for 4addr " | ||
| 359 | "nullfunc frame\n", sdata->name); | ||
| 360 | return; | 356 | return; |
| 361 | } | 357 | |
| 362 | skb_reserve(skb, local->hw.extra_tx_headroom); | 358 | skb_reserve(skb, local->hw.extra_tx_headroom); |
| 363 | 359 | ||
| 364 | nullfunc = (struct ieee80211_hdr *) skb_put(skb, 30); | 360 | nullfunc = (struct ieee80211_hdr *) skb_put(skb, 30); |
| @@ -394,6 +390,9 @@ static void ieee80211_chswitch_work(struct work_struct *work) | |||
| 394 | /* call "hw_config" only if doing sw channel switch */ | 390 | /* call "hw_config" only if doing sw channel switch */ |
| 395 | ieee80211_hw_config(sdata->local, | 391 | ieee80211_hw_config(sdata->local, |
| 396 | IEEE80211_CONF_CHANGE_CHANNEL); | 392 | IEEE80211_CONF_CHANGE_CHANNEL); |
| 393 | } else { | ||
| 394 | /* update the device channel directly */ | ||
| 395 | sdata->local->hw.conf.channel = sdata->local->oper_channel; | ||
| 397 | } | 396 | } |
| 398 | 397 | ||
| 399 | /* XXX: shouldn't really modify cfg80211-owned data! */ | 398 | /* XXX: shouldn't really modify cfg80211-owned data! */ |
| @@ -1922,8 +1921,24 @@ static void ieee80211_rx_mgmt_beacon(struct ieee80211_sub_if_data *sdata, | |||
| 1922 | 1921 | ||
| 1923 | rcu_read_unlock(); | 1922 | rcu_read_unlock(); |
| 1924 | 1923 | ||
| 1924 | /* | ||
| 1925 | * Whenever the AP announces the HT mode change that can be | ||
| 1926 | * 40MHz intolerant or etc., it would be safer to stop tx | ||
| 1927 | * queues before doing hw config to avoid buffer overflow. | ||
| 1928 | */ | ||
| 1929 | ieee80211_stop_queues_by_reason(&sdata->local->hw, | ||
| 1930 | IEEE80211_QUEUE_STOP_REASON_CHTYPE_CHANGE); | ||
| 1931 | |||
| 1932 | /* flush out all packets */ | ||
| 1933 | synchronize_net(); | ||
| 1934 | |||
| 1935 | drv_flush(local, false); | ||
| 1936 | |||
| 1925 | changed |= ieee80211_enable_ht(sdata, elems.ht_info_elem, | 1937 | changed |= ieee80211_enable_ht(sdata, elems.ht_info_elem, |
| 1926 | bssid, ap_ht_cap_flags); | 1938 | bssid, ap_ht_cap_flags); |
| 1939 | |||
| 1940 | ieee80211_wake_queues_by_reason(&sdata->local->hw, | ||
| 1941 | IEEE80211_QUEUE_STOP_REASON_CHTYPE_CHANGE); | ||
| 1927 | } | 1942 | } |
| 1928 | 1943 | ||
| 1929 | /* Note: country IE parsing is done for us by cfg80211 */ | 1944 | /* Note: country IE parsing is done for us by cfg80211 */ |
| @@ -2441,11 +2456,8 @@ static int ieee80211_pre_assoc(struct ieee80211_sub_if_data *sdata, | |||
| 2441 | int err; | 2456 | int err; |
| 2442 | 2457 | ||
| 2443 | sta = sta_info_alloc(sdata, bssid, GFP_KERNEL); | 2458 | sta = sta_info_alloc(sdata, bssid, GFP_KERNEL); |
| 2444 | if (!sta) { | 2459 | if (!sta) |
| 2445 | printk(KERN_DEBUG "%s: failed to alloc STA entry for" | ||
| 2446 | " the AP\n", sdata->name); | ||
| 2447 | return -ENOMEM; | 2460 | return -ENOMEM; |
| 2448 | } | ||
| 2449 | 2461 | ||
| 2450 | sta->dummy = true; | 2462 | sta->dummy = true; |
| 2451 | 2463 | ||
diff --git a/net/mac80211/rc80211_minstrel_ht.c b/net/mac80211/rc80211_minstrel_ht.c index 21588386a302..e19249b0f971 100644 --- a/net/mac80211/rc80211_minstrel_ht.c +++ b/net/mac80211/rc80211_minstrel_ht.c | |||
| @@ -452,7 +452,8 @@ minstrel_ht_tx_status(void *priv, struct ieee80211_supported_band *sband, | |||
| 452 | 452 | ||
| 453 | if (time_after(jiffies, mi->stats_update + (mp->update_interval / 2 * HZ) / 1000)) { | 453 | if (time_after(jiffies, mi->stats_update + (mp->update_interval / 2 * HZ) / 1000)) { |
| 454 | minstrel_ht_update_stats(mp, mi); | 454 | minstrel_ht_update_stats(mp, mi); |
| 455 | minstrel_aggr_check(mp, sta, skb); | 455 | if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) |
| 456 | minstrel_aggr_check(mp, sta, skb); | ||
| 456 | } | 457 | } |
| 457 | } | 458 | } |
| 458 | 459 | ||
diff --git a/net/mac80211/rx.c b/net/mac80211/rx.c index f45fd2fedc24..db46601e50bf 100644 --- a/net/mac80211/rx.c +++ b/net/mac80211/rx.c | |||
| @@ -476,7 +476,6 @@ static ieee80211_rx_result | |||
| 476 | ieee80211_rx_mesh_check(struct ieee80211_rx_data *rx) | 476 | ieee80211_rx_mesh_check(struct ieee80211_rx_data *rx) |
| 477 | { | 477 | { |
| 478 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)rx->skb->data; | 478 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)rx->skb->data; |
| 479 | unsigned int hdrlen = ieee80211_hdrlen(hdr->frame_control); | ||
| 480 | char *dev_addr = rx->sdata->vif.addr; | 479 | char *dev_addr = rx->sdata->vif.addr; |
| 481 | 480 | ||
| 482 | if (ieee80211_is_data(hdr->frame_control)) { | 481 | if (ieee80211_is_data(hdr->frame_control)) { |
| @@ -524,14 +523,6 @@ ieee80211_rx_mesh_check(struct ieee80211_rx_data *rx) | |||
| 524 | 523 | ||
| 525 | } | 524 | } |
| 526 | 525 | ||
| 527 | #define msh_h_get(h, l) ((struct ieee80211s_hdr *) ((u8 *)h + l)) | ||
| 528 | |||
| 529 | if (ieee80211_is_data(hdr->frame_control) && | ||
| 530 | is_multicast_ether_addr(hdr->addr1) && | ||
| 531 | mesh_rmc_check(hdr->addr3, msh_h_get(hdr, hdrlen), rx->sdata)) | ||
| 532 | return RX_DROP_MONITOR; | ||
| 533 | #undef msh_h_get | ||
| 534 | |||
| 535 | return RX_CONTINUE; | 526 | return RX_CONTINUE; |
| 536 | } | 527 | } |
| 537 | 528 | ||
| @@ -1840,6 +1831,12 @@ ieee80211_rx_h_mesh_fwding(struct ieee80211_rx_data *rx) | |||
| 1840 | hdrlen = ieee80211_hdrlen(hdr->frame_control); | 1831 | hdrlen = ieee80211_hdrlen(hdr->frame_control); |
| 1841 | mesh_hdr = (struct ieee80211s_hdr *) (skb->data + hdrlen); | 1832 | mesh_hdr = (struct ieee80211s_hdr *) (skb->data + hdrlen); |
| 1842 | 1833 | ||
| 1834 | /* frame is in RMC, don't forward */ | ||
| 1835 | if (ieee80211_is_data(hdr->frame_control) && | ||
| 1836 | is_multicast_ether_addr(hdr->addr1) && | ||
| 1837 | mesh_rmc_check(hdr->addr3, mesh_hdr, rx->sdata)) | ||
| 1838 | return RX_DROP_MONITOR; | ||
| 1839 | |||
| 1843 | if (!ieee80211_is_data(hdr->frame_control)) | 1840 | if (!ieee80211_is_data(hdr->frame_control)) |
| 1844 | return RX_CONTINUE; | 1841 | return RX_CONTINUE; |
| 1845 | 1842 | ||
| @@ -1847,6 +1844,12 @@ ieee80211_rx_h_mesh_fwding(struct ieee80211_rx_data *rx) | |||
| 1847 | /* illegal frame */ | 1844 | /* illegal frame */ |
| 1848 | return RX_DROP_MONITOR; | 1845 | return RX_DROP_MONITOR; |
| 1849 | 1846 | ||
| 1847 | if (ieee80211_queue_stopped(&local->hw, skb_get_queue_mapping(skb))) { | ||
| 1848 | IEEE80211_IFSTA_MESH_CTR_INC(&sdata->u.mesh, | ||
| 1849 | dropped_frames_congestion); | ||
| 1850 | return RX_DROP_MONITOR; | ||
| 1851 | } | ||
| 1852 | |||
| 1850 | if (mesh_hdr->flags & MESH_FLAGS_AE) { | 1853 | if (mesh_hdr->flags & MESH_FLAGS_AE) { |
| 1851 | struct mesh_path *mppath; | 1854 | struct mesh_path *mppath; |
| 1852 | char *proxied_addr; | 1855 | char *proxied_addr; |
| @@ -1902,13 +1905,13 @@ ieee80211_rx_h_mesh_fwding(struct ieee80211_rx_data *rx) | |||
| 1902 | memset(info, 0, sizeof(*info)); | 1905 | memset(info, 0, sizeof(*info)); |
| 1903 | info->flags |= IEEE80211_TX_INTFL_NEED_TXPROCESSING; | 1906 | info->flags |= IEEE80211_TX_INTFL_NEED_TXPROCESSING; |
| 1904 | info->control.vif = &rx->sdata->vif; | 1907 | info->control.vif = &rx->sdata->vif; |
| 1905 | skb_set_queue_mapping(skb, | 1908 | if (is_multicast_ether_addr(fwd_hdr->addr1)) { |
| 1906 | ieee80211_select_queue(rx->sdata, fwd_skb)); | ||
| 1907 | ieee80211_set_qos_hdr(local, skb); | ||
| 1908 | if (is_multicast_ether_addr(fwd_hdr->addr1)) | ||
| 1909 | IEEE80211_IFSTA_MESH_CTR_INC(&sdata->u.mesh, | 1909 | IEEE80211_IFSTA_MESH_CTR_INC(&sdata->u.mesh, |
| 1910 | fwded_mcast); | 1910 | fwded_mcast); |
| 1911 | else { | 1911 | skb_set_queue_mapping(fwd_skb, |
| 1912 | ieee80211_select_queue(sdata, fwd_skb)); | ||
| 1913 | ieee80211_set_qos_hdr(sdata, fwd_skb); | ||
| 1914 | } else { | ||
| 1912 | int err; | 1915 | int err; |
| 1913 | /* | 1916 | /* |
| 1914 | * Save TA to addr1 to send TA a path error if a | 1917 | * Save TA to addr1 to send TA a path error if a |
| @@ -2569,12 +2572,12 @@ static void ieee80211_rx_handlers(struct ieee80211_rx_data *rx) | |||
| 2569 | CALL_RXH(ieee80211_rx_h_ps_poll) | 2572 | CALL_RXH(ieee80211_rx_h_ps_poll) |
| 2570 | CALL_RXH(ieee80211_rx_h_michael_mic_verify) | 2573 | CALL_RXH(ieee80211_rx_h_michael_mic_verify) |
| 2571 | /* must be after MMIC verify so header is counted in MPDU mic */ | 2574 | /* must be after MMIC verify so header is counted in MPDU mic */ |
| 2572 | CALL_RXH(ieee80211_rx_h_remove_qos_control) | ||
| 2573 | CALL_RXH(ieee80211_rx_h_amsdu) | ||
| 2574 | #ifdef CONFIG_MAC80211_MESH | 2575 | #ifdef CONFIG_MAC80211_MESH |
| 2575 | if (ieee80211_vif_is_mesh(&rx->sdata->vif)) | 2576 | if (ieee80211_vif_is_mesh(&rx->sdata->vif)) |
| 2576 | CALL_RXH(ieee80211_rx_h_mesh_fwding); | 2577 | CALL_RXH(ieee80211_rx_h_mesh_fwding); |
| 2577 | #endif | 2578 | #endif |
| 2579 | CALL_RXH(ieee80211_rx_h_remove_qos_control) | ||
| 2580 | CALL_RXH(ieee80211_rx_h_amsdu) | ||
| 2578 | CALL_RXH(ieee80211_rx_h_data) | 2581 | CALL_RXH(ieee80211_rx_h_data) |
| 2579 | CALL_RXH(ieee80211_rx_h_ctrl); | 2582 | CALL_RXH(ieee80211_rx_h_ctrl); |
| 2580 | CALL_RXH(ieee80211_rx_h_mgmt_check) | 2583 | CALL_RXH(ieee80211_rx_h_mgmt_check) |
diff --git a/net/mac80211/spectmgmt.c b/net/mac80211/spectmgmt.c index 7733f66ee2c4..578eea3fc04d 100644 --- a/net/mac80211/spectmgmt.c +++ b/net/mac80211/spectmgmt.c | |||
| @@ -32,12 +32,8 @@ static void ieee80211_send_refuse_measurement_request(struct ieee80211_sub_if_da | |||
| 32 | 32 | ||
| 33 | skb = dev_alloc_skb(sizeof(*msr_report) + local->hw.extra_tx_headroom + | 33 | skb = dev_alloc_skb(sizeof(*msr_report) + local->hw.extra_tx_headroom + |
| 34 | sizeof(struct ieee80211_msrment_ie)); | 34 | sizeof(struct ieee80211_msrment_ie)); |
| 35 | 35 | if (!skb) | |
| 36 | if (!skb) { | ||
| 37 | printk(KERN_ERR "%s: failed to allocate buffer for " | ||
| 38 | "measurement report frame\n", sdata->name); | ||
| 39 | return; | 36 | return; |
| 40 | } | ||
| 41 | 37 | ||
| 42 | skb_reserve(skb, local->hw.extra_tx_headroom); | 38 | skb_reserve(skb, local->hw.extra_tx_headroom); |
| 43 | msr_report = (struct ieee80211_mgmt *)skb_put(skb, 24); | 39 | msr_report = (struct ieee80211_mgmt *)skb_put(skb, 24); |
diff --git a/net/mac80211/sta_info.c b/net/mac80211/sta_info.c index 6bc17fb80ee9..695447e988cb 100644 --- a/net/mac80211/sta_info.c +++ b/net/mac80211/sta_info.c | |||
| @@ -691,14 +691,13 @@ void sta_info_clear_tim_bit(struct sta_info *sta) | |||
| 691 | spin_unlock_irqrestore(&sta->local->sta_lock, flags); | 691 | spin_unlock_irqrestore(&sta->local->sta_lock, flags); |
| 692 | } | 692 | } |
| 693 | 693 | ||
| 694 | static int sta_info_buffer_expired(struct sta_info *sta, | 694 | static bool sta_info_buffer_expired(struct sta_info *sta, struct sk_buff *skb) |
| 695 | struct sk_buff *skb) | ||
| 696 | { | 695 | { |
| 697 | struct ieee80211_tx_info *info; | 696 | struct ieee80211_tx_info *info; |
| 698 | int timeout; | 697 | int timeout; |
| 699 | 698 | ||
| 700 | if (!skb) | 699 | if (!skb) |
| 701 | return 0; | 700 | return false; |
| 702 | 701 | ||
| 703 | info = IEEE80211_SKB_CB(skb); | 702 | info = IEEE80211_SKB_CB(skb); |
| 704 | 703 | ||
| @@ -718,9 +717,6 @@ static bool sta_info_cleanup_expire_buffered(struct ieee80211_local *local, | |||
| 718 | unsigned long flags; | 717 | unsigned long flags; |
| 719 | struct sk_buff *skb; | 718 | struct sk_buff *skb; |
| 720 | 719 | ||
| 721 | if (skb_queue_empty(&sta->ps_tx_buf)) | ||
| 722 | return false; | ||
| 723 | |||
| 724 | for (;;) { | 720 | for (;;) { |
| 725 | spin_lock_irqsave(&sta->ps_tx_buf.lock, flags); | 721 | spin_lock_irqsave(&sta->ps_tx_buf.lock, flags); |
| 726 | skb = skb_peek(&sta->ps_tx_buf); | 722 | skb = skb_peek(&sta->ps_tx_buf); |
| @@ -745,7 +741,7 @@ static bool sta_info_cleanup_expire_buffered(struct ieee80211_local *local, | |||
| 745 | sta_info_clear_tim_bit(sta); | 741 | sta_info_clear_tim_bit(sta); |
| 746 | } | 742 | } |
| 747 | 743 | ||
| 748 | return true; | 744 | return !skb_queue_empty(&sta->ps_tx_buf); |
| 749 | } | 745 | } |
| 750 | 746 | ||
| 751 | static int __must_check __sta_info_destroy(struct sta_info *sta) | 747 | static int __must_check __sta_info_destroy(struct sta_info *sta) |
diff --git a/net/mac80211/sta_info.h b/net/mac80211/sta_info.h index e9eb565506da..56a3d38a2cd1 100644 --- a/net/mac80211/sta_info.h +++ b/net/mac80211/sta_info.h | |||
| @@ -86,6 +86,8 @@ enum ieee80211_sta_info_flags { | |||
| 86 | * @stop_initiator: initiator of a session stop | 86 | * @stop_initiator: initiator of a session stop |
| 87 | * @tx_stop: TX DelBA frame when stopping | 87 | * @tx_stop: TX DelBA frame when stopping |
| 88 | * @buf_size: reorder buffer size at receiver | 88 | * @buf_size: reorder buffer size at receiver |
| 89 | * @failed_bar_ssn: ssn of the last failed BAR tx attempt | ||
| 90 | * @bar_pending: BAR needs to be re-sent | ||
| 89 | * | 91 | * |
| 90 | * This structure's lifetime is managed by RCU, assignments to | 92 | * This structure's lifetime is managed by RCU, assignments to |
| 91 | * the array holding it must hold the aggregation mutex. | 93 | * the array holding it must hold the aggregation mutex. |
| @@ -106,6 +108,9 @@ struct tid_ampdu_tx { | |||
| 106 | u8 stop_initiator; | 108 | u8 stop_initiator; |
| 107 | bool tx_stop; | 109 | bool tx_stop; |
| 108 | u8 buf_size; | 110 | u8 buf_size; |
| 111 | |||
| 112 | u16 failed_bar_ssn; | ||
| 113 | bool bar_pending; | ||
| 109 | }; | 114 | }; |
| 110 | 115 | ||
| 111 | /** | 116 | /** |
diff --git a/net/mac80211/status.c b/net/mac80211/status.c index e51bd2a1a073..d50358c45ab0 100644 --- a/net/mac80211/status.c +++ b/net/mac80211/status.c | |||
| @@ -127,12 +127,32 @@ static void ieee80211_handle_filtered_frame(struct ieee80211_local *local, | |||
| 127 | dev_kfree_skb(skb); | 127 | dev_kfree_skb(skb); |
| 128 | } | 128 | } |
| 129 | 129 | ||
| 130 | static void ieee80211_check_pending_bar(struct sta_info *sta, u8 *addr, u8 tid) | ||
| 131 | { | ||
| 132 | struct tid_ampdu_tx *tid_tx; | ||
| 133 | |||
| 134 | tid_tx = rcu_dereference(sta->ampdu_mlme.tid_tx[tid]); | ||
| 135 | if (!tid_tx || !tid_tx->bar_pending) | ||
| 136 | return; | ||
| 137 | |||
| 138 | tid_tx->bar_pending = false; | ||
| 139 | ieee80211_send_bar(&sta->sdata->vif, addr, tid, tid_tx->failed_bar_ssn); | ||
| 140 | } | ||
| 141 | |||
| 130 | static void ieee80211_frame_acked(struct sta_info *sta, struct sk_buff *skb) | 142 | static void ieee80211_frame_acked(struct sta_info *sta, struct sk_buff *skb) |
| 131 | { | 143 | { |
| 132 | struct ieee80211_mgmt *mgmt = (void *) skb->data; | 144 | struct ieee80211_mgmt *mgmt = (void *) skb->data; |
| 133 | struct ieee80211_local *local = sta->local; | 145 | struct ieee80211_local *local = sta->local; |
| 134 | struct ieee80211_sub_if_data *sdata = sta->sdata; | 146 | struct ieee80211_sub_if_data *sdata = sta->sdata; |
| 135 | 147 | ||
| 148 | if (ieee80211_is_data_qos(mgmt->frame_control)) { | ||
| 149 | struct ieee80211_hdr *hdr = (void *) skb->data; | ||
| 150 | u8 *qc = ieee80211_get_qos_ctl(hdr); | ||
| 151 | u16 tid = qc[0] & 0xf; | ||
| 152 | |||
| 153 | ieee80211_check_pending_bar(sta, hdr->addr1, tid); | ||
| 154 | } | ||
| 155 | |||
| 136 | if (ieee80211_is_action(mgmt->frame_control) && | 156 | if (ieee80211_is_action(mgmt->frame_control) && |
| 137 | sdata->vif.type == NL80211_IFTYPE_STATION && | 157 | sdata->vif.type == NL80211_IFTYPE_STATION && |
| 138 | mgmt->u.action.category == WLAN_CATEGORY_HT && | 158 | mgmt->u.action.category == WLAN_CATEGORY_HT && |
| @@ -161,6 +181,18 @@ static void ieee80211_frame_acked(struct sta_info *sta, struct sk_buff *skb) | |||
| 161 | } | 181 | } |
| 162 | } | 182 | } |
| 163 | 183 | ||
| 184 | static void ieee80211_set_bar_pending(struct sta_info *sta, u8 tid, u16 ssn) | ||
| 185 | { | ||
| 186 | struct tid_ampdu_tx *tid_tx; | ||
| 187 | |||
| 188 | tid_tx = rcu_dereference(sta->ampdu_mlme.tid_tx[tid]); | ||
| 189 | if (!tid_tx) | ||
| 190 | return; | ||
| 191 | |||
| 192 | tid_tx->failed_bar_ssn = ssn; | ||
| 193 | tid_tx->bar_pending = true; | ||
| 194 | } | ||
| 195 | |||
| 164 | /* | 196 | /* |
| 165 | * Use a static threshold for now, best value to be determined | 197 | * Use a static threshold for now, best value to be determined |
| 166 | * by testing ... | 198 | * by testing ... |
| @@ -241,23 +273,28 @@ void ieee80211_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb) | |||
| 241 | tid = qc[0] & 0xf; | 273 | tid = qc[0] & 0xf; |
| 242 | ssn = ((le16_to_cpu(hdr->seq_ctrl) + 0x10) | 274 | ssn = ((le16_to_cpu(hdr->seq_ctrl) + 0x10) |
| 243 | & IEEE80211_SCTL_SEQ); | 275 | & IEEE80211_SCTL_SEQ); |
| 244 | ieee80211_send_bar(sta->sdata, hdr->addr1, | 276 | ieee80211_send_bar(&sta->sdata->vif, hdr->addr1, |
| 245 | tid, ssn); | 277 | tid, ssn); |
| 246 | } | 278 | } |
| 247 | 279 | ||
| 248 | if (!acked && ieee80211_is_back_req(fc)) { | 280 | if (!acked && ieee80211_is_back_req(fc)) { |
| 281 | u16 control; | ||
| 282 | |||
| 249 | /* | 283 | /* |
| 250 | * BAR failed, let's tear down the BA session as a | 284 | * BAR failed, store the last SSN and retry sending |
| 251 | * last resort as some STAs (Intel 5100 on Windows) | 285 | * the BAR when the next unicast transmission on the |
| 252 | * can get stuck when the BA window isn't flushed | 286 | * same TID succeeds. |
| 253 | * correctly. | ||
| 254 | */ | 287 | */ |
| 255 | bar = (struct ieee80211_bar *) skb->data; | 288 | bar = (struct ieee80211_bar *) skb->data; |
| 256 | if (!(bar->control & IEEE80211_BAR_CTRL_MULTI_TID)) { | 289 | control = le16_to_cpu(bar->control); |
| 257 | tid = (bar->control & | 290 | if (!(control & IEEE80211_BAR_CTRL_MULTI_TID)) { |
| 291 | u16 ssn = le16_to_cpu(bar->start_seq_num); | ||
| 292 | |||
| 293 | tid = (control & | ||
| 258 | IEEE80211_BAR_CTRL_TID_INFO_MASK) >> | 294 | IEEE80211_BAR_CTRL_TID_INFO_MASK) >> |
| 259 | IEEE80211_BAR_CTRL_TID_INFO_SHIFT; | 295 | IEEE80211_BAR_CTRL_TID_INFO_SHIFT; |
| 260 | ieee80211_stop_tx_ba_session(&sta->sta, tid); | 296 | |
| 297 | ieee80211_set_bar_pending(sta, tid, ssn); | ||
| 261 | } | 298 | } |
| 262 | } | 299 | } |
| 263 | 300 | ||
diff --git a/net/mac80211/tx.c b/net/mac80211/tx.c index 01072639666f..7cd6c28968b2 100644 --- a/net/mac80211/tx.c +++ b/net/mac80211/tx.c | |||
| @@ -1232,7 +1232,8 @@ ieee80211_tx_prepare(struct ieee80211_sub_if_data *sdata, | |||
| 1232 | tx->sta = sta_info_get(sdata, hdr->addr1); | 1232 | tx->sta = sta_info_get(sdata, hdr->addr1); |
| 1233 | 1233 | ||
| 1234 | if (tx->sta && ieee80211_is_data_qos(hdr->frame_control) && | 1234 | if (tx->sta && ieee80211_is_data_qos(hdr->frame_control) && |
| 1235 | (local->hw.flags & IEEE80211_HW_AMPDU_AGGREGATION)) { | 1235 | (local->hw.flags & IEEE80211_HW_AMPDU_AGGREGATION) && |
| 1236 | !(local->hw.flags & IEEE80211_HW_TX_AMPDU_SETUP_IN_HW)) { | ||
| 1236 | struct tid_ampdu_tx *tid_tx; | 1237 | struct tid_ampdu_tx *tid_tx; |
| 1237 | 1238 | ||
| 1238 | qc = ieee80211_get_qos_ctl(hdr); | 1239 | qc = ieee80211_get_qos_ctl(hdr); |
| @@ -1595,7 +1596,7 @@ static void ieee80211_xmit(struct ieee80211_sub_if_data *sdata, | |||
| 1595 | return; | 1596 | return; |
| 1596 | } | 1597 | } |
| 1597 | 1598 | ||
| 1598 | ieee80211_set_qos_hdr(local, skb); | 1599 | ieee80211_set_qos_hdr(sdata, skb); |
| 1599 | ieee80211_tx(sdata, skb, false); | 1600 | ieee80211_tx(sdata, skb, false); |
| 1600 | rcu_read_unlock(); | 1601 | rcu_read_unlock(); |
| 1601 | } | 1602 | } |
| @@ -1878,6 +1879,10 @@ netdev_tx_t ieee80211_subif_start_xmit(struct sk_buff *skb, | |||
| 1878 | rcu_read_unlock(); | 1879 | rcu_read_unlock(); |
| 1879 | } | 1880 | } |
| 1880 | 1881 | ||
| 1882 | /* For mesh, the use of the QoS header is mandatory */ | ||
| 1883 | if (ieee80211_vif_is_mesh(&sdata->vif)) | ||
| 1884 | sta_flags |= WLAN_STA_WME; | ||
| 1885 | |||
| 1881 | /* receiver and we are QoS enabled, use a QoS type frame */ | 1886 | /* receiver and we are QoS enabled, use a QoS type frame */ |
| 1882 | if ((sta_flags & WLAN_STA_WME) && local->hw.queues >= 4) { | 1887 | if ((sta_flags & WLAN_STA_WME) && local->hw.queues >= 4) { |
| 1883 | fc |= cpu_to_le16(IEEE80211_STYPE_QOS_DATA); | 1888 | fc |= cpu_to_le16(IEEE80211_STYPE_QOS_DATA); |
| @@ -2365,11 +2370,9 @@ struct sk_buff *ieee80211_pspoll_get(struct ieee80211_hw *hw, | |||
| 2365 | local = sdata->local; | 2370 | local = sdata->local; |
| 2366 | 2371 | ||
| 2367 | skb = dev_alloc_skb(local->hw.extra_tx_headroom + sizeof(*pspoll)); | 2372 | skb = dev_alloc_skb(local->hw.extra_tx_headroom + sizeof(*pspoll)); |
| 2368 | if (!skb) { | 2373 | if (!skb) |
| 2369 | printk(KERN_DEBUG "%s: failed to allocate buffer for " | ||
| 2370 | "pspoll template\n", sdata->name); | ||
| 2371 | return NULL; | 2374 | return NULL; |
| 2372 | } | 2375 | |
| 2373 | skb_reserve(skb, local->hw.extra_tx_headroom); | 2376 | skb_reserve(skb, local->hw.extra_tx_headroom); |
| 2374 | 2377 | ||
| 2375 | pspoll = (struct ieee80211_pspoll *) skb_put(skb, sizeof(*pspoll)); | 2378 | pspoll = (struct ieee80211_pspoll *) skb_put(skb, sizeof(*pspoll)); |
| @@ -2405,11 +2408,9 @@ struct sk_buff *ieee80211_nullfunc_get(struct ieee80211_hw *hw, | |||
| 2405 | local = sdata->local; | 2408 | local = sdata->local; |
| 2406 | 2409 | ||
| 2407 | skb = dev_alloc_skb(local->hw.extra_tx_headroom + sizeof(*nullfunc)); | 2410 | skb = dev_alloc_skb(local->hw.extra_tx_headroom + sizeof(*nullfunc)); |
| 2408 | if (!skb) { | 2411 | if (!skb) |
| 2409 | printk(KERN_DEBUG "%s: failed to allocate buffer for nullfunc " | ||
| 2410 | "template\n", sdata->name); | ||
| 2411 | return NULL; | 2412 | return NULL; |
| 2412 | } | 2413 | |
| 2413 | skb_reserve(skb, local->hw.extra_tx_headroom); | 2414 | skb_reserve(skb, local->hw.extra_tx_headroom); |
| 2414 | 2415 | ||
| 2415 | nullfunc = (struct ieee80211_hdr_3addr *) skb_put(skb, | 2416 | nullfunc = (struct ieee80211_hdr_3addr *) skb_put(skb, |
| @@ -2444,11 +2445,8 @@ struct sk_buff *ieee80211_probereq_get(struct ieee80211_hw *hw, | |||
| 2444 | 2445 | ||
| 2445 | skb = dev_alloc_skb(local->hw.extra_tx_headroom + sizeof(*hdr) + | 2446 | skb = dev_alloc_skb(local->hw.extra_tx_headroom + sizeof(*hdr) + |
| 2446 | ie_ssid_len + ie_len); | 2447 | ie_ssid_len + ie_len); |
| 2447 | if (!skb) { | 2448 | if (!skb) |
| 2448 | printk(KERN_DEBUG "%s: failed to allocate buffer for probe " | ||
| 2449 | "request template\n", sdata->name); | ||
| 2450 | return NULL; | 2449 | return NULL; |
| 2451 | } | ||
| 2452 | 2450 | ||
| 2453 | skb_reserve(skb, local->hw.extra_tx_headroom); | 2451 | skb_reserve(skb, local->hw.extra_tx_headroom); |
| 2454 | 2452 | ||
diff --git a/net/mac80211/util.c b/net/mac80211/util.c index ce916ff6ef08..4b1466d5b6a1 100644 --- a/net/mac80211/util.c +++ b/net/mac80211/util.c | |||
| @@ -707,11 +707,9 @@ void ieee80211_send_auth(struct ieee80211_sub_if_data *sdata, | |||
| 707 | 707 | ||
| 708 | skb = dev_alloc_skb(local->hw.extra_tx_headroom + | 708 | skb = dev_alloc_skb(local->hw.extra_tx_headroom + |
| 709 | sizeof(*mgmt) + 6 + extra_len); | 709 | sizeof(*mgmt) + 6 + extra_len); |
| 710 | if (!skb) { | 710 | if (!skb) |
| 711 | printk(KERN_DEBUG "%s: failed to allocate buffer for auth " | ||
| 712 | "frame\n", sdata->name); | ||
| 713 | return; | 711 | return; |
| 714 | } | 712 | |
| 715 | skb_reserve(skb, local->hw.extra_tx_headroom); | 713 | skb_reserve(skb, local->hw.extra_tx_headroom); |
| 716 | 714 | ||
| 717 | mgmt = (struct ieee80211_mgmt *) skb_put(skb, 24 + 6); | 715 | mgmt = (struct ieee80211_mgmt *) skb_put(skb, 24 + 6); |
| @@ -864,11 +862,8 @@ struct sk_buff *ieee80211_build_probe_req(struct ieee80211_sub_if_data *sdata, | |||
| 864 | 862 | ||
| 865 | /* FIXME: come up with a proper value */ | 863 | /* FIXME: come up with a proper value */ |
| 866 | buf = kmalloc(200 + ie_len, GFP_KERNEL); | 864 | buf = kmalloc(200 + ie_len, GFP_KERNEL); |
| 867 | if (!buf) { | 865 | if (!buf) |
| 868 | printk(KERN_DEBUG "%s: failed to allocate temporary IE " | ||
| 869 | "buffer\n", sdata->name); | ||
| 870 | return NULL; | 866 | return NULL; |
| 871 | } | ||
| 872 | 867 | ||
| 873 | /* | 868 | /* |
| 874 | * Do not send DS Channel parameter for directed probe requests | 869 | * Do not send DS Channel parameter for directed probe requests |
| @@ -1082,6 +1077,8 @@ int ieee80211_reconfig(struct ieee80211_local *local) | |||
| 1082 | changed |= BSS_CHANGED_IBSS; | 1077 | changed |= BSS_CHANGED_IBSS; |
| 1083 | /* fall through */ | 1078 | /* fall through */ |
| 1084 | case NL80211_IFTYPE_AP: | 1079 | case NL80211_IFTYPE_AP: |
| 1080 | changed |= BSS_CHANGED_SSID; | ||
| 1081 | /* fall through */ | ||
| 1085 | case NL80211_IFTYPE_MESH_POINT: | 1082 | case NL80211_IFTYPE_MESH_POINT: |
| 1086 | changed |= BSS_CHANGED_BEACON | | 1083 | changed |= BSS_CHANGED_BEACON | |
| 1087 | BSS_CHANGED_BEACON_ENABLED; | 1084 | BSS_CHANGED_BEACON_ENABLED; |
diff --git a/net/mac80211/wme.c b/net/mac80211/wme.c index 7a49532f14cb..971004c9b04f 100644 --- a/net/mac80211/wme.c +++ b/net/mac80211/wme.c | |||
| @@ -83,11 +83,7 @@ u16 ieee80211_select_queue(struct ieee80211_sub_if_data *sdata, | |||
| 83 | break; | 83 | break; |
| 84 | #ifdef CONFIG_MAC80211_MESH | 84 | #ifdef CONFIG_MAC80211_MESH |
| 85 | case NL80211_IFTYPE_MESH_POINT: | 85 | case NL80211_IFTYPE_MESH_POINT: |
| 86 | /* | 86 | ra = skb->data; |
| 87 | * XXX: This is clearly broken ... but already was before, | ||
| 88 | * because ieee80211_fill_mesh_addresses() would clear A1 | ||
| 89 | * except for multicast addresses. | ||
| 90 | */ | ||
| 91 | break; | 87 | break; |
| 92 | #endif | 88 | #endif |
| 93 | case NL80211_IFTYPE_STATION: | 89 | case NL80211_IFTYPE_STATION: |
| @@ -139,7 +135,8 @@ u16 ieee80211_downgrade_queue(struct ieee80211_local *local, | |||
| 139 | return ieee802_1d_to_ac[skb->priority]; | 135 | return ieee802_1d_to_ac[skb->priority]; |
| 140 | } | 136 | } |
| 141 | 137 | ||
| 142 | void ieee80211_set_qos_hdr(struct ieee80211_local *local, struct sk_buff *skb) | 138 | void ieee80211_set_qos_hdr(struct ieee80211_sub_if_data *sdata, |
| 139 | struct sk_buff *skb) | ||
| 143 | { | 140 | { |
| 144 | struct ieee80211_hdr *hdr = (void *)skb->data; | 141 | struct ieee80211_hdr *hdr = (void *)skb->data; |
| 145 | 142 | ||
| @@ -150,10 +147,11 @@ void ieee80211_set_qos_hdr(struct ieee80211_local *local, struct sk_buff *skb) | |||
| 150 | 147 | ||
| 151 | tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; | 148 | tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; |
| 152 | 149 | ||
| 153 | if (unlikely(local->wifi_wme_noack_test)) | 150 | if (unlikely(sdata->local->wifi_wme_noack_test)) |
| 154 | ack_policy |= IEEE80211_QOS_CTL_ACK_POLICY_NOACK; | 151 | ack_policy |= IEEE80211_QOS_CTL_ACK_POLICY_NOACK; |
| 155 | /* qos header is 2 bytes, second reserved */ | 152 | /* qos header is 2 bytes */ |
| 156 | *p++ = ack_policy | tid; | 153 | *p++ = ack_policy | tid; |
| 157 | *p = 0; | 154 | *p = ieee80211_vif_is_mesh(&sdata->vif) ? |
| 155 | (IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT >> 8) : 0; | ||
| 158 | } | 156 | } |
| 159 | } | 157 | } |
diff --git a/net/mac80211/wme.h b/net/mac80211/wme.h index faead6d02026..34e166fbf4d4 100644 --- a/net/mac80211/wme.h +++ b/net/mac80211/wme.h | |||
| @@ -17,7 +17,8 @@ extern const int ieee802_1d_to_ac[8]; | |||
| 17 | 17 | ||
| 18 | u16 ieee80211_select_queue(struct ieee80211_sub_if_data *sdata, | 18 | u16 ieee80211_select_queue(struct ieee80211_sub_if_data *sdata, |
| 19 | struct sk_buff *skb); | 19 | struct sk_buff *skb); |
| 20 | void ieee80211_set_qos_hdr(struct ieee80211_local *local, struct sk_buff *skb); | 20 | void ieee80211_set_qos_hdr(struct ieee80211_sub_if_data *sdata, |
| 21 | struct sk_buff *skb); | ||
| 21 | u16 ieee80211_downgrade_queue(struct ieee80211_local *local, | 22 | u16 ieee80211_downgrade_queue(struct ieee80211_local *local, |
| 22 | struct sk_buff *skb); | 23 | struct sk_buff *skb); |
| 23 | 24 | ||
diff --git a/net/mac80211/work.c b/net/mac80211/work.c index 380b9a7462b6..bac34394c05e 100644 --- a/net/mac80211/work.c +++ b/net/mac80211/work.c | |||
| @@ -229,11 +229,9 @@ static void ieee80211_send_assoc(struct ieee80211_sub_if_data *sdata, | |||
| 229 | wk->ie_len + /* extra IEs */ | 229 | wk->ie_len + /* extra IEs */ |
| 230 | 9, /* WMM */ | 230 | 9, /* WMM */ |
| 231 | GFP_KERNEL); | 231 | GFP_KERNEL); |
| 232 | if (!skb) { | 232 | if (!skb) |
| 233 | printk(KERN_DEBUG "%s: failed to allocate buffer for assoc " | ||
| 234 | "frame\n", sdata->name); | ||
| 235 | return; | 233 | return; |
| 236 | } | 234 | |
| 237 | skb_reserve(skb, local->hw.extra_tx_headroom); | 235 | skb_reserve(skb, local->hw.extra_tx_headroom); |
| 238 | 236 | ||
| 239 | capab = WLAN_CAPABILITY_ESS; | 237 | capab = WLAN_CAPABILITY_ESS; |
diff --git a/net/rfkill/rfkill-regulator.c b/net/rfkill/rfkill-regulator.c index 18dc512a10f3..3ca7277a3c36 100644 --- a/net/rfkill/rfkill-regulator.c +++ b/net/rfkill/rfkill-regulator.c | |||
| @@ -90,7 +90,6 @@ static int __devinit rfkill_regulator_probe(struct platform_device *pdev) | |||
| 90 | pdata->type, | 90 | pdata->type, |
| 91 | &rfkill_regulator_ops, rfkill_data); | 91 | &rfkill_regulator_ops, rfkill_data); |
| 92 | if (rf_kill == NULL) { | 92 | if (rf_kill == NULL) { |
| 93 | dev_err(&pdev->dev, "Cannot alloc rfkill device\n"); | ||
| 94 | ret = -ENOMEM; | 93 | ret = -ENOMEM; |
| 95 | goto err_rfkill_alloc; | 94 | goto err_rfkill_alloc; |
| 96 | } | 95 | } |
diff --git a/net/wireless/core.c b/net/wireless/core.c index 645437cfc464..44cbebac25e0 100644 --- a/net/wireless/core.c +++ b/net/wireless/core.c | |||
| @@ -582,7 +582,7 @@ int wiphy_register(struct wiphy *wiphy) | |||
| 582 | } | 582 | } |
| 583 | 583 | ||
| 584 | /* set up regulatory info */ | 584 | /* set up regulatory info */ |
| 585 | wiphy_update_regulatory(wiphy, NL80211_REGDOM_SET_BY_CORE); | 585 | regulatory_update(wiphy, NL80211_REGDOM_SET_BY_CORE); |
| 586 | 586 | ||
| 587 | list_add_rcu(&rdev->list, &cfg80211_rdev_list); | 587 | list_add_rcu(&rdev->list, &cfg80211_rdev_list); |
| 588 | cfg80211_rdev_list_generation++; | 588 | cfg80211_rdev_list_generation++; |
diff --git a/net/wireless/core.h b/net/wireless/core.h index 8672e028022f..796a4bdf8b0d 100644 --- a/net/wireless/core.h +++ b/net/wireless/core.h | |||
| @@ -279,8 +279,6 @@ extern int cfg80211_dev_rename(struct cfg80211_registered_device *rdev, | |||
| 279 | char *newname); | 279 | char *newname); |
| 280 | 280 | ||
| 281 | void ieee80211_set_bitrate_flags(struct wiphy *wiphy); | 281 | void ieee80211_set_bitrate_flags(struct wiphy *wiphy); |
| 282 | void wiphy_update_regulatory(struct wiphy *wiphy, | ||
| 283 | enum nl80211_reg_initiator setby); | ||
| 284 | 282 | ||
| 285 | void cfg80211_bss_expire(struct cfg80211_registered_device *dev); | 283 | void cfg80211_bss_expire(struct cfg80211_registered_device *dev); |
| 286 | void cfg80211_bss_age(struct cfg80211_registered_device *dev, | 284 | void cfg80211_bss_age(struct cfg80211_registered_device *dev, |
diff --git a/net/wireless/lib80211_crypt_ccmp.c b/net/wireless/lib80211_crypt_ccmp.c index dacb3b4b1bdb..755738d26bb4 100644 --- a/net/wireless/lib80211_crypt_ccmp.c +++ b/net/wireless/lib80211_crypt_ccmp.c | |||
| @@ -77,8 +77,6 @@ static void *lib80211_ccmp_init(int key_idx) | |||
| 77 | 77 | ||
| 78 | priv->tfm = crypto_alloc_cipher("aes", 0, CRYPTO_ALG_ASYNC); | 78 | priv->tfm = crypto_alloc_cipher("aes", 0, CRYPTO_ALG_ASYNC); |
| 79 | if (IS_ERR(priv->tfm)) { | 79 | if (IS_ERR(priv->tfm)) { |
| 80 | printk(KERN_DEBUG "lib80211_crypt_ccmp: could not allocate " | ||
| 81 | "crypto API aes\n"); | ||
| 82 | priv->tfm = NULL; | 80 | priv->tfm = NULL; |
| 83 | goto fail; | 81 | goto fail; |
| 84 | } | 82 | } |
diff --git a/net/wireless/lib80211_crypt_tkip.c b/net/wireless/lib80211_crypt_tkip.c index 7ea4f2b0770e..38734846c19e 100644 --- a/net/wireless/lib80211_crypt_tkip.c +++ b/net/wireless/lib80211_crypt_tkip.c | |||
| @@ -101,7 +101,6 @@ static void *lib80211_tkip_init(int key_idx) | |||
| 101 | priv->tx_tfm_arc4 = crypto_alloc_blkcipher("ecb(arc4)", 0, | 101 | priv->tx_tfm_arc4 = crypto_alloc_blkcipher("ecb(arc4)", 0, |
| 102 | CRYPTO_ALG_ASYNC); | 102 | CRYPTO_ALG_ASYNC); |
| 103 | if (IS_ERR(priv->tx_tfm_arc4)) { | 103 | if (IS_ERR(priv->tx_tfm_arc4)) { |
| 104 | printk(KERN_DEBUG pr_fmt("could not allocate crypto API arc4\n")); | ||
| 105 | priv->tx_tfm_arc4 = NULL; | 104 | priv->tx_tfm_arc4 = NULL; |
| 106 | goto fail; | 105 | goto fail; |
| 107 | } | 106 | } |
| @@ -109,7 +108,6 @@ static void *lib80211_tkip_init(int key_idx) | |||
| 109 | priv->tx_tfm_michael = crypto_alloc_hash("michael_mic", 0, | 108 | priv->tx_tfm_michael = crypto_alloc_hash("michael_mic", 0, |
| 110 | CRYPTO_ALG_ASYNC); | 109 | CRYPTO_ALG_ASYNC); |
| 111 | if (IS_ERR(priv->tx_tfm_michael)) { | 110 | if (IS_ERR(priv->tx_tfm_michael)) { |
| 112 | printk(KERN_DEBUG pr_fmt("could not allocate crypto API michael_mic\n")); | ||
| 113 | priv->tx_tfm_michael = NULL; | 111 | priv->tx_tfm_michael = NULL; |
| 114 | goto fail; | 112 | goto fail; |
| 115 | } | 113 | } |
| @@ -117,7 +115,6 @@ static void *lib80211_tkip_init(int key_idx) | |||
| 117 | priv->rx_tfm_arc4 = crypto_alloc_blkcipher("ecb(arc4)", 0, | 115 | priv->rx_tfm_arc4 = crypto_alloc_blkcipher("ecb(arc4)", 0, |
| 118 | CRYPTO_ALG_ASYNC); | 116 | CRYPTO_ALG_ASYNC); |
| 119 | if (IS_ERR(priv->rx_tfm_arc4)) { | 117 | if (IS_ERR(priv->rx_tfm_arc4)) { |
| 120 | printk(KERN_DEBUG pr_fmt("could not allocate crypto API arc4\n")); | ||
| 121 | priv->rx_tfm_arc4 = NULL; | 118 | priv->rx_tfm_arc4 = NULL; |
| 122 | goto fail; | 119 | goto fail; |
| 123 | } | 120 | } |
| @@ -125,7 +122,6 @@ static void *lib80211_tkip_init(int key_idx) | |||
| 125 | priv->rx_tfm_michael = crypto_alloc_hash("michael_mic", 0, | 122 | priv->rx_tfm_michael = crypto_alloc_hash("michael_mic", 0, |
| 126 | CRYPTO_ALG_ASYNC); | 123 | CRYPTO_ALG_ASYNC); |
| 127 | if (IS_ERR(priv->rx_tfm_michael)) { | 124 | if (IS_ERR(priv->rx_tfm_michael)) { |
| 128 | printk(KERN_DEBUG pr_fmt("could not allocate crypto API michael_mic\n")); | ||
| 129 | priv->rx_tfm_michael = NULL; | 125 | priv->rx_tfm_michael = NULL; |
| 130 | goto fail; | 126 | goto fail; |
| 131 | } | 127 | } |
diff --git a/net/wireless/lib80211_crypt_wep.c b/net/wireless/lib80211_crypt_wep.c index 2f265e033ae2..c1304018fc1c 100644 --- a/net/wireless/lib80211_crypt_wep.c +++ b/net/wireless/lib80211_crypt_wep.c | |||
| @@ -50,16 +50,12 @@ static void *lib80211_wep_init(int keyidx) | |||
| 50 | 50 | ||
| 51 | priv->tx_tfm = crypto_alloc_blkcipher("ecb(arc4)", 0, CRYPTO_ALG_ASYNC); | 51 | priv->tx_tfm = crypto_alloc_blkcipher("ecb(arc4)", 0, CRYPTO_ALG_ASYNC); |
| 52 | if (IS_ERR(priv->tx_tfm)) { | 52 | if (IS_ERR(priv->tx_tfm)) { |
| 53 | printk(KERN_DEBUG "lib80211_crypt_wep: could not allocate " | ||
| 54 | "crypto API arc4\n"); | ||
| 55 | priv->tx_tfm = NULL; | 53 | priv->tx_tfm = NULL; |
| 56 | goto fail; | 54 | goto fail; |
| 57 | } | 55 | } |
| 58 | 56 | ||
| 59 | priv->rx_tfm = crypto_alloc_blkcipher("ecb(arc4)", 0, CRYPTO_ALG_ASYNC); | 57 | priv->rx_tfm = crypto_alloc_blkcipher("ecb(arc4)", 0, CRYPTO_ALG_ASYNC); |
| 60 | if (IS_ERR(priv->rx_tfm)) { | 58 | if (IS_ERR(priv->rx_tfm)) { |
| 61 | printk(KERN_DEBUG "lib80211_crypt_wep: could not allocate " | ||
| 62 | "crypto API arc4\n"); | ||
| 63 | priv->rx_tfm = NULL; | 59 | priv->rx_tfm = NULL; |
| 64 | goto fail; | 60 | goto fail; |
| 65 | } | 61 | } |
diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c index bddb5595c659..11089541bb03 100644 --- a/net/wireless/nl80211.c +++ b/net/wireless/nl80211.c | |||
| @@ -189,6 +189,8 @@ static const struct nla_policy nl80211_policy[NL80211_ATTR_MAX+1] = { | |||
| 189 | .len = IEEE80211_MAX_DATA_LEN }, | 189 | .len = IEEE80211_MAX_DATA_LEN }, |
| 190 | [NL80211_ATTR_IE_ASSOC_RESP] = { .type = NLA_BINARY, | 190 | [NL80211_ATTR_IE_ASSOC_RESP] = { .type = NLA_BINARY, |
| 191 | .len = IEEE80211_MAX_DATA_LEN }, | 191 | .len = IEEE80211_MAX_DATA_LEN }, |
| 192 | [NL80211_ATTR_ROAM_SUPPORT] = { .type = NLA_FLAG }, | ||
| 193 | [NL80211_ATTR_SCHED_SCAN_MATCH] = { .type = NLA_NESTED }, | ||
| 192 | }; | 194 | }; |
| 193 | 195 | ||
| 194 | /* policy for the key attributes */ | 196 | /* policy for the key attributes */ |
| @@ -231,6 +233,12 @@ nl80211_rekey_policy[NUM_NL80211_REKEY_DATA] = { | |||
| 231 | [NL80211_REKEY_DATA_REPLAY_CTR] = { .len = NL80211_REPLAY_CTR_LEN }, | 233 | [NL80211_REKEY_DATA_REPLAY_CTR] = { .len = NL80211_REPLAY_CTR_LEN }, |
| 232 | }; | 234 | }; |
| 233 | 235 | ||
| 236 | static const struct nla_policy | ||
| 237 | nl80211_match_policy[NL80211_SCHED_SCAN_MATCH_ATTR_MAX + 1] = { | ||
| 238 | [NL80211_ATTR_SCHED_SCAN_MATCH_SSID] = { .type = NLA_BINARY, | ||
| 239 | .len = IEEE80211_MAX_SSID_LEN }, | ||
| 240 | }; | ||
| 241 | |||
| 234 | /* ifidx get helper */ | 242 | /* ifidx get helper */ |
| 235 | static int nl80211_get_ifidx(struct netlink_callback *cb) | 243 | static int nl80211_get_ifidx(struct netlink_callback *cb) |
| 236 | { | 244 | { |
| @@ -714,11 +722,18 @@ static int nl80211_send_wiphy(struct sk_buff *msg, u32 pid, u32 seq, int flags, | |||
| 714 | dev->wiphy.max_scan_ie_len); | 722 | dev->wiphy.max_scan_ie_len); |
| 715 | NLA_PUT_U16(msg, NL80211_ATTR_MAX_SCHED_SCAN_IE_LEN, | 723 | NLA_PUT_U16(msg, NL80211_ATTR_MAX_SCHED_SCAN_IE_LEN, |
| 716 | dev->wiphy.max_sched_scan_ie_len); | 724 | dev->wiphy.max_sched_scan_ie_len); |
| 725 | NLA_PUT_U8(msg, NL80211_ATTR_MAX_MATCH_SETS, | ||
| 726 | dev->wiphy.max_match_sets); | ||
| 717 | 727 | ||
| 718 | if (dev->wiphy.flags & WIPHY_FLAG_IBSS_RSN) | 728 | if (dev->wiphy.flags & WIPHY_FLAG_IBSS_RSN) |
| 719 | NLA_PUT_FLAG(msg, NL80211_ATTR_SUPPORT_IBSS_RSN); | 729 | NLA_PUT_FLAG(msg, NL80211_ATTR_SUPPORT_IBSS_RSN); |
| 720 | if (dev->wiphy.flags & WIPHY_FLAG_MESH_AUTH) | 730 | if (dev->wiphy.flags & WIPHY_FLAG_MESH_AUTH) |
| 721 | NLA_PUT_FLAG(msg, NL80211_ATTR_SUPPORT_MESH_AUTH); | 731 | NLA_PUT_FLAG(msg, NL80211_ATTR_SUPPORT_MESH_AUTH); |
| 732 | if (dev->wiphy.flags & WIPHY_FLAG_AP_UAPSD) | ||
| 733 | NLA_PUT_FLAG(msg, NL80211_ATTR_SUPPORT_AP_UAPSD); | ||
| 734 | |||
| 735 | if (dev->wiphy.flags & WIPHY_FLAG_SUPPORTS_FW_ROAM) | ||
| 736 | NLA_PUT_FLAG(msg, NL80211_ATTR_ROAM_SUPPORT); | ||
| 722 | 737 | ||
| 723 | NLA_PUT(msg, NL80211_ATTR_CIPHER_SUITES, | 738 | NLA_PUT(msg, NL80211_ATTR_CIPHER_SUITES, |
| 724 | sizeof(u32) * dev->wiphy.n_cipher_suites, | 739 | sizeof(u32) * dev->wiphy.n_cipher_suites, |
| @@ -2597,7 +2612,8 @@ static int nl80211_new_station(struct sk_buff *skb, struct genl_info *info) | |||
| 2597 | return -EINVAL; | 2612 | return -EINVAL; |
| 2598 | 2613 | ||
| 2599 | /* parse WME attributes if sta is WME capable */ | 2614 | /* parse WME attributes if sta is WME capable */ |
| 2600 | if ((params.sta_flags_set & NL80211_STA_FLAG_WME) && | 2615 | if ((rdev->wiphy.flags & WIPHY_FLAG_AP_UAPSD) && |
| 2616 | (params.sta_flags_set & NL80211_STA_FLAG_WME) && | ||
| 2601 | info->attrs[NL80211_ATTR_STA_WME]) { | 2617 | info->attrs[NL80211_ATTR_STA_WME]) { |
| 2602 | struct nlattr *tb[NL80211_STA_WME_MAX + 1]; | 2618 | struct nlattr *tb[NL80211_STA_WME_MAX + 1]; |
| 2603 | struct nlattr *nla; | 2619 | struct nlattr *nla; |
| @@ -2611,10 +2627,15 @@ static int nl80211_new_station(struct sk_buff *skb, struct genl_info *info) | |||
| 2611 | if (tb[NL80211_STA_WME_UAPSD_QUEUES]) | 2627 | if (tb[NL80211_STA_WME_UAPSD_QUEUES]) |
| 2612 | params.uapsd_queues = | 2628 | params.uapsd_queues = |
| 2613 | nla_get_u8(tb[NL80211_STA_WME_UAPSD_QUEUES]); | 2629 | nla_get_u8(tb[NL80211_STA_WME_UAPSD_QUEUES]); |
| 2630 | if (params.uapsd_queues & ~IEEE80211_WMM_IE_STA_QOSINFO_AC_MASK) | ||
| 2631 | return -EINVAL; | ||
| 2614 | 2632 | ||
| 2615 | if (tb[NL80211_STA_WME_MAX_SP]) | 2633 | if (tb[NL80211_STA_WME_MAX_SP]) |
| 2616 | params.max_sp = | 2634 | params.max_sp = |
| 2617 | nla_get_u8(tb[NL80211_STA_WME_MAX_SP]); | 2635 | nla_get_u8(tb[NL80211_STA_WME_MAX_SP]); |
| 2636 | |||
| 2637 | if (params.max_sp & ~IEEE80211_WMM_IE_STA_QOSINFO_SP_MASK) | ||
| 2638 | return -EINVAL; | ||
| 2618 | } | 2639 | } |
| 2619 | 2640 | ||
| 2620 | if (dev->ieee80211_ptr->iftype != NL80211_IFTYPE_AP && | 2641 | if (dev->ieee80211_ptr->iftype != NL80211_IFTYPE_AP && |
| @@ -3625,10 +3646,11 @@ static int nl80211_start_sched_scan(struct sk_buff *skb, | |||
| 3625 | struct net_device *dev = info->user_ptr[1]; | 3646 | struct net_device *dev = info->user_ptr[1]; |
| 3626 | struct nlattr *attr; | 3647 | struct nlattr *attr; |
| 3627 | struct wiphy *wiphy; | 3648 | struct wiphy *wiphy; |
| 3628 | int err, tmp, n_ssids = 0, n_channels, i; | 3649 | int err, tmp, n_ssids = 0, n_match_sets = 0, n_channels, i; |
| 3629 | u32 interval; | 3650 | u32 interval; |
| 3630 | enum ieee80211_band band; | 3651 | enum ieee80211_band band; |
| 3631 | size_t ie_len; | 3652 | size_t ie_len; |
| 3653 | struct nlattr *tb[NL80211_SCHED_SCAN_MATCH_ATTR_MAX + 1]; | ||
| 3632 | 3654 | ||
| 3633 | if (!(rdev->wiphy.flags & WIPHY_FLAG_SUPPORTS_SCHED_SCAN) || | 3655 | if (!(rdev->wiphy.flags & WIPHY_FLAG_SUPPORTS_SCHED_SCAN) || |
| 3634 | !rdev->ops->sched_scan_start) | 3656 | !rdev->ops->sched_scan_start) |
| @@ -3667,6 +3689,15 @@ static int nl80211_start_sched_scan(struct sk_buff *skb, | |||
| 3667 | if (n_ssids > wiphy->max_sched_scan_ssids) | 3689 | if (n_ssids > wiphy->max_sched_scan_ssids) |
| 3668 | return -EINVAL; | 3690 | return -EINVAL; |
| 3669 | 3691 | ||
| 3692 | if (info->attrs[NL80211_ATTR_SCHED_SCAN_MATCH]) | ||
| 3693 | nla_for_each_nested(attr, | ||
| 3694 | info->attrs[NL80211_ATTR_SCHED_SCAN_MATCH], | ||
| 3695 | tmp) | ||
| 3696 | n_match_sets++; | ||
| 3697 | |||
| 3698 | if (n_match_sets > wiphy->max_match_sets) | ||
| 3699 | return -EINVAL; | ||
| 3700 | |||
| 3670 | if (info->attrs[NL80211_ATTR_IE]) | 3701 | if (info->attrs[NL80211_ATTR_IE]) |
| 3671 | ie_len = nla_len(info->attrs[NL80211_ATTR_IE]); | 3702 | ie_len = nla_len(info->attrs[NL80211_ATTR_IE]); |
| 3672 | else | 3703 | else |
| @@ -3684,6 +3715,7 @@ static int nl80211_start_sched_scan(struct sk_buff *skb, | |||
| 3684 | 3715 | ||
| 3685 | request = kzalloc(sizeof(*request) | 3716 | request = kzalloc(sizeof(*request) |
| 3686 | + sizeof(*request->ssids) * n_ssids | 3717 | + sizeof(*request->ssids) * n_ssids |
| 3718 | + sizeof(*request->match_sets) * n_match_sets | ||
| 3687 | + sizeof(*request->channels) * n_channels | 3719 | + sizeof(*request->channels) * n_channels |
| 3688 | + ie_len, GFP_KERNEL); | 3720 | + ie_len, GFP_KERNEL); |
| 3689 | if (!request) { | 3721 | if (!request) { |
| @@ -3701,6 +3733,18 @@ static int nl80211_start_sched_scan(struct sk_buff *skb, | |||
| 3701 | request->ie = (void *)(request->channels + n_channels); | 3733 | request->ie = (void *)(request->channels + n_channels); |
| 3702 | } | 3734 | } |
| 3703 | 3735 | ||
| 3736 | if (n_match_sets) { | ||
| 3737 | if (request->ie) | ||
| 3738 | request->match_sets = (void *)(request->ie + ie_len); | ||
| 3739 | else if (request->ssids) | ||
| 3740 | request->match_sets = | ||
| 3741 | (void *)(request->ssids + n_ssids); | ||
| 3742 | else | ||
| 3743 | request->match_sets = | ||
| 3744 | (void *)(request->channels + n_channels); | ||
| 3745 | } | ||
| 3746 | request->n_match_sets = n_match_sets; | ||
| 3747 | |||
| 3704 | i = 0; | 3748 | i = 0; |
| 3705 | if (info->attrs[NL80211_ATTR_SCAN_FREQUENCIES]) { | 3749 | if (info->attrs[NL80211_ATTR_SCAN_FREQUENCIES]) { |
| 3706 | /* user specified, bail out if channel not found */ | 3750 | /* user specified, bail out if channel not found */ |
| @@ -3765,6 +3809,31 @@ static int nl80211_start_sched_scan(struct sk_buff *skb, | |||
| 3765 | } | 3809 | } |
| 3766 | } | 3810 | } |
| 3767 | 3811 | ||
| 3812 | i = 0; | ||
| 3813 | if (info->attrs[NL80211_ATTR_SCHED_SCAN_MATCH]) { | ||
| 3814 | nla_for_each_nested(attr, | ||
| 3815 | info->attrs[NL80211_ATTR_SCHED_SCAN_MATCH], | ||
| 3816 | tmp) { | ||
| 3817 | struct nlattr *ssid; | ||
| 3818 | |||
| 3819 | nla_parse(tb, NL80211_SCHED_SCAN_MATCH_ATTR_MAX, | ||
| 3820 | nla_data(attr), nla_len(attr), | ||
| 3821 | nl80211_match_policy); | ||
| 3822 | ssid = tb[NL80211_ATTR_SCHED_SCAN_MATCH_SSID]; | ||
| 3823 | if (ssid) { | ||
| 3824 | if (nla_len(ssid) > IEEE80211_MAX_SSID_LEN) { | ||
| 3825 | err = -EINVAL; | ||
| 3826 | goto out_free; | ||
| 3827 | } | ||
| 3828 | memcpy(request->match_sets[i].ssid.ssid, | ||
| 3829 | nla_data(ssid), nla_len(ssid)); | ||
| 3830 | request->match_sets[i].ssid.ssid_len = | ||
| 3831 | nla_len(ssid); | ||
| 3832 | } | ||
| 3833 | i++; | ||
| 3834 | } | ||
| 3835 | } | ||
| 3836 | |||
| 3768 | if (info->attrs[NL80211_ATTR_IE]) { | 3837 | if (info->attrs[NL80211_ATTR_IE]) { |
| 3769 | request->ie_len = nla_len(info->attrs[NL80211_ATTR_IE]); | 3838 | request->ie_len = nla_len(info->attrs[NL80211_ATTR_IE]); |
| 3770 | memcpy((void *)request->ie, | 3839 | memcpy((void *)request->ie, |
diff --git a/net/wireless/reg.c b/net/wireless/reg.c index 9f3aa5cabdef..18fc37b6f2bd 100644 --- a/net/wireless/reg.c +++ b/net/wireless/reg.c | |||
| @@ -751,9 +751,10 @@ static void chan_reg_rule_print_dbg(struct ieee80211_channel *chan, | |||
| 751 | chan->center_freq, | 751 | chan->center_freq, |
| 752 | KHZ_TO_MHZ(desired_bw_khz)); | 752 | KHZ_TO_MHZ(desired_bw_khz)); |
| 753 | 753 | ||
| 754 | REG_DBG_PRINT("%d KHz - %d KHz @ KHz), (%s mBi, %d mBm)\n", | 754 | REG_DBG_PRINT("%d KHz - %d KHz @ %d KHz), (%s mBi, %d mBm)\n", |
| 755 | freq_range->start_freq_khz, | 755 | freq_range->start_freq_khz, |
| 756 | freq_range->end_freq_khz, | 756 | freq_range->end_freq_khz, |
| 757 | freq_range->max_bandwidth_khz, | ||
| 757 | max_antenna_gain, | 758 | max_antenna_gain, |
| 758 | power_rule->max_eirp); | 759 | power_rule->max_eirp); |
| 759 | } | 760 | } |
| @@ -910,14 +911,6 @@ static bool ignore_reg_update(struct wiphy *wiphy, | |||
| 910 | return false; | 911 | return false; |
| 911 | } | 912 | } |
| 912 | 913 | ||
| 913 | static void update_all_wiphy_regulatory(enum nl80211_reg_initiator initiator) | ||
| 914 | { | ||
| 915 | struct cfg80211_registered_device *rdev; | ||
| 916 | |||
| 917 | list_for_each_entry(rdev, &cfg80211_rdev_list, list) | ||
| 918 | wiphy_update_regulatory(&rdev->wiphy, initiator); | ||
| 919 | } | ||
| 920 | |||
| 921 | static void handle_reg_beacon(struct wiphy *wiphy, | 914 | static void handle_reg_beacon(struct wiphy *wiphy, |
| 922 | unsigned int chan_idx, | 915 | unsigned int chan_idx, |
| 923 | struct reg_beacon *reg_beacon) | 916 | struct reg_beacon *reg_beacon) |
| @@ -1117,11 +1110,13 @@ static void reg_process_ht_flags(struct wiphy *wiphy) | |||
| 1117 | 1110 | ||
| 1118 | } | 1111 | } |
| 1119 | 1112 | ||
| 1120 | void wiphy_update_regulatory(struct wiphy *wiphy, | 1113 | static void wiphy_update_regulatory(struct wiphy *wiphy, |
| 1121 | enum nl80211_reg_initiator initiator) | 1114 | enum nl80211_reg_initiator initiator) |
| 1122 | { | 1115 | { |
| 1123 | enum ieee80211_band band; | 1116 | enum ieee80211_band band; |
| 1124 | 1117 | ||
| 1118 | assert_reg_lock(); | ||
| 1119 | |||
| 1125 | if (ignore_reg_update(wiphy, initiator)) | 1120 | if (ignore_reg_update(wiphy, initiator)) |
| 1126 | return; | 1121 | return; |
| 1127 | 1122 | ||
| @@ -1136,6 +1131,22 @@ void wiphy_update_regulatory(struct wiphy *wiphy, | |||
| 1136 | wiphy->reg_notifier(wiphy, last_request); | 1131 | wiphy->reg_notifier(wiphy, last_request); |
| 1137 | } | 1132 | } |
| 1138 | 1133 | ||
| 1134 | void regulatory_update(struct wiphy *wiphy, | ||
| 1135 | enum nl80211_reg_initiator setby) | ||
| 1136 | { | ||
| 1137 | mutex_lock(®_mutex); | ||
| 1138 | wiphy_update_regulatory(wiphy, setby); | ||
| 1139 | mutex_unlock(®_mutex); | ||
| 1140 | } | ||
| 1141 | |||
| 1142 | static void update_all_wiphy_regulatory(enum nl80211_reg_initiator initiator) | ||
| 1143 | { | ||
| 1144 | struct cfg80211_registered_device *rdev; | ||
| 1145 | |||
| 1146 | list_for_each_entry(rdev, &cfg80211_rdev_list, list) | ||
| 1147 | wiphy_update_regulatory(&rdev->wiphy, initiator); | ||
| 1148 | } | ||
| 1149 | |||
| 1139 | static void handle_channel_custom(struct wiphy *wiphy, | 1150 | static void handle_channel_custom(struct wiphy *wiphy, |
| 1140 | enum ieee80211_band band, | 1151 | enum ieee80211_band band, |
| 1141 | unsigned int chan_idx, | 1152 | unsigned int chan_idx, |
diff --git a/net/wireless/reg.h b/net/wireless/reg.h index b67d1c3a2fb9..4a56799d868d 100644 --- a/net/wireless/reg.h +++ b/net/wireless/reg.h | |||
| @@ -16,6 +16,8 @@ void regulatory_exit(void); | |||
| 16 | 16 | ||
| 17 | int set_regdom(const struct ieee80211_regdomain *rd); | 17 | int set_regdom(const struct ieee80211_regdomain *rd); |
| 18 | 18 | ||
| 19 | void regulatory_update(struct wiphy *wiphy, enum nl80211_reg_initiator setby); | ||
| 20 | |||
| 19 | /** | 21 | /** |
| 20 | * regulatory_hint_found_beacon - hints a beacon was found on a channel | 22 | * regulatory_hint_found_beacon - hints a beacon was found on a channel |
| 21 | * @wiphy: the wireless device where the beacon was found on | 23 | * @wiphy: the wireless device where the beacon was found on |
diff --git a/net/wireless/util.c b/net/wireless/util.c index eef82f79554d..39dbf4ad7ca1 100644 --- a/net/wireless/util.c +++ b/net/wireless/util.c | |||
| @@ -513,10 +513,9 @@ int ieee80211_data_from_8023(struct sk_buff *skb, const u8 *addr, | |||
| 513 | if (head_need) | 513 | if (head_need) |
| 514 | skb_orphan(skb); | 514 | skb_orphan(skb); |
| 515 | 515 | ||
| 516 | if (pskb_expand_head(skb, head_need, 0, GFP_ATOMIC)) { | 516 | if (pskb_expand_head(skb, head_need, 0, GFP_ATOMIC)) |
| 517 | pr_err("failed to reallocate Tx buffer\n"); | ||
| 518 | return -ENOMEM; | 517 | return -ENOMEM; |
| 519 | } | 518 | |
| 520 | skb->truesize += head_need; | 519 | skb->truesize += head_need; |
| 521 | } | 520 | } |
| 522 | 521 | ||