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authorKukjin Kim <kgene.kim@samsung.com>2011-02-14 02:08:04 -0500
committerKukjin Kim <kgene.kim@samsung.com>2011-02-21 23:51:14 -0500
commitb3ed3a174c419702eddf9fb28636f6e4baa29d03 (patch)
treeb4c58aab5e891ae4fa36924844e6ff9e2dd47f75
parent7d30e8b3815f804139271dfc31962ab74ce89650 (diff)
ARM: EXYNOS4: Update Clock part
This patch updates Clock part of EXYNOS4 according to the change of ARCH name, EXYNOS4. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat
-rw-r--r--arch/arm/mach-exynos4/clock.c (renamed from arch/arm/mach-s5pv310/clock.c)190
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-clock.h (renamed from arch/arm/mach-s5pv310/include/mach/regs-clock.h)8
2 files changed, 99 insertions, 99 deletions
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-exynos4/clock.c
index fc7c2f8d165e..72d53d5e54af 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/clock.c 1/* linux/arch/arm/mach-exynos4/clock.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Clock support 6 * EXYNOS4 - Clock support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -46,72 +46,72 @@ static struct clk clk_sclk_usbphy1 = {
46 .id = -1, 46 .id = -1,
47}; 47};
48 48
49static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable) 49static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
50{ 50{
51 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable); 51 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
52} 52}
53 53
54static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable) 54static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
55{ 55{
56 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable); 56 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
57} 57}
58 58
59static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable) 59static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
60{ 60{
61 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable); 61 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
62} 62}
63 63
64static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) 64static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
65{ 65{
66 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable); 66 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
67} 67}
68 68
69static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) 69static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
70{ 70{
71 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable); 71 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
72} 72}
73 73
74static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) 74static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
75{ 75{
76 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable); 76 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
77} 77}
78 78
79static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable) 79static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
80{ 80{
81 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable); 81 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
82} 82}
83 83
84static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable) 84static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
85{ 85{
86 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable); 86 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
87} 87}
88 88
89static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable) 89static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
90{ 90{
91 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable); 91 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
92} 92}
93 93
94static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable) 94static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
95{ 95{
96 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable); 96 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
97} 97}
98 98
99static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable) 99static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
100{ 100{
101 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable); 101 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
102} 102}
103 103
104static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable) 104static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
105{ 105{
106 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable); 106 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
107} 107}
108 108
109static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable) 109static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
110{ 110{
111 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable); 111 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
112} 112}
113 113
114static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable) 114static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
115{ 115{
116 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable); 116 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
117} 117}
@@ -358,7 +358,7 @@ static struct clksrc_clk clk_vpllsrc = {
358 .clk = { 358 .clk = {
359 .name = "vpll_src", 359 .name = "vpll_src",
360 .id = -1, 360 .id = -1,
361 .enable = s5pv310_clksrc_mask_top_ctrl, 361 .enable = exynos4_clksrc_mask_top_ctrl,
362 .ctrlbit = (1 << 0), 362 .ctrlbit = (1 << 0),
363 }, 363 },
364 .sources = &clkset_vpllsrc, 364 .sources = &clkset_vpllsrc,
@@ -389,205 +389,205 @@ static struct clk init_clocks_off[] = {
389 .name = "timers", 389 .name = "timers",
390 .id = -1, 390 .id = -1,
391 .parent = &clk_aclk_100.clk, 391 .parent = &clk_aclk_100.clk,
392 .enable = s5pv310_clk_ip_peril_ctrl, 392 .enable = exynos4_clk_ip_peril_ctrl,
393 .ctrlbit = (1<<24), 393 .ctrlbit = (1<<24),
394 }, { 394 }, {
395 .name = "csis", 395 .name = "csis",
396 .id = 0, 396 .id = 0,
397 .enable = s5pv310_clk_ip_cam_ctrl, 397 .enable = exynos4_clk_ip_cam_ctrl,
398 .ctrlbit = (1 << 4), 398 .ctrlbit = (1 << 4),
399 }, { 399 }, {
400 .name = "csis", 400 .name = "csis",
401 .id = 1, 401 .id = 1,
402 .enable = s5pv310_clk_ip_cam_ctrl, 402 .enable = exynos4_clk_ip_cam_ctrl,
403 .ctrlbit = (1 << 5), 403 .ctrlbit = (1 << 5),
404 }, { 404 }, {
405 .name = "fimc", 405 .name = "fimc",
406 .id = 0, 406 .id = 0,
407 .enable = s5pv310_clk_ip_cam_ctrl, 407 .enable = exynos4_clk_ip_cam_ctrl,
408 .ctrlbit = (1 << 0), 408 .ctrlbit = (1 << 0),
409 }, { 409 }, {
410 .name = "fimc", 410 .name = "fimc",
411 .id = 1, 411 .id = 1,
412 .enable = s5pv310_clk_ip_cam_ctrl, 412 .enable = exynos4_clk_ip_cam_ctrl,
413 .ctrlbit = (1 << 1), 413 .ctrlbit = (1 << 1),
414 }, { 414 }, {
415 .name = "fimc", 415 .name = "fimc",
416 .id = 2, 416 .id = 2,
417 .enable = s5pv310_clk_ip_cam_ctrl, 417 .enable = exynos4_clk_ip_cam_ctrl,
418 .ctrlbit = (1 << 2), 418 .ctrlbit = (1 << 2),
419 }, { 419 }, {
420 .name = "fimc", 420 .name = "fimc",
421 .id = 3, 421 .id = 3,
422 .enable = s5pv310_clk_ip_cam_ctrl, 422 .enable = exynos4_clk_ip_cam_ctrl,
423 .ctrlbit = (1 << 3), 423 .ctrlbit = (1 << 3),
424 }, { 424 }, {
425 .name = "fimd", 425 .name = "fimd",
426 .id = 0, 426 .id = 0,
427 .enable = s5pv310_clk_ip_lcd0_ctrl, 427 .enable = exynos4_clk_ip_lcd0_ctrl,
428 .ctrlbit = (1 << 0), 428 .ctrlbit = (1 << 0),
429 }, { 429 }, {
430 .name = "fimd", 430 .name = "fimd",
431 .id = 1, 431 .id = 1,
432 .enable = s5pv310_clk_ip_lcd1_ctrl, 432 .enable = exynos4_clk_ip_lcd1_ctrl,
433 .ctrlbit = (1 << 0), 433 .ctrlbit = (1 << 0),
434 }, { 434 }, {
435 .name = "hsmmc", 435 .name = "hsmmc",
436 .id = 0, 436 .id = 0,
437 .parent = &clk_aclk_133.clk, 437 .parent = &clk_aclk_133.clk,
438 .enable = s5pv310_clk_ip_fsys_ctrl, 438 .enable = exynos4_clk_ip_fsys_ctrl,
439 .ctrlbit = (1 << 5), 439 .ctrlbit = (1 << 5),
440 }, { 440 }, {
441 .name = "hsmmc", 441 .name = "hsmmc",
442 .id = 1, 442 .id = 1,
443 .parent = &clk_aclk_133.clk, 443 .parent = &clk_aclk_133.clk,
444 .enable = s5pv310_clk_ip_fsys_ctrl, 444 .enable = exynos4_clk_ip_fsys_ctrl,
445 .ctrlbit = (1 << 6), 445 .ctrlbit = (1 << 6),
446 }, { 446 }, {
447 .name = "hsmmc", 447 .name = "hsmmc",
448 .id = 2, 448 .id = 2,
449 .parent = &clk_aclk_133.clk, 449 .parent = &clk_aclk_133.clk,
450 .enable = s5pv310_clk_ip_fsys_ctrl, 450 .enable = exynos4_clk_ip_fsys_ctrl,
451 .ctrlbit = (1 << 7), 451 .ctrlbit = (1 << 7),
452 }, { 452 }, {
453 .name = "hsmmc", 453 .name = "hsmmc",
454 .id = 3, 454 .id = 3,
455 .parent = &clk_aclk_133.clk, 455 .parent = &clk_aclk_133.clk,
456 .enable = s5pv310_clk_ip_fsys_ctrl, 456 .enable = exynos4_clk_ip_fsys_ctrl,
457 .ctrlbit = (1 << 8), 457 .ctrlbit = (1 << 8),
458 }, { 458 }, {
459 .name = "hsmmc", 459 .name = "hsmmc",
460 .id = 4, 460 .id = 4,
461 .parent = &clk_aclk_133.clk, 461 .parent = &clk_aclk_133.clk,
462 .enable = s5pv310_clk_ip_fsys_ctrl, 462 .enable = exynos4_clk_ip_fsys_ctrl,
463 .ctrlbit = (1 << 9), 463 .ctrlbit = (1 << 9),
464 }, { 464 }, {
465 .name = "sata", 465 .name = "sata",
466 .id = -1, 466 .id = -1,
467 .enable = s5pv310_clk_ip_fsys_ctrl, 467 .enable = exynos4_clk_ip_fsys_ctrl,
468 .ctrlbit = (1 << 10), 468 .ctrlbit = (1 << 10),
469 }, { 469 }, {
470 .name = "pdma", 470 .name = "pdma",
471 .id = 0, 471 .id = 0,
472 .enable = s5pv310_clk_ip_fsys_ctrl, 472 .enable = exynos4_clk_ip_fsys_ctrl,
473 .ctrlbit = (1 << 0), 473 .ctrlbit = (1 << 0),
474 }, { 474 }, {
475 .name = "pdma", 475 .name = "pdma",
476 .id = 1, 476 .id = 1,
477 .enable = s5pv310_clk_ip_fsys_ctrl, 477 .enable = exynos4_clk_ip_fsys_ctrl,
478 .ctrlbit = (1 << 1), 478 .ctrlbit = (1 << 1),
479 }, { 479 }, {
480 .name = "adc", 480 .name = "adc",
481 .id = -1, 481 .id = -1,
482 .enable = s5pv310_clk_ip_peril_ctrl, 482 .enable = exynos4_clk_ip_peril_ctrl,
483 .ctrlbit = (1 << 15), 483 .ctrlbit = (1 << 15),
484 }, { 484 }, {
485 .name = "rtc", 485 .name = "rtc",
486 .id = -1, 486 .id = -1,
487 .enable = s5pv310_clk_ip_perir_ctrl, 487 .enable = exynos4_clk_ip_perir_ctrl,
488 .ctrlbit = (1 << 15), 488 .ctrlbit = (1 << 15),
489 }, { 489 }, {
490 .name = "watchdog", 490 .name = "watchdog",
491 .id = -1, 491 .id = -1,
492 .enable = s5pv310_clk_ip_perir_ctrl, 492 .enable = exynos4_clk_ip_perir_ctrl,
493 .ctrlbit = (1 << 14), 493 .ctrlbit = (1 << 14),
494 }, { 494 }, {
495 .name = "usbhost", 495 .name = "usbhost",
496 .id = -1, 496 .id = -1,
497 .enable = s5pv310_clk_ip_fsys_ctrl , 497 .enable = exynos4_clk_ip_fsys_ctrl ,
498 .ctrlbit = (1 << 12), 498 .ctrlbit = (1 << 12),
499 }, { 499 }, {
500 .name = "otg", 500 .name = "otg",
501 .id = -1, 501 .id = -1,
502 .enable = s5pv310_clk_ip_fsys_ctrl, 502 .enable = exynos4_clk_ip_fsys_ctrl,
503 .ctrlbit = (1 << 13), 503 .ctrlbit = (1 << 13),
504 }, { 504 }, {
505 .name = "spi", 505 .name = "spi",
506 .id = 0, 506 .id = 0,
507 .enable = s5pv310_clk_ip_peril_ctrl, 507 .enable = exynos4_clk_ip_peril_ctrl,
508 .ctrlbit = (1 << 16), 508 .ctrlbit = (1 << 16),
509 }, { 509 }, {
510 .name = "spi", 510 .name = "spi",
511 .id = 1, 511 .id = 1,
512 .enable = s5pv310_clk_ip_peril_ctrl, 512 .enable = exynos4_clk_ip_peril_ctrl,
513 .ctrlbit = (1 << 17), 513 .ctrlbit = (1 << 17),
514 }, { 514 }, {
515 .name = "spi", 515 .name = "spi",
516 .id = 2, 516 .id = 2,
517 .enable = s5pv310_clk_ip_peril_ctrl, 517 .enable = exynos4_clk_ip_peril_ctrl,
518 .ctrlbit = (1 << 18), 518 .ctrlbit = (1 << 18),
519 }, { 519 }, {
520 .name = "iis", 520 .name = "iis",
521 .id = 0, 521 .id = 0,
522 .enable = s5pv310_clk_ip_peril_ctrl, 522 .enable = exynos4_clk_ip_peril_ctrl,
523 .ctrlbit = (1 << 19), 523 .ctrlbit = (1 << 19),
524 }, { 524 }, {
525 .name = "iis", 525 .name = "iis",
526 .id = 1, 526 .id = 1,
527 .enable = s5pv310_clk_ip_peril_ctrl, 527 .enable = exynos4_clk_ip_peril_ctrl,
528 .ctrlbit = (1 << 20), 528 .ctrlbit = (1 << 20),
529 }, { 529 }, {
530 .name = "iis", 530 .name = "iis",
531 .id = 2, 531 .id = 2,
532 .enable = s5pv310_clk_ip_peril_ctrl, 532 .enable = exynos4_clk_ip_peril_ctrl,
533 .ctrlbit = (1 << 21), 533 .ctrlbit = (1 << 21),
534 }, { 534 }, {
535 .name = "ac97", 535 .name = "ac97",
536 .id = -1, 536 .id = -1,
537 .enable = s5pv310_clk_ip_peril_ctrl, 537 .enable = exynos4_clk_ip_peril_ctrl,
538 .ctrlbit = (1 << 27), 538 .ctrlbit = (1 << 27),
539 }, { 539 }, {
540 .name = "fimg2d", 540 .name = "fimg2d",
541 .id = -1, 541 .id = -1,
542 .enable = s5pv310_clk_ip_image_ctrl, 542 .enable = exynos4_clk_ip_image_ctrl,
543 .ctrlbit = (1 << 0), 543 .ctrlbit = (1 << 0),
544 }, { 544 }, {
545 .name = "i2c", 545 .name = "i2c",
546 .id = 0, 546 .id = 0,
547 .parent = &clk_aclk_100.clk, 547 .parent = &clk_aclk_100.clk,
548 .enable = s5pv310_clk_ip_peril_ctrl, 548 .enable = exynos4_clk_ip_peril_ctrl,
549 .ctrlbit = (1 << 6), 549 .ctrlbit = (1 << 6),
550 }, { 550 }, {
551 .name = "i2c", 551 .name = "i2c",
552 .id = 1, 552 .id = 1,
553 .parent = &clk_aclk_100.clk, 553 .parent = &clk_aclk_100.clk,
554 .enable = s5pv310_clk_ip_peril_ctrl, 554 .enable = exynos4_clk_ip_peril_ctrl,
555 .ctrlbit = (1 << 7), 555 .ctrlbit = (1 << 7),
556 }, { 556 }, {
557 .name = "i2c", 557 .name = "i2c",
558 .id = 2, 558 .id = 2,
559 .parent = &clk_aclk_100.clk, 559 .parent = &clk_aclk_100.clk,
560 .enable = s5pv310_clk_ip_peril_ctrl, 560 .enable = exynos4_clk_ip_peril_ctrl,
561 .ctrlbit = (1 << 8), 561 .ctrlbit = (1 << 8),
562 }, { 562 }, {
563 .name = "i2c", 563 .name = "i2c",
564 .id = 3, 564 .id = 3,
565 .parent = &clk_aclk_100.clk, 565 .parent = &clk_aclk_100.clk,
566 .enable = s5pv310_clk_ip_peril_ctrl, 566 .enable = exynos4_clk_ip_peril_ctrl,
567 .ctrlbit = (1 << 9), 567 .ctrlbit = (1 << 9),
568 }, { 568 }, {
569 .name = "i2c", 569 .name = "i2c",
570 .id = 4, 570 .id = 4,
571 .parent = &clk_aclk_100.clk, 571 .parent = &clk_aclk_100.clk,
572 .enable = s5pv310_clk_ip_peril_ctrl, 572 .enable = exynos4_clk_ip_peril_ctrl,
573 .ctrlbit = (1 << 10), 573 .ctrlbit = (1 << 10),
574 }, { 574 }, {
575 .name = "i2c", 575 .name = "i2c",
576 .id = 5, 576 .id = 5,
577 .parent = &clk_aclk_100.clk, 577 .parent = &clk_aclk_100.clk,
578 .enable = s5pv310_clk_ip_peril_ctrl, 578 .enable = exynos4_clk_ip_peril_ctrl,
579 .ctrlbit = (1 << 11), 579 .ctrlbit = (1 << 11),
580 }, { 580 }, {
581 .name = "i2c", 581 .name = "i2c",
582 .id = 6, 582 .id = 6,
583 .parent = &clk_aclk_100.clk, 583 .parent = &clk_aclk_100.clk,
584 .enable = s5pv310_clk_ip_peril_ctrl, 584 .enable = exynos4_clk_ip_peril_ctrl,
585 .ctrlbit = (1 << 12), 585 .ctrlbit = (1 << 12),
586 }, { 586 }, {
587 .name = "i2c", 587 .name = "i2c",
588 .id = 7, 588 .id = 7,
589 .parent = &clk_aclk_100.clk, 589 .parent = &clk_aclk_100.clk,
590 .enable = s5pv310_clk_ip_peril_ctrl, 590 .enable = exynos4_clk_ip_peril_ctrl,
591 .ctrlbit = (1 << 13), 591 .ctrlbit = (1 << 13),
592 }, 592 },
593}; 593};
@@ -596,32 +596,32 @@ static struct clk init_clocks[] = {
596 { 596 {
597 .name = "uart", 597 .name = "uart",
598 .id = 0, 598 .id = 0,
599 .enable = s5pv310_clk_ip_peril_ctrl, 599 .enable = exynos4_clk_ip_peril_ctrl,
600 .ctrlbit = (1 << 0), 600 .ctrlbit = (1 << 0),
601 }, { 601 }, {
602 .name = "uart", 602 .name = "uart",
603 .id = 1, 603 .id = 1,
604 .enable = s5pv310_clk_ip_peril_ctrl, 604 .enable = exynos4_clk_ip_peril_ctrl,
605 .ctrlbit = (1 << 1), 605 .ctrlbit = (1 << 1),
606 }, { 606 }, {
607 .name = "uart", 607 .name = "uart",
608 .id = 2, 608 .id = 2,
609 .enable = s5pv310_clk_ip_peril_ctrl, 609 .enable = exynos4_clk_ip_peril_ctrl,
610 .ctrlbit = (1 << 2), 610 .ctrlbit = (1 << 2),
611 }, { 611 }, {
612 .name = "uart", 612 .name = "uart",
613 .id = 3, 613 .id = 3,
614 .enable = s5pv310_clk_ip_peril_ctrl, 614 .enable = exynos4_clk_ip_peril_ctrl,
615 .ctrlbit = (1 << 3), 615 .ctrlbit = (1 << 3),
616 }, { 616 }, {
617 .name = "uart", 617 .name = "uart",
618 .id = 4, 618 .id = 4,
619 .enable = s5pv310_clk_ip_peril_ctrl, 619 .enable = exynos4_clk_ip_peril_ctrl,
620 .ctrlbit = (1 << 4), 620 .ctrlbit = (1 << 4),
621 }, { 621 }, {
622 .name = "uart", 622 .name = "uart",
623 .id = 5, 623 .id = 5,
624 .enable = s5pv310_clk_ip_peril_ctrl, 624 .enable = exynos4_clk_ip_peril_ctrl,
625 .ctrlbit = (1 << 5), 625 .ctrlbit = (1 << 5),
626 } 626 }
627}; 627};
@@ -746,7 +746,7 @@ static struct clksrc_clk clksrcs[] = {
746 .clk = { 746 .clk = {
747 .name = "uclk1", 747 .name = "uclk1",
748 .id = 0, 748 .id = 0,
749 .enable = s5pv310_clksrc_mask_peril0_ctrl, 749 .enable = exynos4_clksrc_mask_peril0_ctrl,
750 .ctrlbit = (1 << 0), 750 .ctrlbit = (1 << 0),
751 }, 751 },
752 .sources = &clkset_group, 752 .sources = &clkset_group,
@@ -756,7 +756,7 @@ static struct clksrc_clk clksrcs[] = {
756 .clk = { 756 .clk = {
757 .name = "uclk1", 757 .name = "uclk1",
758 .id = 1, 758 .id = 1,
759 .enable = s5pv310_clksrc_mask_peril0_ctrl, 759 .enable = exynos4_clksrc_mask_peril0_ctrl,
760 .ctrlbit = (1 << 4), 760 .ctrlbit = (1 << 4),
761 }, 761 },
762 .sources = &clkset_group, 762 .sources = &clkset_group,
@@ -766,7 +766,7 @@ static struct clksrc_clk clksrcs[] = {
766 .clk = { 766 .clk = {
767 .name = "uclk1", 767 .name = "uclk1",
768 .id = 2, 768 .id = 2,
769 .enable = s5pv310_clksrc_mask_peril0_ctrl, 769 .enable = exynos4_clksrc_mask_peril0_ctrl,
770 .ctrlbit = (1 << 8), 770 .ctrlbit = (1 << 8),
771 }, 771 },
772 .sources = &clkset_group, 772 .sources = &clkset_group,
@@ -776,7 +776,7 @@ static struct clksrc_clk clksrcs[] = {
776 .clk = { 776 .clk = {
777 .name = "uclk1", 777 .name = "uclk1",
778 .id = 3, 778 .id = 3,
779 .enable = s5pv310_clksrc_mask_peril0_ctrl, 779 .enable = exynos4_clksrc_mask_peril0_ctrl,
780 .ctrlbit = (1 << 12), 780 .ctrlbit = (1 << 12),
781 }, 781 },
782 .sources = &clkset_group, 782 .sources = &clkset_group,
@@ -786,7 +786,7 @@ static struct clksrc_clk clksrcs[] = {
786 .clk = { 786 .clk = {
787 .name = "sclk_pwm", 787 .name = "sclk_pwm",
788 .id = -1, 788 .id = -1,
789 .enable = s5pv310_clksrc_mask_peril0_ctrl, 789 .enable = exynos4_clksrc_mask_peril0_ctrl,
790 .ctrlbit = (1 << 24), 790 .ctrlbit = (1 << 24),
791 }, 791 },
792 .sources = &clkset_group, 792 .sources = &clkset_group,
@@ -796,7 +796,7 @@ static struct clksrc_clk clksrcs[] = {
796 .clk = { 796 .clk = {
797 .name = "sclk_csis", 797 .name = "sclk_csis",
798 .id = 0, 798 .id = 0,
799 .enable = s5pv310_clksrc_mask_cam_ctrl, 799 .enable = exynos4_clksrc_mask_cam_ctrl,
800 .ctrlbit = (1 << 24), 800 .ctrlbit = (1 << 24),
801 }, 801 },
802 .sources = &clkset_group, 802 .sources = &clkset_group,
@@ -806,7 +806,7 @@ static struct clksrc_clk clksrcs[] = {
806 .clk = { 806 .clk = {
807 .name = "sclk_csis", 807 .name = "sclk_csis",
808 .id = 1, 808 .id = 1,
809 .enable = s5pv310_clksrc_mask_cam_ctrl, 809 .enable = exynos4_clksrc_mask_cam_ctrl,
810 .ctrlbit = (1 << 28), 810 .ctrlbit = (1 << 28),
811 }, 811 },
812 .sources = &clkset_group, 812 .sources = &clkset_group,
@@ -816,7 +816,7 @@ static struct clksrc_clk clksrcs[] = {
816 .clk = { 816 .clk = {
817 .name = "sclk_cam", 817 .name = "sclk_cam",
818 .id = 0, 818 .id = 0,
819 .enable = s5pv310_clksrc_mask_cam_ctrl, 819 .enable = exynos4_clksrc_mask_cam_ctrl,
820 .ctrlbit = (1 << 16), 820 .ctrlbit = (1 << 16),
821 }, 821 },
822 .sources = &clkset_group, 822 .sources = &clkset_group,
@@ -826,7 +826,7 @@ static struct clksrc_clk clksrcs[] = {
826 .clk = { 826 .clk = {
827 .name = "sclk_cam", 827 .name = "sclk_cam",
828 .id = 1, 828 .id = 1,
829 .enable = s5pv310_clksrc_mask_cam_ctrl, 829 .enable = exynos4_clksrc_mask_cam_ctrl,
830 .ctrlbit = (1 << 20), 830 .ctrlbit = (1 << 20),
831 }, 831 },
832 .sources = &clkset_group, 832 .sources = &clkset_group,
@@ -836,7 +836,7 @@ static struct clksrc_clk clksrcs[] = {
836 .clk = { 836 .clk = {
837 .name = "sclk_fimc", 837 .name = "sclk_fimc",
838 .id = 0, 838 .id = 0,
839 .enable = s5pv310_clksrc_mask_cam_ctrl, 839 .enable = exynos4_clksrc_mask_cam_ctrl,
840 .ctrlbit = (1 << 0), 840 .ctrlbit = (1 << 0),
841 }, 841 },
842 .sources = &clkset_group, 842 .sources = &clkset_group,
@@ -846,7 +846,7 @@ static struct clksrc_clk clksrcs[] = {
846 .clk = { 846 .clk = {
847 .name = "sclk_fimc", 847 .name = "sclk_fimc",
848 .id = 1, 848 .id = 1,
849 .enable = s5pv310_clksrc_mask_cam_ctrl, 849 .enable = exynos4_clksrc_mask_cam_ctrl,
850 .ctrlbit = (1 << 4), 850 .ctrlbit = (1 << 4),
851 }, 851 },
852 .sources = &clkset_group, 852 .sources = &clkset_group,
@@ -856,7 +856,7 @@ static struct clksrc_clk clksrcs[] = {
856 .clk = { 856 .clk = {
857 .name = "sclk_fimc", 857 .name = "sclk_fimc",
858 .id = 2, 858 .id = 2,
859 .enable = s5pv310_clksrc_mask_cam_ctrl, 859 .enable = exynos4_clksrc_mask_cam_ctrl,
860 .ctrlbit = (1 << 8), 860 .ctrlbit = (1 << 8),
861 }, 861 },
862 .sources = &clkset_group, 862 .sources = &clkset_group,
@@ -866,7 +866,7 @@ static struct clksrc_clk clksrcs[] = {
866 .clk = { 866 .clk = {
867 .name = "sclk_fimc", 867 .name = "sclk_fimc",
868 .id = 3, 868 .id = 3,
869 .enable = s5pv310_clksrc_mask_cam_ctrl, 869 .enable = exynos4_clksrc_mask_cam_ctrl,
870 .ctrlbit = (1 << 12), 870 .ctrlbit = (1 << 12),
871 }, 871 },
872 .sources = &clkset_group, 872 .sources = &clkset_group,
@@ -876,7 +876,7 @@ static struct clksrc_clk clksrcs[] = {
876 .clk = { 876 .clk = {
877 .name = "sclk_fimd", 877 .name = "sclk_fimd",
878 .id = 0, 878 .id = 0,
879 .enable = s5pv310_clksrc_mask_lcd0_ctrl, 879 .enable = exynos4_clksrc_mask_lcd0_ctrl,
880 .ctrlbit = (1 << 0), 880 .ctrlbit = (1 << 0),
881 }, 881 },
882 .sources = &clkset_group, 882 .sources = &clkset_group,
@@ -886,7 +886,7 @@ static struct clksrc_clk clksrcs[] = {
886 .clk = { 886 .clk = {
887 .name = "sclk_fimd", 887 .name = "sclk_fimd",
888 .id = 1, 888 .id = 1,
889 .enable = s5pv310_clksrc_mask_lcd1_ctrl, 889 .enable = exynos4_clksrc_mask_lcd1_ctrl,
890 .ctrlbit = (1 << 0), 890 .ctrlbit = (1 << 0),
891 }, 891 },
892 .sources = &clkset_group, 892 .sources = &clkset_group,
@@ -896,7 +896,7 @@ static struct clksrc_clk clksrcs[] = {
896 .clk = { 896 .clk = {
897 .name = "sclk_sata", 897 .name = "sclk_sata",
898 .id = -1, 898 .id = -1,
899 .enable = s5pv310_clksrc_mask_fsys_ctrl, 899 .enable = exynos4_clksrc_mask_fsys_ctrl,
900 .ctrlbit = (1 << 24), 900 .ctrlbit = (1 << 24),
901 }, 901 },
902 .sources = &clkset_mout_corebus, 902 .sources = &clkset_mout_corebus,
@@ -906,7 +906,7 @@ static struct clksrc_clk clksrcs[] = {
906 .clk = { 906 .clk = {
907 .name = "sclk_spi", 907 .name = "sclk_spi",
908 .id = 0, 908 .id = 0,
909 .enable = s5pv310_clksrc_mask_peril1_ctrl, 909 .enable = exynos4_clksrc_mask_peril1_ctrl,
910 .ctrlbit = (1 << 16), 910 .ctrlbit = (1 << 16),
911 }, 911 },
912 .sources = &clkset_group, 912 .sources = &clkset_group,
@@ -916,7 +916,7 @@ static struct clksrc_clk clksrcs[] = {
916 .clk = { 916 .clk = {
917 .name = "sclk_spi", 917 .name = "sclk_spi",
918 .id = 1, 918 .id = 1,
919 .enable = s5pv310_clksrc_mask_peril1_ctrl, 919 .enable = exynos4_clksrc_mask_peril1_ctrl,
920 .ctrlbit = (1 << 20), 920 .ctrlbit = (1 << 20),
921 }, 921 },
922 .sources = &clkset_group, 922 .sources = &clkset_group,
@@ -926,7 +926,7 @@ static struct clksrc_clk clksrcs[] = {
926 .clk = { 926 .clk = {
927 .name = "sclk_spi", 927 .name = "sclk_spi",
928 .id = 2, 928 .id = 2,
929 .enable = s5pv310_clksrc_mask_peril1_ctrl, 929 .enable = exynos4_clksrc_mask_peril1_ctrl,
930 .ctrlbit = (1 << 24), 930 .ctrlbit = (1 << 24),
931 }, 931 },
932 .sources = &clkset_group, 932 .sources = &clkset_group,
@@ -945,7 +945,7 @@ static struct clksrc_clk clksrcs[] = {
945 .name = "sclk_mmc", 945 .name = "sclk_mmc",
946 .id = 0, 946 .id = 0,
947 .parent = &clk_dout_mmc0.clk, 947 .parent = &clk_dout_mmc0.clk,
948 .enable = s5pv310_clksrc_mask_fsys_ctrl, 948 .enable = exynos4_clksrc_mask_fsys_ctrl,
949 .ctrlbit = (1 << 0), 949 .ctrlbit = (1 << 0),
950 }, 950 },
951 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, 951 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
@@ -954,7 +954,7 @@ static struct clksrc_clk clksrcs[] = {
954 .name = "sclk_mmc", 954 .name = "sclk_mmc",
955 .id = 1, 955 .id = 1,
956 .parent = &clk_dout_mmc1.clk, 956 .parent = &clk_dout_mmc1.clk,
957 .enable = s5pv310_clksrc_mask_fsys_ctrl, 957 .enable = exynos4_clksrc_mask_fsys_ctrl,
958 .ctrlbit = (1 << 4), 958 .ctrlbit = (1 << 4),
959 }, 959 },
960 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, 960 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
@@ -963,7 +963,7 @@ static struct clksrc_clk clksrcs[] = {
963 .name = "sclk_mmc", 963 .name = "sclk_mmc",
964 .id = 2, 964 .id = 2,
965 .parent = &clk_dout_mmc2.clk, 965 .parent = &clk_dout_mmc2.clk,
966 .enable = s5pv310_clksrc_mask_fsys_ctrl, 966 .enable = exynos4_clksrc_mask_fsys_ctrl,
967 .ctrlbit = (1 << 8), 967 .ctrlbit = (1 << 8),
968 }, 968 },
969 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, 969 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
@@ -972,7 +972,7 @@ static struct clksrc_clk clksrcs[] = {
972 .name = "sclk_mmc", 972 .name = "sclk_mmc",
973 .id = 3, 973 .id = 3,
974 .parent = &clk_dout_mmc3.clk, 974 .parent = &clk_dout_mmc3.clk,
975 .enable = s5pv310_clksrc_mask_fsys_ctrl, 975 .enable = exynos4_clksrc_mask_fsys_ctrl,
976 .ctrlbit = (1 << 12), 976 .ctrlbit = (1 << 12),
977 }, 977 },
978 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, 978 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
@@ -981,7 +981,7 @@ static struct clksrc_clk clksrcs[] = {
981 .name = "sclk_mmc", 981 .name = "sclk_mmc",
982 .id = 4, 982 .id = 4,
983 .parent = &clk_dout_mmc4.clk, 983 .parent = &clk_dout_mmc4.clk,
984 .enable = s5pv310_clksrc_mask_fsys_ctrl, 984 .enable = exynos4_clksrc_mask_fsys_ctrl,
985 .ctrlbit = (1 << 16), 985 .ctrlbit = (1 << 16),
986 }, 986 },
987 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 }, 987 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
@@ -1022,16 +1022,16 @@ static struct clksrc_clk *sysclks[] = {
1022 1022
1023static int xtal_rate; 1023static int xtal_rate;
1024 1024
1025static unsigned long s5pv310_fout_apll_get_rate(struct clk *clk) 1025static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1026{ 1026{
1027 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508); 1027 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
1028} 1028}
1029 1029
1030static struct clk_ops s5pv310_fout_apll_ops = { 1030static struct clk_ops exynos4_fout_apll_ops = {
1031 .get_rate = s5pv310_fout_apll_get_rate, 1031 .get_rate = exynos4_fout_apll_get_rate,
1032}; 1032};
1033 1033
1034void __init_or_cpufreq s5pv310_setup_clocks(void) 1034void __init_or_cpufreq exynos4_setup_clocks(void)
1035{ 1035{
1036 struct clk *xtal_clk; 1036 struct clk *xtal_clk;
1037 unsigned long apll; 1037 unsigned long apll;
@@ -1070,12 +1070,12 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
1070 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), 1070 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1071 __raw_readl(S5P_VPLL_CON1), pll_4650); 1071 __raw_readl(S5P_VPLL_CON1), pll_4650);
1072 1072
1073 clk_fout_apll.ops = &s5pv310_fout_apll_ops; 1073 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1074 clk_fout_mpll.rate = mpll; 1074 clk_fout_mpll.rate = mpll;
1075 clk_fout_epll.rate = epll; 1075 clk_fout_epll.rate = epll;
1076 clk_fout_vpll.rate = vpll; 1076 clk_fout_vpll.rate = vpll;
1077 1077
1078 printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", 1078 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1079 apll, mpll, epll, vpll); 1079 apll, mpll, epll, vpll);
1080 1080
1081 armclk = clk_get_rate(&clk_armclk.clk); 1081 armclk = clk_get_rate(&clk_armclk.clk);
@@ -1086,7 +1086,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
1086 aclk_160 = clk_get_rate(&clk_aclk_160.clk); 1086 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1087 aclk_133 = clk_get_rate(&clk_aclk_133.clk); 1087 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1088 1088
1089 printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n" 1089 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1090 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n", 1090 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1091 armclk, sclk_dmc, aclk_200, 1091 armclk, sclk_dmc, aclk_200,
1092 aclk_100, aclk_160, aclk_133); 1092 aclk_100, aclk_160, aclk_133);
@@ -1103,7 +1103,7 @@ static struct clk *clks[] __initdata = {
1103 /* Nothing here yet */ 1103 /* Nothing here yet */
1104}; 1104};
1105 1105
1106void __init s5pv310_register_clocks(void) 1106void __init exynos4_register_clocks(void)
1107{ 1107{
1108 int ptr; 1108 int ptr;
1109 1109
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index b5c4ada1cff5..ba8f91c04e19 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h 1/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Clock register definitions 6 * EXYNOS4 - Clock register definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 05:50:10 -0500