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authorRanjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>2014-02-27 13:32:42 -0500
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:57:53 -0400
commitaf533c2b301980abf1eee1311fa76b1cd2f70cf2 (patch)
tree2cb19b2716eb500c723bb18e5b9324d01db0f794
parent375bef227558169e2abb0819b9b857920cb6d8af (diff)
ENGR00301394 ARM:dts:imx6sx:Add support for imx6sx-19x19-arm2 board support
Add dts files to support iMX6SX 19x19 ddr3 validation board. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/imx6sx-19x19-arm2.dts169
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi12
3 files changed, 182 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 239ebf8cfe63..ecb8219f16d4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -135,6 +135,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
135 imx6sl-evk-csi.dtb \ 135 imx6sl-evk-csi.dtb \
136 imx6sl-evk-ldo.dtb \ 136 imx6sl-evk-ldo.dtb \
137 imx6sx-17x17-arm2.dtb \ 137 imx6sx-17x17-arm2.dtb \
138 imx6sx-19x19-arm2.dtb \
138 imx6sx-sdb.dtb \ 139 imx6sx-sdb.dtb \
139 vf610-twr.dtb 140 vf610-twr.dtb
140dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ 141dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
diff --git a/arch/arm/boot/dts/imx6sx-19x19-arm2.dts b/arch/arm/boot/dts/imx6sx-19x19-arm2.dts
new file mode 100644
index 000000000000..a1bd7e0ebdd5
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-19x19-arm2.dts
@@ -0,0 +1,169 @@
1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include "imx6sx.dtsi"
12
13/ {
14 model = "Freescale i.MX6 SoloX 19x19 ARM2 Board";
15 compatible = "fsl,imx6sx-19x19-arm2", "fsl,imx6sx";
16
17 backlight {
18 compatible = "pwm-backlight";
19 pwms = <&pwm3 0 5000000>;
20 brightness-levels = <0 4 8 16 32 64 128 255>;
21 default-brightness-level = <6>;
22 };
23
24 max7322_reset: max7322-reset {
25 compatible = "gpio-reset";
26 reset-gpios = <&gpio6 18 GPIO_ACTIVE_LOW>;
27 reset-delay-us = <1>;
28 #reset-cells = <0>;
29 };
30
31 pxp_v4l2_out {
32 compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
33 status = "disabled";
34 };
35
36 memory {
37 reg = <0x80000000 0x40000000>;
38 };
39};
40
41&fec1 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_enet1_1>;
44 phy-mode = "rgmii";
45 fsl,num_tx_queues=<3>;
46 fsl,num_rx_queues=<3>;
47 pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>;
48 status = "okay";
49};
50
51&fec2 {
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_enet2_1>;
54 phy-mode = "rgmii";
55 fsl,num_tx_queues=<3>;
56 fsl,num_rx_queues=<3>;
57 status = "disabled";
58};
59
60&gpc {
61 fsl,cpu_pupscr_sw2iso = <0xf>;
62 fsl,cpu_pupscr_sw = <0xf>;
63 fsl,cpu_pdnscr_iso2sw = <0x1>;
64 fsl,cpu_pdnscr_iso = <0x1>;
65 fsl,wdog-reset = <1>; /* watchdog select of reset source */
66};
67
68&i2c1 {
69 clock-frequency = <100000>;
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_i2c1_1>;
72 status = "okay";
73};
74
75&i2c2 {
76 clock-frequency = <100000>;
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_i2c2_1>;
79 status = "okay";
80
81 max7322: gpio@68 {
82 compatible = "maxim,max7322";
83 reg = <0x68>;
84 gpio-controller;
85 #gpio-cells = <2>;
86 resets = <&max7322_reset>;
87 };
88};
89
90&i2c3 {
91 clock-frequency = <100000>;
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_i2c3_1>;
94 status = "okay";
95};
96
97&i2c4 {
98 clock-frequency = <100000>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_i2c4_1>;
101 status = "okay";
102};
103
104&iomuxc {
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_hog_1>;
107
108 hog {
109 pinctrl_hog_1: hoggrp-1 {
110 fsl,pins = <
111 MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x1b0b0
112 >;
113 };
114 };
115};
116
117&pwm3 {
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_pwm3_0>;
120 status = "disabled";
121};
122
123&pxp {
124 status = "disabled";
125};
126
127&uart1 {
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_uart1_1>;
130 status = "okay";
131};
132
133&uart2 {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_uart2_1>;
136 status = "okay";
137};
138
139&qspi2 {
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_qspi2_1>;
142 status = "okay";
143
144 flash0: n25q256a@0 {
145 #address-cells = <1>;
146 #size-cells = <1>;
147 compatible = "micron,n25q256a";
148 spi-max-frequency = <53000000>;
149 reg = <0>;
150 };
151
152 flash1: n25q256a@1 {
153 #address-cells = <1>;
154 #size-cells = <1>;
155 compatible = "micron,n25q256a";
156 spi-max-frequency = <53000000>;
157 reg = <1>;
158 };
159};
160
161&usdhc1 {
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_usdhc1_1>;
164 bus-width = <4>;
165 keep-power-in-suspend;
166 enable-sdio-wakeup;
167 no-1-8-v;
168 status = "okay";
169};
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 0098877cf1d5..0d62756cc3d9 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -1069,6 +1069,18 @@
1069 MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059 1069 MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059
1070 >; 1070 >;
1071 }; 1071 };
1072
1073 usdhc1 {
1074 pinctrl_usdhc1_1: usdhc1grp-1 {
1075 fsl,pins = <
1076 MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059
1077 MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059
1078 MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
1079 MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
1080 MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
1081 MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
1082 >;
1083 };
1072 }; 1084 };
1073 1085
1074 usdhc2 { 1086 usdhc2 {