diff options
author | Josh Wu <josh.wu@atmel.com> | 2012-06-29 05:47:54 -0400 |
---|---|---|
committer | David Woodhouse <David.Woodhouse@intel.com> | 2012-07-06 13:21:09 -0400 |
commit | a41b51a1f7c15a1b00f30a3ad2d0373ad51b883d (patch) | |
tree | 790b3b90ac66aa8dca295f3ec45ea49b05f3de6a | |
parent | fae255253b393d5e4f0d77d5afa103bfc8b47a97 (diff) |
mtd: at91: add dt parameters for Atmel PMECC
Add DT support for PMECC parameters.
Signed-off-by: Hong Xu <hong.xu@atmel.com>
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
-rw-r--r-- | Documentation/devicetree/bindings/mtd/atmel-nand.txt | 40 | ||||
-rw-r--r-- | drivers/mtd/nand/atmel_nand.c | 52 |
2 files changed, 90 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt index a20069502f5a..d555421ea49f 100644 --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt | |||
@@ -3,7 +3,9 @@ Atmel NAND flash | |||
3 | Required properties: | 3 | Required properties: |
4 | - compatible : "atmel,at91rm9200-nand". | 4 | - compatible : "atmel,at91rm9200-nand". |
5 | - reg : should specify localbus address and size used for the chip, | 5 | - reg : should specify localbus address and size used for the chip, |
6 | and if availlable the ECC. | 6 | and hardware ECC controller if available. |
7 | If the hardware ECC is PMECC, it should contain address and size for | ||
8 | PMECC, PMECC Error Location controller and ROM which has lookup tables. | ||
7 | - atmel,nand-addr-offset : offset for the address latch. | 9 | - atmel,nand-addr-offset : offset for the address latch. |
8 | - atmel,nand-cmd-offset : offset for the command latch. | 10 | - atmel,nand-cmd-offset : offset for the command latch. |
9 | - #address-cells, #size-cells : Must be present if the device has sub-nodes | 11 | - #address-cells, #size-cells : Must be present if the device has sub-nodes |
@@ -16,6 +18,15 @@ Optional properties: | |||
16 | - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default. | 18 | - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default. |
17 | Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first", | 19 | Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first", |
18 | "soft_bch". | 20 | "soft_bch". |
21 | - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware. | ||
22 | Only supported by at91sam9x5 or later sam9 product. | ||
23 | - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC | ||
24 | Controller. Supported values are: 2, 4, 8, 12, 24. | ||
25 | - atmel,pmecc-sector-size : sector size for ECC computation. Supported values | ||
26 | are: 512, 1024. | ||
27 | - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM | ||
28 | for different sector size. First one is for sector size 512, the next is for | ||
29 | sector size 1024. | ||
19 | - nand-bus-width : 8 or 16 bus width if not present 8 | 30 | - nand-bus-width : 8 or 16 bus width if not present 8 |
20 | - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false | 31 | - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false |
21 | 32 | ||
@@ -39,3 +50,30 @@ nand0: nand@40000000,0 { | |||
39 | ... | 50 | ... |
40 | }; | 51 | }; |
41 | }; | 52 | }; |
53 | |||
54 | /* for PMECC supported chips */ | ||
55 | nand0: nand@40000000 { | ||
56 | compatible = "atmel,at91rm9200-nand"; | ||
57 | #address-cells = <1>; | ||
58 | #size-cells = <1>; | ||
59 | reg = < 0x40000000 0x10000000 /* bus addr & size */ | ||
60 | 0xffffe000 0x00000600 /* PMECC addr & size */ | ||
61 | 0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */ | ||
62 | 0x00100000 0x00100000 /* ROM addr & size */ | ||
63 | >; | ||
64 | atmel,nand-addr-offset = <21>; /* ale */ | ||
65 | atmel,nand-cmd-offset = <22>; /* cle */ | ||
66 | nand-on-flash-bbt; | ||
67 | nand-ecc-mode = "hw"; | ||
68 | atmel,has-pmecc; /* enable PMECC */ | ||
69 | atmel,pmecc-cap = <2>; | ||
70 | atmel,pmecc-sector-size = <512>; | ||
71 | atmel,pmecc-lookup-table-offset = <0x8000 0x10000>; | ||
72 | gpios = <&pioD 5 0 /* rdy */ | ||
73 | &pioD 4 0 /* nce */ | ||
74 | 0 /* cd */ | ||
75 | >; | ||
76 | partition@0 { | ||
77 | ... | ||
78 | }; | ||
79 | }; | ||
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 7a41a04beb87..b97ad9f78d39 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c | |||
@@ -93,6 +93,11 @@ struct atmel_nand_host { | |||
93 | 93 | ||
94 | struct completion comp; | 94 | struct completion comp; |
95 | struct dma_chan *dma_chan; | 95 | struct dma_chan *dma_chan; |
96 | |||
97 | bool has_pmecc; | ||
98 | u8 pmecc_corr_cap; | ||
99 | u16 pmecc_sector_size; | ||
100 | u32 pmecc_lookup_table_offset; | ||
96 | }; | 101 | }; |
97 | 102 | ||
98 | static int cpu_has_dma(void) | 103 | static int cpu_has_dma(void) |
@@ -481,7 +486,8 @@ static void atmel_nand_hwctl(struct mtd_info *mtd, int mode) | |||
481 | static int __devinit atmel_of_init_port(struct atmel_nand_host *host, | 486 | static int __devinit atmel_of_init_port(struct atmel_nand_host *host, |
482 | struct device_node *np) | 487 | struct device_node *np) |
483 | { | 488 | { |
484 | u32 val; | 489 | u32 val, table_offset; |
490 | u32 offset[2]; | ||
485 | int ecc_mode; | 491 | int ecc_mode; |
486 | struct atmel_nand_data *board = &host->board; | 492 | struct atmel_nand_data *board = &host->board; |
487 | enum of_gpio_flags flags; | 493 | enum of_gpio_flags flags; |
@@ -517,6 +523,50 @@ static int __devinit atmel_of_init_port(struct atmel_nand_host *host, | |||
517 | board->enable_pin = of_get_gpio(np, 1); | 523 | board->enable_pin = of_get_gpio(np, 1); |
518 | board->det_pin = of_get_gpio(np, 2); | 524 | board->det_pin = of_get_gpio(np, 2); |
519 | 525 | ||
526 | host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc"); | ||
527 | |||
528 | if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc) | ||
529 | return 0; /* Not using PMECC */ | ||
530 | |||
531 | /* use PMECC, get correction capability, sector size and lookup | ||
532 | * table offset. | ||
533 | */ | ||
534 | if (of_property_read_u32(np, "atmel,pmecc-cap", &val) != 0) { | ||
535 | dev_err(host->dev, "Cannot decide PMECC Capability\n"); | ||
536 | return -EINVAL; | ||
537 | } else if ((val != 2) && (val != 4) && (val != 8) && (val != 12) && | ||
538 | (val != 24)) { | ||
539 | dev_err(host->dev, | ||
540 | "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n", | ||
541 | val); | ||
542 | return -EINVAL; | ||
543 | } | ||
544 | host->pmecc_corr_cap = (u8)val; | ||
545 | |||
546 | if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) != 0) { | ||
547 | dev_err(host->dev, "Cannot decide PMECC Sector Size\n"); | ||
548 | return -EINVAL; | ||
549 | } else if ((val != 512) && (val != 1024)) { | ||
550 | dev_err(host->dev, | ||
551 | "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n", | ||
552 | val); | ||
553 | return -EINVAL; | ||
554 | } | ||
555 | host->pmecc_sector_size = (u16)val; | ||
556 | |||
557 | if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset", | ||
558 | offset, 2) != 0) { | ||
559 | dev_err(host->dev, "Cannot get PMECC lookup table offset\n"); | ||
560 | return -EINVAL; | ||
561 | } | ||
562 | table_offset = host->pmecc_sector_size == 512 ? offset[0] : offset[1]; | ||
563 | |||
564 | if (!table_offset) { | ||
565 | dev_err(host->dev, "Invalid PMECC lookup table offset\n"); | ||
566 | return -EINVAL; | ||
567 | } | ||
568 | host->pmecc_lookup_table_offset = table_offset; | ||
569 | |||
520 | return 0; | 570 | return 0; |
521 | } | 571 | } |
522 | #else | 572 | #else |