diff options
author | Simon Horman <horms@verge.net.au> | 2011-06-20 19:00:08 -0400 |
---|---|---|
committer | Chris Ball <cjb@laptop.org> | 2011-07-20 17:20:55 -0400 |
commit | 95c7348d948dc4832434ddfaeba804ac14732f02 (patch) | |
tree | f1795c7d0ad42672d0884430f070f2cdaeed07f2 | |
parent | 4c2b8f26eb8b54203e0e7834e0f7a11a7ae15ef1 (diff) |
mmc: tmio: name 0xd8 as CTL_DMA_ENABLE
This reflects at least the current usage of this register
and I think it improves the readability of the code ever so slightly.
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Cc: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
Signed-off-by: Chris Ball <cjb@laptop.org>
-rw-r--r-- | drivers/mmc/host/tmio_mmc_dma.c | 2 | ||||
-rw-r--r-- | include/linux/mmc/tmio.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/drivers/mmc/host/tmio_mmc_dma.c b/drivers/mmc/host/tmio_mmc_dma.c index 25f1ad6cbe09..9c4da6637503 100644 --- a/drivers/mmc/host/tmio_mmc_dma.c +++ b/drivers/mmc/host/tmio_mmc_dma.c | |||
@@ -26,7 +26,7 @@ static void tmio_mmc_enable_dma(struct tmio_mmc_host *host, bool enable) | |||
26 | { | 26 | { |
27 | #if defined(CONFIG_SUPERH) || defined(CONFIG_ARCH_SHMOBILE) | 27 | #if defined(CONFIG_SUPERH) || defined(CONFIG_ARCH_SHMOBILE) |
28 | /* Switch DMA mode on or off - SuperH specific? */ | 28 | /* Switch DMA mode on or off - SuperH specific? */ |
29 | writew(enable ? 2 : 0, host->ctl + (0xd8 << host->bus_shift)); | 29 | writew(enable ? 2 : 0, host->ctl + (CTL_DMA_ENABLE << host->bus_shift)); |
30 | #endif | 30 | #endif |
31 | } | 31 | } |
32 | 32 | ||
diff --git a/include/linux/mmc/tmio.h b/include/linux/mmc/tmio.h index 551490f0613d..3ae377623db0 100644 --- a/include/linux/mmc/tmio.h +++ b/include/linux/mmc/tmio.h | |||
@@ -30,6 +30,7 @@ | |||
30 | #define CTL_TRANSACTION_CTL 0x34 | 30 | #define CTL_TRANSACTION_CTL 0x34 |
31 | #define CTL_SDIO_STATUS 0x36 | 31 | #define CTL_SDIO_STATUS 0x36 |
32 | #define CTL_SDIO_IRQ_MASK 0x38 | 32 | #define CTL_SDIO_IRQ_MASK 0x38 |
33 | #define CTL_DMA_ENABLE 0xd8 | ||
33 | #define CTL_RESET_SD 0xe0 | 34 | #define CTL_RESET_SD 0xe0 |
34 | #define CTL_SDIO_REGS 0x100 | 35 | #define CTL_SDIO_REGS 0x100 |
35 | #define CTL_CLK_AND_WAIT_CTL 0x138 | 36 | #define CTL_CLK_AND_WAIT_CTL 0x138 |