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authorTony Lindgren <tony@atomide.com>2012-10-16 17:54:19 -0400
committerTony Lindgren <tony@atomide.com>2012-10-16 17:54:19 -0400
commit94709014ea8d2f24fbc1e6eb6982e801e325bd47 (patch)
treea99f2f7184d414d44fccb648a71565cab2c670b3
parentddffeb8c4d0331609ef2581d84de4d763607bd37 (diff)
parent3ef5d0071cf6c8b9a00b559232bb700ad59999d7 (diff)
Merge tag 'gpmc-czimage' of git://gitorious.org/x0148406-public/linux-kernel into omap-for-v3.8/cleanup-headers-gpmc
gpmc cleanup for common ARM zImage
Diffstat
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c2
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c2
-rw-r--r--arch/arm/mach-omap2/board-apollon.c2
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c5
-rw-r--r--arch/arm/mach-omap2/board-cm-t3517.c5
-rw-r--r--arch/arm/mach-omap2/board-devkit8000.c10
-rw-r--r--arch/arm/mach-omap2/board-flash.c50
-rw-r--r--arch/arm/mach-omap2/board-flash.h8
-rw-r--r--arch/arm/mach-omap2/board-h4.c2
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c5
-rw-r--r--arch/arm/mach-omap2/board-ldp.c6
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c1
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c10
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c8
-rw-r--r--arch/arm/mach-omap2/board-omap3logic.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c3
-rw-r--r--arch/arm/mach-omap2/board-omap3stalker.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3touchbook.c10
-rw-r--r--arch/arm/mach-omap2/board-overo.c9
-rw-r--r--arch/arm/mach-omap2/board-rm680.c3
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c3
-rw-r--r--arch/arm/mach-omap2/board-rx51.c2
-rw-r--r--arch/arm/mach-omap2/board-zoom-debugboard.c2
-rw-r--r--arch/arm/mach-omap2/board-zoom.c5
-rw-r--r--arch/arm/mach-omap2/common-board-devices.c46
-rw-r--r--arch/arm/mach-omap2/common-board-devices.h1
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c85
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.h27
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.c214
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.h24
-rw-r--r--arch/arm/mach-omap2/gpmc-smc91x.c2
-rw-r--r--arch/arm/mach-omap2/gpmc-smsc911x.c2
-rw-r--r--arch/arm/mach-omap2/gpmc.c459
-rw-r--r--arch/arm/mach-omap2/gpmc.h (renamed from arch/arm/plat-omap/include/plat/gpmc.h)61
-rw-r--r--arch/arm/mach-omap2/pm34xx.c2
-rw-r--r--arch/arm/mach-omap2/usb-tusb6010.c2
-rw-r--r--drivers/mtd/nand/omap2.c125
-rw-r--r--drivers/mtd/onenand/omap2.c9
-rw-r--r--include/linux/platform_data/mtd-nand-omap2.h46
-rw-r--r--include/linux/platform_data/mtd-onenand-omap2.h28
40 files changed, 493 insertions, 797 deletions
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 95b384d54f8a..49e49d0b7cf5 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -34,7 +34,7 @@
34#include <asm/mach/map.h> 34#include <asm/mach/map.h>
35 35
36#include "common.h" 36#include "common.h"
37#include <plat/gpmc.h> 37#include "gpmc.h"
38#include <plat/usb.h> 38#include <plat/usb.h>
39#include "gpmc-smc91x.h" 39#include "gpmc-smc91x.h"
40 40
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 96cd3693e1ae..5ad0901fddb4 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -33,7 +33,7 @@
33#include <plat/usb.h> 33#include <plat/usb.h>
34#include "common.h" 34#include "common.h"
35#include <plat/dma.h> 35#include <plat/dma.h>
36#include <plat/gpmc.h> 36#include "gpmc.h"
37#include <video/omapdss.h> 37#include <video/omapdss.h>
38#include <video/omap-panel-tfp410.h> 38#include <video/omap-panel-tfp410.h>
39 39
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index cea3abace815..8cdd18699de6 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -35,7 +35,7 @@
35 35
36#include <plat/led.h> 36#include <plat/led.h>
37#include "common.h" 37#include "common.h"
38#include <plat/gpmc.h> 38#include "gpmc.h"
39 39
40#include <video/omapdss.h> 40#include <video/omapdss.h>
41#include <video/omap-panel-generic-dpi.h> 41#include <video/omap-panel-generic-dpi.h>
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 376d26eb601c..73e2ba9b343b 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -40,7 +40,7 @@
40 40
41#include "common.h" 41#include "common.h"
42#include <linux/platform_data/mtd-nand-omap2.h> 42#include <linux/platform_data/mtd-nand-omap2.h>
43#include <plat/gpmc.h> 43#include "gpmc.h"
44#include <plat/usb.h> 44#include <plat/usb.h>
45#include <video/omapdss.h> 45#include <video/omapdss.h>
46#include <video/omap-panel-generic-dpi.h> 46#include <video/omap-panel-generic-dpi.h>
@@ -53,6 +53,7 @@
53#include "sdram-micron-mt46h32m32lf-6.h" 53#include "sdram-micron-mt46h32m32lf-6.h"
54#include "hsmmc.h" 54#include "hsmmc.h"
55#include "common-board-devices.h" 55#include "common-board-devices.h"
56#include "gpmc-nand.h"
56 57
57#define CM_T35_GPIO_PENDOWN 57 58#define CM_T35_GPIO_PENDOWN 57
58#define SB_T35_USB_HUB_RESET_GPIO 167 59#define SB_T35_USB_HUB_RESET_GPIO 167
@@ -181,7 +182,7 @@ static struct omap_nand_platform_data cm_t35_nand_data = {
181 182
182static void __init cm_t35_init_nand(void) 183static void __init cm_t35_init_nand(void)
183{ 184{
184 if (gpmc_nand_init(&cm_t35_nand_data) < 0) 185 if (gpmc_nand_init(&cm_t35_nand_data, NULL) < 0)
185 pr_err("CM-T35: Unable to register NAND device\n"); 186 pr_err("CM-T35: Unable to register NAND device\n");
186} 187}
187#else 188#else
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 59c0a45f75b0..b5495e415024 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -41,7 +41,7 @@
41#include "common.h" 41#include "common.h"
42#include <plat/usb.h> 42#include <plat/usb.h>
43#include <linux/platform_data/mtd-nand-omap2.h> 43#include <linux/platform_data/mtd-nand-omap2.h>
44#include <plat/gpmc.h> 44#include "gpmc.h"
45 45
46#include "am35xx.h" 46#include "am35xx.h"
47 47
@@ -49,6 +49,7 @@
49#include "control.h" 49#include "control.h"
50#include "common-board-devices.h" 50#include "common-board-devices.h"
51#include "am35xx-emac.h" 51#include "am35xx-emac.h"
52#include "gpmc-nand.h"
52 53
53#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) 54#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
54static struct gpio_led cm_t3517_leds[] = { 55static struct gpio_led cm_t3517_leds[] = {
@@ -240,7 +241,7 @@ static struct omap_nand_platform_data cm_t3517_nand_data = {
240 241
241static void __init cm_t3517_init_nand(void) 242static void __init cm_t3517_init_nand(void)
242{ 243{
243 if (gpmc_nand_init(&cm_t3517_nand_data) < 0) 244 if (gpmc_nand_init(&cm_t3517_nand_data, NULL) < 0)
244 pr_err("CM-T3517: NAND initialization failed\n"); 245 pr_err("CM-T3517: NAND initialization failed\n");
245} 246}
246#else 247#else
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 1fd161e934c7..3eedb8fd0370 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -39,7 +39,7 @@
39#include <asm/mach/flash.h> 39#include <asm/mach/flash.h>
40 40
41#include "common.h" 41#include "common.h"
42#include <plat/gpmc.h> 42#include "gpmc.h"
43#include <linux/platform_data/mtd-nand-omap2.h> 43#include <linux/platform_data/mtd-nand-omap2.h>
44#include <plat/usb.h> 44#include <plat/usb.h>
45#include <video/omapdss.h> 45#include <video/omapdss.h>
@@ -55,8 +55,11 @@
55#include "sdram-micron-mt46h32m32lf-6.h" 55#include "sdram-micron-mt46h32m32lf-6.h"
56#include "mux.h" 56#include "mux.h"
57#include "hsmmc.h" 57#include "hsmmc.h"
58#include "board-flash.h"
58#include "common-board-devices.h" 59#include "common-board-devices.h"
59 60
61#define NAND_CS 0
62
60#define OMAP_DM9000_GPIO_IRQ 25 63#define OMAP_DM9000_GPIO_IRQ 25
61#define OMAP3_DEVKIT_TS_GPIO 27 64#define OMAP3_DEVKIT_TS_GPIO 27
62 65
@@ -621,8 +624,9 @@ static void __init devkit8000_init(void)
621 624
622 usb_musb_init(NULL); 625 usb_musb_init(NULL);
623 usbhs_init(&usbhs_bdata); 626 usbhs_init(&usbhs_bdata);
624 omap_nand_flash_init(NAND_BUSWIDTH_16, devkit8000_nand_partitions, 627 board_nand_init(devkit8000_nand_partitions,
625 ARRAY_SIZE(devkit8000_nand_partitions)); 628 ARRAY_SIZE(devkit8000_nand_partitions), NAND_CS,
629 NAND_BUSWIDTH_16, NULL);
626 omap_twl4030_audio_init("omap3beagle"); 630 omap_twl4030_audio_init("omap3beagle");
627 631
628 /* Ensure SDRC pins are mux'd for self-refresh */ 632 /* Ensure SDRC pins are mux'd for self-refresh */
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index e642acf9cad0..020b96b91f73 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -18,13 +18,15 @@
18#include <linux/io.h> 18#include <linux/io.h>
19 19
20#include <plat/cpu.h> 20#include <plat/cpu.h>
21#include <plat/gpmc.h> 21#include "gpmc.h"
22#include <linux/platform_data/mtd-nand-omap2.h> 22#include <linux/platform_data/mtd-nand-omap2.h>
23#include <linux/platform_data/mtd-onenand-omap2.h> 23#include <linux/platform_data/mtd-onenand-omap2.h>
24#include <plat/tc.h> 24#include <plat/tc.h>
25 25
26#include "common.h" 26#include "common.h"
27#include "board-flash.h" 27#include "board-flash.h"
28#include "gpmc-onenand.h"
29#include "gpmc-nand.h"
28 30
29#define REG_FPGA_REV 0x10 31#define REG_FPGA_REV 0x10
30#define REG_FPGA_DIP_SWITCH_INPUT2 0x60 32#define REG_FPGA_DIP_SWITCH_INPUT2 0x60
@@ -104,36 +106,35 @@ __init board_onenand_init(struct mtd_partition *onenand_parts,
104 defined(CONFIG_MTD_NAND_OMAP2_MODULE) 106 defined(CONFIG_MTD_NAND_OMAP2_MODULE)
105 107
106/* Note that all values in this struct are in nanoseconds */ 108/* Note that all values in this struct are in nanoseconds */
107static struct gpmc_timings nand_timings = { 109struct gpmc_timings nand_default_timings[1] = {
110 {
111 .sync_clk = 0,
108 112
109 .sync_clk = 0, 113 .cs_on = 0,
114 .cs_rd_off = 36,
115 .cs_wr_off = 36,
110 116
111 .cs_on = 0, 117 .adv_on = 6,
112 .cs_rd_off = 36, 118 .adv_rd_off = 24,
113 .cs_wr_off = 36, 119 .adv_wr_off = 36,
114 120
115 .adv_on = 6, 121 .we_off = 30,
116 .adv_rd_off = 24, 122 .oe_off = 48,
117 .adv_wr_off = 36,
118 123
119 .we_off = 30, 124 .access = 54,
120 .oe_off = 48, 125 .rd_cycle = 72,
126 .wr_cycle = 72,
121 127
122 .access = 54, 128 .wr_access = 30,
123 .rd_cycle = 72, 129 .wr_data_mux_bus = 0,
124 .wr_cycle = 72, 130 },
125
126 .wr_access = 30,
127 .wr_data_mux_bus = 0,
128}; 131};
129 132
130static struct omap_nand_platform_data board_nand_data = { 133static struct omap_nand_platform_data board_nand_data;
131 .gpmc_t = &nand_timings,
132};
133 134
134void 135void
135__init board_nand_init(struct mtd_partition *nand_parts, 136__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
136 u8 nr_parts, u8 cs, int nand_type) 137 int nand_type, struct gpmc_timings *gpmc_t)
137{ 138{
138 board_nand_data.cs = cs; 139 board_nand_data.cs = cs;
139 board_nand_data.parts = nand_parts; 140 board_nand_data.parts = nand_parts;
@@ -141,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts,
141 board_nand_data.devsize = nand_type; 142 board_nand_data.devsize = nand_type;
142 143
143 board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT; 144 board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
144 gpmc_nand_init(&board_nand_data); 145 gpmc_nand_init(&board_nand_data, gpmc_t);
145} 146}
146#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ 147#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
147 148
@@ -238,5 +239,6 @@ void __init board_flash_init(struct flash_partitions partition_info[],
238 pr_err("NAND: Unable to find configuration in GPMC\n"); 239 pr_err("NAND: Unable to find configuration in GPMC\n");
239 else 240 else
240 board_nand_init(partition_info[2].parts, 241 board_nand_init(partition_info[2].parts,
241 partition_info[2].nr_parts, nandcs, nand_type); 242 partition_info[2].nr_parts, nandcs,
243 nand_type, nand_default_timings);
242} 244}
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index c44b70d52021..2fb5d41a9fae 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -12,7 +12,7 @@
12 */ 12 */
13#include <linux/mtd/mtd.h> 13#include <linux/mtd/mtd.h>
14#include <linux/mtd/partitions.h> 14#include <linux/mtd/partitions.h>
15#include <plat/gpmc.h> 15#include "gpmc.h"
16 16
17#define PDC_NOR 1 17#define PDC_NOR 1
18#define PDC_NAND 2 18#define PDC_NAND 2
@@ -40,12 +40,14 @@ static inline void board_flash_init(struct flash_partitions part[],
40#if defined(CONFIG_MTD_NAND_OMAP2) || \ 40#if defined(CONFIG_MTD_NAND_OMAP2) || \
41 defined(CONFIG_MTD_NAND_OMAP2_MODULE) 41 defined(CONFIG_MTD_NAND_OMAP2_MODULE)
42extern void board_nand_init(struct mtd_partition *nand_parts, 42extern void board_nand_init(struct mtd_partition *nand_parts,
43 u8 nr_parts, u8 cs, int nand_type); 43 u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t);
44extern struct gpmc_timings nand_default_timings[];
44#else 45#else
45static inline void board_nand_init(struct mtd_partition *nand_parts, 46static inline void board_nand_init(struct mtd_partition *nand_parts,
46 u8 nr_parts, u8 cs, int nand_type) 47 u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t)
47{ 48{
48} 49}
50#define nand_default_timings NULL
49#endif 51#endif
50 52
51#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ 53#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 8d04bf851af4..65ebf58e66e2 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -33,7 +33,6 @@
33 33
34#include <plat/menelaus.h> 34#include <plat/menelaus.h>
35#include <plat/dma.h> 35#include <plat/dma.h>
36#include <plat/gpmc.h>
37#include "debug-devices.h" 36#include "debug-devices.h"
38 37
39#include <video/omapdss.h> 38#include <video/omapdss.h>
@@ -42,6 +41,7 @@
42#include "common.h" 41#include "common.h"
43#include "mux.h" 42#include "mux.h"
44#include "control.h" 43#include "control.h"
44#include "gpmc.h"
45 45
46#define H4_FLASH_CS 0 46#define H4_FLASH_CS 0
47#define H4_SMC91X_CS 1 47#define H4_SMC91X_CS 1
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 48d5e41dfbfa..9a9a9b5f78b6 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -30,7 +30,7 @@
30#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
31 31
32#include "common.h" 32#include "common.h"
33#include <plat/gpmc.h> 33#include "gpmc.h"
34#include <plat/usb.h> 34#include <plat/usb.h>
35 35
36#include <video/omapdss.h> 36#include <video/omapdss.h>
@@ -43,6 +43,7 @@
43#include "common-board-devices.h" 43#include "common-board-devices.h"
44#include "board-flash.h" 44#include "board-flash.h"
45#include "control.h" 45#include "control.h"
46#include "gpmc-onenand.h"
46 47
47#define IGEP2_SMSC911X_CS 5 48#define IGEP2_SMSC911X_CS 5
48#define IGEP2_SMSC911X_GPIO 176 49#define IGEP2_SMSC911X_GPIO 176
@@ -175,7 +176,7 @@ static void __init igep_flash_init(void)
175 pr_info("IGEP: initializing NAND memory device\n"); 176 pr_info("IGEP: initializing NAND memory device\n");
176 board_nand_init(igep_flash_partitions, 177 board_nand_init(igep_flash_partitions,
177 ARRAY_SIZE(igep_flash_partitions), 178 ARRAY_SIZE(igep_flash_partitions),
178 0, NAND_BUSWIDTH_16); 179 0, NAND_BUSWIDTH_16, nand_default_timings);
179 } else if (mux == IGEP_SYSBOOT_ONENAND) { 180 } else if (mux == IGEP_SYSBOOT_ONENAND) {
180 pr_info("IGEP: initializing OneNAND memory device\n"); 181 pr_info("IGEP: initializing OneNAND memory device\n");
181 board_onenand_init(igep_flash_partitions, 182 board_onenand_init(igep_flash_partitions,
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index ee8c3cfb95b3..e1628cd25ab4 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -35,7 +35,7 @@
35#include <asm/mach/map.h> 35#include <asm/mach/map.h>
36 36
37#include "common.h" 37#include "common.h"
38#include <plat/gpmc.h> 38#include "gpmc.h"
39#include <mach/board-zoom.h> 39#include <mach/board-zoom.h>
40#include <plat/usb.h> 40#include <plat/usb.h>
41#include "gpmc-smsc911x.h" 41#include "gpmc-smsc911x.h"
@@ -420,8 +420,8 @@ static void __init omap_ldp_init(void)
420 omap_serial_init(); 420 omap_serial_init();
421 omap_sdrc_init(NULL, NULL); 421 omap_sdrc_init(NULL, NULL);
422 usb_musb_init(NULL); 422 usb_musb_init(NULL);
423 board_nand_init(ldp_nand_partitions, 423 board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions),
424 ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0); 424 ZOOM_NAND_CS, 0, nand_default_timings);
425 425
426 omap_hsmmc_init(mmc); 426 omap_hsmmc_init(mmc);
427 ldp_display_init(); 427 ldp_display_init();
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index d95f727ca39a..92b19166aac8 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -32,6 +32,7 @@
32#include <plat/mmc.h> 32#include <plat/mmc.h>
33 33
34#include "mux.h" 34#include "mux.h"
35#include "gpmc-onenand.h"
35 36
36#define TUSB6010_ASYNC_CS 1 37#define TUSB6010_ASYNC_CS 1
37#define TUSB6010_SYNC_CS 4 38#define TUSB6010_SYNC_CS 4
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 388c431c745a..f11a5eb595f7 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -41,7 +41,7 @@
41#include "common.h" 41#include "common.h"
42#include <video/omapdss.h> 42#include <video/omapdss.h>
43#include <video/omap-panel-tfp410.h> 43#include <video/omap-panel-tfp410.h>
44#include <plat/gpmc.h> 44#include "gpmc.h"
45#include <linux/platform_data/mtd-nand-omap2.h> 45#include <linux/platform_data/mtd-nand-omap2.h>
46#include <plat/usb.h> 46#include <plat/usb.h>
47#include <plat/omap_device.h> 47#include <plat/omap_device.h>
@@ -49,8 +49,11 @@
49#include "mux.h" 49#include "mux.h"
50#include "hsmmc.h" 50#include "hsmmc.h"
51#include "pm.h" 51#include "pm.h"
52#include "board-flash.h"
52#include "common-board-devices.h" 53#include "common-board-devices.h"
53 54
55#define NAND_CS 0
56
54/* 57/*
55 * OMAP3 Beagle revision 58 * OMAP3 Beagle revision
56 * Run time detection of Beagle revision is done by reading GPIO. 59 * Run time detection of Beagle revision is done by reading GPIO.
@@ -512,8 +515,9 @@ static void __init omap3_beagle_init(void)
512 515
513 usb_musb_init(NULL); 516 usb_musb_init(NULL);
514 usbhs_init(&usbhs_bdata); 517 usbhs_init(&usbhs_bdata);
515 omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions, 518 board_nand_init(omap3beagle_nand_partitions,
516 ARRAY_SIZE(omap3beagle_nand_partitions)); 519 ARRAY_SIZE(omap3beagle_nand_partitions), NAND_CS,
520 NAND_BUSWIDTH_16, NULL);
517 omap_twl4030_audio_init("omap3beagle"); 521 omap_twl4030_audio_init("omap3beagle");
518 522
519 /* Ensure msecure is mux'd to be able to set the RTC. */ 523 /* Ensure msecure is mux'd to be able to set the RTC. */
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index b9b776b6c954..1d8e926b52fe 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -56,6 +56,9 @@
56#include "sdram-micron-mt46h32m32lf-6.h" 56#include "sdram-micron-mt46h32m32lf-6.h"
57#include "hsmmc.h" 57#include "hsmmc.h"
58#include "common-board-devices.h" 58#include "common-board-devices.h"
59#include "board-flash.h"
60
61#define NAND_CS 0
59 62
60#define OMAP3_EVM_TS_GPIO 175 63#define OMAP3_EVM_TS_GPIO 175
61#define OMAP3_EVM_EHCI_VBUS 22 64#define OMAP3_EVM_EHCI_VBUS 22
@@ -731,8 +734,9 @@ static void __init omap3_evm_init(void)
731 } 734 }
732 usb_musb_init(&musb_board_data); 735 usb_musb_init(&musb_board_data);
733 usbhs_init(&usbhs_bdata); 736 usbhs_init(&usbhs_bdata);
734 omap_nand_flash_init(NAND_BUSWIDTH_16, omap3evm_nand_partitions, 737 board_nand_init(omap3evm_nand_partitions,
735 ARRAY_SIZE(omap3evm_nand_partitions)); 738 ARRAY_SIZE(omap3evm_nand_partitions), NAND_CS,
739 NAND_BUSWIDTH_16, NULL);
736 740
737 omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL); 741 omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
738 omap3evm_init_smsc911x(); 742 omap3evm_init_smsc911x();
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 7bd8253b5d1d..5cfade235bb4 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -35,7 +35,7 @@
35#include <asm/mach/map.h> 35#include <asm/mach/map.h>
36 36
37#include "gpmc-smsc911x.h" 37#include "gpmc-smsc911x.h"
38#include <plat/gpmc.h> 38#include "gpmc.h"
39#include <plat/sdrc.h> 39#include <plat/sdrc.h>
40#include <plat/usb.h> 40#include <plat/usb.h>
41 41
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 00a1f4ae6e44..f286b4b4bd5b 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -50,6 +50,7 @@
50#include "sdram-micron-mt46h32m32lf-6.h" 50#include "sdram-micron-mt46h32m32lf-6.h"
51#include "hsmmc.h" 51#include "hsmmc.h"
52#include "common-board-devices.h" 52#include "common-board-devices.h"
53#include "gpmc-nand.h"
53 54
54#define PANDORA_WIFI_IRQ_GPIO 21 55#define PANDORA_WIFI_IRQ_GPIO 21
55#define PANDORA_WIFI_NRESET_GPIO 23 56#define PANDORA_WIFI_NRESET_GPIO 23
@@ -602,7 +603,7 @@ static void __init omap3pandora_init(void)
602 omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL); 603 omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);
603 usbhs_init(&usbhs_bdata); 604 usbhs_init(&usbhs_bdata);
604 usb_musb_init(NULL); 605 usb_musb_init(NULL);
605 gpmc_nand_init(&pandora_nand_data); 606 gpmc_nand_init(&pandora_nand_data, NULL);
606 607
607 /* Ensure SDRC pins are mux'd for self-refresh */ 608 /* Ensure SDRC pins are mux'd for self-refresh */
608 omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); 609 omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 731235eb319e..3c83b9fbff45 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -40,7 +40,7 @@
40#include <asm/mach/flash.h> 40#include <asm/mach/flash.h>
41 41
42#include "common.h" 42#include "common.h"
43#include <plat/gpmc.h> 43#include "gpmc.h"
44#include <linux/platform_data/mtd-nand-omap2.h> 44#include <linux/platform_data/mtd-nand-omap2.h>
45#include <plat/usb.h> 45#include <plat/usb.h>
46#include <video/omapdss.h> 46#include <video/omapdss.h>
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 944ffc436577..cd282ae0856b 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -44,12 +44,13 @@
44#include <asm/system_info.h> 44#include <asm/system_info.h>
45 45
46#include "common.h" 46#include "common.h"
47#include <plat/gpmc.h> 47#include "gpmc.h"
48#include <linux/platform_data/mtd-nand-omap2.h> 48#include <linux/platform_data/mtd-nand-omap2.h>
49#include <plat/usb.h> 49#include <plat/usb.h>
50 50
51#include "mux.h" 51#include "mux.h"
52#include "hsmmc.h" 52#include "hsmmc.h"
53#include "board-flash.h"
53#include "common-board-devices.h" 54#include "common-board-devices.h"
54 55
55#include <asm/setup.h> 56#include <asm/setup.h>
@@ -59,6 +60,8 @@
59#define TB_BL_PWM_TIMER 9 60#define TB_BL_PWM_TIMER 9
60#define TB_KILL_POWER_GPIO 168 61#define TB_KILL_POWER_GPIO 168
61 62
63#define NAND_CS 0
64
62static unsigned long touchbook_revision; 65static unsigned long touchbook_revision;
63 66
64static struct mtd_partition omap3touchbook_nand_partitions[] = { 67static struct mtd_partition omap3touchbook_nand_partitions[] = {
@@ -365,8 +368,9 @@ static void __init omap3_touchbook_init(void)
365 omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata); 368 omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
366 usb_musb_init(NULL); 369 usb_musb_init(NULL);
367 usbhs_init(&usbhs_bdata); 370 usbhs_init(&usbhs_bdata);
368 omap_nand_flash_init(NAND_BUSWIDTH_16, omap3touchbook_nand_partitions, 371 board_nand_init(omap3touchbook_nand_partitions,
369 ARRAY_SIZE(omap3touchbook_nand_partitions)); 372 ARRAY_SIZE(omap3touchbook_nand_partitions), NAND_CS,
373 NAND_BUSWIDTH_16, NULL);
370 374
371 /* Ensure SDRC pins are mux'd for self-refresh */ 375 /* Ensure SDRC pins are mux'd for self-refresh */
372 omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); 376 omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index b700685762b5..3a9d1fa8bebd 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -49,14 +49,17 @@
49#include <video/omapdss.h> 49#include <video/omapdss.h>
50#include <video/omap-panel-generic-dpi.h> 50#include <video/omap-panel-generic-dpi.h>
51#include <video/omap-panel-tfp410.h> 51#include <video/omap-panel-tfp410.h>
52#include <plat/gpmc.h> 52#include "gpmc.h"
53#include <plat/usb.h> 53#include <plat/usb.h>
54 54
55#include "mux.h" 55#include "mux.h"
56#include "sdram-micron-mt46h32m32lf-6.h" 56#include "sdram-micron-mt46h32m32lf-6.h"
57#include "hsmmc.h" 57#include "hsmmc.h"
58#include "board-flash.h"
58#include "common-board-devices.h" 59#include "common-board-devices.h"
59 60
61#define NAND_CS 0
62
60#define OVERO_GPIO_BT_XGATE 15 63#define OVERO_GPIO_BT_XGATE 15
61#define OVERO_GPIO_W2W_NRESET 16 64#define OVERO_GPIO_W2W_NRESET 16
62#define OVERO_GPIO_PENDOWN 114 65#define OVERO_GPIO_PENDOWN 114
@@ -495,8 +498,8 @@ static void __init overo_init(void)
495 omap_serial_init(); 498 omap_serial_init();
496 omap_sdrc_init(mt46h32m32lf6_sdrc_params, 499 omap_sdrc_init(mt46h32m32lf6_sdrc_params,
497 mt46h32m32lf6_sdrc_params); 500 mt46h32m32lf6_sdrc_params);
498 omap_nand_flash_init(0, overo_nand_partitions, 501 board_nand_init(overo_nand_partitions,
499 ARRAY_SIZE(overo_nand_partitions)); 502 ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
500 usb_musb_init(NULL); 503 usb_musb_init(NULL);
501 usbhs_init(&usbhs_bdata); 504 usbhs_init(&usbhs_bdata);
502 overo_spi_init(); 505 overo_spi_init();
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 45997bfbcbd2..3c3a47317f8f 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -25,7 +25,7 @@
25#include <plat/i2c.h> 25#include <plat/i2c.h>
26#include <plat/mmc.h> 26#include <plat/mmc.h>
27#include <plat/usb.h> 27#include <plat/usb.h>
28#include <plat/gpmc.h> 28#include "gpmc.h"
29#include "common.h" 29#include "common.h"
30#include <plat/serial.h> 30#include <plat/serial.h>
31 31
@@ -33,6 +33,7 @@
33#include "hsmmc.h" 33#include "hsmmc.h"
34#include "sdram-nokia.h" 34#include "sdram-nokia.h"
35#include "common-board-devices.h" 35#include "common-board-devices.h"
36#include "gpmc-onenand.h"
36 37
37static struct regulator_consumer_supply rm680_vemmc_consumers[] = { 38static struct regulator_consumer_supply rm680_vemmc_consumers[] = {
38 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), 39 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 020e03c95bfe..42b6056decae 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -32,7 +32,7 @@
32 32
33#include "common.h" 33#include "common.h"
34#include <plat/dma.h> 34#include <plat/dma.h>
35#include <plat/gpmc.h> 35#include "gpmc.h"
36#include <plat/omap-pm.h> 36#include <plat/omap-pm.h>
37#include "gpmc-smc91x.h" 37#include "gpmc-smc91x.h"
38 38
@@ -54,6 +54,7 @@
54#include "mux.h" 54#include "mux.h"
55#include "hsmmc.h" 55#include "hsmmc.h"
56#include "common-board-devices.h" 56#include "common-board-devices.h"
57#include "gpmc-onenand.h"
57 58
58#define SYSTEM_REV_B_USES_VAUX3 0x1699 59#define SYSTEM_REV_B_USES_VAUX3 0x1699
59#define SYSTEM_REV_S_USES_VAUX3 0x8 60#define SYSTEM_REV_S_USES_VAUX3 0x8
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 7bbb05d9689b..88ba5be475b7 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -25,7 +25,7 @@
25 25
26#include "common.h" 26#include "common.h"
27#include <plat/dma.h> 27#include <plat/dma.h>
28#include <plat/gpmc.h> 28#include "gpmc.h"
29#include <plat/usb.h> 29#include <plat/usb.h>
30 30
31#include "mux.h" 31#include "mux.h"
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index afb2278a29f6..be9f71d436bf 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -17,7 +17,7 @@
17#include <linux/regulator/fixed.h> 17#include <linux/regulator/fixed.h>
18#include <linux/regulator/machine.h> 18#include <linux/regulator/machine.h>
19 19
20#include <plat/gpmc.h> 20#include "gpmc.h"
21#include "gpmc-smsc911x.h" 21#include "gpmc-smsc911x.h"
22 22
23#include <mach/board-zoom.h> 23#include <mach/board-zoom.h>
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 4994438e1f46..c39578c1fa6d 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -113,8 +113,9 @@ static void __init omap_zoom_init(void)
113 usbhs_init(&usbhs_bdata); 113 usbhs_init(&usbhs_bdata);
114 } 114 }
115 115
116 board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions), 116 board_nand_init(zoom_nand_partitions,
117 ZOOM_NAND_CS, NAND_BUSWIDTH_16); 117 ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS,
118 NAND_BUSWIDTH_16, nand_default_timings);
118 zoom_debugboard_init(); 119 zoom_debugboard_init();
119 zoom_peripherals_init(); 120 zoom_peripherals_init();
120 121
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 48daac2581b4..ad856092c06a 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -25,7 +25,6 @@
25#include <linux/spi/ads7846.h> 25#include <linux/spi/ads7846.h>
26 26
27#include <linux/platform_data/spi-omap2-mcspi.h> 27#include <linux/platform_data/spi-omap2-mcspi.h>
28#include <linux/platform_data/mtd-nand-omap2.h>
29 28
30#include "common.h" 29#include "common.h"
31#include "common-board-devices.h" 30#include "common-board-devices.h"
@@ -96,48 +95,3 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
96{ 95{
97} 96}
98#endif 97#endif
99
100#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
101static struct omap_nand_platform_data nand_data;
102
103void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
104 int nr_parts)
105{
106 u8 cs = 0;
107 u8 nandcs = GPMC_CS_NUM + 1;
108
109 /* find out the chip-select on which NAND exists */
110 while (cs < GPMC_CS_NUM) {
111 u32 ret = 0;
112 ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
113
114 if ((ret & 0xC00) == 0x800) {
115 printk(KERN_INFO "Found NAND on CS%d\n", cs);
116 if (nandcs > GPMC_CS_NUM)
117 nandcs = cs;
118 }
119 cs++;
120 }
121
122 if (nandcs > GPMC_CS_NUM) {
123 pr_info("NAND: Unable to find configuration in GPMC\n");
124 return;
125 }
126
127 if (nandcs < GPMC_CS_NUM) {
128 nand_data.cs = nandcs;
129 nand_data.parts = parts;
130 nand_data.nr_parts = nr_parts;
131 nand_data.devsize = options;
132
133 printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
134 if (gpmc_nand_init(&nand_data) < 0)
135 printk(KERN_ERR "Unable to register NAND device\n");
136 }
137}
138#else
139void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
140 int nr_parts)
141{
142}
143#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index a0b4a42836ab..72bb41b3fd25 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -10,6 +10,5 @@ struct ads7846_platform_data;
10 10
11void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce, 11void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
12 struct ads7846_platform_data *board_pdata); 12 struct ads7846_platform_data *board_pdata);
13void omap_nand_flash_init(int opts, struct mtd_partition *parts, int n_parts);
14 13
15#endif /* __OMAP_COMMON_BOARD_DEVICES__ */ 14#endif /* __OMAP_COMMON_BOARD_DEVICES__ */
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 4acf497faeb3..8607735b3ab3 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -17,9 +17,12 @@
17 17
18#include <asm/mach/flash.h> 18#include <asm/mach/flash.h>
19 19
20#include <plat/gpmc.h> 20#include "gpmc.h"
21
22#include "soc.h" 21#include "soc.h"
22#include "gpmc-nand.h"
23
24/* minimum size for IO mapping */
25#define NAND_IO_SIZE 4
23 26
24static struct resource gpmc_nand_resource[] = { 27static struct resource gpmc_nand_resource[] = {
25 { 28 {
@@ -40,41 +43,36 @@ static struct platform_device gpmc_nand_device = {
40 .resource = gpmc_nand_resource, 43 .resource = gpmc_nand_resource,
41}; 44};
42 45
43static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data) 46static int omap2_nand_gpmc_retime(
47 struct omap_nand_platform_data *gpmc_nand_data,
48 struct gpmc_timings *gpmc_t)
44{ 49{
45 struct gpmc_timings t; 50 struct gpmc_timings t;
46 int err; 51 int err;
47 52
48 if (!gpmc_nand_data->gpmc_t)
49 return 0;
50
51 memset(&t, 0, sizeof(t)); 53 memset(&t, 0, sizeof(t));
52 t.sync_clk = gpmc_nand_data->gpmc_t->sync_clk; 54 t.sync_clk = gpmc_t->sync_clk;
53 t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on); 55 t.cs_on = gpmc_round_ns_to_ticks(gpmc_t->cs_on);
54 t.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on); 56 t.adv_on = gpmc_round_ns_to_ticks(gpmc_t->adv_on);
55 57
56 /* Read */ 58 /* Read */
57 t.adv_rd_off = gpmc_round_ns_to_ticks( 59 t.adv_rd_off = gpmc_round_ns_to_ticks(gpmc_t->adv_rd_off);
58 gpmc_nand_data->gpmc_t->adv_rd_off);
59 t.oe_on = t.adv_on; 60 t.oe_on = t.adv_on;
60 t.access = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->access); 61 t.access = gpmc_round_ns_to_ticks(gpmc_t->access);
61 t.oe_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->oe_off); 62 t.oe_off = gpmc_round_ns_to_ticks(gpmc_t->oe_off);
62 t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_rd_off); 63 t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_t->cs_rd_off);
63 t.rd_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->rd_cycle); 64 t.rd_cycle = gpmc_round_ns_to_ticks(gpmc_t->rd_cycle);
64 65
65 /* Write */ 66 /* Write */
66 t.adv_wr_off = gpmc_round_ns_to_ticks( 67 t.adv_wr_off = gpmc_round_ns_to_ticks(gpmc_t->adv_wr_off);
67 gpmc_nand_data->gpmc_t->adv_wr_off);
68 t.we_on = t.oe_on; 68 t.we_on = t.oe_on;
69 if (cpu_is_omap34xx()) { 69 if (cpu_is_omap34xx()) {
70 t.wr_data_mux_bus = gpmc_round_ns_to_ticks( 70 t.wr_data_mux_bus = gpmc_round_ns_to_ticks(gpmc_t->wr_data_mux_bus);
71 gpmc_nand_data->gpmc_t->wr_data_mux_bus); 71 t.wr_access = gpmc_round_ns_to_ticks(gpmc_t->wr_access);
72 t.wr_access = gpmc_round_ns_to_ticks(
73 gpmc_nand_data->gpmc_t->wr_access);
74 } 72 }
75 t.we_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->we_off); 73 t.we_off = gpmc_round_ns_to_ticks(gpmc_t->we_off);
76 t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_wr_off); 74 t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_t->cs_wr_off);
77 t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); 75 t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_t->wr_cycle);
78 76
79 /* Configure GPMC */ 77 /* Configure GPMC */
80 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) 78 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
@@ -91,7 +89,29 @@ static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data
91 return 0; 89 return 0;
92} 90}
93 91
94int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data) 92static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
93{
94 /* support only OMAP3 class */
95 if (!cpu_is_omap34xx()) {
96 pr_err("BCH ecc is not supported on this CPU\n");
97 return 0;
98 }
99
100 /*
101 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
102 * Other chips may be added if confirmed to work.
103 */
104 if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
105 (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
106 pr_err("BCH 4-bit mode is not supported on this CPU\n");
107 return 0;
108 }
109
110 return 1;
111}
112
113int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
114 struct gpmc_timings *gpmc_t)
95{ 115{
96 int err = 0; 116 int err = 0;
97 struct device *dev = &gpmc_nand_device.dev; 117 struct device *dev = &gpmc_nand_device.dev;
@@ -112,11 +132,13 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
112 gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); 132 gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
113 gpmc_nand_resource[2].start = 133 gpmc_nand_resource[2].start =
114 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); 134 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
115 /* Set timings in GPMC */ 135
116 err = omap2_nand_gpmc_retime(gpmc_nand_data); 136 if (gpmc_t) {
117 if (err < 0) { 137 err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t);
118 dev_err(dev, "Unable to set gpmc timings: %d\n", err); 138 if (err < 0) {
119 return err; 139 dev_err(dev, "Unable to set gpmc timings: %d\n", err);
140 return err;
141 }
120 } 142 }
121 143
122 /* Enable RD PIN Monitoring Reg */ 144 /* Enable RD PIN Monitoring Reg */
@@ -126,6 +148,9 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
126 148
127 gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); 149 gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
128 150
151 if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt))
152 return -EINVAL;
153
129 err = platform_device_register(&gpmc_nand_device); 154 err = platform_device_register(&gpmc_nand_device);
130 if (err < 0) { 155 if (err < 0) {
131 dev_err(dev, "Unable to register NAND device\n"); 156 dev_err(dev, "Unable to register NAND device\n");
diff --git a/arch/arm/mach-omap2/gpmc-nand.h b/arch/arm/mach-omap2/gpmc-nand.h
new file mode 100644
index 000000000000..d59e1281e851
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc-nand.h
@@ -0,0 +1,27 @@
1/*
2 * arch/arm/mach-omap2/gpmc-nand.h
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __OMAP2_GPMC_NAND_H
11#define __OMAP2_GPMC_NAND_H
12
13#include "gpmc.h"
14#include <linux/platform_data/mtd-nand-omap2.h>
15
16#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
17extern int gpmc_nand_init(struct omap_nand_platform_data *d,
18 struct gpmc_timings *gpmc_t);
19#else
20static inline int gpmc_nand_init(struct omap_nand_platform_data *d,
21 struct gpmc_timings *gpmc_t)
22{
23 return 0;
24}
25#endif
26
27#endif
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 916716e1da3b..d102183ed9a5 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -16,15 +16,25 @@
16#include <linux/mtd/onenand_regs.h> 16#include <linux/mtd/onenand_regs.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/platform_data/mtd-onenand-omap2.h> 18#include <linux/platform_data/mtd-onenand-omap2.h>
19#include <linux/err.h>
19 20
20#include <asm/mach/flash.h> 21#include <asm/mach/flash.h>
21 22
22#include <plat/gpmc.h> 23#include "gpmc.h"
23
24#include "soc.h" 24#include "soc.h"
25#include "gpmc-onenand.h"
25 26
26#define ONENAND_IO_SIZE SZ_128K 27#define ONENAND_IO_SIZE SZ_128K
27 28
29#define ONENAND_FLAG_SYNCREAD (1 << 0)
30#define ONENAND_FLAG_SYNCWRITE (1 << 1)
31#define ONENAND_FLAG_HF (1 << 2)
32#define ONENAND_FLAG_VHF (1 << 3)
33
34static unsigned onenand_flags;
35static unsigned latency;
36static int fclk_offset;
37
28static struct omap_onenand_platform_data *gpmc_onenand_data; 38static struct omap_onenand_platform_data *gpmc_onenand_data;
29 39
30static struct resource gpmc_onenand_resource = { 40static struct resource gpmc_onenand_resource = {
@@ -38,11 +48,9 @@ static struct platform_device gpmc_onenand_device = {
38 .resource = &gpmc_onenand_resource, 48 .resource = &gpmc_onenand_resource,
39}; 49};
40 50
41static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) 51static struct gpmc_timings omap2_onenand_calc_async_timings(void)
42{ 52{
43 struct gpmc_timings t; 53 struct gpmc_timings t;
44 u32 reg;
45 int err;
46 54
47 const int t_cer = 15; 55 const int t_cer = 15;
48 const int t_avdp = 12; 56 const int t_avdp = 12;
@@ -55,11 +63,6 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
55 const int t_wpl = 40; 63 const int t_wpl = 40;
56 const int t_wph = 30; 64 const int t_wph = 30;
57 65
58 /* Ensure sync read and sync write are disabled */
59 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
60 reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
61 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
62
63 memset(&t, 0, sizeof(t)); 66 memset(&t, 0, sizeof(t));
64 t.sync_clk = 0; 67 t.sync_clk = 0;
65 t.cs_on = 0; 68 t.cs_on = 0;
@@ -86,25 +89,30 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
86 t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph); 89 t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
87 t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez); 90 t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
88 91
92 return t;
93}
94
95static int gpmc_set_async_mode(int cs, struct gpmc_timings *t)
96{
89 /* Configure GPMC for asynchronous read */ 97 /* Configure GPMC for asynchronous read */
90 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, 98 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
91 GPMC_CONFIG1_DEVICESIZE_16 | 99 GPMC_CONFIG1_DEVICESIZE_16 |
92 GPMC_CONFIG1_MUXADDDATA); 100 GPMC_CONFIG1_MUXADDDATA);
93 101
94 err = gpmc_cs_set_timings(cs, &t); 102 return gpmc_cs_set_timings(cs, t);
95 if (err) 103}
96 return err; 104
105static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
106{
107 u32 reg;
97 108
98 /* Ensure sync read and sync write are disabled */ 109 /* Ensure sync read and sync write are disabled */
99 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); 110 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
100 reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE; 111 reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
101 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); 112 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
102
103 return 0;
104} 113}
105 114
106static void set_onenand_cfg(void __iomem *onenand_base, int latency, 115static void set_onenand_cfg(void __iomem *onenand_base)
107 int sync_read, int sync_write, int hf, int vhf)
108{ 116{
109 u32 reg; 117 u32 reg;
110 118
@@ -112,19 +120,19 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
112 reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9)); 120 reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
113 reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) | 121 reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
114 ONENAND_SYS_CFG1_BL_16; 122 ONENAND_SYS_CFG1_BL_16;
115 if (sync_read) 123 if (onenand_flags & ONENAND_FLAG_SYNCREAD)
116 reg |= ONENAND_SYS_CFG1_SYNC_READ; 124 reg |= ONENAND_SYS_CFG1_SYNC_READ;
117 else 125 else
118 reg &= ~ONENAND_SYS_CFG1_SYNC_READ; 126 reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
119 if (sync_write) 127 if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
120 reg |= ONENAND_SYS_CFG1_SYNC_WRITE; 128 reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
121 else 129 else
122 reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE; 130 reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
123 if (hf) 131 if (onenand_flags & ONENAND_FLAG_HF)
124 reg |= ONENAND_SYS_CFG1_HF; 132 reg |= ONENAND_SYS_CFG1_HF;
125 else 133 else
126 reg &= ~ONENAND_SYS_CFG1_HF; 134 reg &= ~ONENAND_SYS_CFG1_HF;
127 if (vhf) 135 if (onenand_flags & ONENAND_FLAG_VHF)
128 reg |= ONENAND_SYS_CFG1_VHF; 136 reg |= ONENAND_SYS_CFG1_VHF;
129 else 137 else
130 reg &= ~ONENAND_SYS_CFG1_VHF; 138 reg &= ~ONENAND_SYS_CFG1_VHF;
@@ -132,21 +140,10 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
132} 140}
133 141
134static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg, 142static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
135 void __iomem *onenand_base, bool *clk_dep) 143 void __iomem *onenand_base)
136{ 144{
137 u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID); 145 u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
138 int freq = 0; 146 int freq;
139
140 if (cfg->get_freq) {
141 struct onenand_freq_info fi;
142
143 fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
144 fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
145 fi.ver_id = ver;
146 freq = cfg->get_freq(&fi, clk_dep);
147 if (freq)
148 return freq;
149 }
150 147
151 switch ((ver >> 4) & 0xf) { 148 switch ((ver >> 4) & 0xf) {
152 case 0: 149 case 0:
@@ -172,9 +169,9 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
172 return freq; 169 return freq;
173} 170}
174 171
175static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, 172static struct gpmc_timings
176 void __iomem *onenand_base, 173omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
177 int *freq_ptr) 174 int freq)
178{ 175{
179 struct gpmc_timings t; 176 struct gpmc_timings t;
180 const int t_cer = 15; 177 const int t_cer = 15;
@@ -184,29 +181,15 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
184 const int t_wpl = 40; 181 const int t_wpl = 40;
185 const int t_wph = 30; 182 const int t_wph = 30;
186 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; 183 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
187 int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
188 int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
189 int err, ticks_cez;
190 int cs = cfg->cs, freq = *freq_ptr;
191 u32 reg; 184 u32 reg;
192 bool clk_dep = false; 185 int div, fclk_offset_ns, gpmc_clk_ns;
186 int ticks_cez;
187 int cs = cfg->cs;
193 188
194 if (cfg->flags & ONENAND_SYNC_READ) { 189 if (cfg->flags & ONENAND_SYNC_READ)
195 sync_read = 1; 190 onenand_flags = ONENAND_FLAG_SYNCREAD;
196 } else if (cfg->flags & ONENAND_SYNC_READWRITE) { 191 else if (cfg->flags & ONENAND_SYNC_READWRITE)
197 sync_read = 1; 192 onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
198 sync_write = 1;
199 } else
200 return omap2_onenand_set_async_mode(cs, onenand_base);
201
202 if (!freq) {
203 /* Very first call freq is not known */
204 err = omap2_onenand_set_async_mode(cs, onenand_base);
205 if (err)
206 return err;
207 freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
208 first_time = 1;
209 }
210 193
211 switch (freq) { 194 switch (freq) {
212 case 104: 195 case 104:
@@ -244,44 +227,31 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
244 t_ach = 9; 227 t_ach = 9;
245 t_aavdh = 7; 228 t_aavdh = 7;
246 t_rdyo = 15; 229 t_rdyo = 15;
247 sync_write = 0; 230 onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
248 break; 231 break;
249 } 232 }
250 233
251 div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period); 234 div = gpmc_calc_divider(min_gpmc_clk_period);
252 gpmc_clk_ns = gpmc_ticks_to_ns(div); 235 gpmc_clk_ns = gpmc_ticks_to_ns(div);
253 if (gpmc_clk_ns < 15) /* >66Mhz */ 236 if (gpmc_clk_ns < 15) /* >66Mhz */
254 hf = 1; 237 onenand_flags |= ONENAND_FLAG_HF;
238 else
239 onenand_flags &= ~ONENAND_FLAG_HF;
255 if (gpmc_clk_ns < 12) /* >83Mhz */ 240 if (gpmc_clk_ns < 12) /* >83Mhz */
256 vhf = 1; 241 onenand_flags |= ONENAND_FLAG_VHF;
257 if (vhf) 242 else
243 onenand_flags &= ~ONENAND_FLAG_VHF;
244 if (onenand_flags & ONENAND_FLAG_VHF)
258 latency = 8; 245 latency = 8;
259 else if (hf) 246 else if (onenand_flags & ONENAND_FLAG_HF)
260 latency = 6; 247 latency = 6;
261 else if (gpmc_clk_ns >= 25) /* 40 MHz*/ 248 else if (gpmc_clk_ns >= 25) /* 40 MHz*/
262 latency = 3; 249 latency = 3;
263 else 250 else
264 latency = 4; 251 latency = 4;
265 252
266 if (clk_dep) { 253 /* Set synchronous read timings */
267 if (gpmc_clk_ns < 12) { /* >83Mhz */ 254 memset(&t, 0, sizeof(t));
268 t_ces = 3;
269 t_avds = 4;
270 } else if (gpmc_clk_ns < 15) { /* >66Mhz */
271 t_ces = 5;
272 t_avds = 4;
273 } else if (gpmc_clk_ns < 25) { /* >40Mhz */
274 t_ces = 6;
275 t_avds = 5;
276 } else {
277 t_ces = 7;
278 t_avds = 7;
279 }
280 }
281
282 if (first_time)
283 set_onenand_cfg(onenand_base, latency,
284 sync_read, sync_write, hf, vhf);
285 255
286 if (div == 1) { 256 if (div == 1) {
287 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2); 257 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
@@ -307,8 +277,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
307 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg); 277 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
308 } 278 }
309 279
310 /* Set synchronous read timings */
311 memset(&t, 0, sizeof(t));
312 t.sync_clk = min_gpmc_clk_period; 280 t.sync_clk = min_gpmc_clk_period;
313 t.cs_on = 0; 281 t.cs_on = 0;
314 t.adv_on = 0; 282 t.adv_on = 0;
@@ -330,7 +298,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
330 ticks_cez); 298 ticks_cez);
331 299
332 /* Write */ 300 /* Write */
333 if (sync_write) { 301 if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
334 t.adv_wr_off = t.adv_rd_off; 302 t.adv_wr_off = t.adv_rd_off;
335 t.we_on = 0; 303 t.we_on = 0;
336 t.we_off = t.cs_rd_off; 304 t.we_off = t.cs_rd_off;
@@ -355,6 +323,14 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
355 } 323 }
356 } 324 }
357 325
326 return t;
327}
328
329static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t)
330{
331 unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD;
332 unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE;
333
358 /* Configure GPMC for synchronous read */ 334 /* Configure GPMC for synchronous read */
359 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, 335 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
360 GPMC_CONFIG1_WRAPBURST_SUPP | 336 GPMC_CONFIG1_WRAPBURST_SUPP |
@@ -371,11 +347,45 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
371 GPMC_CONFIG1_DEVICETYPE_NOR | 347 GPMC_CONFIG1_DEVICETYPE_NOR |
372 GPMC_CONFIG1_MUXADDDATA); 348 GPMC_CONFIG1_MUXADDDATA);
373 349
374 err = gpmc_cs_set_timings(cs, &t); 350 return gpmc_cs_set_timings(cs, t);
375 if (err) 351}
376 return err; 352
353static int omap2_onenand_setup_async(void __iomem *onenand_base)
354{
355 struct gpmc_timings t;
356 int ret;
357
358 omap2_onenand_set_async_mode(onenand_base);
377 359
378 set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf); 360 t = omap2_onenand_calc_async_timings();
361
362 ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t);
363 if (IS_ERR_VALUE(ret))
364 return ret;
365
366 omap2_onenand_set_async_mode(onenand_base);
367
368 return 0;
369}
370
371static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
372{
373 int ret, freq = *freq_ptr;
374 struct gpmc_timings t;
375
376 if (!freq) {
377 /* Very first call freq is not known */
378 freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
379 set_onenand_cfg(onenand_base);
380 }
381
382 t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq);
383
384 ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t);
385 if (IS_ERR_VALUE(ret))
386 return ret;
387
388 set_onenand_cfg(onenand_base);
379 389
380 *freq_ptr = freq; 390 *freq_ptr = freq;
381 391
@@ -385,15 +395,22 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
385static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) 395static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
386{ 396{
387 struct device *dev = &gpmc_onenand_device.dev; 397 struct device *dev = &gpmc_onenand_device.dev;
398 unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE;
399 int ret;
388 400
389 /* Set sync timings in GPMC */ 401 ret = omap2_onenand_setup_async(onenand_base);
390 if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base, 402 if (ret) {
391 freq_ptr) < 0) { 403 dev_err(dev, "unable to set to async mode\n");
392 dev_err(dev, "Unable to set synchronous mode\n"); 404 return ret;
393 return -EINVAL;
394 } 405 }
395 406
396 return 0; 407 if (!(gpmc_onenand_data->flags & l))
408 return 0;
409
410 ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
411 if (ret)
412 dev_err(dev, "unable to set to sync mode\n");
413 return ret;
397} 414}
398 415
399void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) 416void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
@@ -411,6 +428,11 @@ void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
411 gpmc_onenand_data->flags |= ONENAND_SYNC_READ; 428 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
412 } 429 }
413 430
431 if (cpu_is_omap34xx())
432 gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX;
433 else
434 gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;
435
414 err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE, 436 err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
415 (unsigned long *)&gpmc_onenand_resource.start); 437 (unsigned long *)&gpmc_onenand_resource.start);
416 if (err < 0) { 438 if (err < 0) {
diff --git a/arch/arm/mach-omap2/gpmc-onenand.h b/arch/arm/mach-omap2/gpmc-onenand.h
new file mode 100644
index 000000000000..216f23a8b45c
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc-onenand.h
@@ -0,0 +1,24 @@
1/*
2 * arch/arm/mach-omap2/gpmc-onenand.h
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __OMAP2_GPMC_ONENAND_H
11#define __OMAP2_GPMC_ONENAND_H
12
13#include <linux/platform_data/mtd-onenand-omap2.h>
14
15#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
16extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
17#else
18#define board_onenand_data NULL
19static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
20{
21}
22#endif
23
24#endif
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index 565475310374..6eed907d594c 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -17,7 +17,7 @@
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/smc91x.h> 18#include <linux/smc91x.h>
19 19
20#include <plat/gpmc.h> 20#include "gpmc.h"
21#include "gpmc-smc91x.h" 21#include "gpmc-smc91x.h"
22 22
23#include "soc.h" 23#include "soc.h"
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index 249a0b440cd6..ef990118d32b 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -20,7 +20,7 @@
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/smsc911x.h> 21#include <linux/smsc911x.h>
22 22
23#include <plat/gpmc.h> 23#include "gpmc.h"
24#include "gpmc-smsc911x.h" 24#include "gpmc-smsc911x.h"
25 25
26static struct resource gpmc_smsc911x_resources[] = { 26static struct resource gpmc_smsc911x_resources[] = {
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 5ac5cf30406a..f14bd3f55218 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -26,16 +26,17 @@
26#include <linux/interrupt.h> 26#include <linux/interrupt.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28 28
29#include <linux/platform_data/mtd-nand-omap2.h>
30
29#include <asm/mach-types.h> 31#include <asm/mach-types.h>
30#include <plat/gpmc.h>
31 32
32#include <plat/cpu.h> 33#include <plat/cpu.h>
33#include <plat/gpmc.h>
34#include <plat/sdrc.h> 34#include <plat/sdrc.h>
35#include <plat/omap_device.h> 35#include <plat/omap_device.h>
36 36
37#include "soc.h" 37#include "soc.h"
38#include "common.h" 38#include "common.h"
39#include "gpmc.h"
39 40
40#define DEVICE_NAME "omap-gpmc" 41#define DEVICE_NAME "omap-gpmc"
41 42
@@ -59,6 +60,9 @@
59#define GPMC_ECC_SIZE_CONFIG 0x1fc 60#define GPMC_ECC_SIZE_CONFIG 0x1fc
60#define GPMC_ECC1_RESULT 0x200 61#define GPMC_ECC1_RESULT 0x200
61#define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ 62#define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
63#define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
64#define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
65#define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
62 66
63/* GPMC ECC control settings */ 67/* GPMC ECC control settings */
64#define GPMC_ECC_CTRL_ECCCLEAR 0x100 68#define GPMC_ECC_CTRL_ECCCLEAR 0x100
@@ -75,6 +79,7 @@
75 79
76#define GPMC_CS0_OFFSET 0x60 80#define GPMC_CS0_OFFSET 0x60
77#define GPMC_CS_SIZE 0x30 81#define GPMC_CS_SIZE 0x30
82#define GPMC_BCH_SIZE 0x10
78 83
79#define GPMC_MEM_START 0x00000000 84#define GPMC_MEM_START 0x00000000
80#define GPMC_MEM_END 0x3FFFFFFF 85#define GPMC_MEM_END 0x3FFFFFFF
@@ -137,7 +142,6 @@ static struct resource gpmc_mem_root;
137static struct resource gpmc_cs_mem[GPMC_CS_NUM]; 142static struct resource gpmc_cs_mem[GPMC_CS_NUM];
138static DEFINE_SPINLOCK(gpmc_mem_lock); 143static DEFINE_SPINLOCK(gpmc_mem_lock);
139static unsigned int gpmc_cs_map; /* flag for cs which are initialized */ 144static unsigned int gpmc_cs_map; /* flag for cs which are initialized */
140static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */
141static struct device *gpmc_dev; 145static struct device *gpmc_dev;
142static int gpmc_irq; 146static int gpmc_irq;
143static resource_size_t phys_base, mem_size; 147static resource_size_t phys_base, mem_size;
@@ -158,22 +162,6 @@ static u32 gpmc_read_reg(int idx)
158 return __raw_readl(gpmc_base + idx); 162 return __raw_readl(gpmc_base + idx);
159} 163}
160 164
161static void gpmc_cs_write_byte(int cs, int idx, u8 val)
162{
163 void __iomem *reg_addr;
164
165 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
166 __raw_writeb(val, reg_addr);
167}
168
169static u8 gpmc_cs_read_byte(int cs, int idx)
170{
171 void __iomem *reg_addr;
172
173 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
174 return __raw_readb(reg_addr);
175}
176
177void gpmc_cs_write_reg(int cs, int idx, u32 val) 165void gpmc_cs_write_reg(int cs, int idx, u32 val)
178{ 166{
179 void __iomem *reg_addr; 167 void __iomem *reg_addr;
@@ -288,7 +276,7 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
288 return -1 276 return -1
289#endif 277#endif
290 278
291int gpmc_cs_calc_divider(int cs, unsigned int sync_clk) 279int gpmc_calc_divider(unsigned int sync_clk)
292{ 280{
293 int div; 281 int div;
294 u32 l; 282 u32 l;
@@ -308,7 +296,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
308 int div; 296 int div;
309 u32 l; 297 u32 l;
310 298
311 div = gpmc_cs_calc_divider(cs, t->sync_clk); 299 div = gpmc_calc_divider(t->sync_clk);
312 if (div < 0) 300 if (div < 0)
313 return div; 301 return div;
314 302
@@ -509,44 +497,6 @@ void gpmc_cs_free(int cs)
509EXPORT_SYMBOL(gpmc_cs_free); 497EXPORT_SYMBOL(gpmc_cs_free);
510 498
511/** 499/**
512 * gpmc_read_status - read access request to get the different gpmc status
513 * @cmd: command type
514 * @return status
515 */
516int gpmc_read_status(int cmd)
517{
518 int status = -EINVAL;
519 u32 regval = 0;
520
521 switch (cmd) {
522 case GPMC_GET_IRQ_STATUS:
523 status = gpmc_read_reg(GPMC_IRQSTATUS);
524 break;
525
526 case GPMC_PREFETCH_FIFO_CNT:
527 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
528 status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
529 break;
530
531 case GPMC_PREFETCH_COUNT:
532 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
533 status = GPMC_PREFETCH_STATUS_COUNT(regval);
534 break;
535
536 case GPMC_STATUS_BUFFER:
537 regval = gpmc_read_reg(GPMC_STATUS);
538 /* 1 : buffer is available to write */
539 status = regval & GPMC_STATUS_BUFF_EMPTY;
540 break;
541
542 default:
543 printk(KERN_ERR "gpmc_read_status: Not supported\n");
544 }
545 return status;
546}
547EXPORT_SYMBOL(gpmc_read_status);
548
549/**
550 * gpmc_cs_configure - write request to configure gpmc 500 * gpmc_cs_configure - write request to configure gpmc
551 * @cs: chip select number 501 * @cs: chip select number
552 * @cmd: command type 502 * @cmd: command type
@@ -614,121 +564,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
614} 564}
615EXPORT_SYMBOL(gpmc_cs_configure); 565EXPORT_SYMBOL(gpmc_cs_configure);
616 566
617/**
618 * gpmc_nand_read - nand specific read access request
619 * @cs: chip select number
620 * @cmd: command type
621 */
622int gpmc_nand_read(int cs, int cmd)
623{
624 int rval = -EINVAL;
625
626 switch (cmd) {
627 case GPMC_NAND_DATA:
628 rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
629 break;
630
631 default:
632 printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
633 }
634 return rval;
635}
636EXPORT_SYMBOL(gpmc_nand_read);
637
638/**
639 * gpmc_nand_write - nand specific write request
640 * @cs: chip select number
641 * @cmd: command type
642 * @wval: value to write
643 */
644int gpmc_nand_write(int cs, int cmd, int wval)
645{
646 int err = 0;
647
648 switch (cmd) {
649 case GPMC_NAND_COMMAND:
650 gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
651 break;
652
653 case GPMC_NAND_ADDRESS:
654 gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
655 break;
656
657 case GPMC_NAND_DATA:
658 gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
659
660 default:
661 printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
662 err = -EINVAL;
663 }
664 return err;
665}
666EXPORT_SYMBOL(gpmc_nand_write);
667
668
669
670/**
671 * gpmc_prefetch_enable - configures and starts prefetch transfer
672 * @cs: cs (chip select) number
673 * @fifo_th: fifo threshold to be used for read/ write
674 * @dma_mode: dma mode enable (1) or disable (0)
675 * @u32_count: number of bytes to be transferred
676 * @is_write: prefetch read(0) or write post(1) mode
677 */
678int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
679 unsigned int u32_count, int is_write)
680{
681
682 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
683 pr_err("gpmc: fifo threshold is not supported\n");
684 return -1;
685 } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
686 /* Set the amount of bytes to be prefetched */
687 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
688
689 /* Set dma/mpu mode, the prefetch read / post write and
690 * enable the engine. Set which cs is has requested for.
691 */
692 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
693 PREFETCH_FIFOTHRESHOLD(fifo_th) |
694 ENABLE_PREFETCH |
695 (dma_mode << DMA_MPU_MODE) |
696 (0x1 & is_write)));
697
698 /* Start the prefetch engine */
699 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
700 } else {
701 return -EBUSY;
702 }
703
704 return 0;
705}
706EXPORT_SYMBOL(gpmc_prefetch_enable);
707
708/**
709 * gpmc_prefetch_reset - disables and stops the prefetch engine
710 */
711int gpmc_prefetch_reset(int cs)
712{
713 u32 config1;
714
715 /* check if the same module/cs is trying to reset */
716 config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
717 if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
718 return -EINVAL;
719
720 /* Stop the PFPW engine */
721 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
722
723 /* Reset/disable the PFPW engine */
724 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
725
726 return 0;
727}
728EXPORT_SYMBOL(gpmc_prefetch_reset);
729
730void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) 567void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
731{ 568{
569 int i;
570
732 reg->gpmc_status = gpmc_base + GPMC_STATUS; 571 reg->gpmc_status = gpmc_base + GPMC_STATUS;
733 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + 572 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
734 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; 573 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
@@ -744,7 +583,17 @@ void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
744 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; 583 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
745 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; 584 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
746 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; 585 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
747 reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0; 586
587 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
588 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
589 GPMC_BCH_SIZE * i;
590 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
591 GPMC_BCH_SIZE * i;
592 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
593 GPMC_BCH_SIZE * i;
594 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
595 GPMC_BCH_SIZE * i;
596 }
748} 597}
749 598
750int gpmc_get_client_irq(unsigned irq_config) 599int gpmc_get_client_irq(unsigned irq_config)
@@ -1079,267 +928,3 @@ void omap3_gpmc_restore_context(void)
1079 } 928 }
1080} 929}
1081#endif /* CONFIG_ARCH_OMAP3 */ 930#endif /* CONFIG_ARCH_OMAP3 */
1082
1083/**
1084 * gpmc_enable_hwecc - enable hardware ecc functionality
1085 * @cs: chip select number
1086 * @mode: read/write mode
1087 * @dev_width: device bus width(1 for x16, 0 for x8)
1088 * @ecc_size: bytes for which ECC will be generated
1089 */
1090int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
1091{
1092 unsigned int val;
1093
1094 /* check if ecc module is in used */
1095 if (gpmc_ecc_used != -EINVAL)
1096 return -EINVAL;
1097
1098 gpmc_ecc_used = cs;
1099
1100 /* clear ecc and enable bits */
1101 gpmc_write_reg(GPMC_ECC_CONTROL,
1102 GPMC_ECC_CTRL_ECCCLEAR |
1103 GPMC_ECC_CTRL_ECCREG1);
1104
1105 /* program ecc and result sizes */
1106 val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
1107 gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
1108
1109 switch (mode) {
1110 case GPMC_ECC_READ:
1111 case GPMC_ECC_WRITE:
1112 gpmc_write_reg(GPMC_ECC_CONTROL,
1113 GPMC_ECC_CTRL_ECCCLEAR |
1114 GPMC_ECC_CTRL_ECCREG1);
1115 break;
1116 case GPMC_ECC_READSYN:
1117 gpmc_write_reg(GPMC_ECC_CONTROL,
1118 GPMC_ECC_CTRL_ECCCLEAR |
1119 GPMC_ECC_CTRL_ECCDISABLE);
1120 break;
1121 default:
1122 printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
1123 break;
1124 }
1125
1126 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
1127 val = (dev_width << 7) | (cs << 1) | (0x1);
1128 gpmc_write_reg(GPMC_ECC_CONFIG, val);
1129 return 0;
1130}
1131EXPORT_SYMBOL_GPL(gpmc_enable_hwecc);
1132
1133/**
1134 * gpmc_calculate_ecc - generate non-inverted ecc bytes
1135 * @cs: chip select number
1136 * @dat: data pointer over which ecc is computed
1137 * @ecc_code: ecc code buffer
1138 *
1139 * Using non-inverted ECC is considered ugly since writing a blank
1140 * page (padding) will clear the ECC bytes. This is not a problem as long
1141 * no one is trying to write data on the seemingly unused page. Reading
1142 * an erased page will produce an ECC mismatch between generated and read
1143 * ECC bytes that has to be dealt with separately.
1144 */
1145int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
1146{
1147 unsigned int val = 0x0;
1148
1149 if (gpmc_ecc_used != cs)
1150 return -EINVAL;
1151
1152 /* read ecc result */
1153 val = gpmc_read_reg(GPMC_ECC1_RESULT);
1154 *ecc_code++ = val; /* P128e, ..., P1e */
1155 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
1156 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
1157 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
1158
1159 gpmc_ecc_used = -EINVAL;
1160 return 0;
1161}
1162EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
1163
1164#ifdef CONFIG_ARCH_OMAP3
1165
1166/**
1167 * gpmc_init_hwecc_bch - initialize hardware BCH ecc functionality
1168 * @cs: chip select number
1169 * @nsectors: how many 512-byte sectors to process
1170 * @nerrors: how many errors to correct per sector (4 or 8)
1171 *
1172 * This function must be executed before any call to gpmc_enable_hwecc_bch.
1173 */
1174int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors)
1175{
1176 /* check if ecc module is in use */
1177 if (gpmc_ecc_used != -EINVAL)
1178 return -EINVAL;
1179
1180 /* support only OMAP3 class */
1181 if (!cpu_is_omap34xx()) {
1182 printk(KERN_ERR "BCH ecc is not supported on this CPU\n");
1183 return -EINVAL;
1184 }
1185
1186 /*
1187 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
1188 * Other chips may be added if confirmed to work.
1189 */
1190 if ((nerrors == 4) &&
1191 (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
1192 printk(KERN_ERR "BCH 4-bit mode is not supported on this CPU\n");
1193 return -EINVAL;
1194 }
1195
1196 /* sanity check */
1197 if (nsectors > 8) {
1198 printk(KERN_ERR "BCH cannot process %d sectors (max is 8)\n",
1199 nsectors);
1200 return -EINVAL;
1201 }
1202
1203 return 0;
1204}
1205EXPORT_SYMBOL_GPL(gpmc_init_hwecc_bch);
1206
1207/**
1208 * gpmc_enable_hwecc_bch - enable hardware BCH ecc functionality
1209 * @cs: chip select number
1210 * @mode: read/write mode
1211 * @dev_width: device bus width(1 for x16, 0 for x8)
1212 * @nsectors: how many 512-byte sectors to process
1213 * @nerrors: how many errors to correct per sector (4 or 8)
1214 */
1215int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors,
1216 int nerrors)
1217{
1218 unsigned int val;
1219
1220 /* check if ecc module is in use */
1221 if (gpmc_ecc_used != -EINVAL)
1222 return -EINVAL;
1223
1224 gpmc_ecc_used = cs;
1225
1226 /* clear ecc and enable bits */
1227 gpmc_write_reg(GPMC_ECC_CONTROL, 0x1);
1228
1229 /*
1230 * When using BCH, sector size is hardcoded to 512 bytes.
1231 * Here we are using wrapping mode 6 both for reading and writing, with:
1232 * size0 = 0 (no additional protected byte in spare area)
1233 * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1234 */
1235 gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, (32 << 22) | (0 << 12));
1236
1237 /* BCH configuration */
1238 val = ((1 << 16) | /* enable BCH */
1239 (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
1240 (0x06 << 8) | /* wrap mode = 6 */
1241 (dev_width << 7) | /* bus width */
1242 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1243 (cs << 1) | /* ECC CS */
1244 (0x1)); /* enable ECC */
1245
1246 gpmc_write_reg(GPMC_ECC_CONFIG, val);
1247 gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
1248 return 0;
1249}
1250EXPORT_SYMBOL_GPL(gpmc_enable_hwecc_bch);
1251
1252/**
1253 * gpmc_calculate_ecc_bch4 - Generate 7 ecc bytes per sector of 512 data bytes
1254 * @cs: chip select number
1255 * @dat: The pointer to data on which ecc is computed
1256 * @ecc: The ecc output buffer
1257 */
1258int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc)
1259{
1260 int i;
1261 unsigned long nsectors, reg, val1, val2;
1262
1263 if (gpmc_ecc_used != cs)
1264 return -EINVAL;
1265
1266 nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
1267
1268 for (i = 0; i < nsectors; i++) {
1269
1270 reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
1271
1272 /* Read hw-computed remainder */
1273 val1 = gpmc_read_reg(reg + 0);
1274 val2 = gpmc_read_reg(reg + 4);
1275
1276 /*
1277 * Add constant polynomial to remainder, in order to get an ecc
1278 * sequence of 0xFFs for a buffer filled with 0xFFs; and
1279 * left-justify the resulting polynomial.
1280 */
1281 *ecc++ = 0x28 ^ ((val2 >> 12) & 0xFF);
1282 *ecc++ = 0x13 ^ ((val2 >> 4) & 0xFF);
1283 *ecc++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
1284 *ecc++ = 0x39 ^ ((val1 >> 20) & 0xFF);
1285 *ecc++ = 0x96 ^ ((val1 >> 12) & 0xFF);
1286 *ecc++ = 0xac ^ ((val1 >> 4) & 0xFF);
1287 *ecc++ = 0x7f ^ ((val1 & 0xF) << 4);
1288 }
1289
1290 gpmc_ecc_used = -EINVAL;
1291 return 0;
1292}
1293EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch4);
1294
1295/**
1296 * gpmc_calculate_ecc_bch8 - Generate 13 ecc bytes per block of 512 data bytes
1297 * @cs: chip select number
1298 * @dat: The pointer to data on which ecc is computed
1299 * @ecc: The ecc output buffer
1300 */
1301int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc)
1302{
1303 int i;
1304 unsigned long nsectors, reg, val1, val2, val3, val4;
1305
1306 if (gpmc_ecc_used != cs)
1307 return -EINVAL;
1308
1309 nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
1310
1311 for (i = 0; i < nsectors; i++) {
1312
1313 reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
1314
1315 /* Read hw-computed remainder */
1316 val1 = gpmc_read_reg(reg + 0);
1317 val2 = gpmc_read_reg(reg + 4);
1318 val3 = gpmc_read_reg(reg + 8);
1319 val4 = gpmc_read_reg(reg + 12);
1320
1321 /*
1322 * Add constant polynomial to remainder, in order to get an ecc
1323 * sequence of 0xFFs for a buffer filled with 0xFFs.
1324 */
1325 *ecc++ = 0xef ^ (val4 & 0xFF);
1326 *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
1327 *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
1328 *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
1329 *ecc++ = 0xed ^ (val3 & 0xFF);
1330 *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
1331 *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
1332 *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
1333 *ecc++ = 0x97 ^ (val2 & 0xFF);
1334 *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
1335 *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
1336 *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
1337 *ecc++ = 0xb5 ^ (val1 & 0xFF);
1338 }
1339
1340 gpmc_ecc_used = -EINVAL;
1341 return 0;
1342}
1343EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch8);
1344
1345#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/mach-omap2/gpmc.h
index 2e6e2597178c..79f4dfc2adb3 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/mach-omap2/gpmc.h
@@ -11,6 +11,8 @@
11#ifndef __OMAP2_GPMC_H 11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H 12#define __OMAP2_GPMC_H
13 13
14#include <linux/platform_data/mtd-nand-omap2.h>
15
14/* Maximum Number of Chip Selects */ 16/* Maximum Number of Chip Selects */
15#define GPMC_CS_NUM 8 17#define GPMC_CS_NUM 8
16 18
@@ -32,15 +34,6 @@
32#define GPMC_SET_IRQ_STATUS 0x00000004 34#define GPMC_SET_IRQ_STATUS 0x00000004
33#define GPMC_CONFIG_WP 0x00000005 35#define GPMC_CONFIG_WP 0x00000005
34 36
35#define GPMC_GET_IRQ_STATUS 0x00000006
36#define GPMC_PREFETCH_FIFO_CNT 0x00000007 /* bytes available in FIFO for r/w */
37#define GPMC_PREFETCH_COUNT 0x00000008 /* remaining bytes to be read/write*/
38#define GPMC_STATUS_BUFFER 0x00000009 /* 1: buffer is available to write */
39
40#define GPMC_NAND_COMMAND 0x0000000a
41#define GPMC_NAND_ADDRESS 0x0000000b
42#define GPMC_NAND_DATA 0x0000000c
43
44#define GPMC_ENABLE_IRQ 0x0000000d 37#define GPMC_ENABLE_IRQ 0x0000000d
45 38
46/* ECC commands */ 39/* ECC commands */
@@ -76,25 +69,10 @@
76#define GPMC_DEVICETYPE_NOR 0 69#define GPMC_DEVICETYPE_NOR 0
77#define GPMC_DEVICETYPE_NAND 2 70#define GPMC_DEVICETYPE_NAND 2
78#define GPMC_CONFIG_WRITEPROTECT 0x00000010 71#define GPMC_CONFIG_WRITEPROTECT 0x00000010
79#define GPMC_STATUS_BUFF_EMPTY 0x00000001
80#define WR_RD_PIN_MONITORING 0x00600000 72#define WR_RD_PIN_MONITORING 0x00600000
81#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
82#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
83#define GPMC_IRQ_FIFOEVENTENABLE 0x01 73#define GPMC_IRQ_FIFOEVENTENABLE 0x01
84#define GPMC_IRQ_COUNT_EVENT 0x02 74#define GPMC_IRQ_COUNT_EVENT 0x02
85 75
86#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
87#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
88
89enum omap_ecc {
90 /* 1-bit ecc: stored at end of spare area */
91 OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
92 OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
93 /* 1-bit ecc: stored at beginning of spare area as romcode */
94 OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
95 OMAP_ECC_BCH4_CODE_HW, /* 4-bit BCH ecc code */
96 OMAP_ECC_BCH8_CODE_HW, /* 8-bit BCH ecc code */
97};
98 76
99/* 77/*
100 * Note that all values in this struct are in nanoseconds except sync_clk 78 * Note that all values in this struct are in nanoseconds except sync_clk
@@ -133,22 +111,6 @@ struct gpmc_timings {
133 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */ 111 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
134}; 112};
135 113
136struct gpmc_nand_regs {
137 void __iomem *gpmc_status;
138 void __iomem *gpmc_nand_command;
139 void __iomem *gpmc_nand_address;
140 void __iomem *gpmc_nand_data;
141 void __iomem *gpmc_prefetch_config1;
142 void __iomem *gpmc_prefetch_config2;
143 void __iomem *gpmc_prefetch_control;
144 void __iomem *gpmc_prefetch_status;
145 void __iomem *gpmc_ecc_config;
146 void __iomem *gpmc_ecc_control;
147 void __iomem *gpmc_ecc_size_config;
148 void __iomem *gpmc_ecc1_result;
149 void __iomem *gpmc_bch_result0;
150};
151
152extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs); 114extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
153extern int gpmc_get_client_irq(unsigned irq_config); 115extern int gpmc_get_client_irq(unsigned irq_config);
154 116
@@ -160,31 +122,14 @@ extern unsigned long gpmc_get_fclk_period(void);
160 122
161extern void gpmc_cs_write_reg(int cs, int idx, u32 val); 123extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
162extern u32 gpmc_cs_read_reg(int cs, int idx); 124extern u32 gpmc_cs_read_reg(int cs, int idx);
163extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk); 125extern int gpmc_calc_divider(unsigned int sync_clk);
164extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); 126extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
165extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); 127extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
166extern void gpmc_cs_free(int cs); 128extern void gpmc_cs_free(int cs);
167extern int gpmc_cs_set_reserved(int cs, int reserved); 129extern int gpmc_cs_set_reserved(int cs, int reserved);
168extern int gpmc_cs_reserved(int cs); 130extern int gpmc_cs_reserved(int cs);
169extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
170 unsigned int u32_count, int is_write);
171extern int gpmc_prefetch_reset(int cs);
172extern void omap3_gpmc_save_context(void); 131extern void omap3_gpmc_save_context(void);
173extern void omap3_gpmc_restore_context(void); 132extern void omap3_gpmc_restore_context(void);
174extern int gpmc_read_status(int cmd);
175extern int gpmc_cs_configure(int cs, int cmd, int wval); 133extern int gpmc_cs_configure(int cs, int cmd, int wval);
176extern int gpmc_nand_read(int cs, int cmd);
177extern int gpmc_nand_write(int cs, int cmd, int wval);
178
179int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size);
180int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code);
181
182#ifdef CONFIG_ARCH_OMAP3
183int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors);
184int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors,
185 int nerrors);
186int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc);
187int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc);
188#endif /* CONFIG_ARCH_OMAP3 */
189 134
190#endif 135#endif
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index ba670db1fd37..ed98f4f9e667 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -40,7 +40,7 @@
40#include "powerdomain.h" 40#include "powerdomain.h"
41#include <plat/sdrc.h> 41#include <plat/sdrc.h>
42#include <plat/prcm.h> 42#include <plat/prcm.h>
43#include <plat/gpmc.h> 43#include "gpmc.h"
44#include <plat/dma.h> 44#include <plat/dma.h>
45 45
46#include "common.h" 46#include "common.h"
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 805bea6edf17..6064425ed47b 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -18,7 +18,7 @@
18 18
19#include <linux/usb/musb.h> 19#include <linux/usb/musb.h>
20 20
21#include <plat/gpmc.h> 21#include "gpmc.h"
22 22
23#include "mux.h" 23#include "mux.h"
24 24
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 5b3138620646..3282b151aa03 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -28,7 +28,6 @@
28#endif 28#endif
29 29
30#include <plat/dma.h> 30#include <plat/dma.h>
31#include <plat/gpmc.h>
32#include <linux/platform_data/mtd-nand-omap2.h> 31#include <linux/platform_data/mtd-nand-omap2.h>
33 32
34#define DRIVER_NAME "omap2-nand" 33#define DRIVER_NAME "omap2-nand"
@@ -106,10 +105,16 @@
106#define CS_MASK 0x7 105#define CS_MASK 0x7
107#define ENABLE_PREFETCH (0x1 << 7) 106#define ENABLE_PREFETCH (0x1 << 7)
108#define DMA_MPU_MODE_SHIFT 2 107#define DMA_MPU_MODE_SHIFT 2
108#define ECCSIZE0_SHIFT 12
109#define ECCSIZE1_SHIFT 22 109#define ECCSIZE1_SHIFT 22
110#define ECC1RESULTSIZE 0x1 110#define ECC1RESULTSIZE 0x1
111#define ECCCLEAR 0x100 111#define ECCCLEAR 0x100
112#define ECC1 0x1 112#define ECC1 0x1
113#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
114#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
115#define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
116#define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
117#define STATUS_BUFF_EMPTY 0x00000001
113 118
114/* oob info generated runtime depending on ecc algorithm and layout selected */ 119/* oob info generated runtime depending on ecc algorithm and layout selected */
115static struct nand_ecclayout omap_oobinfo; 120static struct nand_ecclayout omap_oobinfo;
@@ -269,7 +274,7 @@ static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
269 /* wait until buffer is available for write */ 274 /* wait until buffer is available for write */
270 do { 275 do {
271 status = readl(info->reg.gpmc_status) & 276 status = readl(info->reg.gpmc_status) &
272 GPMC_STATUS_BUFF_EMPTY; 277 STATUS_BUFF_EMPTY;
273 } while (!status); 278 } while (!status);
274 } 279 }
275} 280}
@@ -307,7 +312,7 @@ static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
307 /* wait until buffer is available for write */ 312 /* wait until buffer is available for write */
308 do { 313 do {
309 status = readl(info->reg.gpmc_status) & 314 status = readl(info->reg.gpmc_status) &
310 GPMC_STATUS_BUFF_EMPTY; 315 STATUS_BUFF_EMPTY;
311 } while (!status); 316 } while (!status);
312 } 317 }
313} 318}
@@ -348,7 +353,7 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
348 } else { 353 } else {
349 do { 354 do {
350 r_count = readl(info->reg.gpmc_prefetch_status); 355 r_count = readl(info->reg.gpmc_prefetch_status);
351 r_count = GPMC_PREFETCH_STATUS_FIFO_CNT(r_count); 356 r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
352 r_count = r_count >> 2; 357 r_count = r_count >> 2;
353 ioread32_rep(info->nand.IO_ADDR_R, p, r_count); 358 ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
354 p += r_count; 359 p += r_count;
@@ -395,7 +400,7 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
395 } else { 400 } else {
396 while (len) { 401 while (len) {
397 w_count = readl(info->reg.gpmc_prefetch_status); 402 w_count = readl(info->reg.gpmc_prefetch_status);
398 w_count = GPMC_PREFETCH_STATUS_FIFO_CNT(w_count); 403 w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
399 w_count = w_count >> 1; 404 w_count = w_count >> 1;
400 for (i = 0; (i < w_count) && len; i++, len -= 2) 405 for (i = 0; (i < w_count) && len; i++, len -= 2)
401 iowrite16(*p++, info->nand.IO_ADDR_W); 406 iowrite16(*p++, info->nand.IO_ADDR_W);
@@ -407,7 +412,7 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
407 do { 412 do {
408 cpu_relax(); 413 cpu_relax();
409 val = readl(info->reg.gpmc_prefetch_status); 414 val = readl(info->reg.gpmc_prefetch_status);
410 val = GPMC_PREFETCH_STATUS_COUNT(val); 415 val = PREFETCH_STATUS_COUNT(val);
411 } while (val && (tim++ < limit)); 416 } while (val && (tim++ < limit));
412 417
413 /* disable and stop the PFPW engine */ 418 /* disable and stop the PFPW engine */
@@ -493,7 +498,7 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
493 do { 498 do {
494 cpu_relax(); 499 cpu_relax();
495 val = readl(info->reg.gpmc_prefetch_status); 500 val = readl(info->reg.gpmc_prefetch_status);
496 val = GPMC_PREFETCH_STATUS_COUNT(val); 501 val = PREFETCH_STATUS_COUNT(val);
497 } while (val && (tim++ < limit)); 502 } while (val && (tim++ < limit));
498 503
499 /* disable and stop the PFPW engine */ 504 /* disable and stop the PFPW engine */
@@ -556,7 +561,7 @@ static irqreturn_t omap_nand_irq(int this_irq, void *dev)
556 u32 bytes; 561 u32 bytes;
557 562
558 bytes = readl(info->reg.gpmc_prefetch_status); 563 bytes = readl(info->reg.gpmc_prefetch_status);
559 bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(bytes); 564 bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
560 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ 565 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
561 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ 566 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
562 if (this_irq == info->gpmc_irq_count) 567 if (this_irq == info->gpmc_irq_count)
@@ -682,7 +687,7 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd,
682 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); 687 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
683 do { 688 do {
684 val = readl(info->reg.gpmc_prefetch_status); 689 val = readl(info->reg.gpmc_prefetch_status);
685 val = GPMC_PREFETCH_STATUS_COUNT(val); 690 val = PREFETCH_STATUS_COUNT(val);
686 cpu_relax(); 691 cpu_relax();
687 } while (val && (tim++ < limit)); 692 } while (val && (tim++ < limit));
688 693
@@ -996,7 +1001,7 @@ static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
996 cond_resched(); 1001 cond_resched();
997 } 1002 }
998 1003
999 status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA); 1004 status = readb(info->reg.gpmc_nand_data);
1000 return status; 1005 return status;
1001} 1006}
1002 1007
@@ -1029,19 +1034,45 @@ static int omap_dev_ready(struct mtd_info *mtd)
1029static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode) 1034static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1030{ 1035{
1031 int nerrors; 1036 int nerrors;
1032 unsigned int dev_width; 1037 unsigned int dev_width, nsectors;
1033 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, 1038 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1034 mtd); 1039 mtd);
1035 struct nand_chip *chip = mtd->priv; 1040 struct nand_chip *chip = mtd->priv;
1041 u32 val;
1036 1042
1037 nerrors = (info->nand.ecc.bytes == 13) ? 8 : 4; 1043 nerrors = (info->nand.ecc.bytes == 13) ? 8 : 4;
1038 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; 1044 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1045 nsectors = 1;
1039 /* 1046 /*
1040 * Program GPMC to perform correction on one 512-byte sector at a time. 1047 * Program GPMC to perform correction on one 512-byte sector at a time.
1041 * Using 4 sectors at a time (i.e. ecc.size = 2048) is also possible and 1048 * Using 4 sectors at a time (i.e. ecc.size = 2048) is also possible and
1042 * gives a slight (5%) performance gain (but requires additional code). 1049 * gives a slight (5%) performance gain (but requires additional code).
1043 */ 1050 */
1044 (void)gpmc_enable_hwecc_bch(info->gpmc_cs, mode, dev_width, 1, nerrors); 1051
1052 writel(ECC1, info->reg.gpmc_ecc_control);
1053
1054 /*
1055 * When using BCH, sector size is hardcoded to 512 bytes.
1056 * Here we are using wrapping mode 6 both for reading and writing, with:
1057 * size0 = 0 (no additional protected byte in spare area)
1058 * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1059 */
1060 val = (32 << ECCSIZE1_SHIFT) | (0 << ECCSIZE0_SHIFT);
1061 writel(val, info->reg.gpmc_ecc_size_config);
1062
1063 /* BCH configuration */
1064 val = ((1 << 16) | /* enable BCH */
1065 (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
1066 (0x06 << 8) | /* wrap mode = 6 */
1067 (dev_width << 7) | /* bus width */
1068 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1069 (info->gpmc_cs << 1) | /* ECC CS */
1070 (0x1)); /* enable ECC */
1071
1072 writel(val, info->reg.gpmc_ecc_config);
1073
1074 /* clear ecc and enable bits */
1075 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1045} 1076}
1046 1077
1047/** 1078/**
@@ -1055,7 +1086,32 @@ static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat,
1055{ 1086{
1056 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, 1087 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1057 mtd); 1088 mtd);
1058 return gpmc_calculate_ecc_bch4(info->gpmc_cs, dat, ecc_code); 1089 unsigned long nsectors, val1, val2;
1090 int i;
1091
1092 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1093
1094 for (i = 0; i < nsectors; i++) {
1095
1096 /* Read hw-computed remainder */
1097 val1 = readl(info->reg.gpmc_bch_result0[i]);
1098 val2 = readl(info->reg.gpmc_bch_result1[i]);
1099
1100 /*
1101 * Add constant polynomial to remainder, in order to get an ecc
1102 * sequence of 0xFFs for a buffer filled with 0xFFs; and
1103 * left-justify the resulting polynomial.
1104 */
1105 *ecc_code++ = 0x28 ^ ((val2 >> 12) & 0xFF);
1106 *ecc_code++ = 0x13 ^ ((val2 >> 4) & 0xFF);
1107 *ecc_code++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
1108 *ecc_code++ = 0x39 ^ ((val1 >> 20) & 0xFF);
1109 *ecc_code++ = 0x96 ^ ((val1 >> 12) & 0xFF);
1110 *ecc_code++ = 0xac ^ ((val1 >> 4) & 0xFF);
1111 *ecc_code++ = 0x7f ^ ((val1 & 0xF) << 4);
1112 }
1113
1114 return 0;
1059} 1115}
1060 1116
1061/** 1117/**
@@ -1069,7 +1125,39 @@ static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat,
1069{ 1125{
1070 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, 1126 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1071 mtd); 1127 mtd);
1072 return gpmc_calculate_ecc_bch8(info->gpmc_cs, dat, ecc_code); 1128 unsigned long nsectors, val1, val2, val3, val4;
1129 int i;
1130
1131 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1132
1133 for (i = 0; i < nsectors; i++) {
1134
1135 /* Read hw-computed remainder */
1136 val1 = readl(info->reg.gpmc_bch_result0[i]);
1137 val2 = readl(info->reg.gpmc_bch_result1[i]);
1138 val3 = readl(info->reg.gpmc_bch_result2[i]);
1139 val4 = readl(info->reg.gpmc_bch_result3[i]);
1140
1141 /*
1142 * Add constant polynomial to remainder, in order to get an ecc
1143 * sequence of 0xFFs for a buffer filled with 0xFFs.
1144 */
1145 *ecc_code++ = 0xef ^ (val4 & 0xFF);
1146 *ecc_code++ = 0x51 ^ ((val3 >> 24) & 0xFF);
1147 *ecc_code++ = 0x2e ^ ((val3 >> 16) & 0xFF);
1148 *ecc_code++ = 0x09 ^ ((val3 >> 8) & 0xFF);
1149 *ecc_code++ = 0xed ^ (val3 & 0xFF);
1150 *ecc_code++ = 0x93 ^ ((val2 >> 24) & 0xFF);
1151 *ecc_code++ = 0x9a ^ ((val2 >> 16) & 0xFF);
1152 *ecc_code++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
1153 *ecc_code++ = 0x97 ^ (val2 & 0xFF);
1154 *ecc_code++ = 0x79 ^ ((val1 >> 24) & 0xFF);
1155 *ecc_code++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
1156 *ecc_code++ = 0x24 ^ ((val1 >> 8) & 0xFF);
1157 *ecc_code++ = 0xb5 ^ (val1 & 0xFF);
1158 }
1159
1160 return 0;
1073} 1161}
1074 1162
1075/** 1163/**
@@ -1125,7 +1213,7 @@ static void omap3_free_bch(struct mtd_info *mtd)
1125 */ 1213 */
1126static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt) 1214static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt)
1127{ 1215{
1128 int ret, max_errors; 1216 int max_errors;
1129 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, 1217 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1130 mtd); 1218 mtd);
1131#ifdef CONFIG_MTD_NAND_OMAP_BCH8 1219#ifdef CONFIG_MTD_NAND_OMAP_BCH8
@@ -1142,11 +1230,6 @@ static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt)
1142 goto fail; 1230 goto fail;
1143 } 1231 }
1144 1232
1145 /* initialize GPMC BCH engine */
1146 ret = gpmc_init_hwecc_bch(info->gpmc_cs, 1, max_errors);
1147 if (ret)
1148 goto fail;
1149
1150 /* software bch library is only used to detect and locate errors */ 1233 /* software bch library is only used to detect and locate errors */
1151 info->bch = init_bch(13, max_errors, 0x201b /* hw polynomial */); 1234 info->bch = init_bch(13, max_errors, 0x201b /* hw polynomial */);
1152 if (!info->bch) 1235 if (!info->bch)
@@ -1513,7 +1596,7 @@ static int omap_nand_remove(struct platform_device *pdev)
1513 /* Release NAND device, its internal structures and partitions */ 1596 /* Release NAND device, its internal structures and partitions */
1514 nand_release(&info->mtd); 1597 nand_release(&info->mtd);
1515 iounmap(info->nand.IO_ADDR_R); 1598 iounmap(info->nand.IO_ADDR_R);
1516 release_mem_region(info->phys_base, NAND_IO_SIZE); 1599 release_mem_region(info->phys_base, info->mem_size);
1517 kfree(info); 1600 kfree(info);
1518 return 0; 1601 return 0;
1519} 1602}
diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 1961be985171..959f465a0aa1 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -38,12 +38,10 @@
38#include <linux/regulator/consumer.h> 38#include <linux/regulator/consumer.h>
39 39
40#include <asm/mach/flash.h> 40#include <asm/mach/flash.h>
41#include <plat/gpmc.h>
42#include <linux/platform_data/mtd-onenand-omap2.h> 41#include <linux/platform_data/mtd-onenand-omap2.h>
43#include <asm/gpio.h> 42#include <asm/gpio.h>
44 43
45#include <plat/dma.h> 44#include <plat/dma.h>
46#include <plat/cpu.h>
47 45
48#define DRIVER_NAME "omap2-onenand" 46#define DRIVER_NAME "omap2-onenand"
49 47
@@ -63,6 +61,7 @@ struct omap2_onenand {
63 int freq; 61 int freq;
64 int (*setup)(void __iomem *base, int *freq_ptr); 62 int (*setup)(void __iomem *base, int *freq_ptr);
65 struct regulator *regulator; 63 struct regulator *regulator;
64 u8 flags;
66}; 65};
67 66
68static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data) 67static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
@@ -155,7 +154,7 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state)
155 if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) { 154 if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
156 syscfg |= ONENAND_SYS_CFG1_IOBE; 155 syscfg |= ONENAND_SYS_CFG1_IOBE;
157 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1); 156 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
158 if (cpu_is_omap34xx()) 157 if (c->flags & ONENAND_IN_OMAP34XX)
159 /* Add a delay to let GPIO settle */ 158 /* Add a delay to let GPIO settle */
160 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1); 159 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
161 } 160 }
@@ -639,6 +638,7 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev)
639 638
640 init_completion(&c->irq_done); 639 init_completion(&c->irq_done);
641 init_completion(&c->dma_done); 640 init_completion(&c->dma_done);
641 c->flags = pdata->flags;
642 c->gpmc_cs = pdata->cs; 642 c->gpmc_cs = pdata->cs;
643 c->gpio_irq = pdata->gpio_irq; 643 c->gpio_irq = pdata->gpio_irq;
644 c->dma_channel = pdata->dma_channel; 644 c->dma_channel = pdata->dma_channel;
@@ -729,7 +729,7 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev)
729 this = &c->onenand; 729 this = &c->onenand;
730 if (c->dma_channel >= 0) { 730 if (c->dma_channel >= 0) {
731 this->wait = omap2_onenand_wait; 731 this->wait = omap2_onenand_wait;
732 if (cpu_is_omap34xx()) { 732 if (c->flags & ONENAND_IN_OMAP34XX) {
733 this->read_bufferram = omap3_onenand_read_bufferram; 733 this->read_bufferram = omap3_onenand_read_bufferram;
734 this->write_bufferram = omap3_onenand_write_bufferram; 734 this->write_bufferram = omap3_onenand_write_bufferram;
735 } else { 735 } else {
@@ -803,7 +803,6 @@ static int __devexit omap2_onenand_remove(struct platform_device *pdev)
803 } 803 }
804 iounmap(c->onenand.base); 804 iounmap(c->onenand.base);
805 release_mem_region(c->phys_base, c->mem_size); 805 release_mem_region(c->phys_base, c->mem_size);
806 gpmc_cs_free(c->gpmc_cs);
807 kfree(c); 806 kfree(c);
808 807
809 return 0; 808 return 0;
diff --git a/include/linux/platform_data/mtd-nand-omap2.h b/include/linux/platform_data/mtd-nand-omap2.h
index 1a68c1e5fe53..24d32ca34bef 100644
--- a/include/linux/platform_data/mtd-nand-omap2.h
+++ b/include/linux/platform_data/mtd-nand-omap2.h
@@ -8,9 +8,13 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#include <plat/gpmc.h> 11#ifndef _MTD_NAND_OMAP2_H
12#define _MTD_NAND_OMAP2_H
13
12#include <linux/mtd/partitions.h> 14#include <linux/mtd/partitions.h>
13 15
16#define GPMC_BCH_NUM_REMAINDER 8
17
14enum nand_io { 18enum nand_io {
15 NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */ 19 NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */
16 NAND_OMAP_POLLED, /* polled mode, without prefetch */ 20 NAND_OMAP_POLLED, /* polled mode, without prefetch */
@@ -18,10 +22,38 @@ enum nand_io {
18 NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */ 22 NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */
19}; 23};
20 24
25enum omap_ecc {
26 /* 1-bit ecc: stored at end of spare area */
27 OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
28 OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
29 /* 1-bit ecc: stored at beginning of spare area as romcode */
30 OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
31 OMAP_ECC_BCH4_CODE_HW, /* 4-bit BCH ecc code */
32 OMAP_ECC_BCH8_CODE_HW, /* 8-bit BCH ecc code */
33};
34
35struct gpmc_nand_regs {
36 void __iomem *gpmc_status;
37 void __iomem *gpmc_nand_command;
38 void __iomem *gpmc_nand_address;
39 void __iomem *gpmc_nand_data;
40 void __iomem *gpmc_prefetch_config1;
41 void __iomem *gpmc_prefetch_config2;
42 void __iomem *gpmc_prefetch_control;
43 void __iomem *gpmc_prefetch_status;
44 void __iomem *gpmc_ecc_config;
45 void __iomem *gpmc_ecc_control;
46 void __iomem *gpmc_ecc_size_config;
47 void __iomem *gpmc_ecc1_result;
48 void __iomem *gpmc_bch_result0[GPMC_BCH_NUM_REMAINDER];
49 void __iomem *gpmc_bch_result1[GPMC_BCH_NUM_REMAINDER];
50 void __iomem *gpmc_bch_result2[GPMC_BCH_NUM_REMAINDER];
51 void __iomem *gpmc_bch_result3[GPMC_BCH_NUM_REMAINDER];
52};
53
21struct omap_nand_platform_data { 54struct omap_nand_platform_data {
22 int cs; 55 int cs;
23 struct mtd_partition *parts; 56 struct mtd_partition *parts;
24 struct gpmc_timings *gpmc_t;
25 int nr_parts; 57 int nr_parts;
26 bool dev_ready; 58 bool dev_ready;
27 enum nand_io xfer_type; 59 enum nand_io xfer_type;
@@ -30,14 +62,4 @@ struct omap_nand_platform_data {
30 struct gpmc_nand_regs reg; 62 struct gpmc_nand_regs reg;
31}; 63};
32 64
33/* minimum size for IO mapping */
34#define NAND_IO_SIZE 4
35
36#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
37extern int gpmc_nand_init(struct omap_nand_platform_data *d);
38#else
39static inline int gpmc_nand_init(struct omap_nand_platform_data *d)
40{
41 return 0;
42}
43#endif 65#endif
diff --git a/include/linux/platform_data/mtd-onenand-omap2.h b/include/linux/platform_data/mtd-onenand-omap2.h
index 2858667d2e4f..685af7e8b120 100644
--- a/include/linux/platform_data/mtd-onenand-omap2.h
+++ b/include/linux/platform_data/mtd-onenand-omap2.h
@@ -9,17 +9,15 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#ifndef __MTD_ONENAND_OMAP2_H
13#define __MTD_ONENAND_OMAP2_H
14
12#include <linux/mtd/mtd.h> 15#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h> 16#include <linux/mtd/partitions.h>
14 17
15#define ONENAND_SYNC_READ (1 << 0) 18#define ONENAND_SYNC_READ (1 << 0)
16#define ONENAND_SYNC_READWRITE (1 << 1) 19#define ONENAND_SYNC_READWRITE (1 << 1)
17 20#define ONENAND_IN_OMAP34XX (1 << 2)
18struct onenand_freq_info {
19 u16 maf_id;
20 u16 dev_id;
21 u16 ver_id;
22};
23 21
24struct omap_onenand_platform_data { 22struct omap_onenand_platform_data {
25 int cs; 23 int cs;
@@ -27,27 +25,9 @@ struct omap_onenand_platform_data {
27 struct mtd_partition *parts; 25 struct mtd_partition *parts;
28 int nr_parts; 26 int nr_parts;
29 int (*onenand_setup)(void __iomem *, int *freq_ptr); 27 int (*onenand_setup)(void __iomem *, int *freq_ptr);
30 int (*get_freq)(const struct onenand_freq_info *freq_info,
31 bool *clk_dep);
32 int dma_channel; 28 int dma_channel;
33 u8 flags; 29 u8 flags;
34 u8 regulator_can_sleep; 30 u8 regulator_can_sleep;
35 u8 skip_initial_unlocking; 31 u8 skip_initial_unlocking;
36}; 32};
37
38#define ONENAND_MAX_PARTITIONS 8
39
40#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
41 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
42
43extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
44
45#else
46
47#define board_onenand_data NULL
48
49static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
50{
51}
52
53#endif 33#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 09:26:23 -0500