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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2012-07-04 08:27:34 -0400
committerBenoit Cousson <b-cousson@ti.com>2012-09-07 13:18:41 -0400
commit926fd45ba9eeb4c3d0454b934161ee884dd82a22 (patch)
treecc72dae1f1078300d513e4f6dd76d094c8ba22d9
parent11c27069cf963f7445a7b515bcb703d90ae0c162 (diff)
ARM: OMAP4: Add L2 Cache Controller in Device Tree
Provide PL310 Level 2 Cache Controller Device Tree support for OMAP4 based devices. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
-rw-r--r--arch/arm/boot/dts/omap4.dtsi9
-rw-r--r--arch/arm/mach-omap2/omap4-common.c6
2 files changed, 14 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index c7dc11feb9da..cb18d2a2971c 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -30,12 +30,21 @@
30 cpus { 30 cpus {
31 cpu@0 { 31 cpu@0 {
32 compatible = "arm,cortex-a9"; 32 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
33 }; 34 };
34 cpu@1 { 35 cpu@1 {
35 compatible = "arm,cortex-a9"; 36 compatible = "arm,cortex-a9";
37 next-level-cache = <&L2>;
36 }; 38 };
37 }; 39 };
38 40
41 L2: l2-cache-controller@48242000 {
42 compatible = "arm,pl310-cache";
43 reg = <0x48242000 0x1000>;
44 cache-unified;
45 cache-level = <2>;
46 };
47
39 /* 48 /*
40 * The soc node represents the soc top level view. It is uses for IPs 49 * The soc node represents the soc top level view. It is uses for IPs
41 * that are not memory mapped in the MPU view or for the MPU itself. 50 * that are not memory mapped in the MPU view or for the MPU itself.
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index c29dee998a79..6f95992f37c6 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -16,6 +16,7 @@
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/platform_device.h> 17#include <linux/platform_device.h>
18#include <linux/memblock.h> 18#include <linux/memblock.h>
19#include <linux/of.h>
19 20
20#include <asm/hardware/gic.h> 21#include <asm/hardware/gic.h>
21#include <asm/hardware/cache-l2x0.h> 22#include <asm/hardware/cache-l2x0.h>
@@ -171,7 +172,10 @@ static int __init omap_l2_cache_init(void)
171 /* Enable PL310 L2 Cache controller */ 172 /* Enable PL310 L2 Cache controller */
172 omap_smc1(0x102, 0x1); 173 omap_smc1(0x102, 0x1);
173 174
174 l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); 175 if (of_have_populated_dt())
176 l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
177 else
178 l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
175 179
176 /* 180 /*
177 * Override default outer_cache.disable with a OMAP4 181 * Override default outer_cache.disable with a OMAP4