ENGR00307635-4 ARM: imx6sx: Use 24.576MHz for both SSI and SAI clocks

SAI derives its mclk from SSI_CLK, so this patch sets a default value for them.

Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>

1 files changed, 7 insertions, 0 deletions

diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index 5b9735c7388a..823ce0f5fe75 100644
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -493,6 +493,13 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
         clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 48000000);
         clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 48000000);
 
+        clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+        clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+        clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+        clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000);
+        clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000);
+        clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000);
+
         clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
         clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000);