diff options
author | Pawel Moll <pawel.moll@arm.com> | 2012-02-23 08:04:51 -0500 |
---|---|---|
committer | Pawel Moll <pawel.moll@arm.com> | 2012-02-24 04:18:19 -0500 |
commit | 8deed1786a6479d0ccda51226582920ab1d6976c (patch) | |
tree | dd857ef58ef0094a1db5e7a088843b3241fa59ab | |
parent | 95d59741d281a64eba60c3283827b73680849770 (diff) |
ARM: vexpress: Add Device Tree support
This patch adds generic Versatile Express DT machine description,
Device Tree description for the motherboard and documentation for
the bindings.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
-rw-r--r-- | Documentation/devicetree/bindings/arm/vexpress.txt | 146 | ||||
-rw-r--r-- | arch/arm/boot/dts/vexpress-v2m.dtsi | 200 | ||||
-rw-r--r-- | arch/arm/mach-vexpress/Kconfig | 47 | ||||
-rw-r--r-- | arch/arm/mach-vexpress/Makefile.boot | 2 | ||||
-rw-r--r-- | arch/arm/mach-vexpress/include/mach/motherboard.h | 6 | ||||
-rw-r--r-- | arch/arm/mach-vexpress/v2m.c | 153 |
6 files changed, 549 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/arm/vexpress.txt b/Documentation/devicetree/bindings/arm/vexpress.txt new file mode 100644 index 000000000000..ec8b50cbb2e8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/vexpress.txt | |||
@@ -0,0 +1,146 @@ | |||
1 | ARM Versatile Express boards family | ||
2 | ----------------------------------- | ||
3 | |||
4 | ARM's Versatile Express platform consists of a motherboard and one | ||
5 | or more daughterboards (tiles). The motherboard provides a set of | ||
6 | peripherals. Processor and RAM "live" on the tiles. | ||
7 | |||
8 | The motherboard and each core tile should be described by a separate | ||
9 | Device Tree source file, with the tile's description including | ||
10 | the motherboard file using a /include/ directive. As the motherboard | ||
11 | can be initialized in one of two different configurations ("memory | ||
12 | maps"), care must be taken to include the correct one. | ||
13 | |||
14 | Required properties in the root node: | ||
15 | - compatible value: | ||
16 | compatible = "arm,vexpress,<model>", "arm,vexpress"; | ||
17 | where <model> is the full tile model name (as used in the tile's | ||
18 | Technical Reference Manual), eg.: | ||
19 | - for Coretile Express A5x2 (V2P-CA5s): | ||
20 | compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; | ||
21 | - for Coretile Express A9x4 (V2P-CA9): | ||
22 | compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; | ||
23 | If a tile comes in several variants or can be used in more then one | ||
24 | configuration, the compatible value should be: | ||
25 | compatible = "arm,vexpress,<model>,<variant>", \ | ||
26 | "arm,vexpress,<model>", "arm,vexpress"; | ||
27 | eg: | ||
28 | - Coretile Express A15x2 (V2P-CA15) with Tech Chip 1: | ||
29 | compatible = "arm,vexpress,v2p-ca15,tc1", \ | ||
30 | "arm,vexpress,v2p-ca15", "arm,vexpress"; | ||
31 | - LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM: | ||
32 | compatible = "arm,vexpress,v2f-2xv6,ca7x3", \ | ||
33 | "arm,vexpress,v2f-2xv6", "arm,vexpress"; | ||
34 | |||
35 | Optional properties in the root node: | ||
36 | - tile model name (use name from the tile's Technical Reference | ||
37 | Manual, eg. "V2P-CA5s") | ||
38 | model = "<model>"; | ||
39 | - tile's HBI number (unique ARM's board model ID, visible on the | ||
40 | PCB's silkscreen) in hexadecimal transcription: | ||
41 | arm,hbi = <0xhbi> | ||
42 | eg: | ||
43 | - for Coretile Express A5x2 (V2P-CA5s) HBI-0191: | ||
44 | arm,hbi = <0x191>; | ||
45 | - Coretile Express A9x4 (V2P-CA9) HBI-0225: | ||
46 | arm,hbi = <0x225>; | ||
47 | |||
48 | Top-level standard "cpus" node is required. It must contain a node | ||
49 | with device_type = "cpu" property for every available core, eg.: | ||
50 | |||
51 | cpus { | ||
52 | #address-cells = <1>; | ||
53 | #size-cells = <0>; | ||
54 | |||
55 | cpu@0 { | ||
56 | device_type = "cpu"; | ||
57 | compatible = "arm,cortex-a5"; | ||
58 | reg = <0>; | ||
59 | }; | ||
60 | }; | ||
61 | |||
62 | The motherboard description file provides a single "motherboard" node | ||
63 | using 2 address cells corresponding to the Static Memory Bus used | ||
64 | between the motherboard and the tile. The first cell defines the Chip | ||
65 | Select (CS) line number, the second cell address offset within the CS. | ||
66 | All interrupt lines between the motherboard and the tile are active | ||
67 | high and are described using single cell. | ||
68 | |||
69 | Optional properties of the "motherboard" node: | ||
70 | - motherboard's memory map variant: | ||
71 | arm,v2m-memory-map = "<name>"; | ||
72 | where name is one of: | ||
73 | - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also | ||
74 | referred to as "ARM Cortex-A Series memory map": | ||
75 | arm,v2m-memory-map = "rs1"; | ||
76 | When this property is missing, the motherboard is using the original | ||
77 | memory map (also known as the "Legacy memory map", primarily used | ||
78 | with the original CoreTile Express A9x4) with peripherals on CS7. | ||
79 | |||
80 | Motherboard .dtsi files provide a set of labelled peripherals that | ||
81 | can be used to obtain required phandle in the tile's "aliases" node: | ||
82 | - UARTs, note that the numbers correspond to the physical connectors | ||
83 | on the motherboard's back panel: | ||
84 | v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3 | ||
85 | - I2C controllers: | ||
86 | v2m_i2c_dvi and v2m_i2c_pcie | ||
87 | - SP804 timers: | ||
88 | v2m_timer01 and v2m_timer23 | ||
89 | |||
90 | Current Linux implementation requires a "arm,v2m_timer" alias | ||
91 | pointing at one of the motherboard's SP804 timers, if it is to be | ||
92 | used as the system timer. This alias should be defined in the | ||
93 | motherboard files. | ||
94 | |||
95 | The tile description must define "ranges", "interrupt-map-mask" and | ||
96 | "interrupt-map" properties to translate the motherboard's address | ||
97 | and interrupt space into one used by the tile's processor. | ||
98 | |||
99 | Abbreviated example: | ||
100 | |||
101 | /dts-v1/; | ||
102 | |||
103 | / { | ||
104 | model = "V2P-CA5s"; | ||
105 | arm,hbi = <0x225>; | ||
106 | compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress"; | ||
107 | interrupt-parent = <&gic>; | ||
108 | #address-cells = <1>; | ||
109 | #size-cells = <1>; | ||
110 | |||
111 | chosen { }; | ||
112 | |||
113 | aliases { | ||
114 | serial0 = &v2m_serial0; | ||
115 | }; | ||
116 | |||
117 | cpus { | ||
118 | #address-cells = <1>; | ||
119 | #size-cells = <0>; | ||
120 | |||
121 | cpu@0 { | ||
122 | device_type = "cpu"; | ||
123 | compatible = "arm,cortex-a5"; | ||
124 | reg = <0>; | ||
125 | }; | ||
126 | }; | ||
127 | |||
128 | gic: interrupt-controller@2c001000 { | ||
129 | compatible = "arm,cortex-a9-gic"; | ||
130 | #interrupt-cells = <3>; | ||
131 | #address-cells = <0>; | ||
132 | interrupt-controller; | ||
133 | reg = <0x2c001000 0x1000>, | ||
134 | <0x2c000100 0x100>; | ||
135 | }; | ||
136 | |||
137 | motherboard { | ||
138 | /* CS0 is visible at 0x08000000 */ | ||
139 | ranges = <0 0 0x08000000 0x04000000>; | ||
140 | interrupt-map-mask = <0 0 63>; | ||
141 | /* Active high IRQ 0 is connected to GIC's SPI0 */ | ||
142 | interrupt-map = <0 0 0 &gic 0 0 4>; | ||
143 | }; | ||
144 | }; | ||
145 | |||
146 | /include/ "vexpress-v2m-rs1.dtsi" | ||
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi new file mode 100644 index 000000000000..a6c9c7c82d53 --- /dev/null +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi | |||
@@ -0,0 +1,200 @@ | |||
1 | /* | ||
2 | * ARM Ltd. Versatile Express | ||
3 | * | ||
4 | * Motherboard Express uATX | ||
5 | * V2M-P1 | ||
6 | * | ||
7 | * HBI-0190D | ||
8 | * | ||
9 | * Original memory map ("Legacy memory map" in the board's | ||
10 | * Technical Reference Manual) | ||
11 | * | ||
12 | * WARNING! The hardware described in this file is independent from the | ||
13 | * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong | ||
14 | * correspondence between the two configurations. | ||
15 | * | ||
16 | * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT | ||
17 | * CHANGES TO vexpress-v2m-rs1.dtsi! | ||
18 | */ | ||
19 | |||
20 | / { | ||
21 | aliases { | ||
22 | arm,v2m_timer = &v2m_timer01; | ||
23 | }; | ||
24 | |||
25 | motherboard { | ||
26 | compatible = "simple-bus"; | ||
27 | #address-cells = <2>; /* SMB chipselect number and offset */ | ||
28 | #size-cells = <1>; | ||
29 | #interrupt-cells = <1>; | ||
30 | |||
31 | flash@0,00000000 { | ||
32 | compatible = "arm,vexpress-flash", "cfi-flash"; | ||
33 | reg = <0 0x00000000 0x04000000>, | ||
34 | <1 0x00000000 0x04000000>; | ||
35 | bank-width = <4>; | ||
36 | }; | ||
37 | |||
38 | psram@2,00000000 { | ||
39 | compatible = "arm,vexpress-psram", "mtd-ram"; | ||
40 | reg = <2 0x00000000 0x02000000>; | ||
41 | bank-width = <4>; | ||
42 | }; | ||
43 | |||
44 | vram@3,00000000 { | ||
45 | compatible = "arm,vexpress-vram"; | ||
46 | reg = <3 0x00000000 0x00800000>; | ||
47 | }; | ||
48 | |||
49 | ethernet@3,02000000 { | ||
50 | compatible = "smsc,lan9118", "smsc,lan9115"; | ||
51 | reg = <3 0x02000000 0x10000>; | ||
52 | interrupts = <15>; | ||
53 | phy-mode = "mii"; | ||
54 | reg-io-width = <4>; | ||
55 | smsc,irq-active-high; | ||
56 | smsc,irq-push-pull; | ||
57 | }; | ||
58 | |||
59 | usb@3,03000000 { | ||
60 | compatible = "nxp,usb-isp1761"; | ||
61 | reg = <3 0x03000000 0x20000>; | ||
62 | interrupts = <16>; | ||
63 | port1-otg; | ||
64 | }; | ||
65 | |||
66 | iofpga@7,00000000 { | ||
67 | compatible = "arm,amba-bus", "simple-bus"; | ||
68 | #address-cells = <1>; | ||
69 | #size-cells = <1>; | ||
70 | ranges = <0 7 0 0x20000>; | ||
71 | |||
72 | sysreg@00000 { | ||
73 | compatible = "arm,vexpress-sysreg"; | ||
74 | reg = <0x00000 0x1000>; | ||
75 | }; | ||
76 | |||
77 | sysctl@01000 { | ||
78 | compatible = "arm,sp810", "arm,primecell"; | ||
79 | reg = <0x01000 0x1000>; | ||
80 | }; | ||
81 | |||
82 | /* PCI-E I2C bus */ | ||
83 | v2m_i2c_pcie: i2c@02000 { | ||
84 | compatible = "arm,versatile-i2c"; | ||
85 | reg = <0x02000 0x1000>; | ||
86 | |||
87 | #address-cells = <1>; | ||
88 | #size-cells = <0>; | ||
89 | |||
90 | pcie-switch@60 { | ||
91 | compatible = "idt,89hpes32h8"; | ||
92 | reg = <0x60>; | ||
93 | }; | ||
94 | }; | ||
95 | |||
96 | aaci@04000 { | ||
97 | compatible = "arm,pl041", "arm,primecell"; | ||
98 | reg = <0x04000 0x1000>; | ||
99 | interrupts = <11>; | ||
100 | }; | ||
101 | |||
102 | mmci@05000 { | ||
103 | compatible = "arm,pl180", "arm,primecell"; | ||
104 | reg = <0x05000 0x1000>; | ||
105 | interrupts = <9 10>; | ||
106 | }; | ||
107 | |||
108 | kmi@06000 { | ||
109 | compatible = "arm,pl050", "arm,primecell"; | ||
110 | reg = <0x06000 0x1000>; | ||
111 | interrupts = <12>; | ||
112 | }; | ||
113 | |||
114 | kmi@07000 { | ||
115 | compatible = "arm,pl050", "arm,primecell"; | ||
116 | reg = <0x07000 0x1000>; | ||
117 | interrupts = <13>; | ||
118 | }; | ||
119 | |||
120 | v2m_serial0: uart@09000 { | ||
121 | compatible = "arm,pl011", "arm,primecell"; | ||
122 | reg = <0x09000 0x1000>; | ||
123 | interrupts = <5>; | ||
124 | }; | ||
125 | |||
126 | v2m_serial1: uart@0a000 { | ||
127 | compatible = "arm,pl011", "arm,primecell"; | ||
128 | reg = <0x0a000 0x1000>; | ||
129 | interrupts = <6>; | ||
130 | }; | ||
131 | |||
132 | v2m_serial2: uart@0b000 { | ||
133 | compatible = "arm,pl011", "arm,primecell"; | ||
134 | reg = <0x0b000 0x1000>; | ||
135 | interrupts = <7>; | ||
136 | }; | ||
137 | |||
138 | v2m_serial3: uart@0c000 { | ||
139 | compatible = "arm,pl011", "arm,primecell"; | ||
140 | reg = <0x0c000 0x1000>; | ||
141 | interrupts = <8>; | ||
142 | }; | ||
143 | |||
144 | wdt@0f000 { | ||
145 | compatible = "arm,sp805", "arm,primecell"; | ||
146 | reg = <0x0f000 0x1000>; | ||
147 | interrupts = <0>; | ||
148 | }; | ||
149 | |||
150 | v2m_timer01: timer@11000 { | ||
151 | compatible = "arm,sp804", "arm,primecell"; | ||
152 | reg = <0x11000 0x1000>; | ||
153 | interrupts = <2>; | ||
154 | }; | ||
155 | |||
156 | v2m_timer23: timer@12000 { | ||
157 | compatible = "arm,sp804", "arm,primecell"; | ||
158 | reg = <0x12000 0x1000>; | ||
159 | }; | ||
160 | |||
161 | /* DVI I2C bus */ | ||
162 | v2m_i2c_dvi: i2c@16000 { | ||
163 | compatible = "arm,versatile-i2c"; | ||
164 | reg = <0x16000 0x1000>; | ||
165 | |||
166 | #address-cells = <1>; | ||
167 | #size-cells = <0>; | ||
168 | |||
169 | dvi-transmitter@39 { | ||
170 | compatible = "sil,sii9022-tpi", "sil,sii9022"; | ||
171 | reg = <0x39>; | ||
172 | }; | ||
173 | |||
174 | dvi-transmitter@60 { | ||
175 | compatible = "sil,sii9022-cpi", "sil,sii9022"; | ||
176 | reg = <0x60>; | ||
177 | }; | ||
178 | }; | ||
179 | |||
180 | rtc@17000 { | ||
181 | compatible = "arm,pl031", "arm,primecell"; | ||
182 | reg = <0x17000 0x1000>; | ||
183 | interrupts = <4>; | ||
184 | }; | ||
185 | |||
186 | compact-flash@1a000 { | ||
187 | compatible = "arm,vexpress-cf", "ata-generic"; | ||
188 | reg = <0x1a000 0x100 | ||
189 | 0x1a100 0xf00>; | ||
190 | reg-shift = <2>; | ||
191 | }; | ||
192 | |||
193 | clcd@1f000 { | ||
194 | compatible = "arm,pl111", "arm,primecell"; | ||
195 | reg = <0x1f000 0x1000>; | ||
196 | interrupts = <14>; | ||
197 | }; | ||
198 | }; | ||
199 | }; | ||
200 | }; | ||
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 9b3d0fbaee72..cf8730d35e70 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig | |||
@@ -1,14 +1,55 @@ | |||
1 | menu "Versatile Express platform type" | 1 | menu "Versatile Express platform type" |
2 | depends on ARCH_VEXPRESS | 2 | depends on ARCH_VEXPRESS |
3 | 3 | ||
4 | config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA | ||
5 | bool | ||
6 | select ARM_ERRATA_720789 | ||
7 | select ARM_ERRATA_751472 | ||
8 | select PL310_ERRATA_753970 if CACHE_PL310 | ||
9 | help | ||
10 | Provides common dependencies for Versatile Express platforms | ||
11 | based on Cortex-A5 and Cortex-A9 processors. In order to | ||
12 | build a working kernel, you must also enable relevant core | ||
13 | tile support or Flattened Device Tree based support options. | ||
14 | |||
4 | config ARCH_VEXPRESS_CA9X4 | 15 | config ARCH_VEXPRESS_CA9X4 |
5 | bool "Versatile Express Cortex-A9x4 tile" | 16 | bool "Versatile Express Cortex-A9x4 tile" |
17 | select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA | ||
18 | select ARM_GIC | ||
6 | select CPU_V7 | 19 | select CPU_V7 |
20 | select HAVE_SMP | ||
21 | select MIGHT_HAVE_CACHE_L2X0 | ||
22 | |||
23 | config ARCH_VEXPRESS_DT | ||
24 | bool "Device Tree support for Versatile Express platforms" | ||
25 | select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA | ||
7 | select ARM_GIC | 26 | select ARM_GIC |
8 | select ARM_ERRATA_720789 | 27 | select ARM_PATCH_PHYS_VIRT |
9 | select ARM_ERRATA_751472 | 28 | select AUTO_ZRELADDR |
10 | select ARM_ERRATA_753970 | 29 | select CPU_V7 |
11 | select HAVE_SMP | 30 | select HAVE_SMP |
12 | select MIGHT_HAVE_CACHE_L2X0 | 31 | select MIGHT_HAVE_CACHE_L2X0 |
32 | select USE_OF | ||
33 | help | ||
34 | New Versatile Express platforms require Flattened Device Tree to | ||
35 | be passed to the kernel. | ||
36 | |||
37 | This option enables support for systems using Cortex processor based | ||
38 | ARM core and logic (FPGA) tiles on the Versatile Express motherboard, | ||
39 | for example: | ||
40 | |||
41 | - CoreTile Express A5x2 (V2P-CA5s) | ||
42 | - CoreTile Express A9x4 (V2P-CA9) | ||
43 | - CoreTile Express A15x2 (V2P-CA15) | ||
44 | - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs | ||
45 | (Soft Macrocell Models) | ||
46 | - Versatile Express RTSMs (Models) | ||
47 | |||
48 | You must boot using a Flattened Device Tree in order to use these | ||
49 | platforms. The traditional (ATAGs) boot method is not usable on | ||
50 | these boards with this option. | ||
51 | |||
52 | If your bootloader supports Flattened Device Tree based booting, | ||
53 | say Y here. | ||
13 | 54 | ||
14 | endmenu | 55 | endmenu |
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot index 8630b3d10a4d..c6dd8918b9ed 100644 --- a/arch/arm/mach-vexpress/Makefile.boot +++ b/arch/arm/mach-vexpress/Makefile.boot | |||
@@ -1,3 +1,5 @@ | |||
1 | # Those numbers are used only by the non-DT V2P-CA9 platform | ||
2 | # The DT-enabled ones require CONFIG_AUTO_ZRELADDR=y | ||
1 | zreladdr-y += 0x60008000 | 3 | zreladdr-y += 0x60008000 |
2 | params_phys-y := 0x60000100 | 4 | params_phys-y := 0x60000100 |
3 | initrd_phys-y := 0x60800000 | 5 | initrd_phys-y := 0x60800000 |
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h index b4c498c1dbee..31a92890893d 100644 --- a/arch/arm/mach-vexpress/include/mach/motherboard.h +++ b/arch/arm/mach-vexpress/include/mach/motherboard.h | |||
@@ -117,6 +117,12 @@ int v2m_cfg_read(u32 devfn, u32 *data); | |||
117 | void v2m_flags_set(u32 data); | 117 | void v2m_flags_set(u32 data); |
118 | 118 | ||
119 | /* | 119 | /* |
120 | * Miscellaneous | ||
121 | */ | ||
122 | #define SYS_MISC_MASTERSITE (1 << 14) | ||
123 | #define SYS_PROCIDx_HBI_MASK 0xfff | ||
124 | |||
125 | /* | ||
120 | * Core tile IDs | 126 | * Core tile IDs |
121 | */ | 127 | */ |
122 | #define V2M_CT_ID_CA9 0x0c000191 | 128 | #define V2M_CT_ID_CA9 0x0c000191 |
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index c76f9144898a..dbf055103000 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c | |||
@@ -6,6 +6,10 @@ | |||
6 | #include <linux/amba/mmci.h> | 6 | #include <linux/amba/mmci.h> |
7 | #include <linux/io.h> | 7 | #include <linux/io.h> |
8 | #include <linux/init.h> | 8 | #include <linux/init.h> |
9 | #include <linux/of_address.h> | ||
10 | #include <linux/of_fdt.h> | ||
11 | #include <linux/of_irq.h> | ||
12 | #include <linux/of_platform.h> | ||
9 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
10 | #include <linux/ata_platform.h> | 14 | #include <linux/ata_platform.h> |
11 | #include <linux/smsc911x.h> | 15 | #include <linux/smsc911x.h> |
@@ -21,6 +25,8 @@ | |||
21 | #include <asm/mach/map.h> | 25 | #include <asm/mach/map.h> |
22 | #include <asm/mach/time.h> | 26 | #include <asm/mach/time.h> |
23 | #include <asm/hardware/arm_timer.h> | 27 | #include <asm/hardware/arm_timer.h> |
28 | #include <asm/hardware/cache-l2x0.h> | ||
29 | #include <asm/hardware/gic.h> | ||
24 | #include <asm/hardware/timer-sp.h> | 30 | #include <asm/hardware/timer-sp.h> |
25 | #include <asm/hardware/sp810.h> | 31 | #include <asm/hardware/sp810.h> |
26 | #include <asm/hardware/gic.h> | 32 | #include <asm/hardware/gic.h> |
@@ -430,8 +436,9 @@ static void __init v2m_populate_ct_desc(void) | |||
430 | ct_desc = ct_descs[i]; | 436 | ct_desc = ct_descs[i]; |
431 | 437 | ||
432 | if (!ct_desc) | 438 | if (!ct_desc) |
433 | panic("vexpress: failed to populate core tile description " | 439 | panic("vexpress: this kernel does not support core tile ID 0x%08x when booting via ATAGs.\n" |
434 | "for tile ID 0x%8x\n", current_tile_id); | 440 | "You may need a device tree blob or a different kernel to boot on this board.\n", |
441 | current_tile_id); | ||
435 | } | 442 | } |
436 | 443 | ||
437 | static void __init v2m_map_io(void) | 444 | static void __init v2m_map_io(void) |
@@ -476,3 +483,145 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express") | |||
476 | .init_machine = v2m_init, | 483 | .init_machine = v2m_init, |
477 | .restart = v2m_restart, | 484 | .restart = v2m_restart, |
478 | MACHINE_END | 485 | MACHINE_END |
486 | |||
487 | #if defined(CONFIG_ARCH_VEXPRESS_DT) | ||
488 | |||
489 | void __init v2m_dt_map_io(void) | ||
490 | { | ||
491 | iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc)); | ||
492 | |||
493 | #if defined(CONFIG_SMP) | ||
494 | vexpress_dt_smp_map_io(); | ||
495 | #endif | ||
496 | } | ||
497 | |||
498 | static struct clk_lookup v2m_dt_lookups[] = { | ||
499 | { /* AMBA bus clock */ | ||
500 | .con_id = "apb_pclk", | ||
501 | .clk = &dummy_apb_pclk, | ||
502 | }, { /* SP804 timers */ | ||
503 | .dev_id = "sp804", | ||
504 | .con_id = "v2m-timer0", | ||
505 | .clk = &v2m_sp804_clk, | ||
506 | }, { /* SP804 timers */ | ||
507 | .dev_id = "sp804", | ||
508 | .con_id = "v2m-timer1", | ||
509 | .clk = &v2m_sp804_clk, | ||
510 | }, { /* PL180 MMCI */ | ||
511 | .dev_id = "mb:mmci", /* 10005000.mmci */ | ||
512 | .clk = &osc2_clk, | ||
513 | }, { /* PL050 KMI0 */ | ||
514 | .dev_id = "10006000.kmi", | ||
515 | .clk = &osc2_clk, | ||
516 | }, { /* PL050 KMI1 */ | ||
517 | .dev_id = "10007000.kmi", | ||
518 | .clk = &osc2_clk, | ||
519 | }, { /* PL011 UART0 */ | ||
520 | .dev_id = "10009000.uart", | ||
521 | .clk = &osc2_clk, | ||
522 | }, { /* PL011 UART1 */ | ||
523 | .dev_id = "1000a000.uart", | ||
524 | .clk = &osc2_clk, | ||
525 | }, { /* PL011 UART2 */ | ||
526 | .dev_id = "1000b000.uart", | ||
527 | .clk = &osc2_clk, | ||
528 | }, { /* PL011 UART3 */ | ||
529 | .dev_id = "1000c000.uart", | ||
530 | .clk = &osc2_clk, | ||
531 | }, { /* SP805 WDT */ | ||
532 | .dev_id = "1000f000.wdt", | ||
533 | .clk = &v2m_ref_clk, | ||
534 | }, { /* PL111 CLCD */ | ||
535 | .dev_id = "1001f000.clcd", | ||
536 | .clk = &osc1_clk, | ||
537 | }, | ||
538 | }; | ||
539 | |||
540 | void __init v2m_dt_init_early(void) | ||
541 | { | ||
542 | struct device_node *node; | ||
543 | u32 dt_hbi; | ||
544 | |||
545 | node = of_find_compatible_node(NULL, NULL, "arm,vexpress-sysreg"); | ||
546 | v2m_sysreg_base = of_iomap(node, 0); | ||
547 | if (WARN_ON(!v2m_sysreg_base)) | ||
548 | return; | ||
549 | |||
550 | /* Confirm board type against DT property, if available */ | ||
551 | if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) { | ||
552 | u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC); | ||
553 | u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ? | ||
554 | V2M_SYS_PROCID1 : V2M_SYS_PROCID0)); | ||
555 | u32 hbi = id & SYS_PROCIDx_HBI_MASK; | ||
556 | |||
557 | if (WARN_ON(dt_hbi != hbi)) | ||
558 | pr_warning("vexpress: DT HBI (%x) is not matching " | ||
559 | "hardware (%x)!\n", dt_hbi, hbi); | ||
560 | } | ||
561 | |||
562 | clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups)); | ||
563 | versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000); | ||
564 | } | ||
565 | |||
566 | static struct of_device_id vexpress_irq_match[] __initdata = { | ||
567 | { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, | ||
568 | {} | ||
569 | }; | ||
570 | |||
571 | static void __init v2m_dt_init_irq(void) | ||
572 | { | ||
573 | of_irq_init(vexpress_irq_match); | ||
574 | } | ||
575 | |||
576 | static void __init v2m_dt_timer_init(void) | ||
577 | { | ||
578 | struct device_node *node; | ||
579 | const char *path; | ||
580 | int err; | ||
581 | |||
582 | node = of_find_compatible_node(NULL, NULL, "arm,sp810"); | ||
583 | v2m_sysctl_init(of_iomap(node, 0)); | ||
584 | |||
585 | err = of_property_read_string(of_aliases, "arm,v2m_timer", &path); | ||
586 | if (WARN_ON(err)) | ||
587 | return; | ||
588 | node = of_find_node_by_path(path); | ||
589 | v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0)); | ||
590 | } | ||
591 | |||
592 | static struct sys_timer v2m_dt_timer = { | ||
593 | .init = v2m_dt_timer_init, | ||
594 | }; | ||
595 | |||
596 | static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = { | ||
597 | OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash", | ||
598 | &v2m_flash_data), | ||
599 | OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data), | ||
600 | {} | ||
601 | }; | ||
602 | |||
603 | static void __init v2m_dt_init(void) | ||
604 | { | ||
605 | l2x0_of_init(0x00400000, 0xfe0fffff); | ||
606 | of_platform_populate(NULL, of_default_bus_match_table, | ||
607 | v2m_dt_auxdata_lookup, NULL); | ||
608 | pm_power_off = v2m_power_off; | ||
609 | } | ||
610 | |||
611 | const static char *v2m_dt_match[] __initconst = { | ||
612 | "arm,vexpress", | ||
613 | NULL, | ||
614 | }; | ||
615 | |||
616 | DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express") | ||
617 | .dt_compat = v2m_dt_match, | ||
618 | .map_io = v2m_dt_map_io, | ||
619 | .init_early = v2m_dt_init_early, | ||
620 | .init_irq = v2m_dt_init_irq, | ||
621 | .timer = &v2m_dt_timer, | ||
622 | .init_machine = v2m_dt_init, | ||
623 | .handle_irq = gic_handle_irq, | ||
624 | .restart = v2m_restart, | ||
625 | MACHINE_END | ||
626 | |||
627 | #endif | ||