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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2013-03-06 18:03:18 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-03-17 16:49:23 -0400
commit86d52df633869b54a6f0b9a8f088be9c89a42c3d (patch)
tree01b8e88d622f109f1e28dfedbd2dba09445e58d6
parentca291363ccc7c0e9b337fe3b46f732247238537e (diff)
drm/i915: add HAS_POWER_WELL
We're starting to add many IS_HASWELL checks for the power well code, so add a HAS_POWER_WELL macro to properly document that we're checking for hardware that has the power down well. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> [danvet: Resolve conflicts since some converted code was added by not-yet merged patches.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c4
2 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ca6b215c090c..71f285c56f1e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1339,6 +1339,7 @@ struct drm_i915_file_private {
1339#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1339#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1340 1340
1341#define HAS_DDI(dev) (IS_HASWELL(dev)) 1341#define HAS_DDI(dev) (IS_HASWELL(dev))
1342#define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1342 1343
1343#define INTEL_PCH_DEVICE_ID_MASK 0xff00 1344#define INTEL_PCH_DEVICE_ID_MASK 0xff00
1344#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 1345#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index be43f7107c99..44a23b9b8e53 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4076,7 +4076,7 @@ void intel_set_power_well(struct drm_device *dev, bool enable)
4076 bool is_enabled, enable_requested; 4076 bool is_enabled, enable_requested;
4077 uint32_t tmp; 4077 uint32_t tmp;
4078 4078
4079 if (!IS_HASWELL(dev)) 4079 if (!HAS_POWER_WELL(dev))
4080 return; 4080 return;
4081 4081
4082 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 4082 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
@@ -4111,7 +4111,7 @@ void intel_init_power_well(struct drm_device *dev)
4111{ 4111{
4112 struct drm_i915_private *dev_priv = dev->dev_private; 4112 struct drm_i915_private *dev_priv = dev->dev_private;
4113 4113
4114 if (!IS_HASWELL(dev)) 4114 if (!HAS_POWER_WELL(dev))
4115 return; 4115 return;
4116 4116
4117 /* For now, we need the power well to be always enabled. */ 4117 /* For now, we need the power well to be always enabled. */