Merge remote branch 'kumar/merge' into merge

5 files changed, 38 insertions, 27 deletions

diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
index 22f64b62d7f6..e0668f877794 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -1,7 +1,7 @@
 /*
  * P1020 RDB Device Tree Source
  *
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009-2011 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -553,7 +553,7 @@
                 reg = <0 0xffe09000 0 0x1000>;
                 bus-range = <0 255>;
                 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
+                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
                 interrupts = <16 2>;
@@ -580,8 +580,8 @@
                 #address-cells = <3>;
                 reg = <0 0xffe0a000 0 0x1000>;
                 bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
                 interrupts = <16 2>;
@@ -590,8 +590,8 @@
                         #size-cells = <2>;
                         #address-cells = <3>;
                         device_type = "pci";
-                        ranges = <0x2000000 0x0 0xc0000000
-                                  0x2000000 0x0 0xc0000000
+                        ranges = <0x2000000 0x0 0x80000000
+                                  0x2000000 0x0 0x80000000
                                   0x0 0x20000000
 
                                   0x1000000 0x0 0x0
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index da4cb0d8d215..e2d48fd4416e 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -1,7 +1,7 @@
 /*
  * P2020 RDB Device Tree Source
  *
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009-2011 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -537,7 +537,7 @@
                 reg = <0 0xffe09000 0 0x1000>;
                 bus-range = <0 255>;
                 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
+                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
                 interrupts = <25 2>;
@@ -564,8 +564,8 @@
                 #address-cells = <3>;
                 reg = <0 0xffe0a000 0 0x1000>;
                 bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
                 interrupts = <26 2>;
@@ -574,8 +574,8 @@
                         #size-cells = <2>;
                         #address-cells = <3>;
                         device_type = "pci";
-                        ranges = <0x2000000 0x0 0xc0000000
-                                  0x2000000 0x0 0xc0000000
+                        ranges = <0x2000000 0x0 0x80000000
+                                  0x2000000 0x0 0x80000000
                                   0x0 0x20000000
 
                                   0x1000000 0x0 0x0
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
index 0fe93d0c8b2e..b69c3a5dc858 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -6,7 +6,7 @@
  * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb,
  * eth1, eth2, sdhc, crypto, global-util, pci0.
  *
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009-2011 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -342,7 +342,7 @@
                 reg = <0 0xffe09000 0 0x1000>;
                 bus-range = <0 255>;
                 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
+                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
                 interrupts = <25 2>;
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
index e95a51285328..7a31d46c01b0 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
@@ -7,7 +7,7 @@
  *
  * Please note to add "-b 1" for core1's dts compiling.
  *
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009-2011 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -162,8 +162,8 @@
                 #address-cells = <3>;
                 reg = <0 0xffe0a000 0 0x1000>;
                 bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
                 interrupts = <26 2>;
@@ -172,8 +172,8 @@
                         #size-cells = <2>;
                         #address-cells = <3>;
                         device_type = "pci";
-                        ranges = <0x2000000 0x0 0xc0000000
-                                  0x2000000 0x0 0xc0000000
+                        ranges = <0x2000000 0x0 0x80000000
+                                  0x2000000 0x0 0x80000000
                                   0x0 0x20000000
 
                                   0x1000000 0x0 0x0
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index ffb5ad080bee..38ab8e2cd7f4 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -1147,13 +1147,14 @@ static struct platform_driver mpc85xx_mc_err_driver = {
 static void __init mpc85xx_mc_clear_rfxe(void *data)
 {
         orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
-        mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000));
+        mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE));
 }
 #endif
 
 static int __init mpc85xx_mc_init(void)
 {
         int res = 0;
+        u32 pvr = 0;
 
         printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
                "(C) 2006 Montavista Software\n");
@@ -1183,12 +1184,17 @@ static int __init mpc85xx_mc_init(void)
 #endif
 
 #ifdef CONFIG_FSL_SOC_BOOKE
-        /*
-         * need to clear HID1[RFXE] to disable machine check int
-         * so we can catch it
-         */
-        if (edac_op_state == EDAC_OPSTATE_INT)
-                on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
+        pvr = mfspr(SPRN_PVR);
+
+        if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
+            (PVR_VER(pvr) == PVR_VER_E500V2)) {
+                /*
+                 * need to clear HID1[RFXE] to disable machine check int
+                 * so we can catch it
+                 */
+                if (edac_op_state == EDAC_OPSTATE_INT)
+                        on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
+        }
 #endif
 
         return 0;
@@ -1206,7 +1212,12 @@ static void __exit mpc85xx_mc_restore_hid1(void *data)
 static void __exit mpc85xx_mc_exit(void)
 {
 #ifdef CONFIG_FSL_SOC_BOOKE
-        on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
+        u32 pvr = mfspr(SPRN_PVR);
+
+        if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
+            (PVR_VER(pvr) == PVR_VER_E500V2)) {
+                on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
+        }
 #endif
 #ifdef CONFIG_PCI
         platform_driver_unregister(&mpc85xx_pci_err_driver);