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authorOlof Johansson <olof@lixom.net>2012-05-12 22:57:34 -0400
committerOlof Johansson <olof@lixom.net>2012-05-12 22:57:34 -0400
commit7af07ad902cce88ebbd2ce0e681d0c541e8f95fa (patch)
tree40a5aedb583c35d16505d96ea8996c413a747fe6
parent7afeca1a30360c7b5cee94fc7ff8f350d582282a (diff)
parent08d98fe0e81cd9424ef2451ed13afe91a9a26f9f (diff)
Merge tag 'ux500-gpio-pins-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/pinctrl
ux500 GPIO and pinctrl changes for kernel 3.5 * tag 'ux500-gpio-pins-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: ARM: ux500: switch MSP to using pinctrl for pins ARM: ux500: alter MSP registration to return a device pointer ARM: ux500: switch to using pinctrl for uart0 ARM: ux500: delete custom pin control system ARM: ux500: switch over to Nomadik pinctrl driver pinctrl: add sleep state definition pinctrl/nomadik: implement pin configuration pinctrl/nomadik: implement pin multiplexing pinctrl/nomadik: reuse GPIO debug function for pins pinctrl/nomadik: break out single GPIO debug function pinctrl/nomadik: basic Nomadik pinctrl interface pinctrl/nomadik: !CONFIG_OF build error gpio: move the Nomadik GPIO driver to pinctrl Context conflicts resolved in drivers/pinctrl/Kconfig and drivers/pinctrl/Makefile. Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm/mach-ux500/Kconfig3
-rw-r--r--arch/arm/mach-ux500/Makefile2
-rw-r--r--arch/arm/mach-ux500/board-mop500-msp.c85
-rw-r--r--arch/arm/mach-ux500/board-mop500-pins.c855
-rw-r--r--arch/arm/mach-ux500/board-mop500.c83
-rw-r--r--arch/arm/mach-ux500/board-mop500.h6
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c1
-rw-r--r--arch/arm/mach-ux500/devices-common.h12
-rw-r--r--arch/arm/mach-ux500/pins.c88
-rw-r--r--arch/arm/mach-ux500/pins.h46
-rw-r--r--arch/arm/plat-nomadik/include/plat/pincfg.h13
-rw-r--r--drivers/gpio/Makefile1
-rw-r--r--drivers/pinctrl/Kconfig10
-rw-r--r--drivers/pinctrl/Makefile2
-rw-r--r--drivers/pinctrl/pinctrl-nomadik-db8500.c857
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c (renamed from drivers/gpio/gpio-nomadik.c)572
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.h77
-rw-r--r--include/linux/pinctrl/pinctrl-state.h13
18 files changed, 2050 insertions, 676 deletions
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index ef7099eea0f2..4adb49396665 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -9,6 +9,8 @@ config UX500_SOC_COMMON
9 select ARM_ERRATA_754322 9 select ARM_ERRATA_754322
10 select ARM_ERRATA_764369 10 select ARM_ERRATA_764369
11 select CACHE_L2X0 11 select CACHE_L2X0
12 select PINCTRL
13 select PINCTRL_NOMADIK
12 14
13config UX500_SOC_DB5500 15config UX500_SOC_DB5500
14 bool 16 bool
@@ -20,6 +22,7 @@ config UX500_SOC_DB8500
20 select REGULATOR 22 select REGULATOR
21 select REGULATOR_DB8500_PRCMU 23 select REGULATOR_DB8500_PRCMU
22 select CPU_FREQ_TABLE if CPU_FREQ 24 select CPU_FREQ_TABLE if CPU_FREQ
25 select PINCTRL_DB8500
23 26
24menu "Ux500 target platform (boards)" 27menu "Ux500 target platform (boards)"
25 28
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 015932c6bf08..11729bc62194 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5obj-y := clock.o cpu.o devices.o devices-common.o \ 5obj-y := clock.o cpu.o devices.o devices-common.o \
6 id.o pins.o usb.o timer.o 6 id.o usb.o timer.o
7obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o 7obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
8obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o 8obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o
9obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o 9obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o
diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index c8f6300cb7d2..996048038743 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -7,17 +7,18 @@
7#include <linux/platform_device.h> 7#include <linux/platform_device.h>
8#include <linux/init.h> 8#include <linux/init.h>
9#include <linux/gpio.h> 9#include <linux/gpio.h>
10#include <plat/gpio-nomadik.h> 10#include <linux/pinctrl/consumer.h>
11 11
12#include <plat/gpio-nomadik.h>
12#include <plat/pincfg.h> 13#include <plat/pincfg.h>
13#include <plat/ste_dma40.h> 14#include <plat/ste_dma40.h>
14 15
15#include <mach/devices.h> 16#include <mach/devices.h>
16#include <ste-dma40-db8500.h>
17#include <mach/hardware.h> 17#include <mach/hardware.h>
18#include <mach/irqs.h> 18#include <mach/irqs.h>
19#include <mach/msp.h> 19#include <mach/msp.h>
20 20
21#include "ste-dma40-db8500.h"
21#include "board-mop500.h" 22#include "board-mop500.h"
22#include "devices-db8500.h" 23#include "devices-db8500.h"
23#include "pins-db8500.h" 24#include "pins-db8500.h"
@@ -28,19 +29,10 @@ static DEFINE_SPINLOCK(msp_rxtx_lock);
28/* Reference Count */ 29/* Reference Count */
29static int msp_rxtx_ref; 30static int msp_rxtx_ref;
30 31
31static pin_cfg_t mop500_msp1_pins_init[] = { 32/* Pin modes */
32 GPIO33_MSP1_TXD | PIN_OUTPUT_LOW | PIN_SLPM_WAKEUP_DISABLE, 33struct pinctrl *msp1_p;
33 GPIO34_MSP1_TFS | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_DISABLE, 34struct pinctrl_state *msp1_def;
34 GPIO35_MSP1_TCK | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_DISABLE, 35struct pinctrl_state *msp1_sleep;
35 GPIO36_MSP1_RXD | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_DISABLE,
36};
37
38static pin_cfg_t mop500_msp1_pins_exit[] = {
39 GPIO33_MSP1_TXD | PIN_OUTPUT_LOW | PIN_SLPM_WAKEUP_ENABLE,
40 GPIO34_MSP1_TFS | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_ENABLE,
41 GPIO35_MSP1_TCK | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_ENABLE,
42 GPIO36_MSP1_RXD | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_ENABLE,
43};
44 36
45int msp13_i2s_init(void) 37int msp13_i2s_init(void)
46{ 38{
@@ -48,9 +40,11 @@ int msp13_i2s_init(void)
48 unsigned long flags; 40 unsigned long flags;
49 41
50 spin_lock_irqsave(&msp_rxtx_lock, flags); 42 spin_lock_irqsave(&msp_rxtx_lock, flags);
51 if (msp_rxtx_ref == 0) 43 if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_def))) {
52 retval = nmk_config_pins( 44 retval = pinctrl_select_state(msp1_p, msp1_def);
53 ARRAY_AND_SIZE(mop500_msp1_pins_init)); 45 if (retval)
46 pr_err("could not set MSP1 defstate\n");
47 }
54 if (!retval) 48 if (!retval)
55 msp_rxtx_ref++; 49 msp_rxtx_ref++;
56 spin_unlock_irqrestore(&msp_rxtx_lock, flags); 50 spin_unlock_irqrestore(&msp_rxtx_lock, flags);
@@ -66,9 +60,11 @@ int msp13_i2s_exit(void)
66 spin_lock_irqsave(&msp_rxtx_lock, flags); 60 spin_lock_irqsave(&msp_rxtx_lock, flags);
67 WARN_ON(!msp_rxtx_ref); 61 WARN_ON(!msp_rxtx_ref);
68 msp_rxtx_ref--; 62 msp_rxtx_ref--;
69 if (msp_rxtx_ref == 0) 63 if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_sleep))) {
70 retval = nmk_config_pins_sleep( 64 retval = pinctrl_select_state(msp1_p, msp1_sleep);
71 ARRAY_AND_SIZE(mop500_msp1_pins_exit)); 65 if (retval)
66 pr_err("could not set MSP1 sleepstate\n");
67 }
72 spin_unlock_irqrestore(&msp_rxtx_lock, flags); 68 spin_unlock_irqrestore(&msp_rxtx_lock, flags);
73 69
74 return retval; 70 return retval;
@@ -170,7 +166,8 @@ static struct stedma40_chan_cfg msp2_dma_tx = {
170 /* data_width is set during configuration */ 166 /* data_width is set during configuration */
171}; 167};
172 168
173static int db8500_add_msp_i2s(struct device *parent, int id, 169static struct platform_device *db8500_add_msp_i2s(struct device *parent,
170 int id,
174 resource_size_t base, int irq, 171 resource_size_t base, int irq,
175 struct msp_i2s_platform_data *pdata) 172 struct msp_i2s_platform_data *pdata)
176{ 173{
@@ -188,10 +185,10 @@ static int db8500_add_msp_i2s(struct device *parent, int id,
188 if (!pdev) { 185 if (!pdev) {
189 pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n", 186 pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n",
190 id); 187 id);
191 return -EIO; 188 return NULL;
192 } 189 }
193 190
194 return 0; 191 return pdev;
195} 192}
196 193
197/* Platform device for ASoC U8500 machine */ 194/* Platform device for ASoC U8500 machine */
@@ -228,23 +225,43 @@ static struct msp_i2s_platform_data msp3_platform_data = {
228 225
229int mop500_msp_init(struct device *parent) 226int mop500_msp_init(struct device *parent)
230{ 227{
231 int ret; 228 struct platform_device *msp1;
232 229
233 pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__); 230 pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__);
234 platform_device_register(&snd_soc_u8500); 231 platform_device_register(&snd_soc_u8500);
235 232
236 pr_info("Initialize MSP I2S-devices.\n"); 233 pr_info("Initialize MSP I2S-devices.\n");
237 ret = db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, 234 db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
238 &msp0_platform_data); 235 &msp0_platform_data);
239 ret |= db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, 236 msp1 = db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
240 &msp1_platform_data); 237 &msp1_platform_data);
241 ret |= db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, 238 db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
242 &msp2_platform_data); 239 &msp2_platform_data);
243 ret |= db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, 240 db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
244 &msp3_platform_data); 241 &msp3_platform_data);
242
243 /* Get the pinctrl handle for MSP1 */
244 if (msp1) {
245 msp1_p = pinctrl_get(&msp1->dev);
246 if (IS_ERR(msp1_p))
247 dev_err(&msp1->dev, "could not get MSP1 pinctrl\n");
248 else {
249 msp1_def = pinctrl_lookup_state(msp1_p,
250 PINCTRL_STATE_DEFAULT);
251 if (IS_ERR(msp1_def)) {
252 dev_err(&msp1->dev,
253 "could not get MSP1 defstate\n");
254 }
255 msp1_sleep = pinctrl_lookup_state(msp1_p,
256 PINCTRL_STATE_SLEEP);
257 if (IS_ERR(msp1_sleep))
258 dev_err(&msp1->dev,
259 "could not get MSP1 idlestate\n");
260 }
261 }
245 262
246 pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__); 263 pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
247 platform_device_register(&ux500_pcm); 264 platform_device_register(&ux500_pcm);
248 265
249 return ret; 266 return 0;
250} 267}
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index df5b190d331c..32fd99204464 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -8,6 +8,7 @@
8#include <linux/init.h> 8#include <linux/init.h>
9#include <linux/bug.h> 9#include <linux/bug.h>
10#include <linux/string.h> 10#include <linux/string.h>
11#include <linux/pinctrl/machine.h>
11 12
12#include <asm/mach-types.h> 13#include <asm/mach-types.h>
13#include <plat/pincfg.h> 14#include <plat/pincfg.h>
@@ -16,7 +17,6 @@
16#include <mach/hardware.h> 17#include <mach/hardware.h>
17 18
18#include "pins-db8500.h" 19#include "pins-db8500.h"
19#include "pins.h"
20#include "board-mop500.h" 20#include "board-mop500.h"
21 21
22enum custom_pin_cfg_t { 22enum custom_pin_cfg_t {
@@ -26,399 +26,425 @@ enum custom_pin_cfg_t {
26 26
27static enum custom_pin_cfg_t pinsfor; 27static enum custom_pin_cfg_t pinsfor;
28 28
29static pin_cfg_t mop500_pins_common[] = { 29/* These simply sets bias for pins */
30 /* uMSP0 */ 30#define BIAS(a,b) static unsigned long a[] = { b }
31 GPIO12_MSP0_TXD, 31
32 GPIO13_MSP0_TFS, 32BIAS(pd, PIN_PULL_DOWN);
33 GPIO14_MSP0_TCK, 33BIAS(slpm_gpio_nopull, PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
34 GPIO15_MSP0_RXD, 34BIAS(in_nopull, PIN_INPUT_NOPULL);
35 35BIAS(in_nopull_sleep_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
36 /* MSP2: HDMI */ 36BIAS(in_pu, PIN_INPUT_PULLUP);
37 GPIO193_MSP2_TXD | PIN_INPUT_PULLDOWN, 37BIAS(in_pd, PIN_INPUT_PULLDOWN);
38 GPIO194_MSP2_TCK | PIN_INPUT_PULLDOWN, 38BIAS(in_pd_slpm_in_pu, PIN_INPUT_PULLDOWN|PIN_SLPM_INPUT_PULLUP);
39 GPIO195_MSP2_TFS | PIN_INPUT_PULLDOWN, 39BIAS(in_pu_slpm_out_lo, PIN_INPUT_PULLUP|PIN_SLPM_OUTPUT_LOW);
40 GPIO196_MSP2_RXD | PIN_OUTPUT_LOW, 40BIAS(out_hi, PIN_OUTPUT_HIGH);
41 41BIAS(out_lo, PIN_OUTPUT_LOW);
42 /* LCD TE0 */ 42BIAS(out_lo_sleep_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
43 GPIO68_LCD_VSI0 | PIN_INPUT_PULLUP, 43/* These also force them into GPIO mode */
44 44BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
45 /* Touch screen INTERFACE */ 45BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
46 GPIO84_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT1 */ 46BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
47 47BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
48 /* STMPE1601/tc35893 keypad IRQ */ 48BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
49 GPIO218_GPIO | PIN_INPUT_PULLUP, 49BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
50 50/* Sleep modes */
51 /* UART */ 51BIAS(sleep_in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
52 /* uart-0 pins gpio configuration should be 52BIAS(sleep_in_nopull_wkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE);
53 * kept intact to prevent glitch in tx line 53BIAS(sleep_out_hi_wkup_pdis, PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
54 * when tty dev is opened. Later these pins 54BIAS(sleep_out_lo_wkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
55BIAS(sleep_out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
56
57/* We use these to define hog settings that are always done on boot */
58#define DB8500_MUX_HOG(group,func) \
59 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
60#define DB8500_PIN_HOG(pin,conf) \
61 PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
62
63/* These are default states associated with device and changed runtime */
64#define DB8500_MUX(group,func,dev) \
65 PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
66#define DB8500_PIN(pin,conf,dev) \
67 PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
68
69#define DB8500_PIN_SLEEP(pin,conf,dev) \
70 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
71 pin, conf)
72
73/* Pin control settings */
74static struct pinctrl_map __initdata mop500_family_pinmap[] = {
75 /*
76 * uMSP0, mux in 4 pins, regular placement of RX/TX
77 * explicitly set the pins to no pull
78 */
79 DB8500_MUX_HOG("msp0txrx_a_1", "msp0"),
80 DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"),
81 DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */
82 DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */
83 DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */
84 DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */
85 /* MSP2 for HDMI, pull down TXD, TCK, TFS */
86 DB8500_MUX_HOG("msp2_a_1", "msp2"),
87 DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */
88 DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */
89 DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */
90 DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */
91 /*
92 * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
93 * pull-up
94 * TODO: is this really correct? Snowball doesn't have a LCD.
95 */
96 DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
97 DB8500_PIN_HOG("GPIO68_E1", in_pu),
98 DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
99 /*
100 * STMPE1601/tc35893 keypad IRQ GPIO 218
101 * TODO: set for snowball and HREF really??
102 */
103 DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
104 /*
105 * UART0, we do not mux in u0 here.
106 * uart-0 pins gpio configuration should be kept intact to prevent
107 * a glitch in tx line when the tty dev is opened. Later these pins
55 * are configured to uart mop500_pins_uart0 108 * are configured to uart mop500_pins_uart0
56 *
57 * It will be replaced with uart configuration
58 * once the issue is solved.
59 */ 109 */
60 GPIO0_GPIO | PIN_INPUT_PULLUP, 110 DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
61 GPIO1_GPIO | PIN_OUTPUT_HIGH, 111 DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
62 GPIO2_GPIO | PIN_INPUT_PULLUP, 112 DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
63 GPIO3_GPIO | PIN_OUTPUT_HIGH, 113 DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
64 114 /*
65 GPIO29_U2_RXD | PIN_INPUT_PULLUP, 115 * Mux in UART2 on altfunction C and set pull-ups.
66 GPIO30_U2_TXD | PIN_OUTPUT_HIGH, 116 * TODO: is this used on U8500 variants and Snowball really?
67 GPIO31_U2_CTSn | PIN_INPUT_PULLUP, 117 * The setting on GPIO31 conflicts with magnetometer use on hrefv60
68 GPIO32_U2_RTSn | PIN_OUTPUT_HIGH, 118 */
119 DB8500_MUX_HOG("u2rxtx_c_1", "u2"),
120 DB8500_MUX_HOG("u2ctsrts_c_1", "u2"),
121 DB8500_PIN_HOG("GPIO29_W2", in_pu), /* RXD */
122 DB8500_PIN_HOG("GPIO30_W3", out_hi), /* TXD */
123 DB8500_PIN_HOG("GPIO31_V3", in_pu), /* CTS */
124 DB8500_PIN_HOG("GPIO32_V2", out_hi), /* RTS */
125 /*
126 * The following pin sets were known as "runtime pins" before being
127 * converted to the pinctrl model. Here we model them as "default"
128 * states.
129 */
130 /* Mux in UART0 after initialization */
131 DB8500_MUX("u0_a_1", "u0", "uart0"),
132 DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
133 DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
134 DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
135 DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
136 /* UART0 sleep state */
137 DB8500_PIN_SLEEP("GPIO0_AJ5", sleep_in_wkup_pdis, "uart0"),
138 DB8500_PIN_SLEEP("GPIO1_AJ3", sleep_out_hi_wkup_pdis, "uart0"),
139 DB8500_PIN_SLEEP("GPIO2_AH4", sleep_in_wkup_pdis, "uart0"),
140 DB8500_PIN_SLEEP("GPIO3_AH3", sleep_out_wkup_pdis, "uart0"),
141 /* MSP1 for ALSA codec */
142 DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
143 DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
144 DB8500_PIN("GPIO33_AF2", out_lo_sleep_nowkup, "ux500-msp-i2s.1"),
145 DB8500_PIN("GPIO34_AE1", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
146 DB8500_PIN("GPIO35_AE2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
147 DB8500_PIN("GPIO36_AG2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
148 /* MSP1 sleep state */
149 DB8500_PIN_SLEEP("GPIO33_AF2", sleep_out_lo_wkup, "ux500-msp-i2s.1"),
150 DB8500_PIN_SLEEP("GPIO34_AE1", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
151 DB8500_PIN_SLEEP("GPIO35_AE2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
152 DB8500_PIN_SLEEP("GPIO36_AG2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
153 /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
154 DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
155 DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
156 /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
157 DB8500_MUX("lcdvsi1_a_1", "lcd", "av8100-hdmi"),
158 /* Mux in I2C blocks, put pins into GPIO in sleepmode no pull-up */
159 DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
160 DB8500_PIN("GPIO147_C15", slpm_gpio_nopull, "nmk-i2c.0"),
161 DB8500_PIN("GPIO148_B16", slpm_gpio_nopull, "nmk-i2c.0"),
162 DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
163 DB8500_PIN("GPIO16_AD3", slpm_gpio_nopull, "nmk-i2c.1"),
164 DB8500_PIN("GPIO17_AD4", slpm_gpio_nopull, "nmk-i2c.1"),
165 DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
166 DB8500_PIN("GPIO10_AF5", slpm_gpio_nopull, "nmk-i2c.2"),
167 DB8500_PIN("GPIO11_AG4", slpm_gpio_nopull, "nmk-i2c.2"),
168 DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
169 DB8500_PIN("GPIO229_AG7", slpm_gpio_nopull, "nmk-i2c.3"),
170 DB8500_PIN("GPIO230_AF7", slpm_gpio_nopull, "nmk-i2c.3"),
171 /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
172 DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
173 DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
174 DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */
175 DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */
176 DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */
177 DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */
178 DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */
179 DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */
180 DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
181 DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
182 DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
183 /* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
184 DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
185 DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
186 DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */
187 DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */
188 DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */
189 DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
190 DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
191 DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
192 /* Mux in SDI2 (here called MC2) used for for PoP eMMC */
193 DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
194 DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
195 DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */
196 DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */
197 DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */
198 DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */
199 DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */
200 DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */
201 DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */
202 DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
203 DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
204 DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
205 /* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
206 DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
207 DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
208 DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */
209 DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */
210 DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */
211 DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */
212 DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */
213 DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */
214 DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */
215 DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
216 DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
217 DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
218 /* Mux in USB pins, drive STP high */
219 DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
220 DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
221 /* Mux in SPI2 pins on the "other C1" altfunction */
222 DB8500_MUX("spi2_oc1_1", "spi2", "spi2"),
223 DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
224 DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
225 DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
226 DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
69}; 227};
70 228
71static pin_cfg_t mop500_pins_default[] = { 229/*
72 /* SSP0 */ 230 * These are specifically for the MOP500 and HREFP (pre-v60) version of the
73 GPIO143_SSP0_CLK, 231 * board, which utilized a TC35892 GPIO expander instead of using a lot of
74 GPIO144_SSP0_FRM, 232 * on-chip pins as the HREFv60 and later does.
75 GPIO145_SSP0_RXD | PIN_PULL_DOWN, 233 */
76 GPIO146_SSP0_TXD, 234static struct pinctrl_map __initdata mop500_pinmap[] = {
77 235 /* Mux in SSP0, pull down RXD pin */
78 /* XENON Flashgun INTERFACE */ 236 DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
79 GPIO6_IP_GPIO0 | PIN_INPUT_PULLUP,/* XENON_FLASH_ID */ 237 DB8500_PIN_HOG("GPIO145_C13", pd),
80 GPIO7_IP_GPIO1 | PIN_INPUT_PULLUP,/* XENON_READY */ 238 /*
81 239 * XENON Flashgun on image processor GPIO (controlled from image
82 GPIO217_GPIO | PIN_INPUT_PULLUP, /* TC35892 IRQ */ 240 * processor firmware), mux in these image processor GPIO lines 0
83 241 * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
84 /* sdi0 (removable MMC/SD/SDIO cards) not handled by pm_runtime */ 242 * the pins.
85 GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, 243 */
86 244 DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
87 /* UART */ 245 DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
88 GPIO4_U1_RXD | PIN_INPUT_PULLUP, 246 DB8500_PIN_HOG("GPIO6_AF6", in_pu),
89 GPIO5_U1_TXD | PIN_OUTPUT_HIGH, 247 DB8500_PIN_HOG("GPIO7_AG5", in_pu),
90 GPIO6_U1_CTSn | PIN_INPUT_PULLUP, 248 /* TC35892 IRQ, pull up the line, let the driver mux in the pin */
91 GPIO7_U1_RTSn | PIN_OUTPUT_HIGH, 249 DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
250 /* Mux in UART1 and set the pull-ups */
251 DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
252 DB8500_MUX_HOG("u1ctsrts_a_1", "u1"),
253 DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
254 DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
255 DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* CTS */
256 DB8500_PIN_HOG("GPIO7_AG5", out_hi), /* RTS */
257 /*
258 * Runtime stuff: make it possible to mux in the SKE keypad
259 * and bias the pins
260 */
261 DB8500_MUX("kp_a_2", "kp", "ske"),
262 DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */
263 DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */
264 DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */
265 DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */
266 DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */
267 DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */
268 DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */
269 DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */
270 DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */
271 DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */
272 DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */
273 DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */
274 DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */
275 DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */
276 DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */
277 DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */
278 /* Mux in and drive the SDI0 DAT31DIR line high at runtime */
279 DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
280 DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
92}; 281};
93 282
94static pin_cfg_t hrefv60_pins[] = { 283/*
95 /* WLAN */ 284 * The HREFv60 series of platforms is using available pins on the DB8500
96 GPIO85_GPIO | PIN_OUTPUT_LOW,/* WLAN_ENA */ 285 * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
97 286 * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
98 /* XENON Flashgun INTERFACE */ 287 */
99 GPIO6_IP_GPIO0 | PIN_INPUT_PULLUP,/* XENON_FLASH_ID */ 288static struct pinctrl_map __initdata hrefv60_pinmap[] = {
100 GPIO7_IP_GPIO1 | PIN_INPUT_PULLUP,/* XENON_READY */ 289 /* Drive WLAN_ENA low */
101 290 DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
102 /* Assistant LED INTERFACE */ 291 /*
103 GPIO21_GPIO | PIN_OUTPUT_LOW, /* XENON_EN1 */ 292 * XENON Flashgun on image processor GPIO (controlled from image
104 GPIO64_IP_GPIO4 | PIN_OUTPUT_LOW, /* XENON_EN2 */ 293 * processor firmware), mux in these image processor GPIO lines 0
105 294 * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
106 /* Magnetometer */ 295 * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
107 GPIO31_GPIO | PIN_INPUT_PULLUP, /* magnetometer_INT */ 296 * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
108 GPIO32_GPIO | PIN_INPUT_PULLDOWN, /* Magnetometer DRDY */ 297 */
109 298 DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
110 /* Display Interface */ 299 DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
111 GPIO65_GPIO | PIN_OUTPUT_HIGH, /* DISP1 NO RST */ 300 DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
112 GPIO66_GPIO | PIN_OUTPUT_LOW, /* DISP2 RST */ 301 DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
113 302 DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
114 /* Touch screen INTERFACE */ 303 DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
115 GPIO143_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST1 */ 304 DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
116 305 /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
117 /* Touch screen INTERFACE 2 */ 306 DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
118 GPIO67_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT2 */ 307 DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
119 GPIO146_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST2 */ 308 /*
120 309 * Display Interface 1 uses GPIO 65 for RST (reset).
121 /* ETM_PTM_TRACE INTERFACE */ 310 * Display Interface 2 uses GPIO 66 for RST (reset).
122 GPIO70_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA23 */ 311 * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
123 GPIO71_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA22 */ 312 */
124 GPIO72_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA21 */ 313 DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
125 GPIO73_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA20 */ 314 DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
126 GPIO74_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA19 */ 315 /*
127 316 * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
128 /* NAHJ INTERFACE */ 317 * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
129 GPIO76_GPIO | PIN_OUTPUT_LOW,/* NAHJ_CTRL */ 318 * reset signals low.
130 GPIO216_GPIO | PIN_OUTPUT_HIGH,/* NAHJ_CTRL_INV */ 319 */
131 320 DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
132 /* NFC INTERFACE */ 321 DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
133 GPIO77_GPIO | PIN_OUTPUT_LOW, /* NFC_ENA */ 322 DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
134 GPIO144_GPIO | PIN_INPUT_PULLDOWN, /* NFC_IRQ */ 323 /*
135 GPIO142_GPIO | PIN_OUTPUT_LOW, /* NFC_RESET */ 324 * Drive D19-D23 for the ETM PTM trace interface low,
136 325 * (presumably pins are unconnected therefore grounded here,
137 /* Keyboard MATRIX INTERFACE */ 326 * the "other alt C1" setting enables these pins)
138 GPIO90_MC5_CMD | PIN_OUTPUT_LOW, /* KP_O_1 */ 327 */
139 GPIO87_MC5_DAT1 | PIN_OUTPUT_LOW, /* KP_O_2 */ 328 DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
140 GPIO86_MC5_DAT0 | PIN_OUTPUT_LOW, /* KP_O_3 */ 329 DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
141 GPIO96_KP_O6 | PIN_OUTPUT_LOW, /* KP_O_6 */ 330 DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
142 GPIO94_KP_O7 | PIN_OUTPUT_LOW, /* KP_O_7 */ 331 DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
143 GPIO93_MC5_DAT4 | PIN_INPUT_PULLUP, /* KP_I_0 */ 332 DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
144 GPIO89_MC5_DAT3 | PIN_INPUT_PULLUP, /* KP_I_2 */ 333 /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
145 GPIO88_MC5_DAT2 | PIN_INPUT_PULLUP, /* KP_I_3 */ 334 DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
146 GPIO91_GPIO | PIN_INPUT_PULLUP, /* FORCE_SENSING_INT */ 335 DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
147 GPIO92_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_RST */ 336 /* NFC ENA and RESET to low, pulldown IRQ line */
148 GPIO97_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_WU */ 337 DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
149 338 DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
150 /* DiPro Sensor Interface */ 339 DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
151 GPIO139_GPIO | PIN_INPUT_PULLUP, /* DIPRO_INT */ 340 /*
152 341 * SKE keyboard partly on alt A and partly on "Other alt C1"
153 /* Audio Amplifier Interface */ 342 * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
154 GPIO149_GPIO | PIN_OUTPUT_HIGH, /* VAUDIO_HF_EN, enable MAX8968 */ 343 * rows of 6 keys, then pull up force sensing interrup and
155 344 * drive reset and force sensing WU low.
156 /* GBF INTERFACE */ 345 */
157 GPIO171_GPIO | PIN_OUTPUT_LOW, /* GBF_ENA_RESET */ 346 DB8500_MUX_HOG("kp_a_1", "kp"),
158 347 DB8500_MUX_HOG("kp_oc1_1", "kp"),
159 /* MSP : HDTV INTERFACE */ 348 DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
160 GPIO192_GPIO | PIN_INPUT_PULLDOWN, 349 DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
161 350 DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
162 /* ACCELEROMETER_INTERFACE */ 351 DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
163 GPIO82_GPIO | PIN_INPUT_PULLUP, /* ACC_INT1 */ 352 DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
164 GPIO83_GPIO | PIN_INPUT_PULLUP, /* ACC_INT2 */ 353 DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
165 354 DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
166 /* SD card detect */ 355 DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
167 GPIO95_GPIO | PIN_INPUT_PULLUP, 356 DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
357 DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
358 DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
359 /* DiPro Sensor interrupt */
360 DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
361 /* Audio Amplifier HF enable */
362 DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
363 /* GBF interface, pull low to reset state */
364 DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
365 /* MSP : HDTV INTERFACE GPIO line */
366 DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
367 /* Accelerometer interrupt lines */
368 DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
369 DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
370 /* SD card detect GPIO pin */
371 DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu),
372 /*
373 * Runtime stuff
374 * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
375 * etc.
376 */
377 DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
378 DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
379 DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
380 /*
381 * Make it possible to mux in the SKE keypad and bias the pins
382 * FIXME: what's the point with this on HREFv60? KP/SKE is already
383 * muxed in at another place! Enabling this will bork.
384 */
385 DB8500_MUX("kp_a_2", "kp", "ske"),
386 DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */
387 DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */
388 DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */
389 DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */
390 DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */
391 DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */
392 DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */
393 DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */
394 DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */
395 DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */
396 DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */
397 DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */
398 DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */
399 DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */
400 DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */
401 DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */
168}; 402};
169 403
170static pin_cfg_t u9500_pins[] = { 404static struct pinctrl_map __initdata u9500_pinmap[] = {
171 GPIO4_U1_RXD | PIN_INPUT_PULLUP, 405 /* Mux in UART1 (just RX/TX) and set the pull-ups */
172 GPIO5_U1_TXD | PIN_OUTPUT_HIGH, 406 DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
173 GPIO144_GPIO | PIN_INPUT_PULLUP,/* WLAN_IRQ */ 407 DB8500_PIN_HOG("GPIO4_AH6", in_pu),
174 408 DB8500_PIN_HOG("GPIO5_AG6", out_hi),
409 /* WLAN_IRQ line */
410 DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
175 /* HSI */ 411 /* HSI */
176 GPIO219_HSIR_FLA0 | PIN_INPUT_PULLDOWN, 412 DB8500_MUX_HOG("hsir_a_1", "hsi"),
177 GPIO220_HSIR_DAT0 | PIN_INPUT_PULLDOWN, 413 DB8500_MUX_HOG("hsit_a_1", "hsi"),
178 GPIO221_HSIR_RDY0 | PIN_OUTPUT_LOW, 414 DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
179 GPIO222_HSIT_FLA0 | PIN_OUTPUT_LOW, 415 DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
180 GPIO223_HSIT_DAT0 | PIN_OUTPUT_LOW, 416 DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
181 GPIO224_HSIT_RDY0 | PIN_INPUT_PULLDOWN, 417 DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
182 GPIO225_HSIT_CAWAKE0 | PIN_INPUT_PULLDOWN, /* CA_WAKE0 */ 418 DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
183 GPIO226_GPIO | PIN_OUTPUT_HIGH, /* AC_WAKE0 */ 419 DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
420 DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
421 DB8500_PIN_HOG("GPIO226_AF8", out_hi), /* ACWAKE0 */
184}; 422};
185 423
186static pin_cfg_t u8500_pins[] = { 424static struct pinctrl_map __initdata u8500_pinmap[] = {
187 GPIO226_GPIO | PIN_OUTPUT_LOW, /* WLAN_PMU_EN */ 425 DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
188 GPIO4_GPIO | PIN_INPUT_PULLUP,/* WLAN_IRQ */ 426 DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
189}; 427};
190 428
191static pin_cfg_t snowball_pins[] = { 429static struct pinctrl_map __initdata snowball_pinmap[] = {
192 /* SSP0, to AB8500 */ 430 /* Mux in SSP0 connected to AB8500, pull down RXD pin */
193 GPIO143_SSP0_CLK, 431 DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
194 GPIO144_SSP0_FRM, 432 DB8500_PIN_HOG("GPIO145_C13", pd),
195 GPIO145_SSP0_RXD | PIN_PULL_DOWN, 433 /* Always drive the MC0 DAT31DIR line high on these boards */
196 GPIO146_SSP0_TXD, 434 DB8500_PIN_HOG("GPIO21_AB3", out_hi),
197 435 /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
198 /* MMC0: MicroSD card */ 436 DB8500_MUX_HOG("sm_b_1", "sm"),
199 GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, 437 /* Drive RSTn_LAN high */
200 438 DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
201 /* MMC2: LAN */
202 GPIO86_SM_ADQ0,
203 GPIO87_SM_ADQ1,
204 GPIO88_SM_ADQ2,
205 GPIO89_SM_ADQ3,
206 GPIO90_SM_ADQ4,
207 GPIO91_SM_ADQ5,
208 GPIO92_SM_ADQ6,
209 GPIO93_SM_ADQ7,
210
211 GPIO94_SM_ADVn,
212 GPIO95_SM_CS0n,
213 GPIO96_SM_OEn,
214 GPIO97_SM_WEn,
215
216 GPIO128_SM_CKO,
217 GPIO130_SM_FBCLK,
218 GPIO131_SM_ADQ8,
219 GPIO132_SM_ADQ9,
220 GPIO133_SM_ADQ10,
221 GPIO134_SM_ADQ11,
222 GPIO135_SM_ADQ12,
223 GPIO136_SM_ADQ13,
224 GPIO137_SM_ADQ14,
225 GPIO138_SM_ADQ15,
226
227 /* RSTn_LAN */
228 GPIO141_GPIO | PIN_OUTPUT_HIGH,
229
230 /* Accelerometer/Magnetometer */ 439 /* Accelerometer/Magnetometer */
231 GPIO163_GPIO | PIN_INPUT_PULLUP, /* ACCEL_IRQ1 */ 440 DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
232 GPIO164_GPIO | PIN_INPUT_PULLUP, /* ACCEL_IRQ2 */ 441 DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
233 GPIO165_GPIO | PIN_INPUT_PULLUP, /* MAG_DRDY */ 442 DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
234
235 /* WLAN/GBF */ 443 /* WLAN/GBF */
236 GPIO161_GPIO | PIN_OUTPUT_LOW, /* WLAN_PMU_EN */ 444 DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
237 GPIO171_GPIO | PIN_OUTPUT_HIGH,/* GBF_ENA */ 445 DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
238 GPIO215_GPIO | PIN_OUTPUT_LOW,/* WLAN_ENA */ 446 DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
239 GPIO216_GPIO | PIN_INPUT_PULLUP,/* WLAN_IRQ */ 447 DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
240};
241
242/*
243 * I2C
244 */
245
246static UX500_PINS(mop500_pins_i2c0,
247 GPIO147_I2C0_SCL |
248 PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
249 GPIO148_I2C0_SDA |
250 PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
251);
252
253static UX500_PINS(mop500_pins_i2c1,
254 GPIO16_I2C1_SCL |
255 PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
256 GPIO17_I2C1_SDA |
257 PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
258);
259
260static UX500_PINS(mop500_pins_i2c2,
261 GPIO10_I2C2_SDA |
262 PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
263 GPIO11_I2C2_SCL |
264 PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
265);
266
267static UX500_PINS(mop500_pins_i2c3,
268 GPIO229_I2C3_SDA |
269 PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
270 GPIO230_I2C3_SCL |
271 PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
272);
273
274static UX500_PINS(mop500_pins_mcde_tvout,
275 GPIO78_LCD_D8,
276 GPIO79_LCD_D9,
277 GPIO80_LCD_D10,
278 GPIO81_LCD_D11,
279 GPIO150_LCDA_CLK,
280);
281
282static UX500_PINS(mop500_pins_mcde_hdmi,
283 GPIO69_LCD_VSI1 | PIN_INPUT_PULLUP,
284);
285
286static UX500_PINS(mop500_pins_ske,
287 GPIO153_KP_I7 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
288 GPIO154_KP_I6 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
289 GPIO155_KP_I5 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
290 GPIO156_KP_I4 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
291 GPIO161_KP_I3 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
292 GPIO162_KP_I2 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
293 GPIO163_KP_I1 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
294 GPIO164_KP_I0 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
295 GPIO157_KP_O7 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
296 GPIO158_KP_O6 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
297 GPIO159_KP_O5 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
298 GPIO160_KP_O4 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
299 GPIO165_KP_O3 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
300 GPIO166_KP_O2 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
301 GPIO167_KP_O1 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
302 GPIO168_KP_O0 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
303);
304
305/* sdi0 (removable MMC/SD/SDIO cards) */
306static UX500_PINS(mop500_pins_sdi0,
307 GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH,
308 GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH,
309 GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH,
310
311 GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL,
312 GPIO23_MC0_CLK | PIN_OUTPUT_LOW,
313 GPIO24_MC0_CMD | PIN_INPUT_PULLUP,
314 GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP,
315 GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP,
316 GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP,
317 GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP,
318);
319
320/* sdi1 (WLAN CW1200) */
321static UX500_PINS(mop500_pins_sdi1,
322 GPIO208_MC1_CLK | PIN_OUTPUT_LOW,
323 GPIO209_MC1_FBCLK | PIN_INPUT_NOPULL,
324 GPIO210_MC1_CMD | PIN_INPUT_PULLUP,
325 GPIO211_MC1_DAT0 | PIN_INPUT_PULLUP,
326 GPIO212_MC1_DAT1 | PIN_INPUT_PULLUP,
327 GPIO213_MC1_DAT2 | PIN_INPUT_PULLUP,
328 GPIO214_MC1_DAT3 | PIN_INPUT_PULLUP,
329);
330
331/* sdi2 (POP eMMC) */
332static UX500_PINS(mop500_pins_sdi2,
333 GPIO128_MC2_CLK | PIN_OUTPUT_LOW,
334 GPIO129_MC2_CMD | PIN_INPUT_PULLUP,
335 GPIO130_MC2_FBCLK | PIN_INPUT_NOPULL,
336 GPIO131_MC2_DAT0 | PIN_INPUT_PULLUP,
337 GPIO132_MC2_DAT1 | PIN_INPUT_PULLUP,
338 GPIO133_MC2_DAT2 | PIN_INPUT_PULLUP,
339 GPIO134_MC2_DAT3 | PIN_INPUT_PULLUP,
340 GPIO135_MC2_DAT4 | PIN_INPUT_PULLUP,
341 GPIO136_MC2_DAT5 | PIN_INPUT_PULLUP,
342 GPIO137_MC2_DAT6 | PIN_INPUT_PULLUP,
343 GPIO138_MC2_DAT7 | PIN_INPUT_PULLUP,
344);
345
346/* sdi4 (PCB eMMC) */
347static UX500_PINS(mop500_pins_sdi4,
348 GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP,
349 GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP,
350 GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP,
351 GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP,
352 GPIO201_MC4_CMD | PIN_INPUT_PULLUP,
353 GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL,
354 GPIO203_MC4_CLK | PIN_OUTPUT_LOW,
355 GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP,
356 GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP,
357 GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP,
358 GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP,
359);
360
361/* USB */
362static UX500_PINS(mop500_pins_usb,
363 GPIO256_USB_NXT,
364 GPIO257_USB_STP | PIN_OUTPUT_HIGH,
365 GPIO258_USB_XCLK,
366 GPIO259_USB_DIR,
367 GPIO260_USB_DAT7,
368 GPIO261_USB_DAT6,
369 GPIO262_USB_DAT5,
370 GPIO263_USB_DAT4,
371 GPIO264_USB_DAT3,
372 GPIO265_USB_DAT2,
373 GPIO266_USB_DAT1,
374 GPIO267_USB_DAT0,
375);
376
377/* SPI2 */
378static UX500_PINS(mop500_pins_spi2,
379 GPIO216_GPIO | PIN_OUTPUT_HIGH,
380 GPIO218_SPI2_RXD | PIN_INPUT_PULLDOWN,
381 GPIO215_SPI2_TXD | PIN_OUTPUT_LOW,
382 GPIO217_SPI2_CLK | PIN_OUTPUT_LOW,
383);
384
385static UX500_PINS(mop500_pins_sensors1p_v60,
386 GPIO217_GPIO| PIN_INPUT_PULLUP |
387 PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
388 GPIO145_GPIO | PIN_INPUT_PULLDOWN |
389 PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
390 GPIO139_GPIO | PIN_INPUT_PULLUP |
391 PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
392);
393
394static UX500_PINS(mop500_pins_sensors1p,
395 PIN_CFG_INPUT(GPIO_PROX_SENSOR, GPIO, NOPULL),
396 PIN_CFG_INPUT(GPIO_HAL_SENSOR, GPIO, NOPULL),
397);
398
399static struct ux500_pin_lookup mop500_runtime_pins[] = {
400 PIN_LOOKUP("mcde-tvout", &mop500_pins_mcde_tvout),
401 PIN_LOOKUP("av8100-hdmi", &mop500_pins_mcde_hdmi),
402 PIN_LOOKUP("nmk-i2c.0", &mop500_pins_i2c0),
403 PIN_LOOKUP("nmk-i2c.1", &mop500_pins_i2c1),
404 PIN_LOOKUP("nmk-i2c.2", &mop500_pins_i2c2),
405 PIN_LOOKUP("nmk-i2c.3", &mop500_pins_i2c3),
406 PIN_LOOKUP("sdi0", &mop500_pins_sdi0),
407 PIN_LOOKUP("sdi1", &mop500_pins_sdi1),
408 PIN_LOOKUP("sdi2", &mop500_pins_sdi2),
409 PIN_LOOKUP("sdi4", &mop500_pins_sdi4),
410 PIN_LOOKUP("musb-ux500.0", &mop500_pins_usb),
411 PIN_LOOKUP("spi2", &mop500_pins_spi2),
412};
413
414static struct ux500_pin_lookup mop500_runtime_pins_v60[] = {
415 PIN_LOOKUP("ske", &mop500_pins_ske),
416 PIN_LOOKUP("gpio-keys.0", &mop500_pins_sensors1p_v60),
417};
418
419static struct ux500_pin_lookup mop500_runtime_pins_pre_v60[] = {
420 PIN_LOOKUP("ske", &mop500_pins_ske),
421 PIN_LOOKUP("gpio-keys.0", &mop500_pins_sensors1p),
422}; 448};
423 449
424/* 450/*
@@ -444,64 +470,45 @@ int pins_for_u9500(void)
444 return 0; 470 return 0;
445} 471}
446 472
447void __init mop500_pins_init(void) 473static void __init mop500_href_family_pinmaps_init(void)
448{ 474{
449 nmk_config_pins(mop500_pins_common,
450 ARRAY_SIZE(mop500_pins_common));
451
452 ux500_pins_add(mop500_runtime_pins, ARRAY_SIZE(mop500_runtime_pins));
453
454 ux500_pins_add(mop500_runtime_pins_pre_v60,
455 ARRAY_SIZE(mop500_runtime_pins_pre_v60));
456
457 switch (pinsfor) { 475 switch (pinsfor) {
458 case PINS_FOR_U9500: 476 case PINS_FOR_U9500:
459 nmk_config_pins(u9500_pins, ARRAY_SIZE(u9500_pins)); 477 pinctrl_register_mappings(u9500_pinmap,
478 ARRAY_SIZE(u9500_pinmap));
460 break; 479 break;
461
462 case PINS_FOR_DEFAULT: 480 case PINS_FOR_DEFAULT:
463 nmk_config_pins(u8500_pins, ARRAY_SIZE(u8500_pins)); 481 pinctrl_register_mappings(u8500_pinmap,
482 ARRAY_SIZE(u8500_pinmap));
464 default: 483 default:
465 break; 484 break;
466 } 485 }
467
468 nmk_config_pins(mop500_pins_default,
469 ARRAY_SIZE(mop500_pins_default));
470} 486}
471 487
472void __init snowball_pins_init(void) 488void __init mop500_pinmaps_init(void)
473{ 489{
474 nmk_config_pins(mop500_pins_common, 490 pinctrl_register_mappings(mop500_family_pinmap,
475 ARRAY_SIZE(mop500_pins_common)); 491 ARRAY_SIZE(mop500_family_pinmap));
476 492 pinctrl_register_mappings(mop500_pinmap,
477 ux500_pins_add(mop500_runtime_pins, ARRAY_SIZE(mop500_runtime_pins)); 493 ARRAY_SIZE(mop500_pinmap));
478 494 mop500_href_family_pinmaps_init();
479 nmk_config_pins(u8500_pins, ARRAY_SIZE(u8500_pins));
480
481 nmk_config_pins(snowball_pins, ARRAY_SIZE(snowball_pins));
482} 495}
483 496
484void __init hrefv60_pins_init(void) 497void __init snowball_pinmaps_init(void)
485{ 498{
486 nmk_config_pins(mop500_pins_common, 499 pinctrl_register_mappings(mop500_family_pinmap,
487 ARRAY_SIZE(mop500_pins_common)); 500 ARRAY_SIZE(mop500_family_pinmap));
488 501 pinctrl_register_mappings(snowball_pinmap,
489 ux500_pins_add(mop500_runtime_pins, ARRAY_SIZE(mop500_runtime_pins)); 502 ARRAY_SIZE(snowball_pinmap));
490 503 pinctrl_register_mappings(u8500_pinmap,
491 ux500_pins_add(mop500_runtime_pins_v60, 504 ARRAY_SIZE(u8500_pinmap));
492 ARRAY_SIZE(mop500_runtime_pins_v60)); 505}
493
494 nmk_config_pins(hrefv60_pins,
495 ARRAY_SIZE(hrefv60_pins));
496
497 switch (pinsfor) {
498 case PINS_FOR_U9500:
499 nmk_config_pins(u9500_pins, ARRAY_SIZE(u9500_pins));
500 break;
501 506
502 case PINS_FOR_DEFAULT: 507void __init hrefv60_pinmaps_init(void)
503 nmk_config_pins(u8500_pins, ARRAY_SIZE(u8500_pins)); 508{
504 default: 509 pinctrl_register_mappings(mop500_family_pinmap,
505 break; 510 ARRAY_SIZE(mop500_family_pinmap));
506 } 511 pinctrl_register_mappings(hrefv60_pinmap,
512 ARRAY_SIZE(hrefv60_pinmap));
513 mop500_href_family_pinmaps_init();
507} 514}
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index ca0d62599f70..1dc31652b97a 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -1,3 +1,4 @@
1
1/* 2/*
2 * Copyright (C) 2008-2009 ST-Ericsson 3 * Copyright (C) 2008-2009 ST-Ericsson
3 * 4 *
@@ -29,18 +30,17 @@
29#include <linux/smsc911x.h> 30#include <linux/smsc911x.h>
30#include <linux/gpio_keys.h> 31#include <linux/gpio_keys.h>
31#include <linux/delay.h> 32#include <linux/delay.h>
32
33#include <linux/of.h> 33#include <linux/of.h>
34#include <linux/of_platform.h> 34#include <linux/of_platform.h>
35
36#include <linux/leds.h> 35#include <linux/leds.h>
36#include <linux/pinctrl/consumer.h>
37
37#include <asm/mach-types.h> 38#include <asm/mach-types.h>
38#include <asm/mach/arch.h> 39#include <asm/mach/arch.h>
39#include <asm/hardware/gic.h> 40#include <asm/hardware/gic.h>
40 41
41#include <plat/i2c.h> 42#include <plat/i2c.h>
42#include <plat/ste_dma40.h> 43#include <plat/ste_dma40.h>
43#include <plat/pincfg.h>
44#include <plat/gpio-nomadik.h> 44#include <plat/gpio-nomadik.h>
45 45
46#include <mach/hardware.h> 46#include <mach/hardware.h>
@@ -48,7 +48,6 @@
48#include <mach/devices.h> 48#include <mach/devices.h>
49#include <mach/irqs.h> 49#include <mach/irqs.h>
50 50
51#include "pins-db8500.h"
52#include "ste-dma40-db8500.h" 51#include "ste-dma40-db8500.h"
53#include "devices-db8500.h" 52#include "devices-db8500.h"
54#include "board-mop500.h" 53#include "board-mop500.h"
@@ -521,14 +520,6 @@ static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
521}; 520};
522#endif 521#endif
523 522
524
525static pin_cfg_t mop500_pins_uart0[] = {
526 GPIO0_U0_CTSn | PIN_INPUT_PULLUP,
527 GPIO1_U0_RTSn | PIN_OUTPUT_HIGH,
528 GPIO2_U0_RXD | PIN_INPUT_PULLUP,
529 GPIO3_U0_TXD | PIN_OUTPUT_HIGH,
530};
531
532#define PRCC_K_SOFTRST_SET 0x18 523#define PRCC_K_SOFTRST_SET 0x18
533#define PRCC_K_SOFTRST_CLEAR 0x1C 524#define PRCC_K_SOFTRST_CLEAR 0x1C
534static void ux500_uart0_reset(void) 525static void ux500_uart0_reset(void)
@@ -549,24 +540,33 @@ static void ux500_uart0_reset(void)
549 udelay(1); 540 udelay(1);
550} 541}
551 542
543/* This needs to be referenced by callbacks */
544struct pinctrl *u0_p;
545struct pinctrl_state *u0_def;
546struct pinctrl_state *u0_sleep;
547
552static void ux500_uart0_init(void) 548static void ux500_uart0_init(void)
553{ 549{
554 int ret; 550 int ret;
555 551
556 ret = nmk_config_pins(mop500_pins_uart0, 552 if (IS_ERR(u0_p) || IS_ERR(u0_def))
557 ARRAY_SIZE(mop500_pins_uart0)); 553 return;
558 if (ret < 0) 554
559 pr_err("pl011: uart pins_enable failed\n"); 555 ret = pinctrl_select_state(u0_p, u0_def);
556 if (ret)
557 pr_err("could not set UART0 defstate\n");
560} 558}
561 559
562static void ux500_uart0_exit(void) 560static void ux500_uart0_exit(void)
563{ 561{
564 int ret; 562 int ret;
565 563
566 ret = nmk_config_pins_sleep(mop500_pins_uart0, 564 if (IS_ERR(u0_p) || IS_ERR(u0_sleep))
567 ARRAY_SIZE(mop500_pins_uart0)); 565 return;
568 if (ret < 0) 566
569 pr_err("pl011: uart pins_disable failed\n"); 567 ret = pinctrl_select_state(u0_p, u0_sleep);
568 if (ret)
569 pr_err("could not set UART0 idlestate\n");
570} 570}
571 571
572static struct amba_pl011_data uart0_plat = { 572static struct amba_pl011_data uart0_plat = {
@@ -598,7 +598,28 @@ static struct amba_pl011_data uart2_plat = {
598 598
599static void __init mop500_uart_init(struct device *parent) 599static void __init mop500_uart_init(struct device *parent)
600{ 600{
601 db8500_add_uart0(parent, &uart0_plat); 601 struct amba_device *uart0_device;
602
603 uart0_device = db8500_add_uart0(parent, &uart0_plat);
604 if (uart0_device) {
605 u0_p = pinctrl_get(&uart0_device->dev);
606 if (IS_ERR(u0_p))
607 dev_err(&uart0_device->dev,
608 "could not get UART0 pinctrl\n");
609 else {
610 u0_def = pinctrl_lookup_state(u0_p,
611 PINCTRL_STATE_DEFAULT);
612 if (IS_ERR(u0_def)) {
613 dev_err(&uart0_device->dev,
614 "could not get UART0 defstate\n");
615 }
616 u0_sleep = pinctrl_lookup_state(u0_p,
617 PINCTRL_STATE_SLEEP);
618 if (IS_ERR(u0_sleep))
619 dev_err(&uart0_device->dev,
620 "could not get UART0 idlestate\n");
621 }
622 }
602 db8500_add_uart1(parent, &uart1_plat); 623 db8500_add_uart1(parent, &uart1_plat);
603 db8500_add_uart2(parent, &uart2_plat); 624 db8500_add_uart2(parent, &uart2_plat);
604} 625}
@@ -618,10 +639,9 @@ static void __init mop500_init_machine(void)
618 639
619 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; 640 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
620 641
642 mop500_pinmaps_init();
621 parent = u8500_init_devices(); 643 parent = u8500_init_devices();
622 644
623 mop500_pins_init();
624
625 /* FIXME: parent of ab8500 should be prcmu */ 645 /* FIXME: parent of ab8500 should be prcmu */
626 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) 646 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
627 mop500_platform_devs[i]->dev.parent = parent; 647 mop500_platform_devs[i]->dev.parent = parent;
@@ -651,10 +671,9 @@ static void __init snowball_init_machine(void)
651 int i2c0_devs; 671 int i2c0_devs;
652 int i; 672 int i;
653 673
674 snowball_pinmaps_init();
654 parent = u8500_init_devices(); 675 parent = u8500_init_devices();
655 676
656 snowball_pins_init();
657
658 for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++) 677 for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
659 snowball_platform_devs[i]->dev.parent = parent; 678 snowball_platform_devs[i]->dev.parent = parent;
660 679
@@ -689,10 +708,9 @@ static void __init hrefv60_init_machine(void)
689 */ 708 */
690 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; 709 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
691 710
711 hrefv60_pinmaps_init();
692 parent = u8500_init_devices(); 712 parent = u8500_init_devices();
693 713
694 hrefv60_pins_init();
695
696 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) 714 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
697 mop500_platform_devs[i]->dev.parent = parent; 715 mop500_platform_devs[i]->dev.parent = parent;
698 716
@@ -781,6 +799,14 @@ static void __init u8500_init_machine(void)
781 int i2c0_devs; 799 int i2c0_devs;
782 int i; 800 int i;
783 801
802 /* Pinmaps must be in place before devices register */
803 if (of_machine_is_compatible("st-ericsson,mop500"))
804 mop500_pinmaps_init();
805 else if (of_machine_is_compatible("calaosystems,snowball-a9500"))
806 snowball_pinmaps_init();
807 else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
808 hrefv60_pinmaps_init();
809
784 parent = u8500_init_devices(); 810 parent = u8500_init_devices();
785 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); 811 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
786 812
@@ -794,14 +820,12 @@ static void __init u8500_init_machine(void)
794 820
795 if (of_machine_is_compatible("st-ericsson,mop500")) { 821 if (of_machine_is_compatible("st-ericsson,mop500")) {
796 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; 822 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
797 mop500_pins_init();
798 823
799 platform_add_devices(mop500_platform_devs, 824 platform_add_devices(mop500_platform_devs,
800 ARRAY_SIZE(mop500_platform_devs)); 825 ARRAY_SIZE(mop500_platform_devs));
801 826
802 mop500_sdi_init(parent); 827 mop500_sdi_init(parent);
803 } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { 828 } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
804 snowball_pins_init();
805 platform_add_devices(snowball_platform_devs, 829 platform_add_devices(snowball_platform_devs,
806 ARRAY_SIZE(snowball_platform_devs)); 830 ARRAY_SIZE(snowball_platform_devs));
807 831
@@ -814,7 +838,6 @@ static void __init u8500_init_machine(void)
814 */ 838 */
815 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; 839 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
816 i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; 840 i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
817 hrefv60_pins_init();
818 platform_add_devices(mop500_platform_devs, 841 platform_add_devices(mop500_platform_devs,
819 ARRAY_SIZE(mop500_platform_devs)); 842 ARRAY_SIZE(mop500_platform_devs));
820 843
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 91dc63fe101b..bc44c07c71a9 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -85,9 +85,9 @@ extern void hrefv60_sdi_init(struct device *parent);
85extern void mop500_sdi_tc35892_init(struct device *parent); 85extern void mop500_sdi_tc35892_init(struct device *parent);
86void __init mop500_u8500uib_init(void); 86void __init mop500_u8500uib_init(void);
87void __init mop500_stuib_init(void); 87void __init mop500_stuib_init(void);
88void __init mop500_pins_init(void); 88void __init mop500_pinmaps_init(void);
89void __init hrefv60_pins_init(void); 89void __init snowball_pinmaps_init(void);
90void __init snowball_pins_init(void); 90void __init hrefv60_pinmaps_init(void);
91 91
92void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, 92void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
93 unsigned n); 93 unsigned n);
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 9bd8163896cf..d992d2b44907 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -141,6 +141,7 @@ static void __init db8500_add_gpios(struct device *parent)
141 141
142 dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base), 142 dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
143 IRQ_DB8500_GPIO0, &pdata); 143 IRQ_DB8500_GPIO0, &pdata);
144 dbx500_add_pinctrl(parent, "pinctrl-db8500");
144} 145}
145 146
146static int usb_db8500_rx_dma_cfg[] = { 147static int usb_db8500_rx_dma_cfg[] = {
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index 39c74ec82add..939f7503e8db 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -93,4 +93,16 @@ struct nmk_gpio_platform_data;
93void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num, 93void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
94 int irq, struct nmk_gpio_platform_data *pdata); 94 int irq, struct nmk_gpio_platform_data *pdata);
95 95
96static inline void
97dbx500_add_pinctrl(struct device *parent, const char *name)
98{
99 struct platform_device_info pdevinfo = {
100 .parent = parent,
101 .name = name,
102 .id = -1,
103 };
104
105 platform_device_register_full(&pdevinfo);
106}
107
96#endif 108#endif
diff --git a/arch/arm/mach-ux500/pins.c b/arch/arm/mach-ux500/pins.c
deleted file mode 100644
index 38c1d47b29a1..000000000000
--- a/arch/arm/mach-ux500/pins.c
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL), version 2
6 */
7
8#include <linux/kernel.h>
9#include <linux/string.h>
10#include <linux/device.h>
11#include <linux/mutex.h>
12#include <linux/spinlock.h>
13#include <linux/err.h>
14#include <plat/pincfg.h>
15
16#include "pins.h"
17
18static LIST_HEAD(pin_lookups);
19static DEFINE_MUTEX(pin_lookups_mutex);
20static DEFINE_SPINLOCK(pins_lock);
21
22void __init ux500_pins_add(struct ux500_pin_lookup *pl, size_t num)
23{
24 mutex_lock(&pin_lookups_mutex);
25
26 while (num--) {
27 list_add_tail(&pl->node, &pin_lookups);
28 pl++;
29 }
30
31 mutex_unlock(&pin_lookups_mutex);
32}
33
34struct ux500_pins *ux500_pins_get(const char *name)
35{
36 struct ux500_pins *pins = NULL;
37 struct ux500_pin_lookup *pl;
38
39 mutex_lock(&pin_lookups_mutex);
40
41 list_for_each_entry(pl, &pin_lookups, node) {
42 if (!strcmp(pl->name, name)) {
43 pins = pl->pins;
44 goto out;
45 }
46 }
47
48out:
49 mutex_unlock(&pin_lookups_mutex);
50 return pins;
51}
52
53int ux500_pins_enable(struct ux500_pins *pins)
54{
55 unsigned long flags;
56 int ret = 0;
57
58 spin_lock_irqsave(&pins_lock, flags);
59
60 if (pins->usage++ == 0)
61 ret = nmk_config_pins(pins->cfg, pins->num);
62
63 spin_unlock_irqrestore(&pins_lock, flags);
64 return ret;
65}
66
67int ux500_pins_disable(struct ux500_pins *pins)
68{
69 unsigned long flags;
70 int ret = 0;
71
72 spin_lock_irqsave(&pins_lock, flags);
73
74 if (WARN_ON(pins->usage == 0))
75 goto out;
76
77 if (--pins->usage == 0)
78 ret = nmk_config_pins_sleep(pins->cfg, pins->num);
79
80out:
81 spin_unlock_irqrestore(&pins_lock, flags);
82 return ret;
83}
84
85void ux500_pins_put(struct ux500_pins *pins)
86{
87 WARN_ON(!pins);
88}
diff --git a/arch/arm/mach-ux500/pins.h b/arch/arm/mach-ux500/pins.h
deleted file mode 100644
index 0d36af2e7d92..000000000000
--- a/arch/arm/mach-ux500/pins.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL), version 2
6 */
7
8#ifndef __MACH_UX500_PINS_H
9#define __MACH_UX500_PINS_H
10
11#include <linux/list.h>
12#include <plat/pincfg.h>
13
14#define PIN_LOOKUP(_name, _pins) \
15{ \
16 .name = _name, \
17 .pins = _pins, \
18}
19
20#define UX500_PINS(name, pins...) \
21struct ux500_pins name = { \
22 .cfg = (pin_cfg_t[]) {pins}, \
23 .num = ARRAY_SIZE(((pin_cfg_t[]) {pins})), \
24}
25
26struct ux500_pins {
27 int usage;
28 int num;
29 pin_cfg_t *cfg;
30};
31
32struct ux500_pin_lookup {
33 struct list_head node;
34 const char *name;
35 struct ux500_pins *pins;
36};
37
38void __init ux500_pins_add(struct ux500_pin_lookup *pl, size_t num);
39void __init ux500_offchip_gpio_init(struct ux500_pins *pins);
40struct ux500_pins *ux500_pins_get(const char *name);
41int ux500_pins_enable(struct ux500_pins *pins);
42int ux500_pins_disable(struct ux500_pins *pins);
43void ux500_pins_put(struct ux500_pins *pins);
44int pins_for_u9500(void);
45
46#endif
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
index c015133a7ad3..9c949c7c98a7 100644
--- a/arch/arm/plat-nomadik/include/plat/pincfg.h
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -124,6 +124,19 @@ typedef unsigned long pin_cfg_t;
124#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) 124#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
125#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) 125#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
126 126
127#define PIN_GPIOMODE_SHIFT 26
128#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
129#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
130#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
131#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
132
133#define PIN_SLEEPMODE_SHIFT 27
134#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
135#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
136#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
137#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
138
139
127/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ 140/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
128#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) 141#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
129#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) 142#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 007f54bd0081..a4193ab1b266 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -36,7 +36,6 @@ obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o
36obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o 36obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o
37obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o 37obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
38obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o 38obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o
39obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o
40obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o 39obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o
41obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o 40obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o
42obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o 41obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index a54a93112cba..cc01c758bbfc 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -64,6 +64,16 @@ config PINCTRL_IMX28
64 select PINCONF 64 select PINCONF
65 select PINCTRL_MXS 65 select PINCTRL_MXS
66 66
67config PINCTRL_NOMADIK
68 bool "Nomadik pin controller driver"
69 depends on ARCH_U8500
70 select PINMUX
71 select PINCONF
72
73config PINCTRL_DB8500
74 bool "DB8500 pin controller driver"
75 depends on PINCTRL_NOMADIK && ARCH_U8500
76
67config PINCTRL_PXA168 77config PINCTRL_PXA168
68 bool "PXA168 pin controller driver" 78 bool "PXA168 pin controller driver"
69 depends on ARCH_MMP 79 depends on ARCH_MMP
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index c9b0be56ff49..8e764ade929a 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,6 +16,8 @@ obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
16obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o 16obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
17obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o 17obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
18obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o 18obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
19obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
20obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
19obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o 21obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
20obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o 22obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
21obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o 23obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8500.c b/drivers/pinctrl/pinctrl-nomadik-db8500.c
new file mode 100644
index 000000000000..8b2022276f71
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik-db8500.c
@@ -0,0 +1,857 @@
1#include <linux/kernel.h>
2#include <linux/pinctrl/pinctrl.h>
3#include "pinctrl-nomadik.h"
4
5/* All the pins that can be used for GPIO and some other functions */
6#define _GPIO(offset) (offset)
7
8#define DB8500_PIN_AJ5 _GPIO(0)
9#define DB8500_PIN_AJ3 _GPIO(1)
10#define DB8500_PIN_AH4 _GPIO(2)
11#define DB8500_PIN_AH3 _GPIO(3)
12#define DB8500_PIN_AH6 _GPIO(4)
13#define DB8500_PIN_AG6 _GPIO(5)
14#define DB8500_PIN_AF6 _GPIO(6)
15#define DB8500_PIN_AG5 _GPIO(7)
16#define DB8500_PIN_AD5 _GPIO(8)
17#define DB8500_PIN_AE4 _GPIO(9)
18#define DB8500_PIN_AF5 _GPIO(10)
19#define DB8500_PIN_AG4 _GPIO(11)
20#define DB8500_PIN_AC4 _GPIO(12)
21#define DB8500_PIN_AF3 _GPIO(13)
22#define DB8500_PIN_AE3 _GPIO(14)
23#define DB8500_PIN_AC3 _GPIO(15)
24#define DB8500_PIN_AD3 _GPIO(16)
25#define DB8500_PIN_AD4 _GPIO(17)
26#define DB8500_PIN_AC2 _GPIO(18)
27#define DB8500_PIN_AC1 _GPIO(19)
28#define DB8500_PIN_AB4 _GPIO(20)
29#define DB8500_PIN_AB3 _GPIO(21)
30#define DB8500_PIN_AA3 _GPIO(22)
31#define DB8500_PIN_AA4 _GPIO(23)
32#define DB8500_PIN_AB2 _GPIO(24)
33#define DB8500_PIN_Y4 _GPIO(25)
34#define DB8500_PIN_Y2 _GPIO(26)
35#define DB8500_PIN_AA2 _GPIO(27)
36#define DB8500_PIN_AA1 _GPIO(28)
37#define DB8500_PIN_W2 _GPIO(29)
38#define DB8500_PIN_W3 _GPIO(30)
39#define DB8500_PIN_V3 _GPIO(31)
40#define DB8500_PIN_V2 _GPIO(32)
41#define DB8500_PIN_AF2 _GPIO(33)
42#define DB8500_PIN_AE1 _GPIO(34)
43#define DB8500_PIN_AE2 _GPIO(35)
44#define DB8500_PIN_AG2 _GPIO(36)
45/* Hole */
46#define DB8500_PIN_F3 _GPIO(64)
47#define DB8500_PIN_F1 _GPIO(65)
48#define DB8500_PIN_G3 _GPIO(66)
49#define DB8500_PIN_G2 _GPIO(67)
50#define DB8500_PIN_E1 _GPIO(68)
51#define DB8500_PIN_E2 _GPIO(69)
52#define DB8500_PIN_G5 _GPIO(70)
53#define DB8500_PIN_G4 _GPIO(71)
54#define DB8500_PIN_H4 _GPIO(72)
55#define DB8500_PIN_H3 _GPIO(73)
56#define DB8500_PIN_J3 _GPIO(74)
57#define DB8500_PIN_H2 _GPIO(75)
58#define DB8500_PIN_J2 _GPIO(76)
59#define DB8500_PIN_H1 _GPIO(77)
60#define DB8500_PIN_F4 _GPIO(78)
61#define DB8500_PIN_E3 _GPIO(79)
62#define DB8500_PIN_E4 _GPIO(80)
63#define DB8500_PIN_D2 _GPIO(81)
64#define DB8500_PIN_C1 _GPIO(82)
65#define DB8500_PIN_D3 _GPIO(83)
66#define DB8500_PIN_C2 _GPIO(84)
67#define DB8500_PIN_D5 _GPIO(85)
68#define DB8500_PIN_C6 _GPIO(86)
69#define DB8500_PIN_B3 _GPIO(87)
70#define DB8500_PIN_C4 _GPIO(88)
71#define DB8500_PIN_E6 _GPIO(89)
72#define DB8500_PIN_A3 _GPIO(90)
73#define DB8500_PIN_B6 _GPIO(91)
74#define DB8500_PIN_D6 _GPIO(92)
75#define DB8500_PIN_B7 _GPIO(93)
76#define DB8500_PIN_D7 _GPIO(94)
77#define DB8500_PIN_E8 _GPIO(95)
78#define DB8500_PIN_D8 _GPIO(96)
79#define DB8500_PIN_D9 _GPIO(97)
80/* Hole */
81#define DB8500_PIN_A5 _GPIO(128)
82#define DB8500_PIN_B4 _GPIO(129)
83#define DB8500_PIN_C8 _GPIO(130)
84#define DB8500_PIN_A12 _GPIO(131)
85#define DB8500_PIN_C10 _GPIO(132)
86#define DB8500_PIN_B10 _GPIO(133)
87#define DB8500_PIN_B9 _GPIO(134)
88#define DB8500_PIN_A9 _GPIO(135)
89#define DB8500_PIN_C7 _GPIO(136)
90#define DB8500_PIN_A7 _GPIO(137)
91#define DB8500_PIN_C5 _GPIO(138)
92#define DB8500_PIN_C9 _GPIO(139)
93#define DB8500_PIN_B11 _GPIO(140)
94#define DB8500_PIN_C12 _GPIO(141)
95#define DB8500_PIN_C11 _GPIO(142)
96#define DB8500_PIN_D12 _GPIO(143)
97#define DB8500_PIN_B13 _GPIO(144)
98#define DB8500_PIN_C13 _GPIO(145)
99#define DB8500_PIN_D13 _GPIO(146)
100#define DB8500_PIN_C15 _GPIO(147)
101#define DB8500_PIN_B16 _GPIO(148)
102#define DB8500_PIN_B14 _GPIO(149)
103#define DB8500_PIN_C14 _GPIO(150)
104#define DB8500_PIN_D17 _GPIO(151)
105#define DB8500_PIN_D16 _GPIO(152)
106#define DB8500_PIN_B17 _GPIO(153)
107#define DB8500_PIN_C16 _GPIO(154)
108#define DB8500_PIN_C19 _GPIO(155)
109#define DB8500_PIN_C17 _GPIO(156)
110#define DB8500_PIN_A18 _GPIO(157)
111#define DB8500_PIN_C18 _GPIO(158)
112#define DB8500_PIN_B19 _GPIO(159)
113#define DB8500_PIN_B20 _GPIO(160)
114#define DB8500_PIN_D21 _GPIO(161)
115#define DB8500_PIN_D20 _GPIO(162)
116#define DB8500_PIN_C20 _GPIO(163)
117#define DB8500_PIN_B21 _GPIO(164)
118#define DB8500_PIN_C21 _GPIO(165)
119#define DB8500_PIN_A22 _GPIO(166)
120#define DB8500_PIN_B24 _GPIO(167)
121#define DB8500_PIN_C22 _GPIO(168)
122#define DB8500_PIN_D22 _GPIO(169)
123#define DB8500_PIN_C23 _GPIO(170)
124#define DB8500_PIN_D23 _GPIO(171)
125/* Hole */
126#define DB8500_PIN_AJ27 _GPIO(192)
127#define DB8500_PIN_AH27 _GPIO(193)
128#define DB8500_PIN_AF27 _GPIO(194)
129#define DB8500_PIN_AG28 _GPIO(195)
130#define DB8500_PIN_AG26 _GPIO(196)
131#define DB8500_PIN_AH24 _GPIO(197)
132#define DB8500_PIN_AG25 _GPIO(198)
133#define DB8500_PIN_AH23 _GPIO(199)
134#define DB8500_PIN_AH26 _GPIO(200)
135#define DB8500_PIN_AF24 _GPIO(201)
136#define DB8500_PIN_AF25 _GPIO(202)
137#define DB8500_PIN_AE23 _GPIO(203)
138#define DB8500_PIN_AF23 _GPIO(204)
139#define DB8500_PIN_AG23 _GPIO(205)
140#define DB8500_PIN_AG24 _GPIO(206)
141#define DB8500_PIN_AJ23 _GPIO(207)
142#define DB8500_PIN_AH16 _GPIO(208)
143#define DB8500_PIN_AG15 _GPIO(209)
144#define DB8500_PIN_AJ15 _GPIO(210)
145#define DB8500_PIN_AG14 _GPIO(211)
146#define DB8500_PIN_AF13 _GPIO(212)
147#define DB8500_PIN_AG13 _GPIO(213)
148#define DB8500_PIN_AH15 _GPIO(214)
149#define DB8500_PIN_AH13 _GPIO(215)
150#define DB8500_PIN_AG12 _GPIO(216)
151#define DB8500_PIN_AH12 _GPIO(217)
152#define DB8500_PIN_AH11 _GPIO(218)
153#define DB8500_PIN_AG10 _GPIO(219)
154#define DB8500_PIN_AH10 _GPIO(220)
155#define DB8500_PIN_AJ11 _GPIO(221)
156#define DB8500_PIN_AJ9 _GPIO(222)
157#define DB8500_PIN_AH9 _GPIO(223)
158#define DB8500_PIN_AG9 _GPIO(224)
159#define DB8500_PIN_AG8 _GPIO(225)
160#define DB8500_PIN_AF8 _GPIO(226)
161#define DB8500_PIN_AH7 _GPIO(227)
162#define DB8500_PIN_AJ6 _GPIO(228)
163#define DB8500_PIN_AG7 _GPIO(229)
164#define DB8500_PIN_AF7 _GPIO(230)
165/* Hole */
166#define DB8500_PIN_AF28 _GPIO(256)
167#define DB8500_PIN_AE29 _GPIO(257)
168#define DB8500_PIN_AD29 _GPIO(258)
169#define DB8500_PIN_AC29 _GPIO(259)
170#define DB8500_PIN_AD28 _GPIO(260)
171#define DB8500_PIN_AD26 _GPIO(261)
172#define DB8500_PIN_AE26 _GPIO(262)
173#define DB8500_PIN_AG29 _GPIO(263)
174#define DB8500_PIN_AE27 _GPIO(264)
175#define DB8500_PIN_AD27 _GPIO(265)
176#define DB8500_PIN_AC28 _GPIO(266)
177#define DB8500_PIN_AC27 _GPIO(267)
178
179/*
180 * The names of the pins are denoted by GPIO number and ball name, even
181 * though they can be used for other things than GPIO, this is the first
182 * column in the table of the data sheet and often used on schematics and
183 * such.
184 */
185static const struct pinctrl_pin_desc nmk_db8500_pins[] = {
186 PINCTRL_PIN(DB8500_PIN_AJ5, "GPIO0_AJ5"),
187 PINCTRL_PIN(DB8500_PIN_AJ3, "GPIO1_AJ3"),
188 PINCTRL_PIN(DB8500_PIN_AH4, "GPIO2_AH4"),
189 PINCTRL_PIN(DB8500_PIN_AH3, "GPIO3_AH3"),
190 PINCTRL_PIN(DB8500_PIN_AH6, "GPIO4_AH6"),
191 PINCTRL_PIN(DB8500_PIN_AG6, "GPIO5_AG6"),
192 PINCTRL_PIN(DB8500_PIN_AF6, "GPIO6_AF6"),
193 PINCTRL_PIN(DB8500_PIN_AG5, "GPIO7_AG5"),
194 PINCTRL_PIN(DB8500_PIN_AD5, "GPIO8_AD5"),
195 PINCTRL_PIN(DB8500_PIN_AE4, "GPIO9_AE4"),
196 PINCTRL_PIN(DB8500_PIN_AF5, "GPIO10_AF5"),
197 PINCTRL_PIN(DB8500_PIN_AG4, "GPIO11_AG4"),
198 PINCTRL_PIN(DB8500_PIN_AC4, "GPIO12_AC4"),
199 PINCTRL_PIN(DB8500_PIN_AF3, "GPIO13_AF3"),
200 PINCTRL_PIN(DB8500_PIN_AE3, "GPIO14_AE3"),
201 PINCTRL_PIN(DB8500_PIN_AC3, "GPIO15_AC3"),
202 PINCTRL_PIN(DB8500_PIN_AD3, "GPIO16_AD3"),
203 PINCTRL_PIN(DB8500_PIN_AD4, "GPIO17_AD4"),
204 PINCTRL_PIN(DB8500_PIN_AC2, "GPIO18_AC2"),
205 PINCTRL_PIN(DB8500_PIN_AC1, "GPIO19_AC1"),
206 PINCTRL_PIN(DB8500_PIN_AB4, "GPIO20_AB4"),
207 PINCTRL_PIN(DB8500_PIN_AB3, "GPIO21_AB3"),
208 PINCTRL_PIN(DB8500_PIN_AA3, "GPIO22_AA3"),
209 PINCTRL_PIN(DB8500_PIN_AA4, "GPIO23_AA4"),
210 PINCTRL_PIN(DB8500_PIN_AB2, "GPIO24_AB2"),
211 PINCTRL_PIN(DB8500_PIN_Y4, "GPIO25_Y4"),
212 PINCTRL_PIN(DB8500_PIN_Y2, "GPIO26_Y2"),
213 PINCTRL_PIN(DB8500_PIN_AA2, "GPIO27_AA2"),
214 PINCTRL_PIN(DB8500_PIN_AA1, "GPIO28_AA1"),
215 PINCTRL_PIN(DB8500_PIN_W2, "GPIO29_W2"),
216 PINCTRL_PIN(DB8500_PIN_W3, "GPIO30_W3"),
217 PINCTRL_PIN(DB8500_PIN_V3, "GPIO31_V3"),
218 PINCTRL_PIN(DB8500_PIN_V2, "GPIO32_V2"),
219 PINCTRL_PIN(DB8500_PIN_AF2, "GPIO33_AF2"),
220 PINCTRL_PIN(DB8500_PIN_AE1, "GPIO34_AE1"),
221 PINCTRL_PIN(DB8500_PIN_AE2, "GPIO35_AE2"),
222 PINCTRL_PIN(DB8500_PIN_AG2, "GPIO36_AG2"),
223 /* Hole */
224 PINCTRL_PIN(DB8500_PIN_F3, "GPIO64_F3"),
225 PINCTRL_PIN(DB8500_PIN_F1, "GPIO65_F1"),
226 PINCTRL_PIN(DB8500_PIN_G3, "GPIO66_G3"),
227 PINCTRL_PIN(DB8500_PIN_G2, "GPIO67_G2"),
228 PINCTRL_PIN(DB8500_PIN_E1, "GPIO68_E1"),
229 PINCTRL_PIN(DB8500_PIN_E2, "GPIO69_E2"),
230 PINCTRL_PIN(DB8500_PIN_G5, "GPIO70_G5"),
231 PINCTRL_PIN(DB8500_PIN_G4, "GPIO71_G4"),
232 PINCTRL_PIN(DB8500_PIN_H4, "GPIO72_H4"),
233 PINCTRL_PIN(DB8500_PIN_H3, "GPIO73_H3"),
234 PINCTRL_PIN(DB8500_PIN_J3, "GPIO74_J3"),
235 PINCTRL_PIN(DB8500_PIN_H2, "GPIO75_H2"),
236 PINCTRL_PIN(DB8500_PIN_J2, "GPIO76_J2"),
237 PINCTRL_PIN(DB8500_PIN_H1, "GPIO77_H1"),
238 PINCTRL_PIN(DB8500_PIN_F4, "GPIO78_F4"),
239 PINCTRL_PIN(DB8500_PIN_E3, "GPIO79_E3"),
240 PINCTRL_PIN(DB8500_PIN_E4, "GPIO80_E4"),
241 PINCTRL_PIN(DB8500_PIN_D2, "GPIO81_D2"),
242 PINCTRL_PIN(DB8500_PIN_C1, "GPIO82_C1"),
243 PINCTRL_PIN(DB8500_PIN_D3, "GPIO83_D3"),
244 PINCTRL_PIN(DB8500_PIN_C2, "GPIO84_C2"),
245 PINCTRL_PIN(DB8500_PIN_D5, "GPIO85_D5"),
246 PINCTRL_PIN(DB8500_PIN_C6, "GPIO86_C6"),
247 PINCTRL_PIN(DB8500_PIN_B3, "GPIO87_B3"),
248 PINCTRL_PIN(DB8500_PIN_C4, "GPIO88_C4"),
249 PINCTRL_PIN(DB8500_PIN_E6, "GPIO89_E6"),
250 PINCTRL_PIN(DB8500_PIN_A3, "GPIO90_A3"),
251 PINCTRL_PIN(DB8500_PIN_B6, "GPIO91_B6"),
252 PINCTRL_PIN(DB8500_PIN_D6, "GPIO92_D6"),
253 PINCTRL_PIN(DB8500_PIN_B7, "GPIO93_B7"),
254 PINCTRL_PIN(DB8500_PIN_D7, "GPIO94_D7"),
255 PINCTRL_PIN(DB8500_PIN_E8, "GPIO95_E8"),
256 PINCTRL_PIN(DB8500_PIN_D8, "GPIO96_D8"),
257 PINCTRL_PIN(DB8500_PIN_D9, "GPIO97_D9"),
258 /* Hole */
259 PINCTRL_PIN(DB8500_PIN_A5, "GPIO128_A5"),
260 PINCTRL_PIN(DB8500_PIN_B4, "GPIO129_B4"),
261 PINCTRL_PIN(DB8500_PIN_C8, "GPIO130_C8"),
262 PINCTRL_PIN(DB8500_PIN_A12, "GPIO131_A12"),
263 PINCTRL_PIN(DB8500_PIN_C10, "GPIO132_C10"),
264 PINCTRL_PIN(DB8500_PIN_B10, "GPIO133_B10"),
265 PINCTRL_PIN(DB8500_PIN_B9, "GPIO134_B9"),
266 PINCTRL_PIN(DB8500_PIN_A9, "GPIO135_A9"),
267 PINCTRL_PIN(DB8500_PIN_C7, "GPIO136_C7"),
268 PINCTRL_PIN(DB8500_PIN_A7, "GPIO137_A7"),
269 PINCTRL_PIN(DB8500_PIN_C5, "GPIO138_C5"),
270 PINCTRL_PIN(DB8500_PIN_C9, "GPIO139_C9"),
271 PINCTRL_PIN(DB8500_PIN_B11, "GPIO140_B11"),
272 PINCTRL_PIN(DB8500_PIN_C12, "GPIO141_C12"),
273 PINCTRL_PIN(DB8500_PIN_C11, "GPIO142_C11"),
274 PINCTRL_PIN(DB8500_PIN_D12, "GPIO143_D12"),
275 PINCTRL_PIN(DB8500_PIN_B13, "GPIO144_B13"),
276 PINCTRL_PIN(DB8500_PIN_C13, "GPIO145_C13"),
277 PINCTRL_PIN(DB8500_PIN_D13, "GPIO146_D13"),
278 PINCTRL_PIN(DB8500_PIN_C15, "GPIO147_C15"),
279 PINCTRL_PIN(DB8500_PIN_B16, "GPIO148_B16"),
280 PINCTRL_PIN(DB8500_PIN_B14, "GPIO149_B14"),
281 PINCTRL_PIN(DB8500_PIN_C14, "GPIO150_C14"),
282 PINCTRL_PIN(DB8500_PIN_D17, "GPIO151_D17"),
283 PINCTRL_PIN(DB8500_PIN_D16, "GPIO152_D16"),
284 PINCTRL_PIN(DB8500_PIN_B17, "GPIO153_B17"),
285 PINCTRL_PIN(DB8500_PIN_C16, "GPIO154_C16"),
286 PINCTRL_PIN(DB8500_PIN_C19, "GPIO155_C19"),
287 PINCTRL_PIN(DB8500_PIN_C17, "GPIO156_C17"),
288 PINCTRL_PIN(DB8500_PIN_A18, "GPIO157_A18"),
289 PINCTRL_PIN(DB8500_PIN_C18, "GPIO158_C18"),
290 PINCTRL_PIN(DB8500_PIN_B19, "GPIO159_B19"),
291 PINCTRL_PIN(DB8500_PIN_B20, "GPIO160_B20"),
292 PINCTRL_PIN(DB8500_PIN_D21, "GPIO161_D21"),
293 PINCTRL_PIN(DB8500_PIN_D20, "GPIO162_D20"),
294 PINCTRL_PIN(DB8500_PIN_C20, "GPIO163_C20"),
295 PINCTRL_PIN(DB8500_PIN_B21, "GPIO164_B21"),
296 PINCTRL_PIN(DB8500_PIN_C21, "GPIO165_C21"),
297 PINCTRL_PIN(DB8500_PIN_A22, "GPIO166_A22"),
298 PINCTRL_PIN(DB8500_PIN_B24, "GPIO167_B24"),
299 PINCTRL_PIN(DB8500_PIN_C22, "GPIO168_C22"),
300 PINCTRL_PIN(DB8500_PIN_D22, "GPIO169_D22"),
301 PINCTRL_PIN(DB8500_PIN_C23, "GPIO170_C23"),
302 PINCTRL_PIN(DB8500_PIN_D23, "GPIO171_D23"),
303 /* Hole */
304 PINCTRL_PIN(DB8500_PIN_AJ27, "GPIO192_AJ27"),
305 PINCTRL_PIN(DB8500_PIN_AH27, "GPIO193_AH27"),
306 PINCTRL_PIN(DB8500_PIN_AF27, "GPIO194_AF27"),
307 PINCTRL_PIN(DB8500_PIN_AG28, "GPIO195_AG28"),
308 PINCTRL_PIN(DB8500_PIN_AG26, "GPIO196_AG26"),
309 PINCTRL_PIN(DB8500_PIN_AH24, "GPIO197_AH24"),
310 PINCTRL_PIN(DB8500_PIN_AG25, "GPIO198_AG25"),
311 PINCTRL_PIN(DB8500_PIN_AH23, "GPIO199_AH23"),
312 PINCTRL_PIN(DB8500_PIN_AH26, "GPIO200_AH26"),
313 PINCTRL_PIN(DB8500_PIN_AF24, "GPIO201_AF24"),
314 PINCTRL_PIN(DB8500_PIN_AF25, "GPIO202_AF25"),
315 PINCTRL_PIN(DB8500_PIN_AE23, "GPIO203_AE23"),
316 PINCTRL_PIN(DB8500_PIN_AF23, "GPIO204_AF23"),
317 PINCTRL_PIN(DB8500_PIN_AG23, "GPIO205_AG23"),
318 PINCTRL_PIN(DB8500_PIN_AG24, "GPIO206_AG24"),
319 PINCTRL_PIN(DB8500_PIN_AJ23, "GPIO207_AJ23"),
320 PINCTRL_PIN(DB8500_PIN_AH16, "GPIO208_AH16"),
321 PINCTRL_PIN(DB8500_PIN_AG15, "GPIO209_AG15"),
322 PINCTRL_PIN(DB8500_PIN_AJ15, "GPIO210_AJ15"),
323 PINCTRL_PIN(DB8500_PIN_AG14, "GPIO211_AG14"),
324 PINCTRL_PIN(DB8500_PIN_AF13, "GPIO212_AF13"),
325 PINCTRL_PIN(DB8500_PIN_AG13, "GPIO213_AG13"),
326 PINCTRL_PIN(DB8500_PIN_AH15, "GPIO214_AH15"),
327 PINCTRL_PIN(DB8500_PIN_AH13, "GPIO215_AH13"),
328 PINCTRL_PIN(DB8500_PIN_AG12, "GPIO216_AG12"),
329 PINCTRL_PIN(DB8500_PIN_AH12, "GPIO217_AH12"),
330 PINCTRL_PIN(DB8500_PIN_AH11, "GPIO218_AH11"),
331 PINCTRL_PIN(DB8500_PIN_AG10, "GPIO219_AG10"),
332 PINCTRL_PIN(DB8500_PIN_AH10, "GPIO220_AH10"),
333 PINCTRL_PIN(DB8500_PIN_AJ11, "GPIO221_AJ11"),
334 PINCTRL_PIN(DB8500_PIN_AJ9, "GPIO222_AJ9"),
335 PINCTRL_PIN(DB8500_PIN_AH9, "GPIO223_AH9"),
336 PINCTRL_PIN(DB8500_PIN_AG9, "GPIO224_AG9"),
337 PINCTRL_PIN(DB8500_PIN_AG8, "GPIO225_AG8"),
338 PINCTRL_PIN(DB8500_PIN_AF8, "GPIO226_AF8"),
339 PINCTRL_PIN(DB8500_PIN_AH7, "GPIO227_AH7"),
340 PINCTRL_PIN(DB8500_PIN_AJ6, "GPIO228_AJ6"),
341 PINCTRL_PIN(DB8500_PIN_AG7, "GPIO229_AG7"),
342 PINCTRL_PIN(DB8500_PIN_AF7, "GPIO230_AF7"),
343 /* Hole */
344 PINCTRL_PIN(DB8500_PIN_AF28, "GPIO256_AF28"),
345 PINCTRL_PIN(DB8500_PIN_AE29, "GPIO257_AE29"),
346 PINCTRL_PIN(DB8500_PIN_AD29, "GPIO258_AD29"),
347 PINCTRL_PIN(DB8500_PIN_AC29, "GPIO259_AC29"),
348 PINCTRL_PIN(DB8500_PIN_AD28, "GPIO260_AD28"),
349 PINCTRL_PIN(DB8500_PIN_AD26, "GPIO261_AD26"),
350 PINCTRL_PIN(DB8500_PIN_AE26, "GPIO262_AE26"),
351 PINCTRL_PIN(DB8500_PIN_AG29, "GPIO263_AG29"),
352 PINCTRL_PIN(DB8500_PIN_AE27, "GPIO264_AE27"),
353 PINCTRL_PIN(DB8500_PIN_AD27, "GPIO265_AD27"),
354 PINCTRL_PIN(DB8500_PIN_AC28, "GPIO266_AC28"),
355 PINCTRL_PIN(DB8500_PIN_AC27, "GPIO267_AC27"),
356};
357
358#define DB8500_GPIO_RANGE(a, b, c) { .name = "DB8500", .id = a, .base = b, \
359 .pin_base = b, .npins = c }
360
361/*
362 * This matches the 32-pin gpio chips registered by the GPIO portion. This
363 * cannot be const since we assign the struct gpio_chip * pointer at runtime.
364 */
365static struct pinctrl_gpio_range nmk_db8500_ranges[] = {
366 DB8500_GPIO_RANGE(0, 0, 32),
367 DB8500_GPIO_RANGE(1, 32, 5),
368 DB8500_GPIO_RANGE(2, 64, 32),
369 DB8500_GPIO_RANGE(3, 96, 2),
370 DB8500_GPIO_RANGE(4, 128, 32),
371 DB8500_GPIO_RANGE(5, 160, 12),
372 DB8500_GPIO_RANGE(6, 192, 32),
373 DB8500_GPIO_RANGE(7, 224, 7),
374 DB8500_GPIO_RANGE(8, 256, 12),
375};
376
377/*
378 * Read the pin group names like this:
379 * u0_a_1 = first groups of pins for uart0 on alt function a
380 * i2c2_b_2 = second group of pins for i2c2 on alt function b
381 *
382 * The groups are arranged as sets per altfunction column, so we can
383 * mux in one group at a time by selecting the same altfunction for them
384 * all. When functions require pins on different altfunctions, you need
385 * to combine several groups.
386 */
387
388/* Altfunction A column */
389static const unsigned u0_a_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3,
390 DB8500_PIN_AH4, DB8500_PIN_AH3 };
391static const unsigned u1rxtx_a_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 };
392static const unsigned u1ctsrts_a_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 };
393/* Image processor I2C line, this is driven by image processor firmware */
394static const unsigned ipi2c_a_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 };
395static const unsigned ipi2c_a_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 };
396/* MSP0 can only be on these pins, but TXD and RXD can be flipped */
397static const unsigned msp0txrx_a_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 };
398static const unsigned msp0tfstck_a_1_pins[] = { DB8500_PIN_AF3, DB8500_PIN_AE3 };
399static const unsigned msp0rfsrck_a_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
400/* Basic pins of the MMC/SD card 0 interface */
401static const unsigned mc0_a_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1,
402 DB8500_PIN_AB4, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2,
403 DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
404/* Often only 4 bits are used, then these are not needed (only used for MMC) */
405static const unsigned mc0_dat47_a_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3,
406 DB8500_PIN_V3, DB8500_PIN_V2};
407static const unsigned mc0dat31dir_a_1_pins[] = { DB8500_PIN_AB3 };
408/* MSP1 can only be on these pins, but TXD and RXD can be flipped */
409static const unsigned msp1txrx_a_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 };
410static const unsigned msp1_a_1_pins[] = { DB8500_PIN_AE1, DB8500_PIN_AE2 };
411/* LCD interface */
412static const unsigned lcdb_a_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
413 DB8500_PIN_G3, DB8500_PIN_G2 };
414static const unsigned lcdvsi0_a_1_pins[] = { DB8500_PIN_E1 };
415static const unsigned lcdvsi1_a_1_pins[] = { DB8500_PIN_E2 };
416static const unsigned lcd_d0_d7_a_1_pins[] = {
417 DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3,
418 DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1 };
419/* D8 thru D11 often used as TVOUT lines */
420static const unsigned lcd_d8_d11_a_1_pins[] = { DB8500_PIN_F4,
421 DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2 };
422static const unsigned lcd_d12_d23_a_1_pins[] = {
423 DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5,
424 DB8500_PIN_C6, DB8500_PIN_B3, DB8500_PIN_C4, DB8500_PIN_E6,
425 DB8500_PIN_A3, DB8500_PIN_B6, DB8500_PIN_D6, DB8500_PIN_B7 };
426static const unsigned kp_a_1_pins[] = { DB8500_PIN_D7, DB8500_PIN_E8,
427 DB8500_PIN_D8, DB8500_PIN_D9 };
428static const unsigned kpskaskb_a_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16 };
429static const unsigned kp_a_2_pins[] = {
430 DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
431 DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
432 DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
433 DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
434/* MC2 has 8 data lines and no direction control, so only for (e)MMC */
435static const unsigned mc2_a_1_pins[] = { DB8500_PIN_A5, DB8500_PIN_B4,
436 DB8500_PIN_C8, DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10,
437 DB8500_PIN_B9, DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7,
438 DB8500_PIN_C5 };
439static const unsigned ssp1_a_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11,
440 DB8500_PIN_C12, DB8500_PIN_C11 };
441static const unsigned ssp0_a_1_pins[] = { DB8500_PIN_D12, DB8500_PIN_B13,
442 DB8500_PIN_C13, DB8500_PIN_D13 };
443static const unsigned i2c0_a_1_pins[] = { DB8500_PIN_C15, DB8500_PIN_B16 };
444/*
445 * Image processor GPIO pins are named "ipgpio" and have their own
446 * numberspace
447 */
448static const unsigned ipgpio0_a_1_pins[] = { DB8500_PIN_B14 };
449static const unsigned ipgpio1_a_1_pins[] = { DB8500_PIN_C14 };
450/* Three modem pins named RF_PURn, MODEM_STATE and MODEM_PWREN */
451static const unsigned modem_a_1_pins[] = { DB8500_PIN_D22, DB8500_PIN_C23,
452 DB8500_PIN_D23 };
453/*
454 * This MSP cannot switch RX and TX, SCK in a separate group since this
455 * seems to be optional.
456 */
457static const unsigned msp2sck_a_1_pins[] = { DB8500_PIN_AJ27 };
458static const unsigned msp2_a_1_pins[] = { DB8500_PIN_AH27, DB8500_PIN_AF27,
459 DB8500_PIN_AG28, DB8500_PIN_AG26 };
460static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25,
461 DB8500_PIN_AH23, DB8500_PIN_AH26, DB8500_PIN_AF24, DB8500_PIN_AF25,
462 DB8500_PIN_AE23, DB8500_PIN_AF23, DB8500_PIN_AG23, DB8500_PIN_AG24,
463 DB8500_PIN_AJ23 };
464/* MC1 has only 4 data pins, designed for SD or SDIO exclusively */
465static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15,
466 DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13,
467 DB8500_PIN_AH15 };
468static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
469 DB8500_PIN_AH12, DB8500_PIN_AH11 };
470static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10 };
471static const unsigned hsit_a_1_pins[] = { DB8500_PIN_AJ11, DB8500_PIN_AJ9,
472 DB8500_PIN_AH9, DB8500_PIN_AG9, DB8500_PIN_AG8, DB8500_PIN_AF8 };
473static const unsigned clkout_a_1_pins[] = { DB8500_PIN_AH7, DB8500_PIN_AJ6 };
474static const unsigned clkout_a_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 };
475static const unsigned usb_a_1_pins[] = { DB8500_PIN_AF28, DB8500_PIN_AE29,
476 DB8500_PIN_AD29, DB8500_PIN_AC29, DB8500_PIN_AD28, DB8500_PIN_AD26,
477 DB8500_PIN_AE26, DB8500_PIN_AG29, DB8500_PIN_AE27, DB8500_PIN_AD27,
478 DB8500_PIN_AC28, DB8500_PIN_AC27 };
479
480/* Altfunction B column */
481static const unsigned trig_b_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3 };
482static const unsigned i2c4_b_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 };
483static const unsigned i2c1_b_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 };
484static const unsigned i2c2_b_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 };
485static const unsigned i2c2_b_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 };
486static const unsigned msp0txrx_b_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 };
487static const unsigned i2c1_b_2_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
488/* Just RX and TX for UART2 */
489static const unsigned u2rxtx_b_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1 };
490static const unsigned uartmodtx_b_1_pins[] = { DB8500_PIN_AB4 };
491static const unsigned msp0sck_b_1_pins[] = { DB8500_PIN_AB3 };
492static const unsigned uartmodrx_b_1_pins[] = { DB8500_PIN_AA3 };
493static const unsigned stmmod_b_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_Y4,
494 DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
495static const unsigned uartmodrx_b_2_pins[] = { DB8500_PIN_AB2 };
496static const unsigned spi3_b_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3,
497 DB8500_PIN_V3, DB8500_PIN_V2 };
498static const unsigned msp1txrx_b_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 };
499static const unsigned kp_b_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
500 DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_E1, DB8500_PIN_E2,
501 DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3,
502 DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1,
503 DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2,
504 DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 };
505static const unsigned sm_b_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
506 DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
507 DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
508 DB8500_PIN_D9, DB8500_PIN_A5, DB8500_PIN_B4, DB8500_PIN_C8,
509 DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, DB8500_PIN_B9,
510 DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, DB8500_PIN_C5,
511 DB8500_PIN_C9, DB8500_PIN_B14 };
512/* This chip select pin can be "ps0" in alt B so have it separately */
513static const unsigned smcs0_b_1_pins[] = { DB8500_PIN_E8 };
514static const unsigned ipgpio7_b_1_pins[] = { DB8500_PIN_B11 };
515static const unsigned ipgpio2_b_1_pins[] = { DB8500_PIN_C12 };
516static const unsigned ipgpio3_b_1_pins[] = { DB8500_PIN_C11 };
517static const unsigned lcdaclk_b_1_pins[] = { DB8500_PIN_C14 };
518static const unsigned lcda_b_1_pins[] = { DB8500_PIN_D22,
519 DB8500_PIN_C23, DB8500_PIN_D23 };
520static const unsigned lcd_b_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16,
521 DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
522 DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
523 DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
524 DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
525static const unsigned ddrtrig_b_1_pins[] = { DB8500_PIN_AJ27 };
526static const unsigned pwl_b_1_pins[] = { DB8500_PIN_AF25 };
527static const unsigned spi1_b_1_pins[] = { DB8500_PIN_AG15, DB8500_PIN_AF13,
528 DB8500_PIN_AG13, DB8500_PIN_AH15 };
529static const unsigned mc3_b_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
530 DB8500_PIN_AH12, DB8500_PIN_AH11, DB8500_PIN_AG10, DB8500_PIN_AH10,
531 DB8500_PIN_AJ11, DB8500_PIN_AJ9, DB8500_PIN_AH9, DB8500_PIN_AG9,
532 DB8500_PIN_AG8 };
533static const unsigned pwl_b_2_pins[] = { DB8500_PIN_AF8 };
534static const unsigned pwl_b_3_pins[] = { DB8500_PIN_AG7 };
535static const unsigned pwl_b_4_pins[] = { DB8500_PIN_AF7 };
536
537/* Altfunction C column */
538static const unsigned ipjtag_c_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3,
539 DB8500_PIN_AH4, DB8500_PIN_AH3, DB8500_PIN_AH6 };
540static const unsigned ipgpio6_c_1_pins[] = { DB8500_PIN_AG6 };
541static const unsigned ipgpio0_c_1_pins[] = { DB8500_PIN_AF6 };
542static const unsigned ipgpio1_c_1_pins[] = { DB8500_PIN_AG5 };
543static const unsigned ipgpio3_c_1_pins[] = { DB8500_PIN_AF5 };
544static const unsigned ipgpio2_c_1_pins[] = { DB8500_PIN_AG4 };
545static const unsigned slim0_c_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
546/* Optional 4-bit Memory Stick interface */
547static const unsigned ms_c_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1,
548 DB8500_PIN_AB3, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2,
549 DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
550static const unsigned iptrigout_c_1_pins[] = { DB8500_PIN_AB4 };
551static const unsigned u2rxtx_c_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3 };
552static const unsigned u2ctsrts_c_1_pins[] = { DB8500_PIN_V3, DB8500_PIN_V2 };
553static const unsigned u0_c_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AE1,
554 DB8500_PIN_AE2, DB8500_PIN_AG2 };
555static const unsigned ipgpio4_c_1_pins[] = { DB8500_PIN_F3 };
556static const unsigned ipgpio5_c_1_pins[] = { DB8500_PIN_F1 };
557static const unsigned ipgpio6_c_2_pins[] = { DB8500_PIN_G3 };
558static const unsigned ipgpio7_c_1_pins[] = { DB8500_PIN_G2 };
559static const unsigned smcleale_c_1_pins[] = { DB8500_PIN_E1, DB8500_PIN_E2 };
560static const unsigned stmape_c_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4,
561 DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3 };
562static const unsigned u2rxtx_c_2_pins[] = { DB8500_PIN_H2, DB8500_PIN_J2 };
563static const unsigned ipgpio2_c_2_pins[] = { DB8500_PIN_F4 };
564static const unsigned ipgpio3_c_2_pins[] = { DB8500_PIN_E3 };
565static const unsigned ipgpio4_c_2_pins[] = { DB8500_PIN_E4 };
566static const unsigned ipgpio5_c_2_pins[] = { DB8500_PIN_D2 };
567static const unsigned mc5_c_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
568 DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
569 DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
570 DB8500_PIN_D9 };
571static const unsigned mc2rstn_c_1_pins[] = { DB8500_PIN_C8 };
572static const unsigned kp_c_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11,
573 DB8500_PIN_C12, DB8500_PIN_C11, DB8500_PIN_D17, DB8500_PIN_D16,
574 DB8500_PIN_C23, DB8500_PIN_D23 };
575static const unsigned smps1_c_1_pins[] = { DB8500_PIN_B14 };
576static const unsigned u2rxtx_c_3_pins[] = { DB8500_PIN_B17, DB8500_PIN_C16 };
577static const unsigned stmape_c_2_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17,
578 DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19 };
579static const unsigned uartmodrx_c_1_pins[] = { DB8500_PIN_D21 };
580static const unsigned uartmodtx_c_1_pins[] = { DB8500_PIN_D20 };
581static const unsigned stmmod_c_1_pins[] = { DB8500_PIN_C20, DB8500_PIN_B21,
582 DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24 };
583static const unsigned usbsim_c_1_pins[] = { DB8500_PIN_D22 };
584static const unsigned mc4rstn_c_1_pins[] = { DB8500_PIN_AF25 };
585static const unsigned clkout_c_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AH12 };
586static const unsigned i2c3_c_1_pins[] = { DB8500_PIN_AG12, DB8500_PIN_AH11 };
587static const unsigned spi0_c_1_pins[] = { DB8500_PIN_AH10, DB8500_PIN_AH9,
588 DB8500_PIN_AG9, DB8500_PIN_AG8 };
589static const unsigned usbsim_c_2_pins[] = { DB8500_PIN_AF8 };
590static const unsigned i2c3_c_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 };
591
592/* Other C1 column */
593static const unsigned kp_oc1_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
594 DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
595 DB8500_PIN_D6, DB8500_PIN_B7 };
596static const unsigned spi2_oc1_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
597 DB8500_PIN_AH12, DB8500_PIN_AH11 };
598
599#define DB8500_PIN_GROUP(a,b) { .name = #a, .pins = a##_pins, \
600 .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
601
602static const struct nmk_pingroup nmk_db8500_groups[] = {
603 /* Altfunction A column */
604 DB8500_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
605 DB8500_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A),
606 DB8500_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A),
607 DB8500_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A),
608 DB8500_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A),
609 DB8500_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A),
610 DB8500_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
611 DB8500_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
612 DB8500_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
613 DB8500_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
614 DB8500_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A),
615 DB8500_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A),
616 DB8500_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A),
617 DB8500_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A),
618 DB8500_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A),
619 DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A),
620 DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A),
621 DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
622 DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A),
623 DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A),
624 DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A),
625 DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
626 DB8500_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A),
627 DB8500_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A),
628 DB8500_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A),
629 DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A),
630 DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
631 DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
632 DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
633 DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
634 DB8500_PIN_GROUP(clkout_a_1, NMK_GPIO_ALT_A),
635 DB8500_PIN_GROUP(clkout_a_2, NMK_GPIO_ALT_A),
636 DB8500_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A),
637 /* Altfunction B column */
638 DB8500_PIN_GROUP(trig_b_1, NMK_GPIO_ALT_B),
639 DB8500_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B),
640 DB8500_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B),
641 DB8500_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B),
642 DB8500_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B),
643 DB8500_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B),
644 DB8500_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B),
645 DB8500_PIN_GROUP(u2rxtx_b_1, NMK_GPIO_ALT_B),
646 DB8500_PIN_GROUP(uartmodtx_b_1, NMK_GPIO_ALT_B),
647 DB8500_PIN_GROUP(msp0sck_b_1, NMK_GPIO_ALT_B),
648 DB8500_PIN_GROUP(uartmodrx_b_1, NMK_GPIO_ALT_B),
649 DB8500_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B),
650 DB8500_PIN_GROUP(uartmodrx_b_2, NMK_GPIO_ALT_B),
651 DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B),
652 DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
653 DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
654 DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
655 DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
656 DB8500_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B),
657 DB8500_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B),
658 DB8500_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B),
659 DB8500_PIN_GROUP(lcdaclk_b_1, NMK_GPIO_ALT_B),
660 DB8500_PIN_GROUP(lcda_b_1, NMK_GPIO_ALT_B),
661 DB8500_PIN_GROUP(lcd_b_1, NMK_GPIO_ALT_B),
662 DB8500_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B),
663 DB8500_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B),
664 DB8500_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B),
665 DB8500_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B),
666 DB8500_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B),
667 DB8500_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B),
668 DB8500_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B),
669 /* Altfunction C column */
670 DB8500_PIN_GROUP(ipjtag_c_1, NMK_GPIO_ALT_C),
671 DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
672 DB8500_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C),
673 DB8500_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C),
674 DB8500_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C),
675 DB8500_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C),
676 DB8500_PIN_GROUP(slim0_c_1, NMK_GPIO_ALT_C),
677 DB8500_PIN_GROUP(ms_c_1, NMK_GPIO_ALT_C),
678 DB8500_PIN_GROUP(iptrigout_c_1, NMK_GPIO_ALT_C),
679 DB8500_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C),
680 DB8500_PIN_GROUP(u2ctsrts_c_1, NMK_GPIO_ALT_C),
681 DB8500_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C),
682 DB8500_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C),
683 DB8500_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C),
684 DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
685 DB8500_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C),
686 DB8500_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C),
687 DB8500_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C),
688 DB8500_PIN_GROUP(u2rxtx_c_2, NMK_GPIO_ALT_C),
689 DB8500_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C),
690 DB8500_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C),
691 DB8500_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C),
692 DB8500_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C),
693 DB8500_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C),
694 DB8500_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C),
695 DB8500_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C),
696 DB8500_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C),
697 DB8500_PIN_GROUP(u2rxtx_c_3, NMK_GPIO_ALT_C),
698 DB8500_PIN_GROUP(stmape_c_2, NMK_GPIO_ALT_C),
699 DB8500_PIN_GROUP(uartmodrx_c_1, NMK_GPIO_ALT_C),
700 DB8500_PIN_GROUP(uartmodtx_c_1, NMK_GPIO_ALT_C),
701 DB8500_PIN_GROUP(stmmod_c_1, NMK_GPIO_ALT_C),
702 DB8500_PIN_GROUP(usbsim_c_1, NMK_GPIO_ALT_C),
703 DB8500_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C),
704 DB8500_PIN_GROUP(clkout_c_1, NMK_GPIO_ALT_C),
705 DB8500_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
706 DB8500_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
707 DB8500_PIN_GROUP(usbsim_c_2, NMK_GPIO_ALT_C),
708 DB8500_PIN_GROUP(i2c3_c_2, NMK_GPIO_ALT_C),
709 /* Other alt C1 column, these are still configured as alt C */
710 DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C),
711 DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C),
712};
713
714/* We use this macro to define the groups applicable to a function */
715#define DB8500_FUNC_GROUPS(a, b...) \
716static const char * const a##_groups[] = { b };
717
718DB8500_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1");
719DB8500_FUNC_GROUPS(u1, "u1rxtx_a_1", "u1ctsrts_a_1");
720/*
721 * UART2 can be muxed out with just RX/TX in four places, CTS+RTS is however
722 * only available on two pins in alternative function C
723 */
724DB8500_FUNC_GROUPS(u2, "u2rxtx_b_1", "u2rxtx_c_1", "u2ctsrts_c_1",
725 "u2rxtx_c_2", "u2rxtx_c_3");
726DB8500_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2");
727/*
728 * MSP0 can only be on a certain set of pins, but the TX/RX pins can be
729 * switched around by selecting the altfunction A or B. The SCK pin is
730 * only available on the altfunction B.
731 */
732DB8500_FUNC_GROUPS(msp0, "msp0txrx_a_1", "msp0tfstck_a_1", "msp0rfstck_a_1",
733 "msp0txrx_b_1", "msp0sck_b_1");
734DB8500_FUNC_GROUPS(mc0, "mc0_a_1");
735/* MSP0 can swap RX/TX like MSP0 but has no SCK pin available */
736DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1");
737DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1");
738DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1",
739 "lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1");
740DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1");
741DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
742DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1");
743DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1");
744DB8500_FUNC_GROUPS(i2c0, "i2c0_a_1");
745/* The image processor has 8 GPIO pins that can be muxed out */
746DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1",
747 "ipgpio2_b_1", "ipgpio3_b_1", "ipgpio6_c_1", "ipgpio0_c_1",
748 "ipgpio1_c_1", "ipgpio3_c_1", "ipgpio2_c_1", "ipgpio4_c_1",
749 "ipgpio5_c_1", "ipgpio6_c_2", "ipgpio7_c_1", "ipgpio2_c_2",
750 "ipgpio3_c_2", "ipgpio4_c_2", "ipgpio5_c_2");
751/* MSP2 can not invert the RX/TX pins but has the optional SCK pin */
752DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1");
753DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
754DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1dir_a_1");
755DB8500_FUNC_GROUPS(hsi, "hsir1_a_1", "hsit1_a_1");
756DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1");
757DB8500_FUNC_GROUPS(usb, "usb_a_1");
758DB8500_FUNC_GROUPS(trig, "trig_b_1");
759DB8500_FUNC_GROUPS(i2c4, "i2c4_b_1");
760DB8500_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2");
761DB8500_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2");
762/*
763 * The modem UART can output its RX and TX pins in some different places,
764 * so select one of each.
765 */
766DB8500_FUNC_GROUPS(uartmod, "uartmodtx_b_1", "uartmodrx_b_1", "uartmodrx_b_2",
767 "uartmodrx_c_1", "uartmod_tx_c_1");
768DB8500_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_c_1");
769DB8500_FUNC_GROUPS(spi3, "spi3_b_1");
770/* Select between CS0 on alt B or PS1 on alt C */
771DB8500_FUNC_GROUPS(sm, "sm_b_1", "smcs0_b_1", "smcleale_c_1", "smps1_c_1");
772DB8500_FUNC_GROUPS(lcda, "lcdaclk_b_1", "lcda_b_1");
773DB8500_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1");
774DB8500_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4");
775DB8500_FUNC_GROUPS(spi1, "spi1_b_1");
776DB8500_FUNC_GROUPS(mc3, "mc3_b_1");
777DB8500_FUNC_GROUPS(ipjtag, "ipjtag_c_1");
778DB8500_FUNC_GROUPS(slim0, "slim0_c_1");
779DB8500_FUNC_GROUPS(ms, "ms_c_1");
780DB8500_FUNC_GROUPS(iptrigout, "iptrigout_c_1");
781DB8500_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_c_2");
782DB8500_FUNC_GROUPS(mc5, "mc5_c_1");
783DB8500_FUNC_GROUPS(usbsim, "usbsim_c_1", "usbsim_c_2");
784DB8500_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c3_c_2");
785DB8500_FUNC_GROUPS(spi0, "spi0_c_1");
786DB8500_FUNC_GROUPS(spi2, "spi2_oc1_1");
787
788#define FUNCTION(fname) \
789 { \
790 .name = #fname, \
791 .groups = fname##_groups, \
792 .ngroups = ARRAY_SIZE(fname##_groups), \
793 }
794
795static const struct nmk_function nmk_db8500_functions[] = {
796 FUNCTION(u0),
797 FUNCTION(u1),
798 FUNCTION(u2),
799 FUNCTION(ipi2c),
800 FUNCTION(msp0),
801 FUNCTION(mc0),
802 FUNCTION(msp1),
803 FUNCTION(lcdb),
804 FUNCTION(lcd),
805 FUNCTION(kp),
806 FUNCTION(mc2),
807 FUNCTION(ssp1),
808 FUNCTION(ssp0),
809 FUNCTION(i2c0),
810 FUNCTION(ipgpio),
811 FUNCTION(msp2),
812 FUNCTION(mc4),
813 FUNCTION(mc1),
814 FUNCTION(hsi),
815 FUNCTION(clkout),
816 FUNCTION(usb),
817 FUNCTION(trig),
818 FUNCTION(i2c4),
819 FUNCTION(i2c1),
820 FUNCTION(i2c2),
821 FUNCTION(uartmod),
822 FUNCTION(stmmod),
823 FUNCTION(spi3),
824 FUNCTION(sm),
825 FUNCTION(lcda),
826 FUNCTION(ddrtrig),
827 FUNCTION(pwl),
828 FUNCTION(spi1),
829 FUNCTION(mc3),
830 FUNCTION(ipjtag),
831 FUNCTION(slim0),
832 FUNCTION(ms),
833 FUNCTION(iptrigout),
834 FUNCTION(stmape),
835 FUNCTION(mc5),
836 FUNCTION(usbsim),
837 FUNCTION(i2c3),
838 FUNCTION(spi0),
839 FUNCTION(spi2),
840};
841
842static const struct nmk_pinctrl_soc_data nmk_db8500_soc = {
843 .gpio_ranges = nmk_db8500_ranges,
844 .gpio_num_ranges = ARRAY_SIZE(nmk_db8500_ranges),
845 .pins = nmk_db8500_pins,
846 .npins = ARRAY_SIZE(nmk_db8500_pins),
847 .functions = nmk_db8500_functions,
848 .nfunctions = ARRAY_SIZE(nmk_db8500_functions),
849 .groups = nmk_db8500_groups,
850 .ngroups = ARRAY_SIZE(nmk_db8500_groups),
851};
852
853void __devinit
854nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
855{
856 *soc = &nmk_db8500_soc;
857}
diff --git a/drivers/gpio/gpio-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 9b126b6d79cc..b8e01c3eaa95 100644
--- a/drivers/gpio/gpio-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -24,12 +24,19 @@
24#include <linux/irq.h> 24#include <linux/irq.h>
25#include <linux/irqdomain.h> 25#include <linux/irqdomain.h>
26#include <linux/slab.h> 26#include <linux/slab.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/pinctrl/pinconf.h>
30/* Since we request GPIOs from ourself */
31#include <linux/pinctrl/consumer.h>
27 32
28#include <asm/mach/irq.h> 33#include <asm/mach/irq.h>
29 34
30#include <plat/pincfg.h> 35#include <plat/pincfg.h>
31#include <plat/gpio-nomadik.h> 36#include <plat/gpio-nomadik.h>
32 37
38#include "pinctrl-nomadik.h"
39
33/* 40/*
34 * The GPIO module in the Nomadik family of Systems-on-Chip is an 41 * The GPIO module in the Nomadik family of Systems-on-Chip is an
35 * AMBA device, managing 32 pins and alternate functions. The logic block 42 * AMBA device, managing 32 pins and alternate functions. The logic block
@@ -64,6 +71,12 @@ struct nmk_gpio_chip {
64 u32 lowemi; 71 u32 lowemi;
65}; 72};
66 73
74struct nmk_pinctrl {
75 struct device *dev;
76 struct pinctrl_dev *pctl;
77 const struct nmk_pinctrl_soc_data *soc;
78};
79
67static struct nmk_gpio_chip * 80static struct nmk_gpio_chip *
68nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; 81nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
69 82
@@ -864,6 +877,25 @@ static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
864} 877}
865 878
866/* I/O Functions */ 879/* I/O Functions */
880
881static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
882{
883 /*
884 * Map back to global GPIO space and request muxing, the direction
885 * parameter does not matter for this controller.
886 */
887 int gpio = chip->base + offset;
888
889 return pinctrl_request_gpio(gpio);
890}
891
892static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
893{
894 int gpio = chip->base + offset;
895
896 pinctrl_free_gpio(gpio);
897}
898
867static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) 899static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
868{ 900{
869 struct nmk_gpio_chip *nmk_chip = 901 struct nmk_gpio_chip *nmk_chip =
@@ -934,14 +966,16 @@ static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
934 966
935#include <linux/seq_file.h> 967#include <linux/seq_file.h>
936 968
937static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 969static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip,
970 unsigned offset, unsigned gpio)
938{ 971{
939 int mode; 972 const char *label = gpiochip_is_requested(chip, offset);
940 unsigned i;
941 unsigned gpio = chip->base;
942 int is_out;
943 struct nmk_gpio_chip *nmk_chip = 973 struct nmk_gpio_chip *nmk_chip =
944 container_of(chip, struct nmk_gpio_chip, chip); 974 container_of(chip, struct nmk_gpio_chip, chip);
975 int mode;
976 bool is_out;
977 bool pull;
978 u32 bit = 1 << offset;
945 const char *modes[] = { 979 const char *modes[] = {
946 [NMK_GPIO_ALT_GPIO] = "gpio", 980 [NMK_GPIO_ALT_GPIO] = "gpio",
947 [NMK_GPIO_ALT_A] = "altA", 981 [NMK_GPIO_ALT_A] = "altA",
@@ -950,61 +984,70 @@ static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
950 }; 984 };
951 985
952 clk_enable(nmk_chip->clk); 986 clk_enable(nmk_chip->clk);
953 987 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
954 for (i = 0; i < chip->ngpio; i++, gpio++) { 988 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
955 const char *label = gpiochip_is_requested(chip, i); 989 mode = nmk_gpio_get_mode(gpio);
956 bool pull; 990
957 u32 bit = 1 << i; 991 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
958 992 gpio, label ?: "(none)",
959 is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit; 993 is_out ? "out" : "in ",
960 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); 994 chip->get
961 mode = nmk_gpio_get_mode(gpio); 995 ? (chip->get(chip, offset) ? "hi" : "lo")
962 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", 996 : "? ",
963 gpio, label ?: "(none)", 997 (mode < 0) ? "unknown" : modes[mode],
964 is_out ? "out" : "in ", 998 pull ? "pull" : "none");
965 chip->get 999
966 ? (chip->get(chip, i) ? "hi" : "lo") 1000 if (label && !is_out) {
967 : "? ", 1001 int irq = gpio_to_irq(gpio);
968 (mode < 0) ? "unknown" : modes[mode], 1002 struct irq_desc *desc = irq_to_desc(irq);
969 pull ? "pull" : "none"); 1003
970 1004 /* This races with request_irq(), set_irq_type(),
971 if (label && !is_out) { 1005 * and set_irq_wake() ... but those are "rare".
972 int irq = gpio_to_irq(gpio); 1006 */
973 struct irq_desc *desc = irq_to_desc(irq); 1007 if (irq >= 0 && desc->action) {
974 1008 char *trigger;
975 /* This races with request_irq(), set_irq_type(), 1009 u32 bitmask = nmk_gpio_get_bitmask(gpio);
976 * and set_irq_wake() ... but those are "rare". 1010
977 */ 1011 if (nmk_chip->edge_rising & bitmask)
978 if (irq >= 0 && desc->action) { 1012 trigger = "edge-rising";
979 char *trigger; 1013 else if (nmk_chip->edge_falling & bitmask)
980 u32 bitmask = nmk_gpio_get_bitmask(gpio); 1014 trigger = "edge-falling";
981 1015 else
982 if (nmk_chip->edge_rising & bitmask) 1016 trigger = "edge-undefined";
983 trigger = "edge-rising"; 1017
984 else if (nmk_chip->edge_falling & bitmask) 1018 seq_printf(s, " irq-%d %s%s",
985 trigger = "edge-falling"; 1019 irq, trigger,
986 else 1020 irqd_is_wakeup_set(&desc->irq_data)
987 trigger = "edge-undefined"; 1021 ? " wakeup" : "");
988
989 seq_printf(s, " irq-%d %s%s",
990 irq, trigger,
991 irqd_is_wakeup_set(&desc->irq_data)
992 ? " wakeup" : "");
993 }
994 } 1022 }
1023 }
1024 clk_disable(nmk_chip->clk);
1025}
1026
1027static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1028{
1029 unsigned i;
1030 unsigned gpio = chip->base;
995 1031
1032 for (i = 0; i < chip->ngpio; i++, gpio++) {
1033 nmk_gpio_dbg_show_one(s, chip, i, gpio);
996 seq_printf(s, "\n"); 1034 seq_printf(s, "\n");
997 } 1035 }
998
999 clk_disable(nmk_chip->clk);
1000} 1036}
1001 1037
1002#else 1038#else
1039static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1040 struct gpio_chip *chip,
1041 unsigned offset, unsigned gpio)
1042{
1043}
1003#define nmk_gpio_dbg_show NULL 1044#define nmk_gpio_dbg_show NULL
1004#endif 1045#endif
1005 1046
1006/* This structure is replicated for each GPIO block allocated at probe time */ 1047/* This structure is replicated for each GPIO block allocated at probe time */
1007static struct gpio_chip nmk_gpio_template = { 1048static struct gpio_chip nmk_gpio_template = {
1049 .request = nmk_gpio_request,
1050 .free = nmk_gpio_free,
1008 .direction_input = nmk_gpio_make_input, 1051 .direction_input = nmk_gpio_make_input,
1009 .get = nmk_gpio_get_input, 1052 .get = nmk_gpio_get_input,
1010 .direction_output = nmk_gpio_make_output, 1053 .direction_output = nmk_gpio_make_output,
@@ -1235,7 +1278,9 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
1235 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); 1278 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1236 clk_disable(nmk_chip->clk); 1279 clk_disable(nmk_chip->clk);
1237 1280
1281#ifdef CONFIG_OF_GPIO
1238 chip->of_node = np; 1282 chip->of_node = np;
1283#endif
1239 1284
1240 ret = gpiochip_add(&nmk_chip->chip); 1285 ret = gpiochip_add(&nmk_chip->chip);
1241 if (ret) 1286 if (ret)
@@ -1280,6 +1325,416 @@ out:
1280 return ret; 1325 return ret;
1281} 1326}
1282 1327
1328static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1329{
1330 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1331
1332 return npct->soc->ngroups;
1333}
1334
1335static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1336 unsigned selector)
1337{
1338 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1339
1340 return npct->soc->groups[selector].name;
1341}
1342
1343static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1344 const unsigned **pins,
1345 unsigned *num_pins)
1346{
1347 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1348
1349 *pins = npct->soc->groups[selector].pins;
1350 *num_pins = npct->soc->groups[selector].npins;
1351 return 0;
1352}
1353
1354static struct pinctrl_gpio_range *
1355nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1356{
1357 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1358 int i;
1359
1360 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1361 struct pinctrl_gpio_range *range;
1362
1363 range = &npct->soc->gpio_ranges[i];
1364 if (offset >= range->pin_base &&
1365 offset <= (range->pin_base + range->npins - 1))
1366 return range;
1367 }
1368 return NULL;
1369}
1370
1371static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1372 unsigned offset)
1373{
1374 struct pinctrl_gpio_range *range;
1375 struct gpio_chip *chip;
1376
1377 range = nmk_match_gpio_range(pctldev, offset);
1378 if (!range || !range->gc) {
1379 seq_printf(s, "invalid pin offset");
1380 return;
1381 }
1382 chip = range->gc;
1383 nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset);
1384}
1385
1386static struct pinctrl_ops nmk_pinctrl_ops = {
1387 .get_groups_count = nmk_get_groups_cnt,
1388 .get_group_name = nmk_get_group_name,
1389 .get_group_pins = nmk_get_group_pins,
1390 .pin_dbg_show = nmk_pin_dbg_show,
1391};
1392
1393static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1394{
1395 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1396
1397 return npct->soc->nfunctions;
1398}
1399
1400static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1401 unsigned function)
1402{
1403 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1404
1405 return npct->soc->functions[function].name;
1406}
1407
1408static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1409 unsigned function,
1410 const char * const **groups,
1411 unsigned * const num_groups)
1412{
1413 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1414
1415 *groups = npct->soc->functions[function].groups;
1416 *num_groups = npct->soc->functions[function].ngroups;
1417
1418 return 0;
1419}
1420
1421static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1422 unsigned group)
1423{
1424 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1425 const struct nmk_pingroup *g;
1426 static unsigned int slpm[NUM_BANKS];
1427 unsigned long flags;
1428 bool glitch;
1429 int ret = -EINVAL;
1430 int i;
1431
1432 g = &npct->soc->groups[group];
1433
1434 if (g->altsetting < 0)
1435 return -EINVAL;
1436
1437 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1438
1439 /* Handle this special glitch on altfunction C */
1440 glitch = (g->altsetting == NMK_GPIO_ALT_C);
1441
1442 if (glitch) {
1443 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1444
1445 /* Initially don't put any pins to sleep when switching */
1446 memset(slpm, 0xff, sizeof(slpm));
1447
1448 /*
1449 * Then mask the pins that need to be sleeping now when we're
1450 * switching to the ALT C function.
1451 */
1452 for (i = 0; i < g->npins; i++)
1453 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1454 nmk_gpio_glitch_slpm_init(slpm);
1455 }
1456
1457 for (i = 0; i < g->npins; i++) {
1458 struct pinctrl_gpio_range *range;
1459 struct nmk_gpio_chip *nmk_chip;
1460 struct gpio_chip *chip;
1461 unsigned bit;
1462
1463 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1464 if (!range) {
1465 dev_err(npct->dev,
1466 "invalid pin offset %d in group %s at index %d\n",
1467 g->pins[i], g->name, i);
1468 goto out_glitch;
1469 }
1470 if (!range->gc) {
1471 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1472 g->pins[i], g->name, i);
1473 goto out_glitch;
1474 }
1475 chip = range->gc;
1476 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1477 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1478
1479 clk_enable(nmk_chip->clk);
1480 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1481 /*
1482 * If the pin is switching to altfunc, and there was an
1483 * interrupt installed on it which has been lazy disabled,
1484 * actually mask the interrupt to prevent spurious interrupts
1485 * that would occur while the pin is under control of the
1486 * peripheral. Only SKE does this.
1487 */
1488 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1489
1490 __nmk_gpio_set_mode_safe(nmk_chip, bit, g->altsetting, glitch);
1491 clk_disable(nmk_chip->clk);
1492 }
1493
1494 /* When all pins are successfully reconfigured we get here */
1495 ret = 0;
1496
1497out_glitch:
1498 if (glitch) {
1499 nmk_gpio_glitch_slpm_restore(slpm);
1500 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1501 }
1502
1503 return ret;
1504}
1505
1506static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1507 unsigned function, unsigned group)
1508{
1509 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1510 const struct nmk_pingroup *g;
1511
1512 g = &npct->soc->groups[group];
1513
1514 if (g->altsetting < 0)
1515 return;
1516
1517 /* Poke out the mux, set the pin to some default state? */
1518 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1519}
1520
1521int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1522 struct pinctrl_gpio_range *range,
1523 unsigned offset)
1524{
1525 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1526 struct nmk_gpio_chip *nmk_chip;
1527 struct gpio_chip *chip;
1528 unsigned bit;
1529
1530 if (!range) {
1531 dev_err(npct->dev, "invalid range\n");
1532 return -EINVAL;
1533 }
1534 if (!range->gc) {
1535 dev_err(npct->dev, "missing GPIO chip in range\n");
1536 return -EINVAL;
1537 }
1538 chip = range->gc;
1539 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1540
1541 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1542
1543 clk_enable(nmk_chip->clk);
1544 bit = offset % NMK_GPIO_PER_CHIP;
1545 /* There is no glitch when converting any pin to GPIO */
1546 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1547 clk_disable(nmk_chip->clk);
1548
1549 return 0;
1550}
1551
1552void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1553 struct pinctrl_gpio_range *range,
1554 unsigned offset)
1555{
1556 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1557
1558 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1559 /* Set the pin to some default state, GPIO is usually default */
1560}
1561
1562static struct pinmux_ops nmk_pinmux_ops = {
1563 .get_functions_count = nmk_pmx_get_funcs_cnt,
1564 .get_function_name = nmk_pmx_get_func_name,
1565 .get_function_groups = nmk_pmx_get_func_groups,
1566 .enable = nmk_pmx_enable,
1567 .disable = nmk_pmx_disable,
1568 .gpio_request_enable = nmk_gpio_request_enable,
1569 .gpio_disable_free = nmk_gpio_disable_free,
1570};
1571
1572int nmk_pin_config_get(struct pinctrl_dev *pctldev,
1573 unsigned pin,
1574 unsigned long *config)
1575{
1576 /* Not implemented */
1577 return -EINVAL;
1578}
1579
1580int nmk_pin_config_set(struct pinctrl_dev *pctldev,
1581 unsigned pin,
1582 unsigned long config)
1583{
1584 static const char *pullnames[] = {
1585 [NMK_GPIO_PULL_NONE] = "none",
1586 [NMK_GPIO_PULL_UP] = "up",
1587 [NMK_GPIO_PULL_DOWN] = "down",
1588 [3] /* illegal */ = "??"
1589 };
1590 static const char *slpmnames[] = {
1591 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1592 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1593 };
1594 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1595 struct nmk_gpio_chip *nmk_chip;
1596 struct pinctrl_gpio_range *range;
1597 struct gpio_chip *chip;
1598 unsigned bit;
1599
1600 /*
1601 * The pin config contains pin number and altfunction fields, here
1602 * we just ignore that part. It's being handled by the framework and
1603 * pinmux callback respectively.
1604 */
1605 pin_cfg_t cfg = (pin_cfg_t) config;
1606 int pull = PIN_PULL(cfg);
1607 int slpm = PIN_SLPM(cfg);
1608 int output = PIN_DIR(cfg);
1609 int val = PIN_VAL(cfg);
1610 bool lowemi = PIN_LOWEMI(cfg);
1611 bool gpiomode = PIN_GPIOMODE(cfg);
1612 bool sleep = PIN_SLEEPMODE(cfg);
1613
1614 range = nmk_match_gpio_range(pctldev, pin);
1615 if (!range) {
1616 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1617 return -EINVAL;
1618 }
1619 if (!range->gc) {
1620 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1621 pin);
1622 return -EINVAL;
1623 }
1624 chip = range->gc;
1625 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1626
1627 if (sleep) {
1628 int slpm_pull = PIN_SLPM_PULL(cfg);
1629 int slpm_output = PIN_SLPM_DIR(cfg);
1630 int slpm_val = PIN_SLPM_VAL(cfg);
1631
1632 /* All pins go into GPIO mode at sleep */
1633 gpiomode = true;
1634
1635 /*
1636 * The SLPM_* values are normal values + 1 to allow zero to
1637 * mean "same as normal".
1638 */
1639 if (slpm_pull)
1640 pull = slpm_pull - 1;
1641 if (slpm_output)
1642 output = slpm_output - 1;
1643 if (slpm_val)
1644 val = slpm_val - 1;
1645
1646 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
1647 pin,
1648 slpm_pull ? pullnames[pull] : "same",
1649 slpm_output ? (output ? "output" : "input") : "same",
1650 slpm_val ? (val ? "high" : "low") : "same");
1651 }
1652
1653 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1654 pin, cfg, pullnames[pull], slpmnames[slpm],
1655 output ? "output " : "input",
1656 output ? (val ? "high" : "low") : "",
1657 lowemi ? "on" : "off" );
1658
1659 clk_enable(nmk_chip->clk);
1660 bit = pin % NMK_GPIO_PER_CHIP;
1661 if (gpiomode)
1662 /* No glitch when going to GPIO mode */
1663 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1664 if (output)
1665 __nmk_gpio_make_output(nmk_chip, bit, val);
1666 else {
1667 __nmk_gpio_make_input(nmk_chip, bit);
1668 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1669 }
1670 /* TODO: isn't this only applicable on output pins? */
1671 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1672
1673 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1674 clk_disable(nmk_chip->clk);
1675 return 0;
1676}
1677
1678static struct pinconf_ops nmk_pinconf_ops = {
1679 .pin_config_get = nmk_pin_config_get,
1680 .pin_config_set = nmk_pin_config_set,
1681};
1682
1683static struct pinctrl_desc nmk_pinctrl_desc = {
1684 .name = "pinctrl-nomadik",
1685 .pctlops = &nmk_pinctrl_ops,
1686 .pmxops = &nmk_pinmux_ops,
1687 .confops = &nmk_pinconf_ops,
1688 .owner = THIS_MODULE,
1689};
1690
1691static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
1692{
1693 const struct platform_device_id *platid = platform_get_device_id(pdev);
1694 struct nmk_pinctrl *npct;
1695 int i;
1696
1697 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1698 if (!npct)
1699 return -ENOMEM;
1700
1701 /* Poke in other ASIC variants here */
1702 if (platid->driver_data == PINCTRL_NMK_DB8500)
1703 nmk_pinctrl_db8500_init(&npct->soc);
1704
1705 /*
1706 * We need all the GPIO drivers to probe FIRST, or we will not be able
1707 * to obtain references to the struct gpio_chip * for them, and we
1708 * need this to proceed.
1709 */
1710 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1711 if (!nmk_gpio_chips[i]) {
1712 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1713 devm_kfree(&pdev->dev, npct);
1714 return -EPROBE_DEFER;
1715 }
1716 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip;
1717 }
1718
1719 nmk_pinctrl_desc.pins = npct->soc->pins;
1720 nmk_pinctrl_desc.npins = npct->soc->npins;
1721 npct->dev = &pdev->dev;
1722 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
1723 if (!npct->pctl) {
1724 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1725 return -EINVAL;
1726 }
1727
1728 /* We will handle a range of GPIO pins */
1729 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
1730 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
1731
1732 platform_set_drvdata(pdev, npct);
1733 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1734
1735 return 0;
1736}
1737
1283static const struct of_device_id nmk_gpio_match[] = { 1738static const struct of_device_id nmk_gpio_match[] = {
1284 { .compatible = "st,nomadik-gpio", }, 1739 { .compatible = "st,nomadik-gpio", },
1285 {} 1740 {}
@@ -1294,9 +1749,28 @@ static struct platform_driver nmk_gpio_driver = {
1294 .probe = nmk_gpio_probe, 1749 .probe = nmk_gpio_probe,
1295}; 1750};
1296 1751
1752static const struct platform_device_id nmk_pinctrl_id[] = {
1753 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1754 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1755};
1756
1757static struct platform_driver nmk_pinctrl_driver = {
1758 .driver = {
1759 .owner = THIS_MODULE,
1760 .name = "pinctrl-nomadik",
1761 },
1762 .probe = nmk_pinctrl_probe,
1763 .id_table = nmk_pinctrl_id,
1764};
1765
1297static int __init nmk_gpio_init(void) 1766static int __init nmk_gpio_init(void)
1298{ 1767{
1299 return platform_driver_register(&nmk_gpio_driver); 1768 int ret;
1769
1770 ret = platform_driver_register(&nmk_gpio_driver);
1771 if (ret)
1772 return ret;
1773 return platform_driver_register(&nmk_pinctrl_driver);
1300} 1774}
1301 1775
1302core_initcall(nmk_gpio_init); 1776core_initcall(nmk_gpio_init);
diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h
new file mode 100644
index 000000000000..bc91aed7185d
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik.h
@@ -0,0 +1,77 @@
1#ifndef PINCTRL_PINCTRL_NOMADIK_H
2#define PINCTRL_PINCTRL_NOMADIK_H
3
4#include <plat/gpio-nomadik.h>
5
6/* Package definitions */
7#define PINCTRL_NMK_STN8815 0
8#define PINCTRL_NMK_DB8500 1
9
10/**
11 * struct nmk_function - Nomadik pinctrl mux function
12 * @name: The name of the function, exported to pinctrl core.
13 * @groups: An array of pin groups that may select this function.
14 * @ngroups: The number of entries in @groups.
15 */
16struct nmk_function {
17 const char *name;
18 const char * const *groups;
19 unsigned ngroups;
20};
21
22/**
23 * struct nmk_pingroup - describes a Nomadik pin group
24 * @name: the name of this specific pin group
25 * @pins: an array of discrete physical pins used in this group, taken
26 * from the driver-local pin enumeration space
27 * @num_pins: the number of pins in this group array, i.e. the number of
28 * elements in .pins so we can iterate over that array
29 * @altsetting: the altsetting to apply to all pins in this group to
30 * configure them to be used by a function
31 */
32struct nmk_pingroup {
33 const char *name;
34 const unsigned int *pins;
35 const unsigned npins;
36 int altsetting;
37};
38
39/**
40 * struct nmk_pinctrl_soc_data - Nomadik pin controller per-SoC configuration
41 * @gpio_ranges: An array of GPIO ranges for this SoC
42 * @gpio_num_ranges: The number of GPIO ranges for this SoC
43 * @pins: An array describing all pins the pin controller affects.
44 * All pins which are also GPIOs must be listed first within the
45 * array, and be numbered identically to the GPIO controller's
46 * numbering.
47 * @npins: The number of entries in @pins.
48 * @functions: The functions supported on this SoC.
49 * @nfunction: The number of entries in @functions.
50 * @groups: An array describing all pin groups the pin SoC supports.
51 * @ngroups: The number of entries in @groups.
52 */
53struct nmk_pinctrl_soc_data {
54 struct pinctrl_gpio_range *gpio_ranges;
55 unsigned gpio_num_ranges;
56 const struct pinctrl_pin_desc *pins;
57 unsigned npins;
58 const struct nmk_function *functions;
59 unsigned nfunctions;
60 const struct nmk_pingroup *groups;
61 unsigned ngroups;
62};
63
64#ifdef CONFIG_PINCTRL_DB8500
65
66void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc);
67
68#else
69
70static inline void
71nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
72{
73}
74
75#endif
76
77#endif /* PINCTRL_PINCTRL_NOMADIK_H */
diff --git a/include/linux/pinctrl/pinctrl-state.h b/include/linux/pinctrl/pinctrl-state.h
index 3920e28b4da7..634608dc6c89 100644
--- a/include/linux/pinctrl/pinctrl-state.h
+++ b/include/linux/pinctrl/pinctrl-state.h
@@ -2,5 +2,18 @@
2 * Standard pin control state definitions 2 * Standard pin control state definitions
3 */ 3 */
4 4
5/**
6 * @PINCTRL_STATE_DEFAULT: the state the pinctrl handle shall be put
7 * into as default, usually this means the pins are up and ready to
8 * be used by the device driver. This state is commonly used by
9 * hogs to configure muxing and pins at boot.
10 * @PINCTRL_STATE_IDLE: the state the pinctrl handle shall be put into
11 * when the pins are idle. Could typically be set from a
12 * pm_runtime_suspend() operation.
13 * @PINCTRL_STATE_SLEEP: the state the pinctrl handle shall be put into
14 * when the pins are sleeping. Could typically be set from a
15 * common suspend() function.
16 */
5#define PINCTRL_STATE_DEFAULT "default" 17#define PINCTRL_STATE_DEFAULT "default"
6#define PINCTRL_STATE_IDLE "idle" 18#define PINCTRL_STATE_IDLE "idle"
19#define PINCTRL_STATE_SLEEP "sleep"
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 17:47:14 -0500