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authorJussi Kivilinna <jussi.kivilinna@mbnet.fi>2012-07-30 03:42:36 -0400
committerHerbert Xu <herbert@gondor.apana.org.au>2012-07-30 03:50:54 -0400
commit76f16f83ee520d6c10356b0f6ff592441a6f08bd (patch)
tree008f57adb70850ca0a019acc3233c1ee11d993fe
parent44a6b8442190cf213081060b610dae2e822f802b (diff)
crypto: hifn_795x - fix 64bit division and undefined __divdi3 on 32bit archs
Commit feb7b7ab928afa97a79a9c424e4e0691f49d63be changed NSEC_PER_SEC to 64-bit constant, which causes "DIV_ROUND_UP(NSEC_PER_SEC, dev->pk_clk_freq)" to generate __divdi3 call on 32-bit archs. Fix this by changing DIV_ROUND_UP to DIV_ROUND_UP_ULL. Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi> Acked-by: Randy Dunlap <rdunlap@xenotime.net> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
-rw-r--r--drivers/crypto/hifn_795x.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/crypto/hifn_795x.c b/drivers/crypto/hifn_795x.c
index c9c4befb5a8d..df14358d7fa1 100644
--- a/drivers/crypto/hifn_795x.c
+++ b/drivers/crypto/hifn_795x.c
@@ -821,8 +821,8 @@ static int hifn_register_rng(struct hifn_device *dev)
821 /* 821 /*
822 * We must wait at least 256 Pk_clk cycles between two reads of the rng. 822 * We must wait at least 256 Pk_clk cycles between two reads of the rng.
823 */ 823 */
824 dev->rng_wait_time = DIV_ROUND_UP(NSEC_PER_SEC, dev->pk_clk_freq) * 824 dev->rng_wait_time = DIV_ROUND_UP_ULL(NSEC_PER_SEC,
825 256; 825 dev->pk_clk_freq) * 256;
826 826
827 dev->rng.name = dev->name; 827 dev->rng.name = dev->name;
828 dev->rng.data_present = hifn_rng_data_present, 828 dev->rng.data_present = hifn_rng_data_present,