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authorHuang Shijie <b32955@freescale.com>2013-09-25 02:58:12 -0400
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:06:04 -0400
commit6f37e5e3df4a1105fc2da954605dff33b7d65ae2 (patch)
treec62e6028f7b7568c94037583b556d8d26a098bbc
parent37b488c0e6699389cc376bff606bf08940652af4 (diff)
mtd: nand: add the "bits per cell" info for legacy ID NAND
The legacy ID NAND are all SLC. This patch sets 1 to the @bits_per_cell for the legacy ID NAND, which means they are all SLC. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-rw-r--r--drivers/mtd/nand/nand_base.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 64ee59eb01b7..d9d2097f37bc 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -3249,6 +3249,9 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3249 mtd->oobsize = mtd->writesize / 32; 3249 mtd->oobsize = mtd->writesize / 32;
3250 *busw = type->options & NAND_BUSWIDTH_16; 3250 *busw = type->options & NAND_BUSWIDTH_16;
3251 3251
3252 /* All legacy ID NAND are small-page, SLC */
3253 chip->bits_per_cell = 1;
3254
3252 /* 3255 /*
3253 * Check for Spansion/AMD ID + repeating 5th, 6th byte since 3256 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3254 * some Spansion chips have erasesize that conflicts with size 3257 * some Spansion chips have erasesize that conflicts with size