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authorWei WANG <wei_wang@realsil.com.cn>2012-11-09 07:53:33 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-11-15 20:30:14 -0500
commit67d16a4686c9b94c8f52a66afe7521909aeb75b4 (patch)
tree16e58ccd12f518cb9d62b7b0000301983e64d129
parentecd43c0d7e504fde69e6e53ac63adfd2feea135a (diff)
drivers/mfd: Add realtek pcie card reader driver
Realtek PCI-E card reader driver adapts requests from upper-level sdmmc/memstick layer to the real physical card reader. Signed-off-by: Wei WANG <wei_wang@realsil.com.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Borislav Petkov <bp@alien8.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat
-rw-r--r--drivers/mfd/Kconfig9
-rw-r--r--drivers/mfd/Makefile3
-rw-r--r--drivers/mfd/rtl8411.c251
-rw-r--r--drivers/mfd/rts5209.c223
-rw-r--r--drivers/mfd/rts5229.c205
-rw-r--r--drivers/mfd/rtsx_pcr.c1251
-rw-r--r--drivers/mfd/rtsx_pcr.h32
-rw-r--r--include/linux/mfd/rtsx_common.h48
-rw-r--r--include/linux/mfd/rtsx_pci.h794
9 files changed, 2816 insertions, 0 deletions
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index acab3ef8a310..867af072d482 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -63,6 +63,15 @@ config MFD_SM501_GPIO
63 lines on the SM501. The platform data is used to supply the 63 lines on the SM501. The platform data is used to supply the
64 base number for the first GPIO line to register. 64 base number for the first GPIO line to register.
65 65
66config MFD_RTSX_PCI
67 tristate "Support for Realtek PCI-E card reader"
68 depends on PCI
69 help
70 This supports for Realtek PCI-Express card reader including rts5209,
71 rts5229, rtl8411, etc. Realtek card reader supports access to many
72 types of memory cards, such as Memory Stick, Memory Stick Pro,
73 Secure Digital and MultiMediaCard.
74
66config MFD_ASIC3 75config MFD_ASIC3
67 bool "Support for Compaq ASIC3" 76 bool "Support for Compaq ASIC3"
68 depends on GENERIC_HARDIRQS && GPIOLIB && ARM 77 depends on GENERIC_HARDIRQS && GPIOLIB && ARM
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index d8ccb630ddb0..b53db06d1b46 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -9,6 +9,9 @@ obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o
9obj-$(CONFIG_MFD_SM501) += sm501.o 9obj-$(CONFIG_MFD_SM501) += sm501.o
10obj-$(CONFIG_MFD_ASIC3) += asic3.o tmio_core.o 10obj-$(CONFIG_MFD_ASIC3) += asic3.o tmio_core.o
11 11
12rtsx_pci-objs := rtsx_pcr.o rts5209.o rts5229.o rtl8411.o
13obj-$(CONFIG_MFD_RTSX_PCI) += rtsx_pci.o
14
12obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o 15obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o
13obj-$(CONFIG_HTC_PASIC3) += htc-pasic3.o 16obj-$(CONFIG_HTC_PASIC3) += htc-pasic3.o
14obj-$(CONFIG_HTC_I2CPLD) += htc-i2cpld.o 17obj-$(CONFIG_HTC_I2CPLD) += htc-i2cpld.o
diff --git a/drivers/mfd/rtl8411.c b/drivers/mfd/rtl8411.c
new file mode 100644
index 000000000000..89f046ca9e41
--- /dev/null
+++ b/drivers/mfd/rtl8411.c
@@ -0,0 +1,251 @@
1/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#include <linux/module.h>
24#include <linux/bitops.h>
25#include <linux/delay.h>
26#include <linux/mfd/rtsx_pci.h>
27
28#include "rtsx_pcr.h"
29
30static u8 rtl8411_get_ic_version(struct rtsx_pcr *pcr)
31{
32 u8 val;
33
34 rtsx_pci_read_register(pcr, SYS_VER, &val);
35 return val & 0x0F;
36}
37
38static int rtl8411_extra_init_hw(struct rtsx_pcr *pcr)
39{
40 return rtsx_pci_write_register(pcr, CD_PAD_CTL,
41 CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE);
42}
43
44static int rtl8411_turn_on_led(struct rtsx_pcr *pcr)
45{
46 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00);
47}
48
49static int rtl8411_turn_off_led(struct rtsx_pcr *pcr)
50{
51 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01);
52}
53
54static int rtl8411_enable_auto_blink(struct rtsx_pcr *pcr)
55{
56 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D);
57}
58
59static int rtl8411_disable_auto_blink(struct rtsx_pcr *pcr)
60{
61 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00);
62}
63
64static int rtl8411_card_power_on(struct rtsx_pcr *pcr, int card)
65{
66 int err;
67
68 rtsx_pci_init_cmd(pcr);
69 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
70 BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON);
71 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_CTL,
72 BPP_LDO_POWB, BPP_LDO_SUSPEND);
73 err = rtsx_pci_send_cmd(pcr, 100);
74 if (err < 0)
75 return err;
76
77 /* To avoid too large in-rush current */
78 udelay(150);
79
80 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
81 BPP_POWER_MASK, BPP_POWER_10_PERCENT_ON);
82 if (err < 0)
83 return err;
84
85 udelay(150);
86
87 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
88 BPP_POWER_MASK, BPP_POWER_15_PERCENT_ON);
89 if (err < 0)
90 return err;
91
92 udelay(150);
93
94 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
95 BPP_POWER_MASK, BPP_POWER_ON);
96 if (err < 0)
97 return err;
98
99 return rtsx_pci_write_register(pcr, LDO_CTL, BPP_LDO_POWB, BPP_LDO_ON);
100}
101
102static int rtl8411_card_power_off(struct rtsx_pcr *pcr, int card)
103{
104 int err;
105
106 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
107 BPP_POWER_MASK, BPP_POWER_OFF);
108 if (err < 0)
109 return err;
110
111 return rtsx_pci_write_register(pcr, LDO_CTL,
112 BPP_LDO_POWB, BPP_LDO_SUSPEND);
113}
114
115static unsigned int rtl8411_cd_deglitch(struct rtsx_pcr *pcr)
116{
117 unsigned int card_exist;
118
119 card_exist = rtsx_pci_readl(pcr, RTSX_BIPR);
120 card_exist &= CARD_EXIST;
121 if (!card_exist) {
122 /* Enable card CD */
123 rtsx_pci_write_register(pcr, CD_PAD_CTL,
124 CD_DISABLE_MASK, CD_ENABLE);
125 /* Enable card interrupt */
126 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x00);
127 return 0;
128 }
129
130 if (hweight32(card_exist) > 1) {
131 rtsx_pci_write_register(pcr, CARD_PWR_CTL,
132 BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON);
133 msleep(100);
134
135 card_exist = rtsx_pci_readl(pcr, RTSX_BIPR);
136 if (card_exist & MS_EXIST)
137 card_exist = MS_EXIST;
138 else if (card_exist & SD_EXIST)
139 card_exist = SD_EXIST;
140 else
141 card_exist = 0;
142
143 rtsx_pci_write_register(pcr, CARD_PWR_CTL,
144 BPP_POWER_MASK, BPP_POWER_OFF);
145
146 dev_dbg(&(pcr->pci->dev),
147 "After CD deglitch, card_exist = 0x%x\n",
148 card_exist);
149 }
150
151 if (card_exist & MS_EXIST) {
152 /* Disable SD interrupt */
153 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x40);
154 rtsx_pci_write_register(pcr, CD_PAD_CTL,
155 CD_DISABLE_MASK, MS_CD_EN_ONLY);
156 } else if (card_exist & SD_EXIST) {
157 /* Disable MS interrupt */
158 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x80);
159 rtsx_pci_write_register(pcr, CD_PAD_CTL,
160 CD_DISABLE_MASK, SD_CD_EN_ONLY);
161 }
162
163 return card_exist;
164}
165
166static const struct pcr_ops rtl8411_pcr_ops = {
167 .extra_init_hw = rtl8411_extra_init_hw,
168 .optimize_phy = NULL,
169 .turn_on_led = rtl8411_turn_on_led,
170 .turn_off_led = rtl8411_turn_off_led,
171 .enable_auto_blink = rtl8411_enable_auto_blink,
172 .disable_auto_blink = rtl8411_disable_auto_blink,
173 .card_power_on = rtl8411_card_power_on,
174 .card_power_off = rtl8411_card_power_off,
175 .cd_deglitch = rtl8411_cd_deglitch,
176};
177
178/* SD Pull Control Enable:
179 * SD_DAT[3:0] ==> pull up
180 * SD_CD ==> pull up
181 * SD_WP ==> pull up
182 * SD_CMD ==> pull up
183 * SD_CLK ==> pull down
184 */
185static const u32 rtl8411_sd_pull_ctl_enable_tbl[] = {
186 RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
187 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
188 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xA9),
189 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
190 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x09),
191 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
192 0,
193};
194
195/* SD Pull Control Disable:
196 * SD_DAT[3:0] ==> pull down
197 * SD_CD ==> pull up
198 * SD_WP ==> pull down
199 * SD_CMD ==> pull down
200 * SD_CLK ==> pull down
201 */
202static const u32 rtl8411_sd_pull_ctl_disable_tbl[] = {
203 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
204 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
205 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
206 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
207 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
208 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
209 0,
210};
211
212/* MS Pull Control Enable:
213 * MS CD ==> pull up
214 * others ==> pull down
215 */
216static const u32 rtl8411_ms_pull_ctl_enable_tbl[] = {
217 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
218 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
219 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
220 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05),
221 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
222 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
223 0,
224};
225
226/* MS Pull Control Disable:
227 * MS CD ==> pull up
228 * others ==> pull down
229 */
230static const u32 rtl8411_ms_pull_ctl_disable_tbl[] = {
231 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
232 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
233 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
234 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
235 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
236 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
237 0,
238};
239
240void rtl8411_init_params(struct rtsx_pcr *pcr)
241{
242 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
243 pcr->num_slots = 2;
244 pcr->ops = &rtl8411_pcr_ops;
245
246 pcr->ic_version = rtl8411_get_ic_version(pcr);
247 pcr->sd_pull_ctl_enable_tbl = rtl8411_sd_pull_ctl_enable_tbl;
248 pcr->sd_pull_ctl_disable_tbl = rtl8411_sd_pull_ctl_disable_tbl;
249 pcr->ms_pull_ctl_enable_tbl = rtl8411_ms_pull_ctl_enable_tbl;
250 pcr->ms_pull_ctl_disable_tbl = rtl8411_ms_pull_ctl_disable_tbl;
251}
diff --git a/drivers/mfd/rts5209.c b/drivers/mfd/rts5209.c
new file mode 100644
index 000000000000..283a4f148084
--- /dev/null
+++ b/drivers/mfd/rts5209.c
@@ -0,0 +1,223 @@
1/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#include <linux/module.h>
24#include <linux/delay.h>
25#include <linux/mfd/rtsx_pci.h>
26
27#include "rtsx_pcr.h"
28
29static u8 rts5209_get_ic_version(struct rtsx_pcr *pcr)
30{
31 u8 val;
32
33 val = rtsx_pci_readb(pcr, 0x1C);
34 return val & 0x0F;
35}
36
37static void rts5209_init_vendor_cfg(struct rtsx_pcr *pcr)
38{
39 u32 val;
40
41 rtsx_pci_read_config_dword(pcr, 0x724, &val);
42 dev_dbg(&(pcr->pci->dev), "Cfg 0x724: 0x%x\n", val);
43
44 if (!(val & 0x80)) {
45 if (val & 0x08)
46 pcr->ms_pmos = false;
47 else
48 pcr->ms_pmos = true;
49 }
50}
51
52static int rts5209_extra_init_hw(struct rtsx_pcr *pcr)
53{
54 rtsx_pci_init_cmd(pcr);
55
56 /* Turn off LED */
57 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO, 0xFF, 0x03);
58 /* Configure GPIO as output */
59 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO_DIR, 0xFF, 0x03);
60
61 return rtsx_pci_send_cmd(pcr, 100);
62}
63
64static int rts5209_optimize_phy(struct rtsx_pcr *pcr)
65{
66 return rtsx_pci_write_phy_register(pcr, 0x00, 0xB966);
67}
68
69static int rts5209_turn_on_led(struct rtsx_pcr *pcr)
70{
71 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00);
72}
73
74static int rts5209_turn_off_led(struct rtsx_pcr *pcr)
75{
76 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01);
77}
78
79static int rts5209_enable_auto_blink(struct rtsx_pcr *pcr)
80{
81 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D);
82}
83
84static int rts5209_disable_auto_blink(struct rtsx_pcr *pcr)
85{
86 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00);
87}
88
89static int rts5209_card_power_on(struct rtsx_pcr *pcr, int card)
90{
91 int err;
92 u8 pwr_mask, partial_pwr_on, pwr_on;
93
94 pwr_mask = SD_POWER_MASK;
95 partial_pwr_on = SD_PARTIAL_POWER_ON;
96 pwr_on = SD_POWER_ON;
97
98 if (pcr->ms_pmos && (card == RTSX_MS_CARD)) {
99 pwr_mask = MS_POWER_MASK;
100 partial_pwr_on = MS_PARTIAL_POWER_ON;
101 pwr_on = MS_POWER_ON;
102 }
103
104 rtsx_pci_init_cmd(pcr);
105 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
106 pwr_mask, partial_pwr_on);
107 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
108 LDO3318_PWR_MASK, 0x04);
109 err = rtsx_pci_send_cmd(pcr, 100);
110 if (err < 0)
111 return err;
112
113 /* To avoid too large in-rush current */
114 udelay(150);
115
116 rtsx_pci_init_cmd(pcr);
117 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, pwr_mask, pwr_on);
118 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
119 LDO3318_PWR_MASK, 0x00);
120 err = rtsx_pci_send_cmd(pcr, 100);
121 if (err < 0)
122 return err;
123
124 return 0;
125}
126
127static int rts5209_card_power_off(struct rtsx_pcr *pcr, int card)
128{
129 u8 pwr_mask, pwr_off;
130
131 pwr_mask = SD_POWER_MASK;
132 pwr_off = SD_POWER_OFF;
133
134 if (pcr->ms_pmos && (card == RTSX_MS_CARD)) {
135 pwr_mask = MS_POWER_MASK;
136 pwr_off = MS_POWER_OFF;
137 }
138
139 rtsx_pci_init_cmd(pcr);
140 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
141 pwr_mask | PMOS_STRG_MASK, pwr_off | PMOS_STRG_400mA);
142 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
143 LDO3318_PWR_MASK, 0X06);
144 return rtsx_pci_send_cmd(pcr, 100);
145}
146
147static const struct pcr_ops rts5209_pcr_ops = {
148 .extra_init_hw = rts5209_extra_init_hw,
149 .optimize_phy = rts5209_optimize_phy,
150 .turn_on_led = rts5209_turn_on_led,
151 .turn_off_led = rts5209_turn_off_led,
152 .enable_auto_blink = rts5209_enable_auto_blink,
153 .disable_auto_blink = rts5209_disable_auto_blink,
154 .card_power_on = rts5209_card_power_on,
155 .card_power_off = rts5209_card_power_off,
156 .cd_deglitch = NULL,
157};
158
159/* SD Pull Control Enable:
160 * SD_DAT[3:0] ==> pull up
161 * SD_CD ==> pull up
162 * SD_WP ==> pull up
163 * SD_CMD ==> pull up
164 * SD_CLK ==> pull down
165 */
166static const u32 rts5209_sd_pull_ctl_enable_tbl[] = {
167 RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
168 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
169 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
170 0,
171};
172
173/* SD Pull Control Disable:
174 * SD_DAT[3:0] ==> pull down
175 * SD_CD ==> pull up
176 * SD_WP ==> pull down
177 * SD_CMD ==> pull down
178 * SD_CLK ==> pull down
179 */
180static const u32 rts5209_sd_pull_ctl_disable_tbl[] = {
181 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x55),
182 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
183 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
184 0,
185};
186
187/* MS Pull Control Enable:
188 * MS CD ==> pull up
189 * others ==> pull down
190 */
191static const u32 rts5209_ms_pull_ctl_enable_tbl[] = {
192 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
193 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
194 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
195 0,
196};
197
198/* MS Pull Control Disable:
199 * MS CD ==> pull up
200 * others ==> pull down
201 */
202static const u32 rts5209_ms_pull_ctl_disable_tbl[] = {
203 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
204 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
205 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
206 0,
207};
208
209void rts5209_init_params(struct rtsx_pcr *pcr)
210{
211 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 |
212 EXTRA_CAPS_SD_SDR104 | EXTRA_CAPS_MMC_8BIT;
213 pcr->num_slots = 2;
214 pcr->ops = &rts5209_pcr_ops;
215
216 rts5209_init_vendor_cfg(pcr);
217
218 pcr->ic_version = rts5209_get_ic_version(pcr);
219 pcr->sd_pull_ctl_enable_tbl = rts5209_sd_pull_ctl_enable_tbl;
220 pcr->sd_pull_ctl_disable_tbl = rts5209_sd_pull_ctl_disable_tbl;
221 pcr->ms_pull_ctl_enable_tbl = rts5209_ms_pull_ctl_enable_tbl;
222 pcr->ms_pull_ctl_disable_tbl = rts5209_ms_pull_ctl_disable_tbl;
223}
diff --git a/drivers/mfd/rts5229.c b/drivers/mfd/rts5229.c
new file mode 100644
index 000000000000..b9dbab266fda
--- /dev/null
+++ b/drivers/mfd/rts5229.c
@@ -0,0 +1,205 @@
1/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#include <linux/module.h>
24#include <linux/delay.h>
25#include <linux/mfd/rtsx_pci.h>
26
27#include "rtsx_pcr.h"
28
29static u8 rts5229_get_ic_version(struct rtsx_pcr *pcr)
30{
31 u8 val;
32
33 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
34 return val & 0x0F;
35}
36
37static int rts5229_extra_init_hw(struct rtsx_pcr *pcr)
38{
39 rtsx_pci_init_cmd(pcr);
40
41 /* Configure GPIO as output */
42 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
43 /* Switch LDO3318 source from DV33 to card_3v3 */
44 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
45 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
46 /* LED shine disabled, set initial shine cycle period */
47 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
48
49 return rtsx_pci_send_cmd(pcr, 100);
50}
51
52static int rts5229_optimize_phy(struct rtsx_pcr *pcr)
53{
54 /* Optimize RX sensitivity */
55 return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
56}
57
58static int rts5229_turn_on_led(struct rtsx_pcr *pcr)
59{
60 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
61}
62
63static int rts5229_turn_off_led(struct rtsx_pcr *pcr)
64{
65 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
66}
67
68static int rts5229_enable_auto_blink(struct rtsx_pcr *pcr)
69{
70 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
71}
72
73static int rts5229_disable_auto_blink(struct rtsx_pcr *pcr)
74{
75 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
76}
77
78static int rts5229_card_power_on(struct rtsx_pcr *pcr, int card)
79{
80 int err;
81
82 rtsx_pci_init_cmd(pcr);
83 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
84 SD_POWER_MASK, SD_PARTIAL_POWER_ON);
85 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
86 LDO3318_PWR_MASK, 0x02);
87 err = rtsx_pci_send_cmd(pcr, 100);
88 if (err < 0)
89 return err;
90
91 /* To avoid too large in-rush current */
92 udelay(150);
93
94 rtsx_pci_init_cmd(pcr);
95 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
96 SD_POWER_MASK, SD_POWER_ON);
97 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
98 LDO3318_PWR_MASK, 0x06);
99 err = rtsx_pci_send_cmd(pcr, 100);
100 if (err < 0)
101 return err;
102
103 return 0;
104}
105
106static int rts5229_card_power_off(struct rtsx_pcr *pcr, int card)
107{
108 rtsx_pci_init_cmd(pcr);
109 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
110 SD_POWER_MASK | PMOS_STRG_MASK,
111 SD_POWER_OFF | PMOS_STRG_400mA);
112 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
113 LDO3318_PWR_MASK, 0X00);
114 return rtsx_pci_send_cmd(pcr, 100);
115}
116
117static const struct pcr_ops rts5229_pcr_ops = {
118 .extra_init_hw = rts5229_extra_init_hw,
119 .optimize_phy = rts5229_optimize_phy,
120 .turn_on_led = rts5229_turn_on_led,
121 .turn_off_led = rts5229_turn_off_led,
122 .enable_auto_blink = rts5229_enable_auto_blink,
123 .disable_auto_blink = rts5229_disable_auto_blink,
124 .card_power_on = rts5229_card_power_on,
125 .card_power_off = rts5229_card_power_off,
126 .cd_deglitch = NULL,
127};
128
129/* SD Pull Control Enable:
130 * SD_DAT[3:0] ==> pull up
131 * SD_CD ==> pull up
132 * SD_WP ==> pull up
133 * SD_CMD ==> pull up
134 * SD_CLK ==> pull down
135 */
136static const u32 rts5229_sd_pull_ctl_enable_tbl1[] = {
137 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
138 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
139 0,
140};
141
142/* For RTS5229 version C */
143static const u32 rts5229_sd_pull_ctl_enable_tbl2[] = {
144 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
145 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD9),
146 0,
147};
148
149/* SD Pull Control Disable:
150 * SD_DAT[3:0] ==> pull down
151 * SD_CD ==> pull up
152 * SD_WP ==> pull down
153 * SD_CMD ==> pull down
154 * SD_CLK ==> pull down
155 */
156static const u32 rts5229_sd_pull_ctl_disable_tbl1[] = {
157 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
158 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
159 0,
160};
161
162/* For RTS5229 version C */
163static const u32 rts5229_sd_pull_ctl_disable_tbl2[] = {
164 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
165 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE5),
166 0,
167};
168
169/* MS Pull Control Enable:
170 * MS CD ==> pull up
171 * others ==> pull down
172 */
173static const u32 rts5229_ms_pull_ctl_enable_tbl[] = {
174 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
175 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
176 0,
177};
178
179/* MS Pull Control Disable:
180 * MS CD ==> pull up
181 * others ==> pull down
182 */
183static const u32 rts5229_ms_pull_ctl_disable_tbl[] = {
184 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
185 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
186 0,
187};
188
189void rts5229_init_params(struct rtsx_pcr *pcr)
190{
191 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
192 pcr->num_slots = 2;
193 pcr->ops = &rts5229_pcr_ops;
194
195 pcr->ic_version = rts5229_get_ic_version(pcr);
196 if (pcr->ic_version == IC_VER_C) {
197 pcr->sd_pull_ctl_enable_tbl = rts5229_sd_pull_ctl_enable_tbl2;
198 pcr->sd_pull_ctl_disable_tbl = rts5229_sd_pull_ctl_disable_tbl2;
199 } else {
200 pcr->sd_pull_ctl_enable_tbl = rts5229_sd_pull_ctl_enable_tbl1;
201 pcr->sd_pull_ctl_disable_tbl = rts5229_sd_pull_ctl_disable_tbl1;
202 }
203 pcr->ms_pull_ctl_enable_tbl = rts5229_ms_pull_ctl_enable_tbl;
204 pcr->ms_pull_ctl_disable_tbl = rts5229_ms_pull_ctl_disable_tbl;
205}
diff --git a/drivers/mfd/rtsx_pcr.c b/drivers/mfd/rtsx_pcr.c
new file mode 100644
index 000000000000..56d4377c62c2
--- /dev/null
+++ b/drivers/mfd/rtsx_pcr.c
@@ -0,0 +1,1251 @@
1/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#include <linux/pci.h>
24#include <linux/module.h>
25#include <linux/dma-mapping.h>
26#include <linux/highmem.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/idr.h>
30#include <linux/platform_device.h>
31#include <linux/mfd/core.h>
32#include <linux/mfd/rtsx_pci.h>
33#include <asm/unaligned.h>
34
35#include "rtsx_pcr.h"
36
37static bool msi_en = true;
38module_param(msi_en, bool, S_IRUGO | S_IWUSR);
39MODULE_PARM_DESC(msi_en, "Enable MSI");
40
41static DEFINE_IDR(rtsx_pci_idr);
42static DEFINE_SPINLOCK(rtsx_pci_lock);
43
44static struct mfd_cell rtsx_pcr_cells[] = {
45 [RTSX_SD_CARD] = {
46 .name = DRV_NAME_RTSX_PCI_SDMMC,
47 },
48 [RTSX_MS_CARD] = {
49 .name = DRV_NAME_RTSX_PCI_MS,
50 },
51};
52
53static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids) = {
54 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
55 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
57 { 0, }
58};
59
60MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
61
62void rtsx_pci_start_run(struct rtsx_pcr *pcr)
63{
64 /* If pci device removed, don't queue idle work any more */
65 if (pcr->remove_pci)
66 return;
67
68 if (pcr->state != PDEV_STAT_RUN) {
69 pcr->state = PDEV_STAT_RUN;
70 if (pcr->ops->enable_auto_blink)
71 pcr->ops->enable_auto_blink(pcr);
72 }
73
74 mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
75}
76EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
77
78int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
79{
80 int i;
81 u32 val = HAIMR_WRITE_START;
82
83 val |= (u32)(addr & 0x3FFF) << 16;
84 val |= (u32)mask << 8;
85 val |= (u32)data;
86
87 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
88
89 for (i = 0; i < MAX_RW_REG_CNT; i++) {
90 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
91 if ((val & HAIMR_TRANS_END) == 0) {
92 if (data != (u8)val)
93 return -EIO;
94 return 0;
95 }
96 }
97
98 return -ETIMEDOUT;
99}
100EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
101
102int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
103{
104 u32 val = HAIMR_READ_START;
105 int i;
106
107 val |= (u32)(addr & 0x3FFF) << 16;
108 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
109
110 for (i = 0; i < MAX_RW_REG_CNT; i++) {
111 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
112 if ((val & HAIMR_TRANS_END) == 0)
113 break;
114 }
115
116 if (i >= MAX_RW_REG_CNT)
117 return -ETIMEDOUT;
118
119 if (data)
120 *data = (u8)(val & 0xFF);
121
122 return 0;
123}
124EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
125
126int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
127{
128 int err, i, finished = 0;
129 u8 tmp;
130
131 rtsx_pci_init_cmd(pcr);
132
133 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
134 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
135 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
136 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
137
138 err = rtsx_pci_send_cmd(pcr, 100);
139 if (err < 0)
140 return err;
141
142 for (i = 0; i < 100000; i++) {
143 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
144 if (err < 0)
145 return err;
146
147 if (!(tmp & 0x80)) {
148 finished = 1;
149 break;
150 }
151 }
152
153 if (!finished)
154 return -ETIMEDOUT;
155
156 return 0;
157}
158EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
159
160int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
161{
162 int err, i, finished = 0;
163 u16 data;
164 u8 *ptr, tmp;
165
166 rtsx_pci_init_cmd(pcr);
167
168 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
169 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
170
171 err = rtsx_pci_send_cmd(pcr, 100);
172 if (err < 0)
173 return err;
174
175 for (i = 0; i < 100000; i++) {
176 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
177 if (err < 0)
178 return err;
179
180 if (!(tmp & 0x80)) {
181 finished = 1;
182 break;
183 }
184 }
185
186 if (!finished)
187 return -ETIMEDOUT;
188
189 rtsx_pci_init_cmd(pcr);
190
191 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
192 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
193
194 err = rtsx_pci_send_cmd(pcr, 100);
195 if (err < 0)
196 return err;
197
198 ptr = rtsx_pci_get_cmd_data(pcr);
199 data = ((u16)ptr[1] << 8) | ptr[0];
200
201 if (val)
202 *val = data;
203
204 return 0;
205}
206EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
207
208void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
209{
210 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
211 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
212
213 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
214 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
215}
216EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
217
218void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
219 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
220{
221 unsigned long flags;
222 u32 val = 0;
223 u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
224
225 val |= (u32)(cmd_type & 0x03) << 30;
226 val |= (u32)(reg_addr & 0x3FFF) << 16;
227 val |= (u32)mask << 8;
228 val |= (u32)data;
229
230 spin_lock_irqsave(&pcr->lock, flags);
231 ptr += pcr->ci;
232 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
233 put_unaligned_le32(val, ptr);
234 ptr++;
235 pcr->ci++;
236 }
237 spin_unlock_irqrestore(&pcr->lock, flags);
238}
239EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
240
241void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
242{
243 u32 val = 1 << 31;
244
245 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
246
247 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
248 /* Hardware Auto Response */
249 val |= 0x40000000;
250 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
251}
252EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
253
254int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
255{
256 struct completion trans_done;
257 u32 val = 1 << 31;
258 long timeleft;
259 unsigned long flags;
260 int err = 0;
261
262 spin_lock_irqsave(&pcr->lock, flags);
263
264 /* set up data structures for the wakeup system */
265 pcr->done = &trans_done;
266 pcr->trans_result = TRANS_NOT_READY;
267 init_completion(&trans_done);
268
269 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
270
271 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
272 /* Hardware Auto Response */
273 val |= 0x40000000;
274 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
275
276 spin_unlock_irqrestore(&pcr->lock, flags);
277
278 /* Wait for TRANS_OK_INT */
279 timeleft = wait_for_completion_interruptible_timeout(
280 &trans_done, msecs_to_jiffies(timeout));
281 if (timeleft <= 0) {
282 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
283 __func__, __LINE__);
284 err = -ETIMEDOUT;
285 goto finish_send_cmd;
286 }
287
288 spin_lock_irqsave(&pcr->lock, flags);
289 if (pcr->trans_result == TRANS_RESULT_FAIL)
290 err = -EINVAL;
291 else if (pcr->trans_result == TRANS_RESULT_OK)
292 err = 0;
293 else if (pcr->trans_result == TRANS_NO_DEVICE)
294 err = -ENODEV;
295 spin_unlock_irqrestore(&pcr->lock, flags);
296
297finish_send_cmd:
298 spin_lock_irqsave(&pcr->lock, flags);
299 pcr->done = NULL;
300 spin_unlock_irqrestore(&pcr->lock, flags);
301
302 if ((err < 0) && (err != -ENODEV))
303 rtsx_pci_stop_cmd(pcr);
304
305 if (pcr->finish_me)
306 complete(pcr->finish_me);
307
308 return err;
309}
310EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
311
312static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
313 dma_addr_t addr, unsigned int len, int end)
314{
315 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
316 u64 val;
317 u8 option = SG_VALID | SG_TRANS_DATA;
318
319 dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
320 (unsigned int)addr, len);
321
322 if (end)
323 option |= SG_END;
324 val = ((u64)addr << 32) | ((u64)len << 12) | option;
325
326 put_unaligned_le64(val, ptr);
327 ptr++;
328 pcr->sgi++;
329}
330
331int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
332 int num_sg, bool read, int timeout)
333{
334 struct completion trans_done;
335 u8 dir;
336 int err = 0, i, count;
337 long timeleft;
338 unsigned long flags;
339 struct scatterlist *sg;
340 enum dma_data_direction dma_dir;
341 u32 val;
342 dma_addr_t addr;
343 unsigned int len;
344
345 dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg);
346
347 /* don't transfer data during abort processing */
348 if (pcr->remove_pci)
349 return -EINVAL;
350
351 if ((sglist == NULL) || (num_sg <= 0))
352 return -EINVAL;
353
354 if (read) {
355 dir = DEVICE_TO_HOST;
356 dma_dir = DMA_FROM_DEVICE;
357 } else {
358 dir = HOST_TO_DEVICE;
359 dma_dir = DMA_TO_DEVICE;
360 }
361
362 count = dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
363 if (count < 1) {
364 dev_err(&(pcr->pci->dev), "scatterlist map failed\n");
365 return -EINVAL;
366 }
367 dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
368
369 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
370 pcr->sgi = 0;
371 for_each_sg(sglist, sg, count, i) {
372 addr = sg_dma_address(sg);
373 len = sg_dma_len(sg);
374 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
375 }
376
377 spin_lock_irqsave(&pcr->lock, flags);
378
379 pcr->done = &trans_done;
380 pcr->trans_result = TRANS_NOT_READY;
381 init_completion(&trans_done);
382 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
383 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
384
385 spin_unlock_irqrestore(&pcr->lock, flags);
386
387 timeleft = wait_for_completion_interruptible_timeout(
388 &trans_done, msecs_to_jiffies(timeout));
389 if (timeleft <= 0) {
390 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
391 __func__, __LINE__);
392 err = -ETIMEDOUT;
393 goto out;
394 }
395
396 spin_lock_irqsave(&pcr->lock, flags);
397
398 if (pcr->trans_result == TRANS_RESULT_FAIL)
399 err = -EINVAL;
400 else if (pcr->trans_result == TRANS_NO_DEVICE)
401 err = -ENODEV;
402
403 spin_unlock_irqrestore(&pcr->lock, flags);
404
405out:
406 spin_lock_irqsave(&pcr->lock, flags);
407 pcr->done = NULL;
408 spin_unlock_irqrestore(&pcr->lock, flags);
409
410 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
411
412 if ((err < 0) && (err != -ENODEV))
413 rtsx_pci_stop_cmd(pcr);
414
415 if (pcr->finish_me)
416 complete(pcr->finish_me);
417
418 return err;
419}
420EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
421
422int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
423{
424 int err;
425 int i, j;
426 u16 reg;
427 u8 *ptr;
428
429 if (buf_len > 512)
430 buf_len = 512;
431
432 ptr = buf;
433 reg = PPBUF_BASE2;
434 for (i = 0; i < buf_len / 256; i++) {
435 rtsx_pci_init_cmd(pcr);
436
437 for (j = 0; j < 256; j++)
438 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
439
440 err = rtsx_pci_send_cmd(pcr, 250);
441 if (err < 0)
442 return err;
443
444 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
445 ptr += 256;
446 }
447
448 if (buf_len % 256) {
449 rtsx_pci_init_cmd(pcr);
450
451 for (j = 0; j < buf_len % 256; j++)
452 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
453
454 err = rtsx_pci_send_cmd(pcr, 250);
455 if (err < 0)
456 return err;
457 }
458
459 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
460
461 return 0;
462}
463EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
464
465int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
466{
467 int err;
468 int i, j;
469 u16 reg;
470 u8 *ptr;
471
472 if (buf_len > 512)
473 buf_len = 512;
474
475 ptr = buf;
476 reg = PPBUF_BASE2;
477 for (i = 0; i < buf_len / 256; i++) {
478 rtsx_pci_init_cmd(pcr);
479
480 for (j = 0; j < 256; j++) {
481 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
482 reg++, 0xFF, *ptr);
483 ptr++;
484 }
485
486 err = rtsx_pci_send_cmd(pcr, 250);
487 if (err < 0)
488 return err;
489 }
490
491 if (buf_len % 256) {
492 rtsx_pci_init_cmd(pcr);
493
494 for (j = 0; j < buf_len % 256; j++) {
495 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
496 reg++, 0xFF, *ptr);
497 ptr++;
498 }
499
500 err = rtsx_pci_send_cmd(pcr, 250);
501 if (err < 0)
502 return err;
503 }
504
505 return 0;
506}
507EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
508
509static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
510{
511 int err;
512
513 rtsx_pci_init_cmd(pcr);
514
515 while (*tbl & 0xFFFF0000) {
516 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
517 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
518 tbl++;
519 }
520
521 err = rtsx_pci_send_cmd(pcr, 100);
522 if (err < 0)
523 return err;
524
525 return 0;
526}
527
528int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
529{
530 const u32 *tbl;
531
532 if (card == RTSX_SD_CARD)
533 tbl = pcr->sd_pull_ctl_enable_tbl;
534 else if (card == RTSX_MS_CARD)
535 tbl = pcr->ms_pull_ctl_enable_tbl;
536 else
537 return -EINVAL;
538
539 return rtsx_pci_set_pull_ctl(pcr, tbl);
540}
541EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
542
543int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
544{
545 const u32 *tbl;
546
547 if (card == RTSX_SD_CARD)
548 tbl = pcr->sd_pull_ctl_disable_tbl;
549 else if (card == RTSX_MS_CARD)
550 tbl = pcr->ms_pull_ctl_disable_tbl;
551 else
552 return -EINVAL;
553
554
555 return rtsx_pci_set_pull_ctl(pcr, tbl);
556}
557EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
558
559static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
560{
561 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
562
563 if (pcr->num_slots > 1)
564 pcr->bier |= MS_INT_EN;
565
566 /* Enable Bus Interrupt */
567 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
568
569 dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
570}
571
572static inline u8 double_ssc_depth(u8 depth)
573{
574 return ((depth > 1) ? (depth - 1) : depth);
575}
576
577static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
578{
579 if (div > CLK_DIV_1) {
580 if (ssc_depth > (div - 1))
581 ssc_depth -= (div - 1);
582 else
583 ssc_depth = SSC_DEPTH_4M;
584 }
585
586 return ssc_depth;
587}
588
589int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
590 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
591{
592 int err, clk;
593 u8 N, min_N, max_N, clk_divider;
594 u8 mcu_cnt, div, max_div;
595 u8 depth[] = {
596 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
597 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
598 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
599 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
600 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
601 };
602
603 if (initial_mode) {
604 /* We use 250k(around) here, in initial stage */
605 clk_divider = SD_CLK_DIVIDE_128;
606 card_clock = 30000000;
607 } else {
608 clk_divider = SD_CLK_DIVIDE_0;
609 }
610 err = rtsx_pci_write_register(pcr, SD_CFG1,
611 SD_CLK_DIVIDE_MASK, clk_divider);
612 if (err < 0)
613 return err;
614
615 card_clock /= 1000000;
616 dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
617
618 min_N = 80;
619 max_N = 208;
620 max_div = CLK_DIV_8;
621
622 clk = card_clock;
623 if (!initial_mode && double_clk)
624 clk = card_clock * 2;
625 dev_dbg(&(pcr->pci->dev),
626 "Internal SSC clock: %dMHz (cur_clock = %d)\n",
627 clk, pcr->cur_clock);
628
629 if (clk == pcr->cur_clock)
630 return 0;
631
632 N = (u8)(clk - 2);
633 if ((clk <= 2) || (N > max_N))
634 return -EINVAL;
635
636 mcu_cnt = (u8)(125/clk + 3);
637 if (mcu_cnt > 15)
638 mcu_cnt = 15;
639
640 /* Make sure that the SSC clock div_n is equal or greater than min_N */
641 div = CLK_DIV_1;
642 while ((N < min_N) && (div < max_div)) {
643 N = (N + 2) * 2 - 2;
644 div++;
645 }
646 dev_dbg(&(pcr->pci->dev), "N = %d, div = %d\n", N, div);
647
648 ssc_depth = depth[ssc_depth];
649 if (double_clk)
650 ssc_depth = double_ssc_depth(ssc_depth);
651
652 ssc_depth = revise_ssc_depth(ssc_depth, div);
653 dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
654
655 rtsx_pci_init_cmd(pcr);
656 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
657 CLK_LOW_FREQ, CLK_LOW_FREQ);
658 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
659 0xFF, (div << 4) | mcu_cnt);
660 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
661 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
662 SSC_DEPTH_MASK, ssc_depth);
663 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N);
664 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
665 if (vpclk) {
666 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
667 PHASE_NOT_RESET, 0);
668 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
669 PHASE_NOT_RESET, PHASE_NOT_RESET);
670 }
671
672 err = rtsx_pci_send_cmd(pcr, 2000);
673 if (err < 0)
674 return err;
675
676 /* Wait SSC clock stable */
677 udelay(10);
678 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
679 if (err < 0)
680 return err;
681
682 pcr->cur_clock = clk;
683 return 0;
684}
685EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
686
687int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
688{
689 if (pcr->ops->card_power_on)
690 return pcr->ops->card_power_on(pcr, card);
691
692 return 0;
693}
694EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
695
696int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
697{
698 if (pcr->ops->card_power_off)
699 return pcr->ops->card_power_off(pcr, card);
700
701 return 0;
702}
703EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
704
705unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
706{
707 unsigned int val;
708
709 val = rtsx_pci_readl(pcr, RTSX_BIPR);
710 if (pcr->ops->cd_deglitch)
711 val = pcr->ops->cd_deglitch(pcr);
712
713 return val;
714}
715EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
716
717void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
718{
719 struct completion finish;
720
721 pcr->finish_me = &finish;
722 init_completion(&finish);
723
724 if (pcr->done)
725 complete(pcr->done);
726
727 if (!pcr->remove_pci)
728 rtsx_pci_stop_cmd(pcr);
729
730 wait_for_completion_interruptible_timeout(&finish,
731 msecs_to_jiffies(2));
732 pcr->finish_me = NULL;
733}
734EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
735
736static void rtsx_pci_card_detect(struct work_struct *work)
737{
738 struct delayed_work *dwork;
739 struct rtsx_pcr *pcr;
740 unsigned long flags;
741 unsigned int card_detect = 0;
742 u32 irq_status;
743
744 dwork = to_delayed_work(work);
745 pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
746
747 dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
748
749 spin_lock_irqsave(&pcr->lock, flags);
750
751 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
752 dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
753
754 if (pcr->card_inserted || pcr->card_removed) {
755 dev_dbg(&(pcr->pci->dev),
756 "card_inserted: 0x%x, card_removed: 0x%x\n",
757 pcr->card_inserted, pcr->card_removed);
758
759 if (pcr->ops->cd_deglitch)
760 pcr->card_inserted = pcr->ops->cd_deglitch(pcr);
761
762 card_detect = pcr->card_inserted | pcr->card_removed;
763 pcr->card_inserted = 0;
764 pcr->card_removed = 0;
765 }
766
767 spin_unlock_irqrestore(&pcr->lock, flags);
768
769 if (card_detect & SD_EXIST)
770 pcr->slots[RTSX_SD_CARD].card_event(
771 pcr->slots[RTSX_SD_CARD].p_dev);
772 if (card_detect & MS_EXIST)
773 pcr->slots[RTSX_MS_CARD].card_event(
774 pcr->slots[RTSX_MS_CARD].p_dev);
775}
776
777static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
778{
779 struct rtsx_pcr *pcr = dev_id;
780 u32 int_reg;
781
782 if (!pcr)
783 return IRQ_NONE;
784
785 spin_lock(&pcr->lock);
786
787 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
788 /* Clear interrupt flag */
789 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
790 if ((int_reg & pcr->bier) == 0) {
791 spin_unlock(&pcr->lock);
792 return IRQ_NONE;
793 }
794 if (int_reg == 0xFFFFFFFF) {
795 spin_unlock(&pcr->lock);
796 return IRQ_HANDLED;
797 }
798
799 int_reg &= (pcr->bier | 0x7FFFFF);
800
801 if (int_reg & SD_INT) {
802 if (int_reg & SD_EXIST) {
803 pcr->card_inserted |= SD_EXIST;
804 } else {
805 pcr->card_removed |= SD_EXIST;
806 pcr->card_inserted &= ~SD_EXIST;
807 }
808 }
809
810 if (int_reg & MS_INT) {
811 if (int_reg & MS_EXIST) {
812 pcr->card_inserted |= MS_EXIST;
813 } else {
814 pcr->card_removed |= MS_EXIST;
815 pcr->card_inserted &= ~MS_EXIST;
816 }
817 }
818
819 if (pcr->card_inserted || pcr->card_removed)
820 schedule_delayed_work(&pcr->carddet_work,
821 msecs_to_jiffies(200));
822
823 if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
824 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
825 pcr->trans_result = TRANS_RESULT_FAIL;
826 if (pcr->done)
827 complete(pcr->done);
828 } else if (int_reg & TRANS_OK_INT) {
829 pcr->trans_result = TRANS_RESULT_OK;
830 if (pcr->done)
831 complete(pcr->done);
832 }
833 }
834
835 spin_unlock(&pcr->lock);
836 return IRQ_HANDLED;
837}
838
839static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
840{
841 dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
842 __func__, pcr->msi_en, pcr->pci->irq);
843
844 if (request_irq(pcr->pci->irq, rtsx_pci_isr,
845 pcr->msi_en ? 0 : IRQF_SHARED,
846 DRV_NAME_RTSX_PCI, pcr)) {
847 dev_err(&(pcr->pci->dev),
848 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
849 pcr->pci->irq);
850 return -1;
851 }
852
853 pcr->irq = pcr->pci->irq;
854 pci_intx(pcr->pci, !pcr->msi_en);
855
856 return 0;
857}
858
859static void rtsx_pci_idle_work(struct work_struct *work)
860{
861 struct delayed_work *dwork = to_delayed_work(work);
862 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
863
864 dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
865
866 mutex_lock(&pcr->pcr_mutex);
867
868 pcr->state = PDEV_STAT_IDLE;
869
870 if (pcr->ops->disable_auto_blink)
871 pcr->ops->disable_auto_blink(pcr);
872 if (pcr->ops->turn_off_led)
873 pcr->ops->turn_off_led(pcr);
874
875 mutex_unlock(&pcr->pcr_mutex);
876}
877
878static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
879{
880 int err;
881
882 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
883
884 rtsx_pci_enable_bus_int(pcr);
885
886 /* Power on SSC */
887 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
888 if (err < 0)
889 return err;
890
891 /* Wait SSC power stable */
892 udelay(200);
893
894 if (pcr->ops->optimize_phy) {
895 err = pcr->ops->optimize_phy(pcr);
896 if (err < 0)
897 return err;
898 }
899
900 rtsx_pci_init_cmd(pcr);
901
902 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
903 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
904
905 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
906 /* Disable card clock */
907 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
908 /* Reset ASPM state to default value */
909 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
910 /* Reset delink mode */
911 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
912 /* Card driving select */
913 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
914 0x07, DRIVER_TYPE_D);
915 /* Enable SSC Clock */
916 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
917 0xFF, SSC_8X_EN | SSC_SEL_4M);
918 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
919 /* Disable cd_pwr_save */
920 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
921 /* Clear Link Ready Interrupt */
922 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
923 LINK_RDY_INT, LINK_RDY_INT);
924 /* Enlarge the estimation window of PERST# glitch
925 * to reduce the chance of invalid card interrupt
926 */
927 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
928 /* Update RC oscillator to 400k
929 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
930 * 1: 2M 0: 400k
931 */
932 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
933 /* Set interrupt write clear
934 * bit 1: U_elbi_if_rd_clr_en
935 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
936 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
937 */
938 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
939 /* Force CLKREQ# PIN to drive 0 to request clock */
940 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
941
942 err = rtsx_pci_send_cmd(pcr, 100);
943 if (err < 0)
944 return err;
945
946 /* Enable clk_request_n to enable clock power management */
947 rtsx_pci_write_config_byte(pcr, 0x81, 1);
948 /* Enter L1 when host tx idle */
949 rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
950
951 if (pcr->ops->extra_init_hw) {
952 err = pcr->ops->extra_init_hw(pcr);
953 if (err < 0)
954 return err;
955 }
956
957 return 0;
958}
959
960static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
961{
962 int err;
963
964 spin_lock_init(&pcr->lock);
965 mutex_init(&pcr->pcr_mutex);
966
967 switch (PCI_PID(pcr)) {
968 default:
969 case 0x5209:
970 rts5209_init_params(pcr);
971 break;
972
973 case 0x5229:
974 rts5229_init_params(pcr);
975 break;
976
977 case 0x5289:
978 rtl8411_init_params(pcr);
979 break;
980 }
981
982 dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
983 PCI_PID(pcr), pcr->ic_version);
984
985 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
986 GFP_KERNEL);
987 if (!pcr->slots)
988 return -ENOMEM;
989
990 pcr->state = PDEV_STAT_IDLE;
991 err = rtsx_pci_init_hw(pcr);
992 if (err < 0) {
993 kfree(pcr->slots);
994 return err;
995 }
996
997 return 0;
998}
999
1000static int __devinit rtsx_pci_probe(struct pci_dev *pcidev,
1001 const struct pci_device_id *id)
1002{
1003 struct rtsx_pcr *pcr;
1004 struct pcr_handle *handle;
1005 u32 base, len;
1006 int ret, i;
1007
1008 dev_dbg(&(pcidev->dev),
1009 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1010 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1011 (int)pcidev->revision);
1012
1013 ret = pci_enable_device(pcidev);
1014 if (ret)
1015 return ret;
1016
1017 ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1018 if (ret)
1019 goto disable;
1020
1021 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1022 if (!pcr) {
1023 ret = -ENOMEM;
1024 goto release_pci;
1025 }
1026
1027 handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1028 if (!handle) {
1029 ret = -ENOMEM;
1030 goto free_pcr;
1031 }
1032 handle->pcr = pcr;
1033
1034 if (!idr_pre_get(&rtsx_pci_idr, GFP_KERNEL)) {
1035 ret = -ENOMEM;
1036 goto free_handle;
1037 }
1038
1039 spin_lock(&rtsx_pci_lock);
1040 ret = idr_get_new(&rtsx_pci_idr, pcr, &pcr->id);
1041 spin_unlock(&rtsx_pci_lock);
1042 if (ret)
1043 goto free_handle;
1044
1045 pcr->pci = pcidev;
1046 dev_set_drvdata(&pcidev->dev, handle);
1047
1048 len = pci_resource_len(pcidev, 0);
1049 base = pci_resource_start(pcidev, 0);
1050 pcr->remap_addr = ioremap_nocache(base, len);
1051 if (!pcr->remap_addr) {
1052 ret = -ENOMEM;
1053 goto free_host;
1054 }
1055
1056 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1057 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1058 GFP_KERNEL);
1059 if (pcr->rtsx_resv_buf == NULL) {
1060 ret = -ENXIO;
1061 goto unmap;
1062 }
1063 pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1064 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1065 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1066 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1067
1068 pcr->card_inserted = 0;
1069 pcr->card_removed = 0;
1070 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1071 INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1072
1073 pcr->msi_en = msi_en;
1074 if (pcr->msi_en) {
1075 ret = pci_enable_msi(pcidev);
1076 if (ret < 0)
1077 pcr->msi_en = false;
1078 }
1079
1080 ret = rtsx_pci_acquire_irq(pcr);
1081 if (ret < 0)
1082 goto free_dma;
1083
1084 pci_set_master(pcidev);
1085 synchronize_irq(pcr->irq);
1086
1087 ret = rtsx_pci_init_chip(pcr);
1088 if (ret < 0)
1089 goto disable_irq;
1090
1091 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1092 rtsx_pcr_cells[i].platform_data = handle;
1093 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1094 }
1095 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1096 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1097 if (ret < 0)
1098 goto disable_irq;
1099
1100 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1101
1102 return 0;
1103
1104disable_irq:
1105 free_irq(pcr->irq, (void *)pcr);
1106free_dma:
1107 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1108 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1109unmap:
1110 iounmap(pcr->remap_addr);
1111free_host:
1112 dev_set_drvdata(&pcidev->dev, NULL);
1113free_handle:
1114 kfree(handle);
1115free_pcr:
1116 kfree(pcr);
1117release_pci:
1118 pci_release_regions(pcidev);
1119disable:
1120 pci_disable_device(pcidev);
1121
1122 return ret;
1123}
1124
1125static void __devexit rtsx_pci_remove(struct pci_dev *pcidev)
1126{
1127 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1128 struct rtsx_pcr *pcr = handle->pcr;
1129
1130 pcr->remove_pci = true;
1131
1132 cancel_delayed_work(&pcr->carddet_work);
1133 cancel_delayed_work(&pcr->idle_work);
1134
1135 mfd_remove_devices(&pcidev->dev);
1136
1137 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1138 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1139 free_irq(pcr->irq, (void *)pcr);
1140 if (pcr->msi_en)
1141 pci_disable_msi(pcr->pci);
1142 iounmap(pcr->remap_addr);
1143
1144 dev_set_drvdata(&pcidev->dev, NULL);
1145 pci_release_regions(pcidev);
1146 pci_disable_device(pcidev);
1147
1148 spin_lock(&rtsx_pci_lock);
1149 idr_remove(&rtsx_pci_idr, pcr->id);
1150 spin_unlock(&rtsx_pci_lock);
1151
1152 kfree(pcr->slots);
1153 kfree(pcr);
1154 kfree(handle);
1155
1156 dev_dbg(&(pcidev->dev),
1157 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1158 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1159}
1160
1161#ifdef CONFIG_PM
1162
1163static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1164{
1165 struct pcr_handle *handle;
1166 struct rtsx_pcr *pcr;
1167 int ret = 0;
1168
1169 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1170
1171 handle = pci_get_drvdata(pcidev);
1172 pcr = handle->pcr;
1173
1174 cancel_delayed_work(&pcr->carddet_work);
1175 cancel_delayed_work(&pcr->idle_work);
1176
1177 mutex_lock(&pcr->pcr_mutex);
1178
1179 if (pcr->ops->turn_off_led)
1180 pcr->ops->turn_off_led(pcr);
1181
1182 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1183 pcr->bier = 0;
1184
1185 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1186 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x02);
1187
1188 pci_save_state(pcidev);
1189 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1190 pci_disable_device(pcidev);
1191 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1192
1193 mutex_unlock(&pcr->pcr_mutex);
1194 return ret;
1195}
1196
1197static int rtsx_pci_resume(struct pci_dev *pcidev)
1198{
1199 struct pcr_handle *handle;
1200 struct rtsx_pcr *pcr;
1201 int ret = 0;
1202
1203 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1204
1205 handle = pci_get_drvdata(pcidev);
1206 pcr = handle->pcr;
1207
1208 mutex_lock(&pcr->pcr_mutex);
1209
1210 pci_set_power_state(pcidev, PCI_D0);
1211 pci_restore_state(pcidev);
1212 ret = pci_enable_device(pcidev);
1213 if (ret)
1214 goto out;
1215 pci_set_master(pcidev);
1216
1217 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1218 if (ret)
1219 goto out;
1220
1221 ret = rtsx_pci_init_hw(pcr);
1222 if (ret)
1223 goto out;
1224
1225 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1226
1227out:
1228 mutex_unlock(&pcr->pcr_mutex);
1229 return ret;
1230}
1231
1232#else /* CONFIG_PM */
1233
1234#define rtsx_pci_suspend NULL
1235#define rtsx_pci_resume NULL
1236
1237#endif /* CONFIG_PM */
1238
1239static struct pci_driver rtsx_pci_driver = {
1240 .name = DRV_NAME_RTSX_PCI,
1241 .id_table = rtsx_pci_ids,
1242 .probe = rtsx_pci_probe,
1243 .remove = __devexit_p(rtsx_pci_remove),
1244 .suspend = rtsx_pci_suspend,
1245 .resume = rtsx_pci_resume,
1246};
1247module_pci_driver(rtsx_pci_driver);
1248
1249MODULE_LICENSE("GPL");
1250MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1251MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");
diff --git a/drivers/mfd/rtsx_pcr.h b/drivers/mfd/rtsx_pcr.h
new file mode 100644
index 000000000000..12462c1df1a9
--- /dev/null
+++ b/drivers/mfd/rtsx_pcr.h
@@ -0,0 +1,32 @@
1/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#ifndef __RTSX_PCR_H
24#define __RTSX_PCR_H
25
26#include <linux/mfd/rtsx_pci.h>
27
28void rts5209_init_params(struct rtsx_pcr *pcr);
29void rts5229_init_params(struct rtsx_pcr *pcr);
30void rtl8411_init_params(struct rtsx_pcr *pcr);
31
32#endif
diff --git a/include/linux/mfd/rtsx_common.h b/include/linux/mfd/rtsx_common.h
new file mode 100644
index 000000000000..a8d393e3066b
--- /dev/null
+++ b/include/linux/mfd/rtsx_common.h
@@ -0,0 +1,48 @@
1/* Driver for Realtek driver-based card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#ifndef __RTSX_COMMON_H
24#define __RTSX_COMMON_H
25
26#define DRV_NAME_RTSX_PCI "rtsx_pci"
27#define DRV_NAME_RTSX_PCI_SDMMC "rtsx_pci_sdmmc"
28#define DRV_NAME_RTSX_PCI_MS "rtsx_pci_ms"
29
30#define RTSX_REG_PAIR(addr, val) (((u32)(addr) << 16) | (u8)(val))
31
32#define RTSX_SSC_DEPTH_4M 0x01
33#define RTSX_SSC_DEPTH_2M 0x02
34#define RTSX_SSC_DEPTH_1M 0x03
35#define RTSX_SSC_DEPTH_500K 0x04
36#define RTSX_SSC_DEPTH_250K 0x05
37
38#define RTSX_SD_CARD 0
39#define RTSX_MS_CARD 1
40
41struct platform_device;
42
43struct rtsx_slot {
44 struct platform_device *p_dev;
45 void (*card_event)(struct platform_device *p_dev);
46};
47
48#endif
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
new file mode 100644
index 000000000000..060b721fcbfb
--- /dev/null
+++ b/include/linux/mfd/rtsx_pci.h
@@ -0,0 +1,794 @@
1/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#ifndef __RTSX_PCI_H
24#define __RTSX_PCI_H
25
26#include <linux/sched.h>
27#include <linux/pci.h>
28
29#include "rtsx_common.h"
30
31#define MAX_RW_REG_CNT 1024
32
33/* PCI Operation Register Address */
34#define RTSX_HCBAR 0x00
35#define RTSX_HCBCTLR 0x04
36#define RTSX_HDBAR 0x08
37#define RTSX_HDBCTLR 0x0C
38#define RTSX_HAIMR 0x10
39#define RTSX_BIPR 0x14
40#define RTSX_BIER 0x18
41
42/* Host command buffer control register */
43#define STOP_CMD (0x01 << 28)
44
45/* Host data buffer control register */
46#define SDMA_MODE 0x00
47#define ADMA_MODE (0x02 << 26)
48#define STOP_DMA (0x01 << 28)
49#define TRIG_DMA (0x01 << 31)
50
51/* Host access internal memory register */
52#define HAIMR_TRANS_START (0x01 << 31)
53#define HAIMR_READ 0x00
54#define HAIMR_WRITE (0x01 << 30)
55#define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ)
56#define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE)
57#define HAIMR_TRANS_END (HAIMR_TRANS_START)
58
59/* Bus interrupt pending register */
60#define CMD_DONE_INT (1 << 31)
61#define DATA_DONE_INT (1 << 30)
62#define TRANS_OK_INT (1 << 29)
63#define TRANS_FAIL_INT (1 << 28)
64#define XD_INT (1 << 27)
65#define MS_INT (1 << 26)
66#define SD_INT (1 << 25)
67#define GPIO0_INT (1 << 24)
68#define OC_INT (1 << 23)
69#define SD_WRITE_PROTECT (1 << 19)
70#define XD_EXIST (1 << 18)
71#define MS_EXIST (1 << 17)
72#define SD_EXIST (1 << 16)
73#define DELINK_INT GPIO0_INT
74#define MS_OC_INT (1 << 23)
75#define SD_OC_INT (1 << 22)
76
77#define CARD_INT (XD_INT | MS_INT | SD_INT)
78#define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
79#define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \
80 CARD_INT | GPIO0_INT | OC_INT)
81
82#define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST)
83
84/* Bus interrupt enable register */
85#define CMD_DONE_INT_EN (1 << 31)
86#define DATA_DONE_INT_EN (1 << 30)
87#define TRANS_OK_INT_EN (1 << 29)
88#define TRANS_FAIL_INT_EN (1 << 28)
89#define XD_INT_EN (1 << 27)
90#define MS_INT_EN (1 << 26)
91#define SD_INT_EN (1 << 25)
92#define GPIO0_INT_EN (1 << 24)
93#define OC_INT_EN (1 << 23)
94#define DELINK_INT_EN GPIO0_INT_EN
95#define MS_OC_INT_EN (1 << 23)
96#define SD_OC_INT_EN (1 << 22)
97
98#define READ_REG_CMD 0
99#define WRITE_REG_CMD 1
100#define CHECK_REG_CMD 2
101
102/*
103 * macros for easy use
104 */
105#define rtsx_pci_writel(pcr, reg, value) \
106 iowrite32(value, (pcr)->remap_addr + reg)
107#define rtsx_pci_readl(pcr, reg) \
108 ioread32((pcr)->remap_addr + reg)
109#define rtsx_pci_writew(pcr, reg, value) \
110 iowrite16(value, (pcr)->remap_addr + reg)
111#define rtsx_pci_readw(pcr, reg) \
112 ioread16((pcr)->remap_addr + reg)
113#define rtsx_pci_writeb(pcr, reg, value) \
114 iowrite8(value, (pcr)->remap_addr + reg)
115#define rtsx_pci_readb(pcr, reg) \
116 ioread8((pcr)->remap_addr + reg)
117
118#define rtsx_pci_read_config_byte(pcr, where, val) \
119 pci_read_config_byte((pcr)->pci, where, val)
120
121#define rtsx_pci_write_config_byte(pcr, where, val) \
122 pci_write_config_byte((pcr)->pci, where, val)
123
124#define rtsx_pci_read_config_dword(pcr, where, val) \
125 pci_read_config_dword((pcr)->pci, where, val)
126
127#define rtsx_pci_write_config_dword(pcr, where, val) \
128 pci_write_config_dword((pcr)->pci, where, val)
129
130#define STATE_TRANS_NONE 0
131#define STATE_TRANS_CMD 1
132#define STATE_TRANS_BUF 2
133#define STATE_TRANS_SG 3
134
135#define TRANS_NOT_READY 0
136#define TRANS_RESULT_OK 1
137#define TRANS_RESULT_FAIL 2
138#define TRANS_NO_DEVICE 3
139
140#define RTSX_RESV_BUF_LEN 4096
141#define HOST_CMDS_BUF_LEN 1024
142#define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
143#define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8)
144#define MAX_SG_ITEM_LEN 0x80000
145
146#define HOST_TO_DEVICE 0
147#define DEVICE_TO_HOST 1
148
149#define MAX_PHASE 31
150#define RX_TUNING_CNT 3
151
152/* SG descriptor */
153#define SG_INT 0x04
154#define SG_END 0x02
155#define SG_VALID 0x01
156
157#define SG_NO_OP 0x00
158#define SG_TRANS_DATA (0x02 << 4)
159#define SG_LINK_DESC (0x03 << 4)
160
161/* SD bank voltage */
162#define SD_IO_3V3 0
163#define SD_IO_1V8 1
164
165
166/* Card Clock Enable Register */
167#define SD_CLK_EN 0x04
168#define MS_CLK_EN 0x08
169
170/* Card Select Register */
171#define SD_MOD_SEL 2
172#define MS_MOD_SEL 3
173
174/* Card Output Enable Register */
175#define SD_OUTPUT_EN 0x04
176#define MS_OUTPUT_EN 0x08
177
178/* CARD_SHARE_MODE */
179#define CARD_SHARE_MASK 0x0F
180#define CARD_SHARE_MULTI_LUN 0x00
181#define CARD_SHARE_NORMAL 0x00
182#define CARD_SHARE_48_SD 0x04
183#define CARD_SHARE_48_MS 0x08
184/* CARD_SHARE_MODE for barossa */
185#define CARD_SHARE_BAROSSA_SD 0x01
186#define CARD_SHARE_BAROSSA_MS 0x02
187
188/* SD30_DRIVE_SEL */
189#define DRIVER_TYPE_A 0x05
190#define DRIVER_TYPE_B 0x03
191#define DRIVER_TYPE_C 0x02
192#define DRIVER_TYPE_D 0x01
193
194/* FPDCTL */
195#define SSC_POWER_DOWN 0x01
196#define SD_OC_POWER_DOWN 0x02
197#define ALL_POWER_DOWN 0x07
198#define OC_POWER_DOWN 0x06
199
200/* CLK_CTL */
201#define CHANGE_CLK 0x01
202
203/* LDO_CTL */
204#define BPP_LDO_POWB 0x03
205#define BPP_LDO_ON 0x00
206#define BPP_LDO_SUSPEND 0x02
207#define BPP_LDO_OFF 0x03
208
209/* CD_PAD_CTL */
210#define CD_DISABLE_MASK 0x07
211#define MS_CD_DISABLE 0x04
212#define SD_CD_DISABLE 0x02
213#define XD_CD_DISABLE 0x01
214#define CD_DISABLE 0x07
215#define CD_ENABLE 0x00
216#define MS_CD_EN_ONLY 0x03
217#define SD_CD_EN_ONLY 0x05
218#define XD_CD_EN_ONLY 0x06
219#define FORCE_CD_LOW_MASK 0x38
220#define FORCE_CD_XD_LOW 0x08
221#define FORCE_CD_SD_LOW 0x10
222#define FORCE_CD_MS_LOW 0x20
223#define CD_AUTO_DISABLE 0x40
224
225/* SD_STAT1 */
226#define SD_CRC7_ERR 0x80
227#define SD_CRC16_ERR 0x40
228#define SD_CRC_WRITE_ERR 0x20
229#define SD_CRC_WRITE_ERR_MASK 0x1C
230#define GET_CRC_TIME_OUT 0x02
231#define SD_TUNING_COMPARE_ERR 0x01
232
233/* SD_STAT2 */
234#define SD_RSP_80CLK_TIMEOUT 0x01
235
236/* SD_BUS_STAT */
237#define SD_CLK_TOGGLE_EN 0x80
238#define SD_CLK_FORCE_STOP 0x40
239#define SD_DAT3_STATUS 0x10
240#define SD_DAT2_STATUS 0x08
241#define SD_DAT1_STATUS 0x04
242#define SD_DAT0_STATUS 0x02
243#define SD_CMD_STATUS 0x01
244
245/* SD_PAD_CTL */
246#define SD_IO_USING_1V8 0x80
247#define SD_IO_USING_3V3 0x7F
248#define TYPE_A_DRIVING 0x00
249#define TYPE_B_DRIVING 0x01
250#define TYPE_C_DRIVING 0x02
251#define TYPE_D_DRIVING 0x03
252
253/* SD_SAMPLE_POINT_CTL */
254#define DDR_FIX_RX_DAT 0x00
255#define DDR_VAR_RX_DAT 0x80
256#define DDR_FIX_RX_DAT_EDGE 0x00
257#define DDR_FIX_RX_DAT_14_DELAY 0x40
258#define DDR_FIX_RX_CMD 0x00
259#define DDR_VAR_RX_CMD 0x20
260#define DDR_FIX_RX_CMD_POS_EDGE 0x00
261#define DDR_FIX_RX_CMD_14_DELAY 0x10
262#define SD20_RX_POS_EDGE 0x00
263#define SD20_RX_14_DELAY 0x08
264#define SD20_RX_SEL_MASK 0x08
265
266/* SD_PUSH_POINT_CTL */
267#define DDR_FIX_TX_CMD_DAT 0x00
268#define DDR_VAR_TX_CMD_DAT 0x80
269#define DDR_FIX_TX_DAT_14_TSU 0x00
270#define DDR_FIX_TX_DAT_12_TSU 0x40
271#define DDR_FIX_TX_CMD_NEG_EDGE 0x00
272#define DDR_FIX_TX_CMD_14_AHEAD 0x20
273#define SD20_TX_NEG_EDGE 0x00
274#define SD20_TX_14_AHEAD 0x10
275#define SD20_TX_SEL_MASK 0x10
276#define DDR_VAR_SDCLK_POL_SWAP 0x01
277
278/* SD_TRANSFER */
279#define SD_TRANSFER_START 0x80
280#define SD_TRANSFER_END 0x40
281#define SD_STAT_IDLE 0x20
282#define SD_TRANSFER_ERR 0x10
283/* SD Transfer Mode definition */
284#define SD_TM_NORMAL_WRITE 0x00
285#define SD_TM_AUTO_WRITE_3 0x01
286#define SD_TM_AUTO_WRITE_4 0x02
287#define SD_TM_AUTO_READ_3 0x05
288#define SD_TM_AUTO_READ_4 0x06
289#define SD_TM_CMD_RSP 0x08
290#define SD_TM_AUTO_WRITE_1 0x09
291#define SD_TM_AUTO_WRITE_2 0x0A
292#define SD_TM_NORMAL_READ 0x0C
293#define SD_TM_AUTO_READ_1 0x0D
294#define SD_TM_AUTO_READ_2 0x0E
295#define SD_TM_AUTO_TUNING 0x0F
296
297/* SD_VPTX_CTL / SD_VPRX_CTL */
298#define PHASE_CHANGE 0x80
299#define PHASE_NOT_RESET 0x40
300
301/* SD_DCMPS_TX_CTL / SD_DCMPS_RX_CTL */
302#define DCMPS_CHANGE 0x80
303#define DCMPS_CHANGE_DONE 0x40
304#define DCMPS_ERROR 0x20
305#define DCMPS_CURRENT_PHASE 0x1F
306
307/* SD Configure 1 Register */
308#define SD_CLK_DIVIDE_0 0x00
309#define SD_CLK_DIVIDE_256 0xC0
310#define SD_CLK_DIVIDE_128 0x80
311#define SD_BUS_WIDTH_1BIT 0x00
312#define SD_BUS_WIDTH_4BIT 0x01
313#define SD_BUS_WIDTH_8BIT 0x02
314#define SD_ASYNC_FIFO_NOT_RST 0x10
315#define SD_20_MODE 0x00
316#define SD_DDR_MODE 0x04
317#define SD_30_MODE 0x08
318
319#define SD_CLK_DIVIDE_MASK 0xC0
320
321/* SD_CMD_STATE */
322#define SD_CMD_IDLE 0x80
323
324/* SD_DATA_STATE */
325#define SD_DATA_IDLE 0x80
326
327/* DCM_DRP_CTL */
328#define DCM_RESET 0x08
329#define DCM_LOCKED 0x04
330#define DCM_208M 0x00
331#define DCM_TX 0x01
332#define DCM_RX 0x02
333
334/* DCM_DRP_TRIG */
335#define DRP_START 0x80
336#define DRP_DONE 0x40
337
338/* DCM_DRP_CFG */
339#define DRP_WRITE 0x80
340#define DRP_READ 0x00
341#define DCM_WRITE_ADDRESS_50 0x50
342#define DCM_WRITE_ADDRESS_51 0x51
343#define DCM_READ_ADDRESS_00 0x00
344#define DCM_READ_ADDRESS_51 0x51
345
346/* IRQSTAT0 */
347#define DMA_DONE_INT 0x80
348#define SUSPEND_INT 0x40
349#define LINK_RDY_INT 0x20
350#define LINK_DOWN_INT 0x10
351
352/* DMACTL */
353#define DMA_RST 0x80
354#define DMA_BUSY 0x04
355#define DMA_DIR_TO_CARD 0x00
356#define DMA_DIR_FROM_CARD 0x02
357#define DMA_EN 0x01
358#define DMA_128 (0 << 4)
359#define DMA_256 (1 << 4)
360#define DMA_512 (2 << 4)
361#define DMA_1024 (3 << 4)
362#define DMA_PACK_SIZE_MASK 0x30
363
364/* SSC_CTL1 */
365#define SSC_RSTB 0x80
366#define SSC_8X_EN 0x40
367#define SSC_FIX_FRAC 0x20
368#define SSC_SEL_1M 0x00
369#define SSC_SEL_2M 0x08
370#define SSC_SEL_4M 0x10
371#define SSC_SEL_8M 0x18
372
373/* SSC_CTL2 */
374#define SSC_DEPTH_MASK 0x07
375#define SSC_DEPTH_DISALBE 0x00
376#define SSC_DEPTH_4M 0x01
377#define SSC_DEPTH_2M 0x02
378#define SSC_DEPTH_1M 0x03
379#define SSC_DEPTH_500K 0x04
380#define SSC_DEPTH_250K 0x05
381
382/* System Clock Control Register */
383#define CLK_LOW_FREQ 0x01
384
385/* System Clock Divider Register */
386#define CLK_DIV_1 0x01
387#define CLK_DIV_2 0x02
388#define CLK_DIV_4 0x03
389#define CLK_DIV_8 0x04
390
391/* MS_CFG */
392#define SAMPLE_TIME_RISING 0x00
393#define SAMPLE_TIME_FALLING 0x80
394#define PUSH_TIME_DEFAULT 0x00
395#define PUSH_TIME_ODD 0x40
396#define NO_EXTEND_TOGGLE 0x00
397#define EXTEND_TOGGLE_CHK 0x20
398#define MS_BUS_WIDTH_1 0x00
399#define MS_BUS_WIDTH_4 0x10
400#define MS_BUS_WIDTH_8 0x18
401#define MS_2K_SECTOR_MODE 0x04
402#define MS_512_SECTOR_MODE 0x00
403#define MS_TOGGLE_TIMEOUT_EN 0x00
404#define MS_TOGGLE_TIMEOUT_DISEN 0x01
405#define MS_NO_CHECK_INT 0x02
406
407/* MS_TRANS_CFG */
408#define WAIT_INT 0x80
409#define NO_WAIT_INT 0x00
410#define NO_AUTO_READ_INT_REG 0x00
411#define AUTO_READ_INT_REG 0x40
412#define MS_CRC16_ERR 0x20
413#define MS_RDY_TIMEOUT 0x10
414#define MS_INT_CMDNK 0x08
415#define MS_INT_BREQ 0x04
416#define MS_INT_ERR 0x02
417#define MS_INT_CED 0x01
418
419/* MS_TRANSFER */
420#define MS_TRANSFER_START 0x80
421#define MS_TRANSFER_END 0x40
422#define MS_TRANSFER_ERR 0x20
423#define MS_BS_STATE 0x10
424#define MS_TM_READ_BYTES 0x00
425#define MS_TM_NORMAL_READ 0x01
426#define MS_TM_WRITE_BYTES 0x04
427#define MS_TM_NORMAL_WRITE 0x05
428#define MS_TM_AUTO_READ 0x08
429#define MS_TM_AUTO_WRITE 0x0C
430
431/* SD Configure 2 Register */
432#define SD_CALCULATE_CRC7 0x00
433#define SD_NO_CALCULATE_CRC7 0x80
434#define SD_CHECK_CRC16 0x00
435#define SD_NO_CHECK_CRC16 0x40
436#define SD_NO_CHECK_WAIT_CRC_TO 0x20
437#define SD_WAIT_BUSY_END 0x08
438#define SD_NO_WAIT_BUSY_END 0x00
439#define SD_CHECK_CRC7 0x00
440#define SD_NO_CHECK_CRC7 0x04
441#define SD_RSP_LEN_0 0x00
442#define SD_RSP_LEN_6 0x01
443#define SD_RSP_LEN_17 0x02
444/* SD/MMC Response Type Definition */
445#define SD_RSP_TYPE_R0 0x04
446#define SD_RSP_TYPE_R1 0x01
447#define SD_RSP_TYPE_R1b 0x09
448#define SD_RSP_TYPE_R2 0x02
449#define SD_RSP_TYPE_R3 0x05
450#define SD_RSP_TYPE_R4 0x05
451#define SD_RSP_TYPE_R5 0x01
452#define SD_RSP_TYPE_R6 0x01
453#define SD_RSP_TYPE_R7 0x01
454
455/* SD_CONFIURE3 */
456#define SD_RSP_80CLK_TIMEOUT_EN 0x01
457
458/* Card Transfer Reset Register */
459#define SPI_STOP 0x01
460#define XD_STOP 0x02
461#define SD_STOP 0x04
462#define MS_STOP 0x08
463#define SPI_CLR_ERR 0x10
464#define XD_CLR_ERR 0x20
465#define SD_CLR_ERR 0x40
466#define MS_CLR_ERR 0x80
467
468/* Card Data Source Register */
469#define PINGPONG_BUFFER 0x01
470#define RING_BUFFER 0x00
471
472/* Card Power Control Register */
473#define PMOS_STRG_MASK 0x10
474#define PMOS_STRG_800mA 0x10
475#define PMOS_STRG_400mA 0x00
476#define SD_POWER_OFF 0x03
477#define SD_PARTIAL_POWER_ON 0x01
478#define SD_POWER_ON 0x00
479#define SD_POWER_MASK 0x03
480#define MS_POWER_OFF 0x0C
481#define MS_PARTIAL_POWER_ON 0x04
482#define MS_POWER_ON 0x00
483#define MS_POWER_MASK 0x0C
484#define BPP_POWER_OFF 0x0F
485#define BPP_POWER_5_PERCENT_ON 0x0E
486#define BPP_POWER_10_PERCENT_ON 0x0C
487#define BPP_POWER_15_PERCENT_ON 0x08
488#define BPP_POWER_ON 0x00
489#define BPP_POWER_MASK 0x0F
490
491/* PWR_GATE_CTRL */
492#define PWR_GATE_EN 0x01
493#define LDO3318_PWR_MASK 0x06
494#define LDO_ON 0x00
495#define LDO_SUSPEND 0x04
496#define LDO_OFF 0x06
497
498/* CARD_CLK_SOURCE */
499#define CRC_FIX_CLK (0x00 << 0)
500#define CRC_VAR_CLK0 (0x01 << 0)
501#define CRC_VAR_CLK1 (0x02 << 0)
502#define SD30_FIX_CLK (0x00 << 2)
503#define SD30_VAR_CLK0 (0x01 << 2)
504#define SD30_VAR_CLK1 (0x02 << 2)
505#define SAMPLE_FIX_CLK (0x00 << 4)
506#define SAMPLE_VAR_CLK0 (0x01 << 4)
507#define SAMPLE_VAR_CLK1 (0x02 << 4)
508
509#define MS_CFG 0xFD40
510#define MS_TPC 0xFD41
511#define MS_TRANS_CFG 0xFD42
512#define MS_TRANSFER 0xFD43
513#define MS_INT_REG 0xFD44
514#define MS_BYTE_CNT 0xFD45
515#define MS_SECTOR_CNT_L 0xFD46
516#define MS_SECTOR_CNT_H 0xFD47
517#define MS_DBUS_H 0xFD48
518
519#define SD_CFG1 0xFDA0
520#define SD_CFG2 0xFDA1
521#define SD_CFG3 0xFDA2
522#define SD_STAT1 0xFDA3
523#define SD_STAT2 0xFDA4
524#define SD_BUS_STAT 0xFDA5
525#define SD_PAD_CTL 0xFDA6
526#define SD_SAMPLE_POINT_CTL 0xFDA7
527#define SD_PUSH_POINT_CTL 0xFDA8
528#define SD_CMD0 0xFDA9
529#define SD_CMD1 0xFDAA
530#define SD_CMD2 0xFDAB
531#define SD_CMD3 0xFDAC
532#define SD_CMD4 0xFDAD
533#define SD_CMD5 0xFDAE
534#define SD_BYTE_CNT_L 0xFDAF
535#define SD_BYTE_CNT_H 0xFDB0
536#define SD_BLOCK_CNT_L 0xFDB1
537#define SD_BLOCK_CNT_H 0xFDB2
538#define SD_TRANSFER 0xFDB3
539#define SD_CMD_STATE 0xFDB5
540#define SD_DATA_STATE 0xFDB6
541
542#define SRCTL 0xFC13
543
544#define DCM_DRP_CTL 0xFC23
545#define DCM_DRP_TRIG 0xFC24
546#define DCM_DRP_CFG 0xFC25
547#define DCM_DRP_WR_DATA_L 0xFC26
548#define DCM_DRP_WR_DATA_H 0xFC27
549#define DCM_DRP_RD_DATA_L 0xFC28
550#define DCM_DRP_RD_DATA_H 0xFC29
551#define SD_VPCLK0_CTL 0xFC2A
552#define SD_VPCLK1_CTL 0xFC2B
553#define SD_DCMPS0_CTL 0xFC2C
554#define SD_DCMPS1_CTL 0xFC2D
555#define SD_VPTX_CTL SD_VPCLK0_CTL
556#define SD_VPRX_CTL SD_VPCLK1_CTL
557#define SD_DCMPS_TX_CTL SD_DCMPS0_CTL
558#define SD_DCMPS_RX_CTL SD_DCMPS1_CTL
559#define CARD_CLK_SOURCE 0xFC2E
560
561#define CARD_PWR_CTL 0xFD50
562#define CARD_CLK_SWITCH 0xFD51
563#define CARD_SHARE_MODE 0xFD52
564#define CARD_DRIVE_SEL 0xFD53
565#define CARD_STOP 0xFD54
566#define CARD_OE 0xFD55
567#define CARD_AUTO_BLINK 0xFD56
568#define CARD_GPIO_DIR 0xFD57
569#define CARD_GPIO 0xFD58
570#define CARD_DATA_SOURCE 0xFD5B
571#define CARD_SELECT 0xFD5C
572#define SD30_DRIVE_SEL 0xFD5E
573#define CARD_CLK_EN 0xFD69
574#define SDIO_CTRL 0xFD6B
575#define CD_PAD_CTL 0xFD73
576
577#define FPDCTL 0xFC00
578#define PDINFO 0xFC01
579
580#define CLK_CTL 0xFC02
581#define CLK_DIV 0xFC03
582#define CLK_SEL 0xFC04
583
584#define SSC_DIV_N_0 0xFC0F
585#define SSC_DIV_N_1 0xFC10
586#define SSC_CTL1 0xFC11
587#define SSC_CTL2 0xFC12
588
589#define RCCTL 0xFC14
590
591#define FPGA_PULL_CTL 0xFC1D
592#define OLT_LED_CTL 0xFC1E
593#define GPIO_CTL 0xFC1F
594
595#define LDO_CTL 0xFC1E
596#define SYS_VER 0xFC32
597
598#define CARD_PULL_CTL1 0xFD60
599#define CARD_PULL_CTL2 0xFD61
600#define CARD_PULL_CTL3 0xFD62
601#define CARD_PULL_CTL4 0xFD63
602#define CARD_PULL_CTL5 0xFD64
603#define CARD_PULL_CTL6 0xFD65
604
605/* PCI Express Related Registers */
606#define IRQEN0 0xFE20
607#define IRQSTAT0 0xFE21
608#define IRQEN1 0xFE22
609#define IRQSTAT1 0xFE23
610#define TLPRIEN 0xFE24
611#define TLPRISTAT 0xFE25
612#define TLPTIEN 0xFE26
613#define TLPTISTAT 0xFE27
614#define DMATC0 0xFE28
615#define DMATC1 0xFE29
616#define DMATC2 0xFE2A
617#define DMATC3 0xFE2B
618#define DMACTL 0xFE2C
619#define BCTL 0xFE2D
620#define RBBC0 0xFE2E
621#define RBBC1 0xFE2F
622#define RBDAT 0xFE30
623#define RBCTL 0xFE34
624#define CFGADDR0 0xFE35
625#define CFGADDR1 0xFE36
626#define CFGDATA0 0xFE37
627#define CFGDATA1 0xFE38
628#define CFGDATA2 0xFE39
629#define CFGDATA3 0xFE3A
630#define CFGRWCTL 0xFE3B
631#define PHYRWCTL 0xFE3C
632#define PHYDATA0 0xFE3D
633#define PHYDATA1 0xFE3E
634#define PHYADDR 0xFE3F
635#define MSGRXDATA0 0xFE40
636#define MSGRXDATA1 0xFE41
637#define MSGRXDATA2 0xFE42
638#define MSGRXDATA3 0xFE43
639#define MSGTXDATA0 0xFE44
640#define MSGTXDATA1 0xFE45
641#define MSGTXDATA2 0xFE46
642#define MSGTXDATA3 0xFE47
643#define MSGTXCTL 0xFE48
644#define PETXCFG 0xFE49
645
646#define CDRESUMECTL 0xFE52
647#define WAKE_SEL_CTL 0xFE54
648#define PME_FORCE_CTL 0xFE56
649#define ASPM_FORCE_CTL 0xFE57
650#define PM_CLK_FORCE_CTL 0xFE58
651#define PERST_GLITCH_WIDTH 0xFE5C
652#define CHANGE_LINK_STATE 0xFE5B
653#define RESET_LOAD_REG 0xFE5E
654#define EFUSE_CONTENT 0xFE5F
655#define HOST_SLEEP_STATE 0xFE60
656#define SDIO_CFG 0xFE70
657
658#define NFTS_TX_CTRL 0xFE72
659
660#define PWR_GATE_CTRL 0xFE75
661#define PWD_SUSPEND_EN 0xFE76
662#define LDO_PWR_SEL 0xFE78
663
664#define DUMMY_REG_RESET_0 0xFE90
665
666/* Memory mapping */
667#define SRAM_BASE 0xE600
668#define RBUF_BASE 0xF400
669#define PPBUF_BASE1 0xF800
670#define PPBUF_BASE2 0xFA00
671#define IMAGE_FLAG_ADDR0 0xCE80
672#define IMAGE_FLAG_ADDR1 0xCE81
673
674#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
675
676struct rtsx_pcr;
677
678struct pcr_handle {
679 struct rtsx_pcr *pcr;
680};
681
682struct pcr_ops {
683 int (*extra_init_hw)(struct rtsx_pcr *pcr);
684 int (*optimize_phy)(struct rtsx_pcr *pcr);
685 int (*turn_on_led)(struct rtsx_pcr *pcr);
686 int (*turn_off_led)(struct rtsx_pcr *pcr);
687 int (*enable_auto_blink)(struct rtsx_pcr *pcr);
688 int (*disable_auto_blink)(struct rtsx_pcr *pcr);
689 int (*card_power_on)(struct rtsx_pcr *pcr, int card);
690 int (*card_power_off)(struct rtsx_pcr *pcr, int card);
691 unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr);
692};
693
694enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
695
696struct rtsx_pcr {
697 struct pci_dev *pci;
698 unsigned int id;
699
700 /* pci resources */
701 unsigned long addr;
702 void __iomem *remap_addr;
703 int irq;
704
705 /* host reserved buffer */
706 void *rtsx_resv_buf;
707 dma_addr_t rtsx_resv_buf_addr;
708
709 void *host_cmds_ptr;
710 dma_addr_t host_cmds_addr;
711 int ci;
712
713 void *host_sg_tbl_ptr;
714 dma_addr_t host_sg_tbl_addr;
715 int sgi;
716
717 u32 bier;
718 char trans_result;
719
720 unsigned int card_inserted;
721 unsigned int card_removed;
722
723 struct delayed_work carddet_work;
724 struct delayed_work idle_work;
725
726 spinlock_t lock;
727 struct mutex pcr_mutex;
728 struct completion *done;
729 struct completion *finish_me;
730
731 unsigned int cur_clock;
732 bool ms_pmos;
733 bool remove_pci;
734 bool msi_en;
735
736#define EXTRA_CAPS_SD_SDR50 (1 << 0)
737#define EXTRA_CAPS_SD_SDR104 (1 << 1)
738#define EXTRA_CAPS_SD_DDR50 (1 << 2)
739#define EXTRA_CAPS_MMC_HSDDR (1 << 3)
740#define EXTRA_CAPS_MMC_HS200 (1 << 4)
741#define EXTRA_CAPS_MMC_8BIT (1 << 5)
742 u32 extra_caps;
743
744#define IC_VER_A 0
745#define IC_VER_B 1
746#define IC_VER_C 2
747#define IC_VER_D 3
748 u8 ic_version;
749
750 const u32 *sd_pull_ctl_enable_tbl;
751 const u32 *sd_pull_ctl_disable_tbl;
752 const u32 *ms_pull_ctl_enable_tbl;
753 const u32 *ms_pull_ctl_disable_tbl;
754
755 const struct pcr_ops *ops;
756 enum PDEV_STAT state;
757
758 int num_slots;
759 struct rtsx_slot *slots;
760};
761
762#define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid))
763#define PCI_VID(pcr) ((pcr)->pci->vendor)
764#define PCI_PID(pcr) ((pcr)->pci->device)
765
766void rtsx_pci_start_run(struct rtsx_pcr *pcr);
767int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
768int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
769int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
770int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
771void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
772void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
773 u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
774void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
775int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
776int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
777 int num_sg, bool read, int timeout);
778int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
779int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
780int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
781int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card);
782int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
783 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
784int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
785int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
786unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
787void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
788
789static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
790{
791 return (u8 *)(pcr->host_cmds_ptr);
792}
793
794#endif
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