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authorJon Hunter <jon-hunter@ti.com>2012-09-23 19:28:27 -0400
committerPaul Walmsley <paul@pwsan.com>2012-09-23 19:28:27 -0400
commit5c3e4ec48586f6dfb482f1c524748948ba14021e (patch)
treed515924d76f922a368832d4e5d389f831700d39e
parentfe47c58ba82c967729c76869a5f10a94c38754f3 (diff)
ARM: OMAP: Add a timer attribute for timers that can interrupt the DSP
Some instances of the DMTIMER peripheral on OMAP devices have the ability to interrupt the on-chip DSP in addition to the ARM CPU. Add a DMTIMER attribute to indicate which timers can interrupt the DSP. By using the omap_dm_timer_request_by_cap() API, driver will now be able to allocate a DMTIMER that can interrupt the DSP based upon this attribute and not require the driver to know which instance has this capability. DMTIMERs that have the ability to interrupt the DSP on OMAP devices are as follows ... - OMAP1 (OMAP5912/16xx/17xx) devices - All 8 DMTIMERs - OMAP2/3/4 devices - DMTIMERs 5-8 Please note that for OMAP3+, timer8 has the ability to interrupt the DSP and generate a PWM output. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
-rw-r--r--arch/arm/mach-omap1/timer.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c9
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c15
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c15
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h1
5 files changed, 39 insertions, 3 deletions
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index aa81593db1af..cdeb9d3ef640 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -141,7 +141,7 @@ static int __init omap1_dm_timer_init(void)
141 141
142 pdata->set_timer_src = omap1_dm_timer_set_src; 142 pdata->set_timer_src = omap1_dm_timer_set_src;
143 pdata->timer_capability = OMAP_TIMER_ALWON | 143 pdata->timer_capability = OMAP_TIMER_ALWON |
144 OMAP_TIMER_NEEDS_RESET; 144 OMAP_TIMER_NEEDS_RESET | OMAP_TIMER_HAS_DSP_IRQ;
145 145
146 ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); 146 ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
147 if (ret) { 147 if (ret) {
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 32c778bf8f08..de39017d2e28 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -240,6 +240,11 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
240 .timer_capability = OMAP_TIMER_HAS_PWM, 240 .timer_capability = OMAP_TIMER_HAS_PWM,
241}; 241};
242 242
243/* timers with DSP interrupt dev attribute */
244static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
245 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
246};
247
243/* timer1 */ 248/* timer1 */
244 249
245struct omap_hwmod omap2xxx_timer1_hwmod = { 250struct omap_hwmod omap2xxx_timer1_hwmod = {
@@ -328,6 +333,7 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
328 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, 333 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
329 }, 334 },
330 }, 335 },
336 .dev_attr = &capability_dsp_dev_attr,
331 .class = &omap2xxx_timer_hwmod_class, 337 .class = &omap2xxx_timer_hwmod_class,
332}; 338};
333 339
@@ -346,6 +352,7 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
346 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, 352 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
347 }, 353 },
348 }, 354 },
355 .dev_attr = &capability_dsp_dev_attr,
349 .class = &omap2xxx_timer_hwmod_class, 356 .class = &omap2xxx_timer_hwmod_class,
350}; 357};
351 358
@@ -364,6 +371,7 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
364 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, 371 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
365 }, 372 },
366 }, 373 },
374 .dev_attr = &capability_dsp_dev_attr,
367 .class = &omap2xxx_timer_hwmod_class, 375 .class = &omap2xxx_timer_hwmod_class,
368}; 376};
369 377
@@ -382,6 +390,7 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
382 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, 390 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
383 }, 391 },
384 }, 392 },
393 .dev_attr = &capability_dsp_dev_attr,
385 .class = &omap2xxx_timer_hwmod_class, 394 .class = &omap2xxx_timer_hwmod_class,
386}; 395};
387 396
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index da6eca0ff79b..5ef9007ace50 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -171,6 +171,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
171 .timer_capability = OMAP_TIMER_HAS_PWM, 171 .timer_capability = OMAP_TIMER_HAS_PWM,
172}; 172};
173 173
174/* timers with DSP interrupt dev attribute */
175static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
176 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
177};
178
179/* pwm timers with DSP interrupt dev attribute */
180static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
181 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
182};
183
174/* timer1 */ 184/* timer1 */
175static struct omap_hwmod omap3xxx_timer1_hwmod = { 185static struct omap_hwmod omap3xxx_timer1_hwmod = {
176 .name = "timer1", 186 .name = "timer1",
@@ -254,6 +264,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
254 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, 264 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
255 }, 265 },
256 }, 266 },
267 .dev_attr = &capability_dsp_dev_attr,
257 .class = &omap3xxx_timer_hwmod_class, 268 .class = &omap3xxx_timer_hwmod_class,
258}; 269};
259 270
@@ -271,6 +282,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
271 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, 282 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
272 }, 283 },
273 }, 284 },
285 .dev_attr = &capability_dsp_dev_attr,
274 .class = &omap3xxx_timer_hwmod_class, 286 .class = &omap3xxx_timer_hwmod_class,
275}; 287};
276 288
@@ -288,6 +300,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
288 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, 300 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
289 }, 301 },
290 }, 302 },
303 .dev_attr = &capability_dsp_dev_attr,
291 .class = &omap3xxx_timer_hwmod_class, 304 .class = &omap3xxx_timer_hwmod_class,
292}; 305};
293 306
@@ -305,7 +318,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
305 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, 318 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
306 }, 319 },
307 }, 320 },
308 .dev_attr = &capability_pwm_dev_attr, 321 .dev_attr = &capability_dsp_pwm_dev_attr,
309 .class = &omap3xxx_timer_hwmod_class, 322 .class = &omap3xxx_timer_hwmod_class,
310}; 323};
311 324
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 46fd80c29a02..17ab2dbc8931 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -3097,6 +3097,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3097 .timer_capability = OMAP_TIMER_HAS_PWM, 3097 .timer_capability = OMAP_TIMER_HAS_PWM,
3098}; 3098};
3099 3099
3100/* timers with DSP interrupt dev attribute */
3101static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3102 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
3103};
3104
3105/* pwm timers with DSP interrupt dev attribute */
3106static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3107 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3108};
3109
3100/* timer1 */ 3110/* timer1 */
3101static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { 3111static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3102 { .irq = 37 + OMAP44XX_IRQ_GIC_START }, 3112 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
@@ -3201,6 +3211,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
3201 .modulemode = MODULEMODE_SWCTRL, 3211 .modulemode = MODULEMODE_SWCTRL,
3202 }, 3212 },
3203 }, 3213 },
3214 .dev_attr = &capability_dsp_dev_attr,
3204}; 3215};
3205 3216
3206/* timer6 */ 3217/* timer6 */
@@ -3223,6 +3234,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
3223 .modulemode = MODULEMODE_SWCTRL, 3234 .modulemode = MODULEMODE_SWCTRL,
3224 }, 3235 },
3225 }, 3236 },
3237 .dev_attr = &capability_dsp_dev_attr,
3226}; 3238};
3227 3239
3228/* timer7 */ 3240/* timer7 */
@@ -3244,6 +3256,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
3244 .modulemode = MODULEMODE_SWCTRL, 3256 .modulemode = MODULEMODE_SWCTRL,
3245 }, 3257 },
3246 }, 3258 },
3259 .dev_attr = &capability_dsp_dev_attr,
3247}; 3260};
3248 3261
3249/* timer8 */ 3262/* timer8 */
@@ -3265,7 +3278,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
3265 .modulemode = MODULEMODE_SWCTRL, 3278 .modulemode = MODULEMODE_SWCTRL,
3266 }, 3279 },
3267 }, 3280 },
3268 .dev_attr = &capability_pwm_dev_attr, 3281 .dev_attr = &capability_dsp_pwm_dev_attr,
3269}; 3282};
3270 3283
3271/* timer9 */ 3284/* timer9 */
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 19e7fa577bd0..85868e98c11c 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -60,6 +60,7 @@
60#define OMAP_TIMER_ALWON 0x40000000 60#define OMAP_TIMER_ALWON 0x40000000
61#define OMAP_TIMER_HAS_PWM 0x20000000 61#define OMAP_TIMER_HAS_PWM 0x20000000
62#define OMAP_TIMER_NEEDS_RESET 0x10000000 62#define OMAP_TIMER_NEEDS_RESET 0x10000000
63#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000
63 64
64struct omap_timer_capability_dev_attr { 65struct omap_timer_capability_dev_attr {
65 u32 timer_capability; 66 u32 timer_capability;