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authorNicolin Chen <Guangyu.Chen@freescale.com>2014-01-06 03:55:07 -0500
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:47:38 -0400
commit521b351b58f4678547c59e1bafa5d2142c1150ed (patch)
treeef430eb29edac612e59c649d3c4b3441bb6ac3c9
parent1f5e453015ae9881c9bede2fcbf62a4ab3a15f4b (diff)
ENGR00295423-3 ASoC: fsl_ssi: Don't disable SSIEN if SSI is already enabled
If disabling SSI when SSI is already in the working state, the whole running substream would be broken. Thus we here replace it to a safer way -- saving the current SSIEN value and restore it afterward. This patch also adds a slot number checking code before setting slot number. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
-rw-r--r--sound/soc/fsl/fsl_ssi.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 46f574895f73..0d711544c023 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -756,6 +756,14 @@ static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
756{ 756{
757 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 757 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
758 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 758 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
759 u32 val;
760
761 /* The slot number should be >= 2 if using Network mode or I2S mode */
762 val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET);
763 if (val && slots < 2) {
764 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
765 return -EINVAL;
766 }
759 767
760 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK, 768 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
761 CCSR_SSI_SxCCR_DC(slots)); 769 CCSR_SSI_SxCCR_DC(slots));
@@ -765,10 +773,11 @@ static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
765 /* The register SxMSKs need SSI to provide essential clock due to 773 /* The register SxMSKs need SSI to provide essential clock due to
766 * hardware design. So we here temporarily enable SSI to set them. 774 * hardware design. So we here temporarily enable SSI to set them.
767 */ 775 */
776 val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
768 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN); 777 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);
769 write_ssi(tx_mask, &ssi->stmsk); 778 write_ssi(tx_mask, &ssi->stmsk);
770 write_ssi(rx_mask, &ssi->srmsk); 779 write_ssi(rx_mask, &ssi->srmsk);
771 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0); 780 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val);
772 781
773 return 0; 782 return 0;
774} 783}