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authorNicolin Chen <b42378@freescale.com>2013-09-24 06:13:41 -0400
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:05:42 -0400
commit4402aa8c6010d6d8b29c647876889659cfb27969 (patch)
treea8a342067d56a291692250df9191714d8ac40c95
parent33959e31c18751927371a609d5e1d7b6310bc876 (diff)
ENGR00280852-3 mxc: asrc: Use regmap to control register accessing
Dropped the legency readl/writel() and use regmap instead. Also removed core clock's clk_prepare() and spin_lock()/unlock() outside regmap due to regmap already has these features. This patch also added a missing writable register to the regmap in order to assure the regsiter updating success. Signed-off-by: Nicolin Chen <b42378@freescale.com>
-rw-r--r--drivers/mxc/asrc/mxc_asrc.c167
-rw-r--r--include/linux/mxc_asrc.h1
2 files changed, 44 insertions, 124 deletions
diff --git a/drivers/mxc/asrc/mxc_asrc.c b/drivers/mxc/asrc/mxc_asrc.c
index 1d00ed3492b9..14e619f8e757 100644
--- a/drivers/mxc/asrc/mxc_asrc.c
+++ b/drivers/mxc/asrc/mxc_asrc.c
@@ -96,48 +96,12 @@ static unsigned char output_clk_map_v2[] = {
96 96
97static unsigned char *input_clk_map, *output_clk_map; 97static unsigned char *input_clk_map, *output_clk_map;
98 98
99/* ALL registers of ASRC are 24-bit efficient */
100static u32 asrc_regmap_read(struct regmap *map, unsigned int reg,
101 unsigned int *val)
102{
103#ifndef ASRC_USE_REGMAP
104 *val = readl((void __iomem *)asrc->vaddr + reg) & 0xffffff;
105 return *val;
106#else
107 return regmap_read(map, reg, val);
108#endif
109}
110
111static void asrc_regmap_write(struct regmap *map, unsigned int reg,
112 unsigned int val)
113{
114#ifndef ASRC_USE_REGMAP
115 writel(val & 0xffffff, (void __iomem *)asrc->vaddr + reg);
116#else
117 return regmap_write(map, reg, val);
118#endif
119}
120
121static void asrc_regmap_update_bits(struct regmap *map, unsigned int reg,
122 unsigned int mask, unsigned int val)
123{
124#ifndef ASRC_USE_REGMAP
125 u32 regval;
126
127 regval = readl((void __iomem *)asrc->vaddr + reg) & 0xffffff;
128 regval = (regval & ~mask) | (val & mask);
129 writel(regval & 0xffffff, (void __iomem *)asrc->vaddr + reg);
130#else
131 regmap_update_bits(map, reg, mask, val);
132#endif
133}
134
135/* Set ASRC_REG_ASRCNCR reg, only supporting one-pair setting at once */ 99/* Set ASRC_REG_ASRCNCR reg, only supporting one-pair setting at once */
136static int asrc_set_channel_number(enum asrc_pair_index index, u32 val) 100static int asrc_set_channel_number(enum asrc_pair_index index, u32 val)
137{ 101{
138 u32 num; 102 u32 num;
139 103
140 asrc_regmap_read(asrc->regmap, REG_ASRCNCR, &num); 104 regmap_read(asrc->regmap, REG_ASRCNCR, &num);
141 105
142 switch (index) { 106 switch (index) {
143 case ASRC_PAIR_A: 107 case ASRC_PAIR_A:
@@ -157,7 +121,7 @@ static int asrc_set_channel_number(enum asrc_pair_index index, u32 val)
157 return -EINVAL; 121 return -EINVAL;
158 } 122 }
159 123
160 asrc_regmap_write(asrc->regmap, REG_ASRCNCR, num); 124 regmap_write(asrc->regmap, REG_ASRCNCR, num);
161 125
162 return 0; 126 return 0;
163} 127}
@@ -208,7 +172,7 @@ static void dump_regs(void)
208 172
209 for (i = 0; i < ARRAY_SIZE(asrc_reg); i++) { 173 for (i = 0; i < ARRAY_SIZE(asrc_reg); i++) {
210 reg = asrc_reg[i]; 174 reg = asrc_reg[i];
211 asrc_regmap_read(asrc->regmap, reg, &val); 175 regmap_read(asrc->regmap, reg, &val);
212 pr_debug("REG addr=0x%x val=0x%x\n", reg, val); 176 pr_debug("REG addr=0x%x val=0x%x\n", reg, val);
213 } 177 }
214} 178}
@@ -246,8 +210,8 @@ static int asrc_set_clock_ratio(enum asrc_pair_index index,
246 break; 210 break;
247 } 211 }
248 212
249 asrc_regmap_write(asrc->regmap, REG_ASRIDRL(index), val); 213 regmap_write(asrc->regmap, REG_ASRIDRL(index), val);
250 asrc_regmap_write(asrc->regmap, REG_ASRIDRH(index), (val >> 24)); 214 regmap_write(asrc->regmap, REG_ASRIDRH(index), (val >> 24));
251 215
252 return 0; 216 return 0;
253} 217}
@@ -287,7 +251,7 @@ static int asrc_set_process_configuration(enum asrc_pair_index index,
287 return -EINVAL; 251 return -EINVAL;
288 } 252 }
289 253
290 asrc_regmap_update_bits(asrc->regmap, REG_ASRCFG, 254 regmap_update_bits(asrc->regmap, REG_ASRCFG,
291 ASRCFG_PREMODx_MASK(index) | ASRCFG_POSTMODx_MASK(index), 255 ASRCFG_PREMODx_MASK(index) | ASRCFG_POSTMODx_MASK(index),
292 ASRCFG_PREMOD(index, asrc_process_table[in][out][0]) | 256 ASRCFG_PREMOD(index, asrc_process_table[in][out][0]) |
293 ASRCFG_POSTMOD(index, asrc_process_table[in][out][1])); 257 ASRCFG_POSTMOD(index, asrc_process_table[in][out][1]));
@@ -372,7 +336,7 @@ int asrc_req_pair(int chn_num, enum asrc_pair_index *index)
372 336
373 if (!ret) { 337 if (!ret) {
374 clk_enable(asrc->asrc_clk); 338 clk_enable(asrc->asrc_clk);
375 clk_enable(asrc->dma_clk); 339 clk_prepare_enable(asrc->dma_clk);
376 } 340 }
377 341
378 return ret; 342 return ret;
@@ -389,11 +353,10 @@ void asrc_release_pair(enum asrc_pair_index index)
389 pair->active = 0; 353 pair->active = 0;
390 pair->overload_error = 0; 354 pair->overload_error = 0;
391 355
392 /* Disable PAIR */
393 asrc_regmap_update_bits(asrc->regmap, REG_ASRCTR,
394 ASRCTR_ASRCEx_MASK(index), 0);
395
396 spin_unlock_irqrestore(&data_lock, lock_flags); 356 spin_unlock_irqrestore(&data_lock, lock_flags);
357
358 /* Disable PAIR */
359 regmap_update_bits(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEx_MASK(index), 0);
397} 360}
398EXPORT_SYMBOL(asrc_release_pair); 361EXPORT_SYMBOL(asrc_release_pair);
399 362
@@ -419,16 +382,15 @@ int asrc_config_pair(struct asrc_config *config)
419 asrc_set_channel_number(index, channel_num); 382 asrc_set_channel_number(index, channel_num);
420 383
421 /* Set the clock source */ 384 /* Set the clock source */
422 asrc_regmap_update_bits(asrc->regmap, REG_ASRCSR, 385 regmap_update_bits(asrc->regmap, REG_ASRCSR,
423 ASRCSR_AICSx_MASK(index) | ASRCSR_AOCSx_MASK(index), 386 ASRCSR_AICSx_MASK(index) | ASRCSR_AOCSx_MASK(index),
424 ASRCSR_AICS(index, input_clk_map[config->inclk]) | 387 ASRCSR_AICS(index, input_clk_map[config->inclk]) |
425 ASRCSR_AOCS(index, output_clk_map[config->outclk])); 388 ASRCSR_AOCS(index, output_clk_map[config->outclk]));
426 389
427 /* Default setting: Automatic selection for processing mode */ 390 /* Default setting: Automatic selection for processing mode */
428 asrc_regmap_update_bits(asrc->regmap, REG_ASRCTR, 391 regmap_update_bits(asrc->regmap, REG_ASRCTR,
429 ASRCTR_ATSx_MASK(index), ASRCTR_ATS(index)); 392 ASRCTR_ATSx_MASK(index), ASRCTR_ATS(index));
430 asrc_regmap_update_bits(asrc->regmap, REG_ASRCTR, 393 regmap_update_bits(asrc->regmap, REG_ASRCTR, ASRCTR_USRx_MASK(index), 0);
431 ASRCTR_USRx_MASK(index), 0);
432 394
433 /* Default Input Clock Divider Setting */ 395 /* Default Input Clock Divider Setting */
434 switch (config->inclk & ASRCSR_AxCSx_MASK) { 396 switch (config->inclk & ASRCSR_AxCSx_MASK) {
@@ -488,7 +450,7 @@ int asrc_config_pair(struct asrc_config *config)
488 } 450 }
489 451
490 /* indiv and outdiv'd include prescaler's value, so add its MASK too */ 452 /* indiv and outdiv'd include prescaler's value, so add its MASK too */
491 asrc_regmap_update_bits(asrc->regmap, REG_ASRCDR(index), 453 regmap_update_bits(asrc->regmap, REG_ASRCDR(index),
492 ASRCDRx_AOCPx_MASK(index) | ASRCDRx_AICPx_MASK(index) | 454 ASRCDRx_AOCPx_MASK(index) | ASRCDRx_AICPx_MASK(index) |
493 ASRCDRx_AOCDx_MASK(index) | ASRCDRx_AICDx_MASK(index), 455 ASRCDRx_AOCDx_MASK(index) | ASRCDRx_AICDx_MASK(index),
494 ASRCDRx_AOCP(index, outdiv) | ASRCDRx_AICP(index, indiv)); 456 ASRCDRx_AOCP(index, outdiv) | ASRCDRx_AICP(index, indiv));
@@ -497,10 +459,10 @@ int asrc_config_pair(struct asrc_config *config)
497 switch (config->inclk & ASRCSR_AxCSx_MASK) { 459 switch (config->inclk & ASRCSR_AxCSx_MASK) {
498 case INCLK_NONE: 460 case INCLK_NONE:
499 /* Clear ASTSx bit to use ideal ratio */ 461 /* Clear ASTSx bit to use ideal ratio */
500 asrc_regmap_update_bits(asrc->regmap, REG_ASRCTR, 462 regmap_update_bits(asrc->regmap, REG_ASRCTR,
501 ASRCTR_ATSx_MASK(index), 0); 463 ASRCTR_ATSx_MASK(index), 0);
502 464
503 asrc_regmap_update_bits(asrc->regmap, REG_ASRCTR, 465 regmap_update_bits(asrc->regmap, REG_ASRCTR,
504 ASRCTR_IDRx_MASK(index) | ASRCTR_USRx_MASK(index), 466 ASRCTR_IDRx_MASK(index) | ASRCTR_USRx_MASK(index),
505 ASRCTR_IDR(index) | ASRCTR_USR(index)); 467 ASRCTR_IDR(index) | ASRCTR_USR(index));
506 468
@@ -540,13 +502,13 @@ int asrc_config_pair(struct asrc_config *config)
540 return -EINVAL; 502 return -EINVAL;
541 } 503 }
542 504
543 asrc_regmap_update_bits(asrc->regmap, REG_ASRMCR1(index), 505 regmap_update_bits(asrc->regmap, REG_ASRMCR1(index),
544 ASRMCR1x_OW16_MASK | ASRMCR1x_IWD_MASK, 506 ASRMCR1x_OW16_MASK | ASRMCR1x_IWD_MASK,
545 ASRMCR1x_OW16(config->output_word_width) | 507 ASRMCR1x_OW16(config->output_word_width) |
546 ASRMCR1x_IWD(config->input_word_width)); 508 ASRMCR1x_IWD(config->input_word_width));
547 509
548 /* Enable BUFFER STALL */ 510 /* Enable BUFFER STALL */
549 asrc_regmap_update_bits(asrc->regmap, REG_ASRMCR(index), 511 regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
550 ASRMCRx_BUFSTALLx_MASK, ASRMCRx_BUFSTALLx); 512 ASRMCRx_BUFSTALLx_MASK, ASRMCRx_BUFSTALLx);
551 513
552 /* Set Threshold for input and output FIFO */ 514 /* Set Threshold for input and output FIFO */
@@ -567,7 +529,7 @@ int asrc_set_watermark(enum asrc_pair_index index, u32 in_wm, u32 out_wm)
567 return -EINVAL; 529 return -EINVAL;
568 } 530 }
569 531
570 asrc_regmap_update_bits(asrc->regmap, REG_ASRMCR(index), 532 regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
571 ASRMCRx_EXTTHRSHx_MASK | ASRMCRx_INFIFO_THRESHOLD_MASK | 533 ASRMCRx_EXTTHRSHx_MASK | ASRMCRx_INFIFO_THRESHOLD_MASK |
572 ASRMCRx_OUTFIFO_THRESHOLD_MASK, 534 ASRMCRx_OUTFIFO_THRESHOLD_MASK,
573 ASRMCRx_EXTTHRSHx | ASRMCRx_INFIFO_THRESHOLD(in_wm) | 535 ASRMCRx_EXTTHRSHx | ASRMCRx_INFIFO_THRESHOLD(in_wm) |
@@ -579,25 +541,20 @@ EXPORT_SYMBOL(asrc_set_watermark);
579 541
580void asrc_start_conv(enum asrc_pair_index index) 542void asrc_start_conv(enum asrc_pair_index index)
581{ 543{
582 unsigned long lock_flags;
583 int reg, retry; 544 int reg, retry;
584 545
585 spin_lock_irqsave(&data_lock, lock_flags); 546 regmap_update_bits(asrc->regmap, REG_ASRCTR,
586
587 asrc_regmap_update_bits(asrc->regmap, REG_ASRCTR,
588 ASRCTR_ASRCEx_MASK(index), ASRCTR_ASRCE(index)); 547 ASRCTR_ASRCEx_MASK(index), ASRCTR_ASRCE(index));
589 548
590 /* Wait for status of initialization */ 549 /* Wait for status of initialization */
591 for (retry = 10, reg = 0; !reg && retry; --retry) { 550 for (retry = 10, reg = 0; !reg && retry; --retry) {
592 udelay(5); 551 udelay(5);
593 asrc_regmap_read(asrc->regmap, REG_ASRCFG, &reg); 552 regmap_read(asrc->regmap, REG_ASRCFG, &reg);
594 reg &= ASRCFG_INIRQx_MASK(index); 553 reg &= ASRCFG_INIRQx_MASK(index);
595 } 554 }
596 555
597 /* Overload Interrupt Enable */ 556 /* Overload Interrupt Enable */
598 asrc_regmap_write(asrc->regmap, REG_ASRIER, ASRIER_AOLIE); 557 regmap_write(asrc->regmap, REG_ASRIER, ASRIER_AOLIE);
599
600 spin_unlock_irqrestore(&data_lock, lock_flags);
601 558
602 return; 559 return;
603} 560}
@@ -605,22 +562,14 @@ EXPORT_SYMBOL(asrc_start_conv);
605 562
606void asrc_stop_conv(enum asrc_pair_index index) 563void asrc_stop_conv(enum asrc_pair_index index)
607{ 564{
608 unsigned long lock_flags; 565 regmap_update_bits(asrc->regmap, REG_ASRCTR,
609
610 spin_lock_irqsave(&data_lock, lock_flags);
611
612 asrc_regmap_update_bits(asrc->regmap, REG_ASRCTR,
613 ASRCTR_ASRCEx_MASK(index), 0); 566 ASRCTR_ASRCEx_MASK(index), 0);
614
615 spin_unlock_irqrestore(&data_lock, lock_flags);
616
617 return;
618} 567}
619EXPORT_SYMBOL(asrc_stop_conv); 568EXPORT_SYMBOL(asrc_stop_conv);
620 569
621void asrc_finish_conv(enum asrc_pair_index index) 570void asrc_finish_conv(enum asrc_pair_index index)
622{ 571{
623 clk_disable(asrc->dma_clk); 572 clk_disable_unprepare(asrc->dma_clk);
624 clk_disable(asrc->asrc_clk); 573 clk_disable(asrc->asrc_clk);
625 return; 574 return;
626} 575}
@@ -634,7 +583,7 @@ static irqreturn_t asrc_isr(int irq, void *dev_id)
634 enum asrc_pair_index index; 583 enum asrc_pair_index index;
635 u32 status; 584 u32 status;
636 585
637 asrc_regmap_read(asrc->regmap, REG_ASRSTR, &status); 586 regmap_read(asrc->regmap, REG_ASRSTR, &status);
638 587
639 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) { 588 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
640 if (asrc->asrc_pair[index].active == 0) 589 if (asrc->asrc_pair[index].active == 0)
@@ -652,8 +601,7 @@ static irqreturn_t asrc_isr(int irq, void *dev_id)
652 } 601 }
653 602
654 /* Clean overload error */ 603 /* Clean overload error */
655 asrc_regmap_update_bits(asrc->regmap, REG_ASRSTR, 604 regmap_write(asrc->regmap, REG_ASRSTR, ASRSTR_AOLE);
656 ASRSTR_AOLE_MASK, ASRSTR_AOLE);
657 605
658 return IRQ_HANDLED; 606 return IRQ_HANDLED;
659} 607}
@@ -683,13 +631,11 @@ EXPORT_SYMBOL(asrc_get_per_addr);
683 631
684static int mxc_init_asrc(void) 632static int mxc_init_asrc(void)
685{ 633{
686 clk_enable(asrc->asrc_clk);
687
688 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */ 634 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
689 asrc_regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN); 635 regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
690 636
691 /* Disable interrupt by default */ 637 /* Disable interrupt by default */
692 asrc_regmap_write(asrc->regmap, REG_ASRIER, 0x0); 638 regmap_write(asrc->regmap, REG_ASRIER, 0x0);
693 639
694 /* Default 2: 6: 2 channel assignment */ 640 /* Default 2: 6: 2 channel assignment */
695 asrc_set_channel_number(ASRC_PAIR_A, 2); 641 asrc_set_channel_number(ASRC_PAIR_A, 2);
@@ -697,23 +643,21 @@ static int mxc_init_asrc(void)
697 asrc_set_channel_number(ASRC_PAIR_C, 2); 643 asrc_set_channel_number(ASRC_PAIR_C, 2);
698 644
699 /* Parameter Registers recommended settings */ 645 /* Parameter Registers recommended settings */
700 asrc_regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff); 646 regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff);
701 asrc_regmap_write(asrc->regmap, REG_ASRPM2, 0x255555); 647 regmap_write(asrc->regmap, REG_ASRPM2, 0x255555);
702 asrc_regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280); 648 regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280);
703 asrc_regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280); 649 regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280);
704 asrc_regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280); 650 regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280);
705 651
706 /* Base address for task queue FIFO. Set to 0x7C */ 652 /* Base address for task queue FIFO. Set to 0x7C */
707 asrc_regmap_update_bits(asrc->regmap, REG_ASRTFR1, 653 regmap_update_bits(asrc->regmap, REG_ASRTFR1,
708 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc)); 654 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
709 655
710 /* Set the processing clock for 76KHz, 133M */ 656 /* Set the processing clock for 76KHz, 133M */
711 asrc_regmap_write(asrc->regmap, REG_ASR76K, 0x06D6); 657 regmap_write(asrc->regmap, REG_ASR76K, 0x06D6);
712 658
713 /* Set the processing clock for 56KHz, 133M */ 659 /* Set the processing clock for 56KHz, 133M */
714 asrc_regmap_write(asrc->regmap, REG_ASR56K, 0x0947); 660 regmap_write(asrc->regmap, REG_ASR56K, 0x0947);
715
716 clk_disable(asrc->asrc_clk);
717 661
718 return 0; 662 return 0;
719} 663}
@@ -753,7 +697,7 @@ static unsigned int asrc_get_output_FIFO_size(enum asrc_pair_index index)
753{ 697{
754 u32 val; 698 u32 val;
755 699
756 asrc_regmap_read(asrc->regmap, REG_ASRFST(index), &val); 700 regmap_read(asrc->regmap, REG_ASRFST(index), &val);
757 701
758 val &= ASRFSTx_OUTPUT_FIFO_MASK; 702 val &= ASRFSTx_OUTPUT_FIFO_MASK;
759 703
@@ -764,7 +708,7 @@ static unsigned int asrc_get_input_FIFO_size(enum asrc_pair_index index)
764{ 708{
765 u32 val; 709 u32 val;
766 710
767 asrc_regmap_read(asrc->regmap, REG_ASRFST(index), &val); 711 regmap_read(asrc->regmap, REG_ASRFST(index), &val);
768 712
769 val &= ASRFSTx_INPUT_FIFO_MASK; 713 val &= ASRFSTx_INPUT_FIFO_MASK;
770 714
@@ -775,14 +719,14 @@ static u32 asrc_read_one_from_output_FIFO(enum asrc_pair_index index)
775{ 719{
776 u32 val; 720 u32 val;
777 721
778 asrc_regmap_read(asrc->regmap, REG_ASRDO(index), &val); 722 regmap_read(asrc->regmap, REG_ASRDO(index), &val);
779 723
780 return val; 724 return val;
781} 725}
782 726
783static void asrc_write_one_to_output_FIFO(enum asrc_pair_index index, u32 val) 727static void asrc_write_one_to_output_FIFO(enum asrc_pair_index index, u32 val)
784{ 728{
785 asrc_regmap_write(asrc->regmap, REG_ASRDI(index), val); 729 regmap_write(asrc->regmap, REG_ASRDI(index), val);
786} 730}
787 731
788static void asrc_read_output_FIFO(struct asrc_pair_params *params) 732static void asrc_read_output_FIFO(struct asrc_pair_params *params)
@@ -1660,7 +1604,7 @@ static int asrc_read_proc_attr(struct file *file, char __user *buf,
1660 if (*off) 1604 if (*off)
1661 return 0; 1605 return 0;
1662 1606
1663 asrc_regmap_read(asrc->regmap, REG_ASRCNCR, &reg); 1607 regmap_read(asrc->regmap, REG_ASRCNCR, &reg);
1664 1608
1665 len += sprintf(tmpbuf, "ANCA: %d\nANCB: %d\nANCC: %d\n", 1609 len += sprintf(tmpbuf, "ANCA: %d\nANCB: %d\nANCC: %d\n",
1666 (int)ASRCNCR_ANCA_get(reg, asrc->channel_bits), 1610 (int)ASRCNCR_ANCA_get(reg, asrc->channel_bits),
@@ -1754,9 +1698,6 @@ static void asrc_proc_remove(void)
1754} 1698}
1755 1699
1756 1700
1757#ifdef ASRC_USE_REGMAP
1758/* ============= ASRC REGMAP ============= */
1759
1760static bool asrc_readable_reg(struct device *dev, unsigned int reg) 1701static bool asrc_readable_reg(struct device *dev, unsigned int reg)
1761{ 1702{
1762 switch (reg) { 1703 switch (reg) {
@@ -1811,6 +1752,7 @@ static bool asrc_writeable_reg(struct device *dev, unsigned int reg)
1811 case REG_ASRCSR: 1752 case REG_ASRCSR:
1812 case REG_ASRCDR1: 1753 case REG_ASRCDR1:
1813 case REG_ASRCDR2: 1754 case REG_ASRCDR2:
1755 case REG_ASRSTR:
1814 case REG_ASRPM1: 1756 case REG_ASRPM1:
1815 case REG_ASRPM2: 1757 case REG_ASRPM2:
1816 case REG_ASRPM3: 1758 case REG_ASRPM3:
@@ -1841,13 +1783,7 @@ static bool asrc_writeable_reg(struct device *dev, unsigned int reg)
1841 } 1783 }
1842} 1784}
1843 1785
1844static bool asrc_volatile_reg(struct device *dev, unsigned int reg) 1786static struct regmap_config asrc_regmap_config = {
1845{
1846 /* Sync all registers after reset */
1847 return true;
1848}
1849
1850static const struct regmap_config asrc_regmap_config = {
1851 .reg_bits = 32, 1787 .reg_bits = 32,
1852 .reg_stride = 4, 1788 .reg_stride = 4,
1853 .val_bits = 32, 1789 .val_bits = 32,
@@ -1855,10 +1791,7 @@ static const struct regmap_config asrc_regmap_config = {
1855 .max_register = REG_ASRMCR1C, 1791 .max_register = REG_ASRMCR1C,
1856 .readable_reg = asrc_readable_reg, 1792 .readable_reg = asrc_readable_reg,
1857 .writeable_reg = asrc_writeable_reg, 1793 .writeable_reg = asrc_writeable_reg,
1858 .volatile_reg = asrc_volatile_reg,
1859 .cache_type = REGCACHE_RBTREE,
1860}; 1794};
1861#endif
1862 1795
1863static int mxc_asrc_probe(struct platform_device *pdev) 1796static int mxc_asrc_probe(struct platform_device *pdev)
1864{ 1797{
@@ -1902,9 +1835,8 @@ static int mxc_asrc_probe(struct platform_device *pdev)
1902 dev_err(&pdev->dev, "failed to map io resources.\n"); 1835 dev_err(&pdev->dev, "failed to map io resources.\n");
1903 return IS_ERR(regs); 1836 return IS_ERR(regs);
1904 } 1837 }
1905 asrc->vaddr = (unsigned long)regs;
1906 1838
1907#ifdef ASRC_USE_REGMAP 1839 /* Register regmap and let it prepare core clock */
1908 asrc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 1840 asrc->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
1909 "core", regs, &asrc_regmap_config); 1841 "core", regs, &asrc_regmap_config);
1910 if (IS_ERR(asrc->regmap)) { 1842 if (IS_ERR(asrc->regmap)) {
@@ -1912,9 +1844,6 @@ static int mxc_asrc_probe(struct platform_device *pdev)
1912 ret = PTR_ERR(asrc->regmap); 1844 ret = PTR_ERR(asrc->regmap);
1913 } 1845 }
1914 1846
1915 regcache_cache_only(asrc->regmap, false);
1916#endif
1917
1918 asrc->irq = irq_of_parse_and_map(np, 0); 1847 asrc->irq = irq_of_parse_and_map(np, 0);
1919 if (asrc->irq == NO_IRQ) { 1848 if (asrc->irq == NO_IRQ) {
1920 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); 1849 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
@@ -1939,10 +1868,6 @@ static int mxc_asrc_probe(struct platform_device *pdev)
1939 ret = PTR_ERR(asrc->dma_clk); 1868 ret = PTR_ERR(asrc->dma_clk);
1940 goto err_iomap; 1869 goto err_iomap;
1941 } 1870 }
1942#ifndef ASRC_USE_REGMAP
1943 clk_prepare(asrc->asrc_clk);
1944 clk_prepare(asrc->dma_clk);
1945#endif
1946 1871
1947 ret = of_property_read_u32_array(pdev->dev.of_node, 1872 ret = of_property_read_u32_array(pdev->dev.of_node,
1948 "fsl,clk-channel-bits", &asrc->channel_bits, 1); 1873 "fsl,clk-channel-bits", &asrc->channel_bits, 1);
@@ -1998,10 +1923,6 @@ err_iomap:
1998 1923
1999static int mxc_asrc_remove(struct platform_device *pdev) 1924static int mxc_asrc_remove(struct platform_device *pdev)
2000{ 1925{
2001#ifndef ASRC_USE_REGMAP
2002 clk_unprepare(asrc->dma_clk);
2003 clk_unprepare(asrc->asrc_clk);
2004#endif
2005 asrc_proc_remove(); 1926 asrc_proc_remove();
2006 misc_deregister(&asrc_miscdev); 1927 misc_deregister(&asrc_miscdev);
2007 1928
diff --git a/include/linux/mxc_asrc.h b/include/linux/mxc_asrc.h
index ef56f3270b96..4397b9713a75 100644
--- a/include/linux/mxc_asrc.h
+++ b/include/linux/mxc_asrc.h
@@ -349,7 +349,6 @@ struct asrc_data {
349 struct asrc_pair asrc_pair[3]; 349 struct asrc_pair asrc_pair[3];
350 struct proc_dir_entry *proc_asrc; 350 struct proc_dir_entry *proc_asrc;
351 struct regmap *regmap; 351 struct regmap *regmap;
352 unsigned long vaddr;
353 unsigned long paddr; 352 unsigned long paddr;
354 struct class *asrc_class; 353 struct class *asrc_class;
355 int asrc_major; 354 int asrc_major;