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authorAlex Deucher <alexdeucher@gmail.com>2009-12-23 03:23:21 -0500
committerDave Airlie <airlied@redhat.com>2010-02-08 18:31:10 -0500
commit40bacf1631a3e8654b1128aa9b72e73ca801c9e4 (patch)
tree9d4dc63b4dfb124203335dd4e541c657417960ce
parent5a6f98f5bff7f975c61d56b5c756b5a96c4db167 (diff)
drm/radeon/kms: add support for hw i2c on r1xx-r5xx
wire hw i2c support into radeon i2c algo. fixes merged: - handle bus probing correctly - use meaningful error numbers - abort if transaction fails - The line mapping is different depending on the asic. - protect hw i2c engine with a mutex - rs300 doesn't have a pin select bit - r200 has a different pin select setup Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/r500_reg.h100
-rw-r--r--drivers/gpu/drm/radeon/radeon.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c71
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_i2c.c597
-rw-r--r--drivers/gpu/drm/radeon/radeon_reg.h48
6 files changed, 736 insertions, 82 deletions
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h
index 74ad89bdf2b5..0cf2ad2a5585 100644
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -717,54 +717,62 @@
717#define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 717#define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988
718 718
719#define AVIVO_DC_GPIO_HPD_A 0x7e94 719#define AVIVO_DC_GPIO_HPD_A 0x7e94
720
721#define AVIVO_GPIO_0 0x7e30
722#define AVIVO_GPIO_1 0x7e40
723#define AVIVO_GPIO_2 0x7e50
724#define AVIVO_GPIO_3 0x7e60
725
726#define AVIVO_DC_GPIO_HPD_Y 0x7e9c 720#define AVIVO_DC_GPIO_HPD_Y 0x7e9c
727 721
728#define AVIVO_I2C_STATUS 0x7d30 722#define AVIVO_DC_I2C_STATUS1 0x7d30
729# define AVIVO_I2C_STATUS_DONE (1 << 0) 723# define AVIVO_DC_I2C_DONE (1 << 0)
730# define AVIVO_I2C_STATUS_NACK (1 << 1) 724# define AVIVO_DC_I2C_NACK (1 << 1)
731# define AVIVO_I2C_STATUS_HALT (1 << 2) 725# define AVIVO_DC_I2C_HALT (1 << 2)
732# define AVIVO_I2C_STATUS_GO (1 << 3) 726# define AVIVO_DC_I2C_GO (1 << 3)
733# define AVIVO_I2C_STATUS_MASK 0x7 727#define AVIVO_DC_I2C_RESET 0x7d34
734/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe 728# define AVIVO_DC_I2C_SOFT_RESET (1 << 0)
735 * DONE? */ 729# define AVIVO_DC_I2C_ABORT (1 << 8)
736# define AVIVO_I2C_STATUS_CMD_RESET 0x7 730#define AVIVO_DC_I2C_CONTROL1 0x7d38
737# define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3) 731# define AVIVO_DC_I2C_START (1 << 0)
738#define AVIVO_I2C_STOP 0x7d34 732# define AVIVO_DC_I2C_STOP (1 << 1)
739#define AVIVO_I2C_START_CNTL 0x7d38 733# define AVIVO_DC_I2C_RECEIVE (1 << 2)
740# define AVIVO_I2C_START (1 << 8) 734# define AVIVO_DC_I2C_EN (1 << 8)
741# define AVIVO_I2C_CONNECTOR0 (0 << 16) 735# define AVIVO_DC_I2C_PIN_SELECT(x) ((x) << 16)
742# define AVIVO_I2C_CONNECTOR1 (1 << 16) 736# define AVIVO_SEL_DDC1 0
743#define R520_I2C_START (1<<0) 737# define AVIVO_SEL_DDC2 1
744#define R520_I2C_STOP (1<<1) 738# define AVIVO_SEL_DDC3 2
745#define R520_I2C_RX (1<<2) 739#define AVIVO_DC_I2C_CONTROL2 0x7d3c
746#define R520_I2C_EN (1<<8) 740# define AVIVO_DC_I2C_ADDR_COUNT(x) ((x) << 0)
747#define R520_I2C_DDC1 (0<<16) 741# define AVIVO_DC_I2C_DATA_COUNT(x) ((x) << 8)
748#define R520_I2C_DDC2 (1<<16) 742#define AVIVO_DC_I2C_CONTROL3 0x7d40
749#define R520_I2C_DDC3 (2<<16) 743# define AVIVO_DC_I2C_DATA_DRIVE_EN (1 << 0)
750#define R520_I2C_DDC_MASK (3<<16) 744# define AVIVO_DC_I2C_DATA_DRIVE_SEL (1 << 1)
751#define AVIVO_I2C_CONTROL2 0x7d3c 745# define AVIVO_DC_I2C_CLK_DRIVE_EN (1 << 7)
752# define AVIVO_I2C_7D3C_SIZE_SHIFT 8 746# define AVIVO_DC_I2C_RD_INTRA_BYTE_DELAY(x) ((x) << 8)
753# define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8) 747# define AVIVO_DC_I2C_WR_INTRA_BYTE_DELAY(x) ((x) << 16)
754#define AVIVO_I2C_CONTROL3 0x7d40 748# define AVIVO_DC_I2C_TIME_LIMIT(x) ((x) << 24)
755/* Reading is done 4 bytes at a time: read the bottom 8 bits from 749#define AVIVO_DC_I2C_DATA 0x7d44
756 * 7d44, four times in a row. 750#define AVIVO_DC_I2C_INTERRUPT_CONTROL 0x7d48
757 * Writing is a little more complex. First write DATA with 751# define AVIVO_DC_I2C_INTERRUPT_STATUS (1 << 0)
758 * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic 752# define AVIVO_DC_I2C_INTERRUPT_AK (1 << 8)
759 * magic number, zz is, I think, the slave address, and yy is the byte 753# define AVIVO_DC_I2C_INTERRUPT_ENABLE (1 << 16)
760 * you want to write. */ 754#define AVIVO_DC_I2C_ARBITRATION 0x7d50
761#define AVIVO_I2C_DATA 0x7d44 755# define AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C (1 << 0)
762#define R520_I2C_ADDR_COUNT_MASK (0x7) 756# define AVIVO_DC_I2C_SW_CAN_USE_I2C (1 << 1)
763#define R520_I2C_DATA_COUNT_SHIFT (8) 757# define AVIVO_DC_I2C_SW_DONE_USING_I2C (1 << 8)
764#define R520_I2C_DATA_COUNT_MASK (0xF00) 758# define AVIVO_DC_I2C_HW_NEEDS_I2C (1 << 9)
765#define AVIVO_I2C_CNTL 0x7d50 759# define AVIVO_DC_I2C_ABORT_HDCP_I2C (1 << 16)
766# define AVIVO_I2C_EN (1 << 0) 760# define AVIVO_DC_I2C_HW_USING_I2C (1 << 17)
767# define AVIVO_I2C_RESET (1 << 8) 761
762#define AVIVO_DC_GPIO_DDC1_MASK 0x7e40
763#define AVIVO_DC_GPIO_DDC1_A 0x7e44
764#define AVIVO_DC_GPIO_DDC1_EN 0x7e48
765#define AVIVO_DC_GPIO_DDC1_Y 0x7e4c
766
767#define AVIVO_DC_GPIO_DDC2_MASK 0x7e50
768#define AVIVO_DC_GPIO_DDC2_A 0x7e54
769#define AVIVO_DC_GPIO_DDC2_EN 0x7e58
770#define AVIVO_DC_GPIO_DDC2_Y 0x7e5c
771
772#define AVIVO_DC_GPIO_DDC3_MASK 0x7e60
773#define AVIVO_DC_GPIO_DDC3_A 0x7e64
774#define AVIVO_DC_GPIO_DDC3_EN 0x7e68
775#define AVIVO_DC_GPIO_DDC3_Y 0x7e6c
768 776
769#define AVIVO_DISP_INTERRUPT_STATUS 0x7edc 777#define AVIVO_DISP_INTERRUPT_STATUS 0x7edc
770# define AVIVO_D1_VBLANK_INTERRUPT (1 << 4) 778# define AVIVO_D1_VBLANK_INTERRUPT (1 << 4)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index f57480ba1355..88113f756ab7 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -829,6 +829,7 @@ struct radeon_device {
829 struct r600_ih ih; /* r6/700 interrupt ring */ 829 struct r600_ih ih; /* r6/700 interrupt ring */
830 struct workqueue_struct *wq; 830 struct workqueue_struct *wq;
831 struct work_struct hotplug_work; 831 struct work_struct hotplug_work;
832 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
832 833
833 /* audio stuff */ 834 /* audio stuff */
834 struct timer_list audio_timer; 835 struct timer_list audio_timer;
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 318afe83e6b0..e208d730f514 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -486,9 +486,65 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
486 i2c.y_data_reg = ddc_line; 486 i2c.y_data_reg = ddc_line;
487 } 487 }
488 488
489 if (rdev->family < CHIP_R200) 489 switch (rdev->family) {
490 i2c.hw_capable = false; 490 case CHIP_R100:
491 else { 491 case CHIP_RV100:
492 case CHIP_RS100:
493 case CHIP_RV200:
494 case CHIP_RS200:
495 case CHIP_RS300:
496 switch (ddc_line) {
497 case RADEON_GPIO_DVI_DDC:
498 /* in theory this should be hw capable,
499 * but it doesn't seem to work
500 */
501 i2c.hw_capable = false;
502 break;
503 default:
504 i2c.hw_capable = false;
505 break;
506 }
507 break;
508 case CHIP_R200:
509 switch (ddc_line) {
510 case RADEON_GPIO_DVI_DDC:
511 case RADEON_GPIO_MONID:
512 i2c.hw_capable = true;
513 break;
514 default:
515 i2c.hw_capable = false;
516 break;
517 }
518 break;
519 case CHIP_RV250:
520 case CHIP_RV280:
521 switch (ddc_line) {
522 case RADEON_GPIO_VGA_DDC:
523 case RADEON_GPIO_DVI_DDC:
524 case RADEON_GPIO_CRT2_DDC:
525 i2c.hw_capable = true;
526 break;
527 default:
528 i2c.hw_capable = false;
529 break;
530 }
531 break;
532 case CHIP_R300:
533 case CHIP_R350:
534 switch (ddc_line) {
535 case RADEON_GPIO_VGA_DDC:
536 case RADEON_GPIO_DVI_DDC:
537 i2c.hw_capable = true;
538 break;
539 default:
540 i2c.hw_capable = false;
541 break;
542 }
543 break;
544 case CHIP_RV350:
545 case CHIP_RV380:
546 case CHIP_RS400:
547 case CHIP_RS480:
492 switch (ddc_line) { 548 switch (ddc_line) {
493 case RADEON_GPIO_VGA_DDC: 549 case RADEON_GPIO_VGA_DDC:
494 case RADEON_GPIO_DVI_DDC: 550 case RADEON_GPIO_DVI_DDC:
@@ -504,6 +560,10 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
504 i2c.hw_capable = false; 560 i2c.hw_capable = false;
505 break; 561 break;
506 } 562 }
563 break;
564 default:
565 i2c.hw_capable = false;
566 break;
507 } 567 }
508 i2c.mm_i2c = false; 568 i2c.mm_i2c = false;
509 i2c.i2c_id = 0; 569 i2c.i2c_id = 0;
@@ -1253,7 +1313,10 @@ bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder
1253 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1313 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1254 break; 1314 break;
1255 case DDC_LCD: /* MM i2c */ 1315 case DDC_LCD: /* MM i2c */
1256 DRM_ERROR("MM i2c requires hw i2c engine\n"); 1316 i2c_bus.valid = true;
1317 i2c_bus.hw_capable = true;
1318 i2c_bus.mm_i2c = true;
1319 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1257 break; 1320 break;
1258 default: 1321 default:
1259 DRM_ERROR("Unsupported gpio %d\n", gpio); 1322 DRM_ERROR("Unsupported gpio %d\n", gpio);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 768b1509fa03..18ac29c505cf 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -638,6 +638,7 @@ int radeon_device_init(struct radeon_device *rdev,
638 mutex_init(&rdev->cs_mutex); 638 mutex_init(&rdev->cs_mutex);
639 mutex_init(&rdev->ib_pool.mutex); 639 mutex_init(&rdev->ib_pool.mutex);
640 mutex_init(&rdev->cp.mutex); 640 mutex_init(&rdev->cp.mutex);
641 mutex_init(&rdev->dc_hw_i2c_mutex);
641 if (rdev->family >= CHIP_R600) 642 if (rdev->family >= CHIP_R600)
642 spin_lock_init(&rdev->ih.lock); 643 spin_lock_init(&rdev->ih.lock);
643 mutex_init(&rdev->gem.mutex); 644 mutex_init(&rdev->gem.mutex);
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index 75b090f60208..b47a5615fe6a 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -26,6 +26,7 @@
26#include "drmP.h" 26#include "drmP.h"
27#include "radeon_drm.h" 27#include "radeon_drm.h"
28#include "radeon.h" 28#include "radeon.h"
29#include "atom.h"
29 30
30/** 31/**
31 * radeon_ddc_probe 32 * radeon_ddc_probe
@@ -71,13 +72,25 @@ static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
71 */ 72 */
72 if (rec->hw_capable) { 73 if (rec->hw_capable) {
73 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { 74 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
74 if (rec->a_clk_reg == RADEON_GPIO_MONID) { 75 u32 reg;
76
77 if (rdev->family >= CHIP_RV350)
78 reg = RADEON_GPIO_MONID;
79 else if ((rdev->family == CHIP_R300) ||
80 (rdev->family == CHIP_R350))
81 reg = RADEON_GPIO_DVI_DDC;
82 else
83 reg = RADEON_GPIO_CRT2_DDC;
84
85 mutex_lock(&rdev->dc_hw_i2c_mutex);
86 if (rec->a_clk_reg == reg) {
75 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 87 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
76 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); 88 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
77 } else { 89 } else {
78 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 90 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
79 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); 91 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
80 } 92 }
93 mutex_unlock(&rdev->dc_hw_i2c_mutex);
81 } 94 }
82 } 95 }
83 96
@@ -168,22 +181,584 @@ static void set_data(void *i2c_priv, int data)
168 WREG32(rec->en_data_reg, val); 181 WREG32(rec->en_data_reg, val);
169} 182}
170 183
171static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap, 184/* hw i2c engine for r1xx-4xx hardware
172 struct i2c_msg *msgs, int num) 185 * hw can buffer up to 15 bytes
186 */
187static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
188 struct i2c_msg *msgs, int num)
189{
190 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
191 struct radeon_device *rdev = i2c->dev->dev_private;
192 struct radeon_i2c_bus_rec *rec = &i2c->rec;
193 struct i2c_msg *p;
194 int i, j, k, ret = num;
195 /* XXX: use get_engine_clock() to get the current sclk */
196 u32 prescale = (((rdev->clock.default_sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
197 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
198 u32 tmp, reg;
199
200 mutex_lock(&rdev->dc_hw_i2c_mutex);
201
202 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
203 RADEON_I2C_START |
204 RADEON_I2C_STOP |
205 RADEON_I2C_GO);
206
207 if (rdev->is_atom_bios) {
208 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
209 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
210 }
211
212 if (rec->mm_i2c) {
213 i2c_cntl_0 = RADEON_I2C_CNTL_0;
214 i2c_cntl_1 = RADEON_I2C_CNTL_1;
215 i2c_data = RADEON_I2C_DATA;
216 } else {
217 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
218 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
219 i2c_data = RADEON_DVI_I2C_DATA;
220
221 switch (rdev->family) {
222 case CHIP_R100:
223 case CHIP_RV100:
224 case CHIP_RS100:
225 case CHIP_RV200:
226 case CHIP_RS200:
227 case CHIP_RS300:
228 switch (rec->mask_clk_reg) {
229 case RADEON_GPIO_DVI_DDC:
230 /* no gpio select bit */
231 break;
232 default:
233 DRM_ERROR("gpio not supported with hw i2c\n");
234 ret = -EINVAL;
235 goto done;
236 }
237 break;
238 case CHIP_R200:
239 /* only bit 4 on r200 */
240 switch (rec->mask_clk_reg) {
241 case RADEON_GPIO_DVI_DDC:
242 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
243 break;
244 case RADEON_GPIO_MONID:
245 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
246 break;
247 default:
248 DRM_ERROR("gpio not supported with hw i2c\n");
249 ret = -EINVAL;
250 goto done;
251 }
252 break;
253 case CHIP_RV250:
254 case CHIP_RV280:
255 /* bits 3 and 4 */
256 switch (rec->mask_clk_reg) {
257 case RADEON_GPIO_DVI_DDC:
258 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
259 break;
260 case RADEON_GPIO_VGA_DDC:
261 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
262 break;
263 case RADEON_GPIO_CRT2_DDC:
264 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
265 break;
266 default:
267 DRM_ERROR("gpio not supported with hw i2c\n");
268 ret = -EINVAL;
269 goto done;
270 }
271 break;
272 case CHIP_R300:
273 case CHIP_R350:
274 /* only bit 4 on r300/r350 */
275 switch (rec->mask_clk_reg) {
276 case RADEON_GPIO_VGA_DDC:
277 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
278 break;
279 case RADEON_GPIO_DVI_DDC:
280 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
281 break;
282 default:
283 DRM_ERROR("gpio not supported with hw i2c\n");
284 ret = -EINVAL;
285 goto done;
286 }
287 break;
288 case CHIP_RV350:
289 case CHIP_RV380:
290 case CHIP_R420:
291 case CHIP_R423:
292 case CHIP_RV410:
293 case CHIP_RS400:
294 case CHIP_RS480:
295 /* bits 3 and 4 */
296 switch (rec->mask_clk_reg) {
297 case RADEON_GPIO_VGA_DDC:
298 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
299 break;
300 case RADEON_GPIO_DVI_DDC:
301 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
302 break;
303 case RADEON_GPIO_MONID:
304 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
305 break;
306 default:
307 DRM_ERROR("gpio not supported with hw i2c\n");
308 ret = -EINVAL;
309 goto done;
310 }
311 break;
312 default:
313 DRM_ERROR("unsupported asic\n");
314 ret = -EINVAL;
315 goto done;
316 break;
317 }
318 }
319
320 /* check for bus probe */
321 p = &msgs[0];
322 if ((num == 1) && (p->len == 0)) {
323 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
324 RADEON_I2C_NACK |
325 RADEON_I2C_HALT |
326 RADEON_I2C_SOFT_RST));
327 WREG32(i2c_data, (p->addr << 1) & 0xff);
328 WREG32(i2c_data, 0);
329 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
330 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
331 RADEON_I2C_EN |
332 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
333 WREG32(i2c_cntl_0, reg);
334 for (k = 0; k < 32; k++) {
335 udelay(10);
336 tmp = RREG32(i2c_cntl_0);
337 if (tmp & RADEON_I2C_GO)
338 continue;
339 tmp = RREG32(i2c_cntl_0);
340 if (tmp & RADEON_I2C_DONE)
341 break;
342 else {
343 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
344 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
345 ret = -EIO;
346 goto done;
347 }
348 }
349 goto done;
350 }
351
352 for (i = 0; i < num; i++) {
353 p = &msgs[i];
354 for (j = 0; j < p->len; j++) {
355 if (p->flags & I2C_M_RD) {
356 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
357 RADEON_I2C_NACK |
358 RADEON_I2C_HALT |
359 RADEON_I2C_SOFT_RST));
360 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
361 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
362 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
363 RADEON_I2C_EN |
364 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
365 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
366 for (k = 0; k < 32; k++) {
367 udelay(10);
368 tmp = RREG32(i2c_cntl_0);
369 if (tmp & RADEON_I2C_GO)
370 continue;
371 tmp = RREG32(i2c_cntl_0);
372 if (tmp & RADEON_I2C_DONE)
373 break;
374 else {
375 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
376 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
377 ret = -EIO;
378 goto done;
379 }
380 }
381 p->buf[j] = RREG32(i2c_data) & 0xff;
382 } else {
383 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
384 RADEON_I2C_NACK |
385 RADEON_I2C_HALT |
386 RADEON_I2C_SOFT_RST));
387 WREG32(i2c_data, (p->addr << 1) & 0xff);
388 WREG32(i2c_data, p->buf[j]);
389 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
390 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
391 RADEON_I2C_EN |
392 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
393 WREG32(i2c_cntl_0, reg);
394 for (k = 0; k < 32; k++) {
395 udelay(10);
396 tmp = RREG32(i2c_cntl_0);
397 if (tmp & RADEON_I2C_GO)
398 continue;
399 tmp = RREG32(i2c_cntl_0);
400 if (tmp & RADEON_I2C_DONE)
401 break;
402 else {
403 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
404 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
405 ret = -EIO;
406 goto done;
407 }
408 }
409 }
410 }
411 }
412
413done:
414 WREG32(i2c_cntl_0, 0);
415 WREG32(i2c_cntl_1, 0);
416 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
417 RADEON_I2C_NACK |
418 RADEON_I2C_HALT |
419 RADEON_I2C_SOFT_RST));
420
421 if (rdev->is_atom_bios) {
422 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
423 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
424 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
425 }
426
427 mutex_unlock(&rdev->dc_hw_i2c_mutex);
428
429 return ret;
430}
431
432/* hw i2c engine for r5xx hardware
433 * hw can buffer up to 15 bytes
434 */
435static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
436 struct i2c_msg *msgs, int num)
437{
438 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
439 struct radeon_device *rdev = i2c->dev->dev_private;
440 struct radeon_i2c_bus_rec *rec = &i2c->rec;
441 struct i2c_msg *p;
442 int i2c_clock = 50;
443 int i, j, remaining, current_count, buffer_offset, ret = num;
444 /* XXX: use get_engine_clock() to get the current sclk */
445 u32 prescale;
446 u32 tmp, reg;
447 u32 saved1, saved2;
448
449 mutex_lock(&rdev->dc_hw_i2c_mutex);
450
451 /* clear gpio mask bits */
452 tmp = RREG32(rec->mask_clk_reg);
453 tmp &= ~rec->mask_clk_mask;
454 WREG32(rec->mask_clk_reg, tmp);
455 tmp = RREG32(rec->mask_clk_reg);
456
457 tmp = RREG32(rec->mask_data_reg);
458 tmp &= ~rec->mask_data_mask;
459 WREG32(rec->mask_data_reg, tmp);
460 tmp = RREG32(rec->mask_data_reg);
461
462 /* clear pin values */
463 tmp = RREG32(rec->a_clk_reg);
464 tmp &= ~rec->a_clk_mask;
465 WREG32(rec->a_clk_reg, tmp);
466 tmp = RREG32(rec->a_clk_reg);
467
468 tmp = RREG32(rec->a_data_reg);
469 tmp &= ~rec->a_data_mask;
470 WREG32(rec->a_data_reg, tmp);
471 tmp = RREG32(rec->a_data_reg);
472
473 /* set the pins to input */
474 tmp = RREG32(rec->en_clk_reg);
475 tmp &= ~rec->en_clk_mask;
476 WREG32(rec->en_clk_reg, tmp);
477 tmp = RREG32(rec->en_clk_reg);
478
479 tmp = RREG32(rec->en_data_reg);
480 tmp &= ~rec->en_data_mask;
481 WREG32(rec->en_data_reg, tmp);
482 tmp = RREG32(rec->en_data_reg);
483
484 /* */
485 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
486 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
487 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
488 saved2 = RREG32(0x494);
489 WREG32(0x494, saved2 | 0x1);
490
491 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
492 for (i = 0; i < 50; i++) {
493 udelay(1);
494 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
495 break;
496 }
497 if (i == 50) {
498 DRM_ERROR("failed to get i2c bus\n");
499 ret = -EBUSY;
500 goto done;
501 }
502
503 if (rdev->family == CHIP_R520)
504 prescale = (127 << 8) + ((rdev->clock.default_sclk * 10) / (4 * 127 * i2c_clock));
505 else
506 prescale = (((rdev->clock.default_sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
507
508 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
509 switch (rec->mask_clk_reg) {
510 case AVIVO_DC_GPIO_DDC1_MASK:
511 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
512 break;
513 case AVIVO_DC_GPIO_DDC2_MASK:
514 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
515 break;
516 case AVIVO_DC_GPIO_DDC3_MASK:
517 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
518 break;
519 default:
520 DRM_ERROR("gpio not supported with hw i2c\n");
521 ret = -EINVAL;
522 goto done;
523 }
524
525 /* check for bus probe */
526 p = &msgs[0];
527 if ((num == 1) && (p->len == 0)) {
528 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
529 AVIVO_DC_I2C_NACK |
530 AVIVO_DC_I2C_HALT));
531 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
532 udelay(1);
533 WREG32(AVIVO_DC_I2C_RESET, 0);
534
535 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
536 WREG32(AVIVO_DC_I2C_DATA, 0);
537
538 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
539 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
540 AVIVO_DC_I2C_DATA_COUNT(1) |
541 (prescale << 16)));
542 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
543 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
544 for (j = 0; j < 200; j++) {
545 udelay(50);
546 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
547 if (tmp & AVIVO_DC_I2C_GO)
548 continue;
549 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
550 if (tmp & AVIVO_DC_I2C_DONE)
551 break;
552 else {
553 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
554 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
555 ret = -EIO;
556 goto done;
557 }
558 }
559 goto done;
560 }
561
562 for (i = 0; i < num; i++) {
563 p = &msgs[i];
564 remaining = p->len;
565 buffer_offset = 0;
566 if (p->flags & I2C_M_RD) {
567 while (remaining) {
568 if (remaining > 15)
569 current_count = 15;
570 else
571 current_count = remaining;
572 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
573 AVIVO_DC_I2C_NACK |
574 AVIVO_DC_I2C_HALT));
575 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
576 udelay(1);
577 WREG32(AVIVO_DC_I2C_RESET, 0);
578
579 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
580 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
581 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
582 AVIVO_DC_I2C_DATA_COUNT(current_count) |
583 (prescale << 16)));
584 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
585 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
586 for (j = 0; j < 200; j++) {
587 udelay(50);
588 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
589 if (tmp & AVIVO_DC_I2C_GO)
590 continue;
591 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
592 if (tmp & AVIVO_DC_I2C_DONE)
593 break;
594 else {
595 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
596 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
597 ret = -EIO;
598 goto done;
599 }
600 }
601 for (j = 0; j < current_count; j++)
602 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
603 remaining -= current_count;
604 buffer_offset += current_count;
605 }
606 } else {
607 while (remaining) {
608 if (remaining > 15)
609 current_count = 15;
610 else
611 current_count = remaining;
612 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
613 AVIVO_DC_I2C_NACK |
614 AVIVO_DC_I2C_HALT));
615 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
616 udelay(1);
617 WREG32(AVIVO_DC_I2C_RESET, 0);
618
619 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
620 for (j = 0; j < current_count; j++)
621 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
622
623 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
624 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
625 AVIVO_DC_I2C_DATA_COUNT(current_count) |
626 (prescale << 16)));
627 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
628 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
629 for (j = 0; j < 200; j++) {
630 udelay(50);
631 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
632 if (tmp & AVIVO_DC_I2C_GO)
633 continue;
634 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
635 if (tmp & AVIVO_DC_I2C_DONE)
636 break;
637 else {
638 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
639 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
640 ret = -EIO;
641 goto done;
642 }
643 }
644 remaining -= current_count;
645 buffer_offset += current_count;
646 }
647 }
648 }
649
650done:
651 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
652 AVIVO_DC_I2C_NACK |
653 AVIVO_DC_I2C_HALT));
654 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
655 udelay(1);
656 WREG32(AVIVO_DC_I2C_RESET, 0);
657
658 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
659 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
660 WREG32(0x494, saved2);
661 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
662 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
663 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
664
665 mutex_unlock(&rdev->dc_hw_i2c_mutex);
666
667 return ret;
668}
669
670static int radeon_sw_i2c_xfer(struct i2c_adapter *i2c_adap,
671 struct i2c_msg *msgs, int num)
173{ 672{
174 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 673 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
175 int ret; 674 int ret;
176 675
177 radeon_i2c_do_lock(i2c, 1); 676 radeon_i2c_do_lock(i2c, 1);
178 if (i2c_transfer(&i2c->algo.radeon.bit_adapter, msgs, num) == num) 677 ret = i2c_transfer(&i2c->algo.radeon.bit_adapter, msgs, num);
179 ret = num;
180 else
181 ret = -1;
182 radeon_i2c_do_lock(i2c, 0); 678 radeon_i2c_do_lock(i2c, 0);
183 679
184 return ret; 680 return ret;
185} 681}
186 682
683static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap,
684 struct i2c_msg *msgs, int num)
685{
686 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
687 struct radeon_device *rdev = i2c->dev->dev_private;
688 struct radeon_i2c_bus_rec *rec = &i2c->rec;
689 int ret;
690
691 switch (rdev->family) {
692 case CHIP_R100:
693 case CHIP_RV100:
694 case CHIP_RS100:
695 case CHIP_RV200:
696 case CHIP_RS200:
697 case CHIP_R200:
698 case CHIP_RV250:
699 case CHIP_RS300:
700 case CHIP_RV280:
701 case CHIP_R300:
702 case CHIP_R350:
703 case CHIP_RV350:
704 case CHIP_RV380:
705 case CHIP_R420:
706 case CHIP_R423:
707 case CHIP_RV410:
708 case CHIP_RS400:
709 case CHIP_RS480:
710 if (rec->hw_capable)
711 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
712 else
713 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
714 break;
715 case CHIP_RS600:
716 case CHIP_RS690:
717 case CHIP_RS740:
718 /* XXX fill in hw i2c implementation */
719 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
720 break;
721 case CHIP_RV515:
722 case CHIP_R520:
723 case CHIP_RV530:
724 case CHIP_RV560:
725 case CHIP_RV570:
726 case CHIP_R580:
727 if (rec->hw_capable) {
728 if (rec->mm_i2c)
729 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
730 else
731 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
732 } else
733 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
734 break;
735 case CHIP_R600:
736 case CHIP_RV610:
737 case CHIP_RV630:
738 case CHIP_RV670:
739 /* XXX fill in hw i2c implementation */
740 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
741 break;
742 case CHIP_RV620:
743 case CHIP_RV635:
744 case CHIP_RS780:
745 case CHIP_RS880:
746 case CHIP_RV770:
747 case CHIP_RV730:
748 case CHIP_RV710:
749 case CHIP_RV740:
750 /* XXX fill in hw i2c implementation */
751 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
752 break;
753 default:
754 DRM_ERROR("i2c: unhandled radeon chip\n");
755 ret = -EIO;
756 break;
757 }
758
759 return ret;
760}
761
187static u32 radeon_i2c_func(struct i2c_adapter *adap) 762static u32 radeon_i2c_func(struct i2c_adapter *adap)
188{ 763{
189 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 764 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
@@ -205,8 +780,6 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
205 if (i2c == NULL) 780 if (i2c == NULL)
206 return NULL; 781 return NULL;
207 782
208 i2c->dev = dev;
209 i2c->rec = *rec;
210 /* set the internal bit adapter */ 783 /* set the internal bit adapter */
211 i2c->algo.radeon.bit_adapter.owner = THIS_MODULE; 784 i2c->algo.radeon.bit_adapter.owner = THIS_MODULE;
212 i2c_set_adapdata(&i2c->algo.radeon.bit_adapter, i2c); 785 i2c_set_adapdata(&i2c->algo.radeon.bit_adapter, i2c);
@@ -223,10 +796,12 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
223 i2c->algo.radeon.bit_data.data = i2c; 796 i2c->algo.radeon.bit_data.data = i2c;
224 ret = i2c_bit_add_bus(&i2c->algo.radeon.bit_adapter); 797 ret = i2c_bit_add_bus(&i2c->algo.radeon.bit_adapter);
225 if (ret) { 798 if (ret) {
226 DRM_INFO("Failed to register internal bit i2c %s\n", name); 799 DRM_ERROR("Failed to register internal bit i2c %s\n", name);
227 goto out_free; 800 goto out_free;
228 } 801 }
229 /* set the radeon i2c adapter */ 802 /* set the radeon i2c adapter */
803 i2c->dev = dev;
804 i2c->rec = *rec;
230 i2c->adapter.owner = THIS_MODULE; 805 i2c->adapter.owner = THIS_MODULE;
231 i2c_set_adapdata(&i2c->adapter, i2c); 806 i2c_set_adapdata(&i2c->adapter, i2c);
232 sprintf(i2c->adapter.name, "Radeon i2c %s", name); 807 sprintf(i2c->adapter.name, "Radeon i2c %s", name);
@@ -234,7 +809,7 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
234 i2c->adapter.algo = &radeon_i2c_algo; 809 i2c->adapter.algo = &radeon_i2c_algo;
235 ret = i2c_add_adapter(&i2c->adapter); 810 ret = i2c_add_adapter(&i2c->adapter);
236 if (ret) { 811 if (ret) {
237 DRM_INFO("Failed to register i2c %s\n", name); 812 DRM_ERROR("Failed to register i2c %s\n", name);
238 goto out_free; 813 goto out_free;
239 } 814 }
240 815
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index 6d0a009dd4a1..b4a06676fff6 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -1060,32 +1060,38 @@
1060 1060
1061 /* Multimedia I2C bus */ 1061 /* Multimedia I2C bus */
1062#define RADEON_I2C_CNTL_0 0x0090 1062#define RADEON_I2C_CNTL_0 0x0090
1063#define RADEON_I2C_DONE (1 << 0) 1063# define RADEON_I2C_DONE (1 << 0)
1064#define RADEON_I2C_NACK (1 << 1) 1064# define RADEON_I2C_NACK (1 << 1)
1065#define RADEON_I2C_HALT (1 << 2) 1065# define RADEON_I2C_HALT (1 << 2)
1066#define RADEON_I2C_SOFT_RST (1 << 5) 1066# define RADEON_I2C_SOFT_RST (1 << 5)
1067#define RADEON_I2C_DRIVE_EN (1 << 6) 1067# define RADEON_I2C_DRIVE_EN (1 << 6)
1068#define RADEON_I2C_DRIVE_SEL (1 << 7) 1068# define RADEON_I2C_DRIVE_SEL (1 << 7)
1069#define RADEON_I2C_START (1 << 8) 1069# define RADEON_I2C_START (1 << 8)
1070#define RADEON_I2C_STOP (1 << 9) 1070# define RADEON_I2C_STOP (1 << 9)
1071#define RADEON_I2C_RECEIVE (1 << 10) 1071# define RADEON_I2C_RECEIVE (1 << 10)
1072#define RADEON_I2C_ABORT (1 << 11) 1072# define RADEON_I2C_ABORT (1 << 11)
1073#define RADEON_I2C_GO (1 << 12) 1073# define RADEON_I2C_GO (1 << 12)
1074#define RADEON_I2C_PRESCALE_SHIFT 16 1074# define RADEON_I2C_PRESCALE_SHIFT 16
1075#define RADEON_I2C_CNTL_1 0x0094 1075#define RADEON_I2C_CNTL_1 0x0094
1076#define RADEON_I2C_DATA_COUNT_SHIFT 0 1076# define RADEON_I2C_DATA_COUNT_SHIFT 0
1077#define RADEON_I2C_ADDR_COUNT_SHIFT 4 1077# define RADEON_I2C_ADDR_COUNT_SHIFT 4
1078#define RADEON_I2C_INTRA_BYTE_DELAY_SHIFT 8 1078# define RADEON_I2C_INTRA_BYTE_DELAY_SHIFT 8
1079#define RADEON_I2C_SEL (1 << 16) 1079# define RADEON_I2C_SEL (1 << 16)
1080#define RADEON_I2C_EN (1 << 17) 1080# define RADEON_I2C_EN (1 << 17)
1081#define RADEON_I2C_TIME_LIMIT_SHIFT 24 1081# define RADEON_I2C_TIME_LIMIT_SHIFT 24
1082#define RADEON_I2C_DATA 0x0098 1082#define RADEON_I2C_DATA 0x0098
1083 1083
1084#define RADEON_DVI_I2C_CNTL_0 0x02e0 1084#define RADEON_DVI_I2C_CNTL_0 0x02e0
1085# define R200_DVI_I2C_PIN_SEL(x) ((x) << 3) 1085# define R200_DVI_I2C_PIN_SEL(x) ((x) << 3)
1086# define R200_SEL_DDC1 0 /* 0x60 - VGA_DDC */ 1086# define R200_SEL_DDC1 0 /* depends on asic */
1087# define R200_SEL_DDC2 1 /* 0x64 - DVI_DDC */ 1087# define R200_SEL_DDC2 1 /* depends on asic */
1088# define R200_SEL_DDC3 2 /* 0x68 - MONID_DDC */ 1088# define R200_SEL_DDC3 2 /* depends on asic */
1089# define RADEON_SW_WANTS_TO_USE_DVI_I2C (1 << 13)
1090# define RADEON_SW_CAN_USE_DVI_I2C (1 << 13)
1091# define RADEON_SW_DONE_USING_DVI_I2C (1 << 14)
1092# define RADEON_HW_NEEDS_DVI_I2C (1 << 14)
1093# define RADEON_ABORT_HW_DVI_I2C (1 << 15)
1094# define RADEON_HW_USING_DVI_I2C (1 << 15)
1089#define RADEON_DVI_I2C_CNTL_1 0x02e4 1095#define RADEON_DVI_I2C_CNTL_1 0x02e4
1090#define RADEON_DVI_I2C_DATA 0x02e8 1096#define RADEON_DVI_I2C_DATA 0x02e8
1091 1097
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 16:40:43 -0500