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authorMark Brown <broonie@opensource.wolfsonmicro.com>2012-09-13 00:53:59 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2012-09-18 23:23:52 -0400
commit35ecf7cd96a79d92c1b8433c950a827a2a723db9 (patch)
tree9f35cb01366abac5ed6b8e490dd85b52a5364c63
parent3706163140939bccd58fba739a9820f1d5eebeaf (diff)
ASoC: wm8961: Convert to direct regmap API usage
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat
-rw-r--r--sound/soc/codecs/wm8961.c426
1 files changed, 161 insertions, 265 deletions
diff --git a/sound/soc/codecs/wm8961.c b/sound/soc/codecs/wm8961.c
index 719fb69a17c8..4ea64d6e68e2 100644
--- a/sound/soc/codecs/wm8961.c
+++ b/sound/soc/codecs/wm8961.c
@@ -19,6 +19,7 @@
19#include <linux/delay.h> 19#include <linux/delay.h>
20#include <linux/pm.h> 20#include <linux/pm.h>
21#include <linux/i2c.h> 21#include <linux/i2c.h>
22#include <linux/regmap.h>
22#include <linux/slab.h> 23#include <linux/slab.h>
23#include <sound/core.h> 24#include <sound/core.h>
24#include <sound/pcm.h> 25#include <sound/pcm.h>
@@ -31,277 +32,158 @@
31 32
32#define WM8961_MAX_REGISTER 0xFC 33#define WM8961_MAX_REGISTER 0xFC
33 34
34static u16 wm8961_reg_defaults[] = { 35static const struct reg_default wm8961_reg_defaults[] = {
35 0x009F, /* R0 - Left Input volume */ 36 { 0, 0x009F }, /* R0 - Left Input volume */
36 0x009F, /* R1 - Right Input volume */ 37 { 1, 0x009F }, /* R1 - Right Input volume */
37 0x0000, /* R2 - LOUT1 volume */ 38 { 2, 0x0000 }, /* R2 - LOUT1 volume */
38 0x0000, /* R3 - ROUT1 volume */ 39 { 3, 0x0000 }, /* R3 - ROUT1 volume */
39 0x0020, /* R4 - Clocking1 */ 40 { 4, 0x0020 }, /* R4 - Clocking1 */
40 0x0008, /* R5 - ADC & DAC Control 1 */ 41 { 5, 0x0008 }, /* R5 - ADC & DAC Control 1 */
41 0x0000, /* R6 - ADC & DAC Control 2 */ 42 { 6, 0x0000 }, /* R6 - ADC & DAC Control 2 */
42 0x000A, /* R7 - Audio Interface 0 */ 43 { 7, 0x000A }, /* R7 - Audio Interface 0 */
43 0x01F4, /* R8 - Clocking2 */ 44 { 8, 0x01F4 }, /* R8 - Clocking2 */
44 0x0000, /* R9 - Audio Interface 1 */ 45 { 9, 0x0000 }, /* R9 - Audio Interface 1 */
45 0x00FF, /* R10 - Left DAC volume */ 46 { 10, 0x00FF }, /* R10 - Left DAC volume */
46 0x00FF, /* R11 - Right DAC volume */ 47 { 11, 0x00FF }, /* R11 - Right DAC volume */
47 0x0000, /* R12 */ 48
48 0x0000, /* R13 */ 49 { 14, 0x0040 }, /* R14 - Audio Interface 2 */
49 0x0040, /* R14 - Audio Interface 2 */ 50
50 0x0000, /* R15 - Software Reset */ 51 { 17, 0x007B }, /* R17 - ALC1 */
51 0x0000, /* R16 */ 52 { 18, 0x0000 }, /* R18 - ALC2 */
52 0x007B, /* R17 - ALC1 */ 53 { 19, 0x0032 }, /* R19 - ALC3 */
53 0x0000, /* R18 - ALC2 */ 54 { 20, 0x0000 }, /* R20 - Noise Gate */
54 0x0032, /* R19 - ALC3 */ 55 { 21, 0x00C0 }, /* R21 - Left ADC volume */
55 0x0000, /* R20 - Noise Gate */ 56 { 22, 0x00C0 }, /* R22 - Right ADC volume */
56 0x00C0, /* R21 - Left ADC volume */ 57 { 23, 0x0120 }, /* R23 - Additional control(1) */
57 0x00C0, /* R22 - Right ADC volume */ 58 { 24, 0x0000 }, /* R24 - Additional control(2) */
58 0x0120, /* R23 - Additional control(1) */ 59 { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */
59 0x0000, /* R24 - Additional control(2) */ 60 { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */
60 0x0000, /* R25 - Pwr Mgmt (1) */ 61 { 27, 0x0000 }, /* R27 - Additional Control (3) */
61 0x0000, /* R26 - Pwr Mgmt (2) */ 62 { 28, 0x0000 }, /* R28 - Anti-pop */
62 0x0000, /* R27 - Additional Control (3) */ 63
63 0x0000, /* R28 - Anti-pop */ 64 { 30, 0x005F }, /* R30 - Clocking 3 */
64 0x0000, /* R29 */ 65
65 0x005F, /* R30 - Clocking 3 */ 66 { 32, 0x0000 }, /* R32 - ADCL signal path */
66 0x0000, /* R31 */ 67 { 33, 0x0000 }, /* R33 - ADCR signal path */
67 0x0000, /* R32 - ADCL signal path */ 68
68 0x0000, /* R33 - ADCR signal path */ 69 { 40, 0x0000 }, /* R40 - LOUT2 volume */
69 0x0000, /* R34 */ 70 { 41, 0x0000 }, /* R41 - ROUT2 volume */
70 0x0000, /* R35 */ 71
71 0x0000, /* R36 */ 72 { 47, 0x0000 }, /* R47 - Pwr Mgmt (3) */
72 0x0000, /* R37 */ 73 { 48, 0x0023 }, /* R48 - Additional Control (4) */
73 0x0000, /* R38 */ 74 { 49, 0x0000 }, /* R49 - Class D Control 1 */
74 0x0000, /* R39 */ 75
75 0x0000, /* R40 - LOUT2 volume */ 76 { 51, 0x0003 }, /* R51 - Class D Control 2 */
76 0x0000, /* R41 - ROUT2 volume */ 77
77 0x0000, /* R42 */ 78 { 56, 0x0106 }, /* R56 - Clocking 4 */
78 0x0000, /* R43 */ 79 { 57, 0x0000 }, /* R57 - DSP Sidetone 0 */
79 0x0000, /* R44 */ 80 { 58, 0x0000 }, /* R58 - DSP Sidetone 1 */
80 0x0000, /* R45 */ 81
81 0x0000, /* R46 */ 82 { 60, 0x0000 }, /* R60 - DC Servo 0 */
82 0x0000, /* R47 - Pwr Mgmt (3) */ 83 { 61, 0x0000 }, /* R61 - DC Servo 1 */
83 0x0023, /* R48 - Additional Control (4) */ 84
84 0x0000, /* R49 - Class D Control 1 */ 85 { 63, 0x015E }, /* R63 - DC Servo 3 */
85 0x0000, /* R50 */ 86
86 0x0003, /* R51 - Class D Control 2 */ 87 { 65, 0x0010 }, /* R65 - DC Servo 5 */
87 0x0000, /* R52 */ 88
88 0x0000, /* R53 */ 89 { 68, 0x0003 }, /* R68 - Analogue PGA Bias */
89 0x0000, /* R54 */ 90 { 69, 0x0000 }, /* R69 - Analogue HP 0 */
90 0x0000, /* R55 */ 91
91 0x0106, /* R56 - Clocking 4 */ 92 { 71, 0x01FB }, /* R71 - Analogue HP 2 */
92 0x0000, /* R57 - DSP Sidetone 0 */ 93 { 72, 0x0000 }, /* R72 - Charge Pump 1 */
93 0x0000, /* R58 - DSP Sidetone 1 */ 94
94 0x0000, /* R59 */ 95 { 82, 0x0000 }, /* R82 - Charge Pump B */
95 0x0000, /* R60 - DC Servo 0 */ 96
96 0x0000, /* R61 - DC Servo 1 */ 97 { 87, 0x0000 }, /* R87 - Write Sequencer 1 */
97 0x0000, /* R62 */ 98 { 88, 0x0000 }, /* R88 - Write Sequencer 2 */
98 0x015E, /* R63 - DC Servo 3 */ 99 { 89, 0x0000 }, /* R89 - Write Sequencer 3 */
99 0x0010, /* R64 */ 100 { 90, 0x0000 }, /* R90 - Write Sequencer 4 */
100 0x0010, /* R65 - DC Servo 5 */ 101 { 91, 0x0000 }, /* R91 - Write Sequencer 5 */
101 0x0000, /* R66 */ 102 { 92, 0x0000 }, /* R92 - Write Sequencer 6 */
102 0x0001, /* R67 */ 103 { 93, 0x0000 }, /* R93 - Write Sequencer 7 */
103 0x0003, /* R68 - Analogue PGA Bias */ 104
104 0x0000, /* R69 - Analogue HP 0 */ 105 { 252, 0x0001 }, /* R252 - General test 1 */
105 0x0060, /* R70 */
106 0x01FB, /* R71 - Analogue HP 2 */
107 0x0000, /* R72 - Charge Pump 1 */
108 0x0065, /* R73 */
109 0x005F, /* R74 */
110 0x0059, /* R75 */
111 0x006B, /* R76 */
112 0x0038, /* R77 */
113 0x000C, /* R78 */
114 0x000A, /* R79 */
115 0x006B, /* R80 */
116 0x0000, /* R81 */
117 0x0000, /* R82 - Charge Pump B */
118 0x0087, /* R83 */
119 0x0000, /* R84 */
120 0x005C, /* R85 */
121 0x0000, /* R86 */
122 0x0000, /* R87 - Write Sequencer 1 */
123 0x0000, /* R88 - Write Sequencer 2 */
124 0x0000, /* R89 - Write Sequencer 3 */
125 0x0000, /* R90 - Write Sequencer 4 */
126 0x0000, /* R91 - Write Sequencer 5 */
127 0x0000, /* R92 - Write Sequencer 6 */
128 0x0000, /* R93 - Write Sequencer 7 */
129 0x0000, /* R94 */
130 0x0000, /* R95 */
131 0x0000, /* R96 */
132 0x0000, /* R97 */
133 0x0000, /* R98 */
134 0x0000, /* R99 */
135 0x0000, /* R100 */
136 0x0000, /* R101 */
137 0x0000, /* R102 */
138 0x0000, /* R103 */
139 0x0000, /* R104 */
140 0x0000, /* R105 */
141 0x0000, /* R106 */
142 0x0000, /* R107 */
143 0x0000, /* R108 */
144 0x0000, /* R109 */
145 0x0000, /* R110 */
146 0x0000, /* R111 */
147 0x0000, /* R112 */
148 0x0000, /* R113 */
149 0x0000, /* R114 */
150 0x0000, /* R115 */
151 0x0000, /* R116 */
152 0x0000, /* R117 */
153 0x0000, /* R118 */
154 0x0000, /* R119 */
155 0x0000, /* R120 */
156 0x0000, /* R121 */
157 0x0000, /* R122 */
158 0x0000, /* R123 */
159 0x0000, /* R124 */
160 0x0000, /* R125 */
161 0x0000, /* R126 */
162 0x0000, /* R127 */
163 0x0000, /* R128 */
164 0x0000, /* R129 */
165 0x0000, /* R130 */
166 0x0000, /* R131 */
167 0x0000, /* R132 */
168 0x0000, /* R133 */
169 0x0000, /* R134 */
170 0x0000, /* R135 */
171 0x0000, /* R136 */
172 0x0000, /* R137 */
173 0x0000, /* R138 */
174 0x0000, /* R139 */
175 0x0000, /* R140 */
176 0x0000, /* R141 */
177 0x0000, /* R142 */
178 0x0000, /* R143 */
179 0x0000, /* R144 */
180 0x0000, /* R145 */
181 0x0000, /* R146 */
182 0x0000, /* R147 */
183 0x0000, /* R148 */
184 0x0000, /* R149 */
185 0x0000, /* R150 */
186 0x0000, /* R151 */
187 0x0000, /* R152 */
188 0x0000, /* R153 */
189 0x0000, /* R154 */
190 0x0000, /* R155 */
191 0x0000, /* R156 */
192 0x0000, /* R157 */
193 0x0000, /* R158 */
194 0x0000, /* R159 */
195 0x0000, /* R160 */
196 0x0000, /* R161 */
197 0x0000, /* R162 */
198 0x0000, /* R163 */
199 0x0000, /* R164 */
200 0x0000, /* R165 */
201 0x0000, /* R166 */
202 0x0000, /* R167 */
203 0x0000, /* R168 */
204 0x0000, /* R169 */
205 0x0000, /* R170 */
206 0x0000, /* R171 */
207 0x0000, /* R172 */
208 0x0000, /* R173 */
209 0x0000, /* R174 */
210 0x0000, /* R175 */
211 0x0000, /* R176 */
212 0x0000, /* R177 */
213 0x0000, /* R178 */
214 0x0000, /* R179 */
215 0x0000, /* R180 */
216 0x0000, /* R181 */
217 0x0000, /* R182 */
218 0x0000, /* R183 */
219 0x0000, /* R184 */
220 0x0000, /* R185 */
221 0x0000, /* R186 */
222 0x0000, /* R187 */
223 0x0000, /* R188 */
224 0x0000, /* R189 */
225 0x0000, /* R190 */
226 0x0000, /* R191 */
227 0x0000, /* R192 */
228 0x0000, /* R193 */
229 0x0000, /* R194 */
230 0x0000, /* R195 */
231 0x0030, /* R196 */
232 0x0006, /* R197 */
233 0x0000, /* R198 */
234 0x0060, /* R199 */
235 0x0000, /* R200 */
236 0x003F, /* R201 */
237 0x0000, /* R202 */
238 0x0000, /* R203 */
239 0x0000, /* R204 */
240 0x0001, /* R205 */
241 0x0000, /* R206 */
242 0x0181, /* R207 */
243 0x0005, /* R208 */
244 0x0008, /* R209 */
245 0x0008, /* R210 */
246 0x0000, /* R211 */
247 0x013B, /* R212 */
248 0x0000, /* R213 */
249 0x0000, /* R214 */
250 0x0000, /* R215 */
251 0x0000, /* R216 */
252 0x0070, /* R217 */
253 0x0000, /* R218 */
254 0x0000, /* R219 */
255 0x0000, /* R220 */
256 0x0000, /* R221 */
257 0x0000, /* R222 */
258 0x0003, /* R223 */
259 0x0000, /* R224 */
260 0x0000, /* R225 */
261 0x0001, /* R226 */
262 0x0008, /* R227 */
263 0x0000, /* R228 */
264 0x0000, /* R229 */
265 0x0000, /* R230 */
266 0x0000, /* R231 */
267 0x0004, /* R232 */
268 0x0000, /* R233 */
269 0x0000, /* R234 */
270 0x0000, /* R235 */
271 0x0000, /* R236 */
272 0x0000, /* R237 */
273 0x0080, /* R238 */
274 0x0000, /* R239 */
275 0x0000, /* R240 */
276 0x0000, /* R241 */
277 0x0000, /* R242 */
278 0x0000, /* R243 */
279 0x0000, /* R244 */
280 0x0052, /* R245 */
281 0x0110, /* R246 */
282 0x0040, /* R247 */
283 0x0000, /* R248 */
284 0x0030, /* R249 */
285 0x0000, /* R250 */
286 0x0000, /* R251 */
287 0x0001, /* R252 - General test 1 */
288}; 106};
289 107
290struct wm8961_priv { 108struct wm8961_priv {
291 enum snd_soc_control_type control_type; 109 struct regmap *regmap;
292 int sysclk; 110 int sysclk;
293}; 111};
294 112
295static int wm8961_volatile_register(struct snd_soc_codec *codec, unsigned int reg) 113static bool wm8961_volatile(struct device *dev, unsigned int reg)
296{ 114{
297 switch (reg) { 115 switch (reg) {
298 case WM8961_SOFTWARE_RESET: 116 case WM8961_SOFTWARE_RESET:
299 case WM8961_WRITE_SEQUENCER_7: 117 case WM8961_WRITE_SEQUENCER_7:
300 case WM8961_DC_SERVO_1: 118 case WM8961_DC_SERVO_1:
301 return 1; 119 return true;
302 120
303 default: 121 default:
304 return 0; 122 return false;
123 }
124}
125
126static bool wm8961_readable(struct device *dev, unsigned int reg)
127{
128 switch (reg) {
129 case WM8961_LEFT_INPUT_VOLUME:
130 case WM8961_RIGHT_INPUT_VOLUME:
131 case WM8961_LOUT1_VOLUME:
132 case WM8961_ROUT1_VOLUME:
133 case WM8961_CLOCKING1:
134 case WM8961_ADC_DAC_CONTROL_1:
135 case WM8961_ADC_DAC_CONTROL_2:
136 case WM8961_AUDIO_INTERFACE_0:
137 case WM8961_CLOCKING2:
138 case WM8961_AUDIO_INTERFACE_1:
139 case WM8961_LEFT_DAC_VOLUME:
140 case WM8961_RIGHT_DAC_VOLUME:
141 case WM8961_AUDIO_INTERFACE_2:
142 case WM8961_SOFTWARE_RESET:
143 case WM8961_ALC1:
144 case WM8961_ALC2:
145 case WM8961_ALC3:
146 case WM8961_NOISE_GATE:
147 case WM8961_LEFT_ADC_VOLUME:
148 case WM8961_RIGHT_ADC_VOLUME:
149 case WM8961_ADDITIONAL_CONTROL_1:
150 case WM8961_ADDITIONAL_CONTROL_2:
151 case WM8961_PWR_MGMT_1:
152 case WM8961_PWR_MGMT_2:
153 case WM8961_ADDITIONAL_CONTROL_3:
154 case WM8961_ANTI_POP:
155 case WM8961_CLOCKING_3:
156 case WM8961_ADCL_SIGNAL_PATH:
157 case WM8961_ADCR_SIGNAL_PATH:
158 case WM8961_LOUT2_VOLUME:
159 case WM8961_ROUT2_VOLUME:
160 case WM8961_PWR_MGMT_3:
161 case WM8961_ADDITIONAL_CONTROL_4:
162 case WM8961_CLASS_D_CONTROL_1:
163 case WM8961_CLASS_D_CONTROL_2:
164 case WM8961_CLOCKING_4:
165 case WM8961_DSP_SIDETONE_0:
166 case WM8961_DSP_SIDETONE_1:
167 case WM8961_DC_SERVO_0:
168 case WM8961_DC_SERVO_1:
169 case WM8961_DC_SERVO_3:
170 case WM8961_DC_SERVO_5:
171 case WM8961_ANALOGUE_PGA_BIAS:
172 case WM8961_ANALOGUE_HP_0:
173 case WM8961_ANALOGUE_HP_2:
174 case WM8961_CHARGE_PUMP_1:
175 case WM8961_CHARGE_PUMP_B:
176 case WM8961_WRITE_SEQUENCER_1:
177 case WM8961_WRITE_SEQUENCER_2:
178 case WM8961_WRITE_SEQUENCER_3:
179 case WM8961_WRITE_SEQUENCER_4:
180 case WM8961_WRITE_SEQUENCER_5:
181 case WM8961_WRITE_SEQUENCER_6:
182 case WM8961_WRITE_SEQUENCER_7:
183 case WM8961_GENERAL_TEST_1:
184 return true;
185 default:
186 return false;
305 } 187 }
306} 188}
307 189
@@ -958,11 +840,12 @@ static struct snd_soc_dai_driver wm8961_dai = {
958 840
959static int wm8961_probe(struct snd_soc_codec *codec) 841static int wm8961_probe(struct snd_soc_codec *codec)
960{ 842{
843 struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
961 struct snd_soc_dapm_context *dapm = &codec->dapm; 844 struct snd_soc_dapm_context *dapm = &codec->dapm;
962 int ret = 0; 845 int ret = 0;
963 u16 reg; 846 u16 reg;
964 847
965 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); 848 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
966 if (ret != 0) { 849 if (ret != 0) {
967 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 850 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
968 return ret; 851 return ret;
@@ -975,9 +858,9 @@ static int wm8961_probe(struct snd_soc_codec *codec)
975 } 858 }
976 859
977 /* This isn't volatile - readback doesn't correspond to write */ 860 /* This isn't volatile - readback doesn't correspond to write */
978 codec->cache_bypass = 1; 861 regcache_cache_bypass(wm8961->regmap, true);
979 reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME); 862 reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
980 codec->cache_bypass = 0; 863 regcache_cache_bypass(wm8961->regmap, false);
981 dev_info(codec->dev, "WM8961 family %d revision %c\n", 864 dev_info(codec->dev, "WM8961 family %d revision %c\n",
982 (reg & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT, 865 (reg & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
983 ((reg & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT) 866 ((reg & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
@@ -1066,10 +949,19 @@ static struct snd_soc_codec_driver soc_codec_dev_wm8961 = {
1066 .suspend = wm8961_suspend, 949 .suspend = wm8961_suspend,
1067 .resume = wm8961_resume, 950 .resume = wm8961_resume,
1068 .set_bias_level = wm8961_set_bias_level, 951 .set_bias_level = wm8961_set_bias_level,
1069 .reg_cache_size = ARRAY_SIZE(wm8961_reg_defaults), 952};
1070 .reg_word_size = sizeof(u16), 953
1071 .reg_cache_default = wm8961_reg_defaults, 954static const struct regmap_config wm8961_regmap = {
1072 .volatile_register = wm8961_volatile_register, 955 .reg_bits = 8,
956 .val_bits = 16,
957 .max_register = WM8961_MAX_REGISTER,
958
959 .reg_defaults = wm8961_reg_defaults,
960 .num_reg_defaults = ARRAY_SIZE(wm8961_reg_defaults),
961 .cache_type = REGCACHE_RBTREE,
962
963 .volatile_reg = wm8961_volatile,
964 .readable_reg = wm8961_readable,
1073}; 965};
1074 966
1075static __devinit int wm8961_i2c_probe(struct i2c_client *i2c, 967static __devinit int wm8961_i2c_probe(struct i2c_client *i2c,
@@ -1083,6 +975,10 @@ static __devinit int wm8961_i2c_probe(struct i2c_client *i2c,
1083 if (wm8961 == NULL) 975 if (wm8961 == NULL)
1084 return -ENOMEM; 976 return -ENOMEM;
1085 977
978 wm8961->regmap = devm_regmap_init_i2c(i2c, &wm8961_regmap);
979 if (IS_ERR(wm8961->regmap))
980 return PTR_ERR(wm8961->regmap);
981
1086 i2c_set_clientdata(i2c, wm8961); 982 i2c_set_clientdata(i2c, wm8961);
1087 983
1088 ret = snd_soc_register_codec(&i2c->dev, 984 ret = snd_soc_register_codec(&i2c->dev,
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-10 14:07:36 -0400