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authorThomas Abraham <thomas.abraham@linaro.org>2011-08-10 06:21:20 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2011-08-23 13:48:31 -0400
commit2a8d7bddf273477d6aa81405c9b4bae223e11ed9 (patch)
treec344956ef3499870b14158f438494ca5f27d0140
parent88bb4ea14c72f89c5265029c1891e5eb6521cc0f (diff)
ARM: SAMSUNG: Remove uart irq handling from plaform code
With uart tx/rx/err interrupt handling moved into the driver for s3c64xx and later SoC's, the uart interrupt handling in plaform code can be removed. The uart device irq resources is reduced to one and the related unused macros are removed. Suggested-by: Grant Likely <grant.likely@secretlab.ca> CC: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-s3c64xx/dev-uart.c60
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/irqs.h30
-rw-r--r--arch/arm/mach-s3c64xx/irq.c25
-rw-r--r--arch/arm/plat-s5p/Kconfig1
-rw-r--r--arch/arm/plat-s5p/dev-uart.c84
-rw-r--r--arch/arm/plat-s5p/include/plat/irqs.h35
-rw-r--r--arch/arm/plat-s5p/irq.c34
-rw-r--r--arch/arm/plat-samsung/Kconfig5
-rw-r--r--arch/arm/plat-samsung/Makefile1
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-serial.h5
-rw-r--r--arch/arm/plat-samsung/irq-uart.c96
12 files changed, 25 insertions, 352 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5ebc5d922ea1..325d2f55744d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -722,7 +722,6 @@ config ARCH_S3C64XX
722 select ARCH_REQUIRE_GPIOLIB 722 select ARCH_REQUIRE_GPIOLIB
723 select SAMSUNG_CLKSRC 723 select SAMSUNG_CLKSRC
724 select SAMSUNG_IRQ_VIC_TIMER 724 select SAMSUNG_IRQ_VIC_TIMER
725 select SAMSUNG_IRQ_UART
726 select S3C_GPIO_TRACK 725 select S3C_GPIO_TRACK
727 select S3C_GPIO_PULL_UPDOWN 726 select S3C_GPIO_PULL_UPDOWN
728 select S3C_GPIO_CFG_S3C24XX 727 select S3C_GPIO_CFG_S3C24XX
diff --git a/arch/arm/mach-s3c64xx/dev-uart.c b/arch/arm/mach-s3c64xx/dev-uart.c
index f797f748b999..c681b99eda08 100644
--- a/arch/arm/mach-s3c64xx/dev-uart.c
+++ b/arch/arm/mach-s3c64xx/dev-uart.c
@@ -37,21 +37,10 @@ static struct resource s3c64xx_uart0_resource[] = {
37 .flags = IORESOURCE_MEM, 37 .flags = IORESOURCE_MEM,
38 }, 38 },
39 [1] = { 39 [1] = {
40 .start = IRQ_S3CUART_RX0, 40 .start = IRQ_UART0,
41 .end = IRQ_S3CUART_RX0, 41 .end = IRQ_UART0,
42 .flags = IORESOURCE_IRQ, 42 .flags = IORESOURCE_IRQ,
43 }, 43 },
44 [2] = {
45 .start = IRQ_S3CUART_TX0,
46 .end = IRQ_S3CUART_TX0,
47 .flags = IORESOURCE_IRQ,
48
49 },
50 [3] = {
51 .start = IRQ_S3CUART_ERR0,
52 .end = IRQ_S3CUART_ERR0,
53 .flags = IORESOURCE_IRQ,
54 }
55}; 44};
56 45
57static struct resource s3c64xx_uart1_resource[] = { 46static struct resource s3c64xx_uart1_resource[] = {
@@ -61,19 +50,8 @@ static struct resource s3c64xx_uart1_resource[] = {
61 .flags = IORESOURCE_MEM, 50 .flags = IORESOURCE_MEM,
62 }, 51 },
63 [1] = { 52 [1] = {
64 .start = IRQ_S3CUART_RX1, 53 .start = IRQ_UART1,
65 .end = IRQ_S3CUART_RX1, 54 .end = IRQ_UART1,
66 .flags = IORESOURCE_IRQ,
67 },
68 [2] = {
69 .start = IRQ_S3CUART_TX1,
70 .end = IRQ_S3CUART_TX1,
71 .flags = IORESOURCE_IRQ,
72
73 },
74 [3] = {
75 .start = IRQ_S3CUART_ERR1,
76 .end = IRQ_S3CUART_ERR1,
77 .flags = IORESOURCE_IRQ, 55 .flags = IORESOURCE_IRQ,
78 }, 56 },
79}; 57};
@@ -85,19 +63,8 @@ static struct resource s3c6xx_uart2_resource[] = {
85 .flags = IORESOURCE_MEM, 63 .flags = IORESOURCE_MEM,
86 }, 64 },
87 [1] = { 65 [1] = {
88 .start = IRQ_S3CUART_RX2, 66 .start = IRQ_UART2,
89 .end = IRQ_S3CUART_RX2, 67 .end = IRQ_UART2,
90 .flags = IORESOURCE_IRQ,
91 },
92 [2] = {
93 .start = IRQ_S3CUART_TX2,
94 .end = IRQ_S3CUART_TX2,
95 .flags = IORESOURCE_IRQ,
96
97 },
98 [3] = {
99 .start = IRQ_S3CUART_ERR2,
100 .end = IRQ_S3CUART_ERR2,
101 .flags = IORESOURCE_IRQ, 68 .flags = IORESOURCE_IRQ,
102 }, 69 },
103}; 70};
@@ -109,19 +76,8 @@ static struct resource s3c64xx_uart3_resource[] = {
109 .flags = IORESOURCE_MEM, 76 .flags = IORESOURCE_MEM,
110 }, 77 },
111 [1] = { 78 [1] = {
112 .start = IRQ_S3CUART_RX3, 79 .start = IRQ_UART3,
113 .end = IRQ_S3CUART_RX3, 80 .end = IRQ_UART3,
114 .flags = IORESOURCE_IRQ,
115 },
116 [2] = {
117 .start = IRQ_S3CUART_TX3,
118 .end = IRQ_S3CUART_TX3,
119 .flags = IORESOURCE_IRQ,
120
121 },
122 [3] = {
123 .start = IRQ_S3CUART_ERR3,
124 .end = IRQ_S3CUART_ERR3,
125 .flags = IORESOURCE_IRQ, 81 .flags = IORESOURCE_IRQ,
126 }, 82 },
127}; 83};
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
index c026f67a80de..443f85b3c203 100644
--- a/arch/arm/mach-s3c64xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -27,36 +27,6 @@
27#define IRQ_VIC0_BASE S3C_IRQ(0) 27#define IRQ_VIC0_BASE S3C_IRQ(0)
28#define IRQ_VIC1_BASE S3C_IRQ(32) 28#define IRQ_VIC1_BASE S3C_IRQ(32)
29 29
30/* UART interrupts, each UART has 4 intterupts per channel so
31 * use the space between the ISA and S3C main interrupts. Note, these
32 * are not in the same order as the S3C24XX series! */
33
34#define IRQ_S3CUART_BASE0 (16)
35#define IRQ_S3CUART_BASE1 (20)
36#define IRQ_S3CUART_BASE2 (24)
37#define IRQ_S3CUART_BASE3 (28)
38
39#define UART_IRQ_RXD (0)
40#define UART_IRQ_ERR (1)
41#define UART_IRQ_TXD (2)
42#define UART_IRQ_MODEM (3)
43
44#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
45#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
46#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
47
48#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
49#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
50#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
51
52#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
53#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
54#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
55
56#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
57#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
58#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
59
60/* VIC based IRQs */ 30/* VIC based IRQs */
61 31
62#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x)) 32#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x))
diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c
index 75d9a0e49193..b07357e94958 100644
--- a/arch/arm/mach-s3c64xx/irq.c
+++ b/arch/arm/mach-s3c64xx/irq.c
@@ -25,29 +25,6 @@
25#include <plat/irq-uart.h> 25#include <plat/irq-uart.h>
26#include <plat/cpu.h> 26#include <plat/cpu.h>
27 27
28static struct s3c_uart_irq uart_irqs[] = {
29 [0] = {
30 .regs = S3C_VA_UART0,
31 .base_irq = IRQ_S3CUART_BASE0,
32 .parent_irq = IRQ_UART0,
33 },
34 [1] = {
35 .regs = S3C_VA_UART1,
36 .base_irq = IRQ_S3CUART_BASE1,
37 .parent_irq = IRQ_UART1,
38 },
39 [2] = {
40 .regs = S3C_VA_UART2,
41 .base_irq = IRQ_S3CUART_BASE2,
42 .parent_irq = IRQ_UART2,
43 },
44 [3] = {
45 .regs = S3C_VA_UART3,
46 .base_irq = IRQ_S3CUART_BASE3,
47 .parent_irq = IRQ_UART3,
48 },
49};
50
51/* setup the sources the vic should advertise resume for, even though it 28/* setup the sources the vic should advertise resume for, even though it
52 * is not doing the wake (set_irq_wake needs to be valid) */ 29 * is not doing the wake (set_irq_wake needs to be valid) */
53#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE)) 30#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
@@ -67,6 +44,4 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
67 44
68 /* add the timer sub-irqs */ 45 /* add the timer sub-irqs */
69 s3c_init_vic_timer_irq(5, IRQ_TIMER0); 46 s3c_init_vic_timer_irq(5, IRQ_TIMER0);
70
71 s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
72} 47}
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 9843c954c042..9a197e55f669 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -22,7 +22,6 @@ config PLAT_S5P
22 select PLAT_SAMSUNG 22 select PLAT_SAMSUNG
23 select SAMSUNG_CLKSRC 23 select SAMSUNG_CLKSRC
24 select SAMSUNG_IRQ_VIC_TIMER 24 select SAMSUNG_IRQ_VIC_TIMER
25 select SAMSUNG_IRQ_UART
26 help 25 help
27 Base platform code for Samsung's S5P series SoC. 26 Base platform code for Samsung's S5P series SoC.
28 27
diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c
index afaf87fdb93e..c9308db36183 100644
--- a/arch/arm/plat-s5p/dev-uart.c
+++ b/arch/arm/plat-s5p/dev-uart.c
@@ -32,20 +32,10 @@ static struct resource s5p_uart0_resource[] = {
32 .flags = IORESOURCE_MEM, 32 .flags = IORESOURCE_MEM,
33 }, 33 },
34 [1] = { 34 [1] = {
35 .start = IRQ_S5P_UART_RX0, 35 .start = IRQ_UART0,
36 .end = IRQ_S5P_UART_RX0, 36 .end = IRQ_UART0,
37 .flags = IORESOURCE_IRQ, 37 .flags = IORESOURCE_IRQ,
38 }, 38 },
39 [2] = {
40 .start = IRQ_S5P_UART_TX0,
41 .end = IRQ_S5P_UART_TX0,
42 .flags = IORESOURCE_IRQ,
43 },
44 [3] = {
45 .start = IRQ_S5P_UART_ERR0,
46 .end = IRQ_S5P_UART_ERR0,
47 .flags = IORESOURCE_IRQ,
48 }
49}; 39};
50 40
51static struct resource s5p_uart1_resource[] = { 41static struct resource s5p_uart1_resource[] = {
@@ -55,18 +45,8 @@ static struct resource s5p_uart1_resource[] = {
55 .flags = IORESOURCE_MEM, 45 .flags = IORESOURCE_MEM,
56 }, 46 },
57 [1] = { 47 [1] = {
58 .start = IRQ_S5P_UART_RX1, 48 .start = IRQ_UART1,
59 .end = IRQ_S5P_UART_RX1, 49 .end = IRQ_UART1,
60 .flags = IORESOURCE_IRQ,
61 },
62 [2] = {
63 .start = IRQ_S5P_UART_TX1,
64 .end = IRQ_S5P_UART_TX1,
65 .flags = IORESOURCE_IRQ,
66 },
67 [3] = {
68 .start = IRQ_S5P_UART_ERR1,
69 .end = IRQ_S5P_UART_ERR1,
70 .flags = IORESOURCE_IRQ, 50 .flags = IORESOURCE_IRQ,
71 }, 51 },
72}; 52};
@@ -78,18 +58,8 @@ static struct resource s5p_uart2_resource[] = {
78 .flags = IORESOURCE_MEM, 58 .flags = IORESOURCE_MEM,
79 }, 59 },
80 [1] = { 60 [1] = {
81 .start = IRQ_S5P_UART_RX2, 61 .start = IRQ_UART2,
82 .end = IRQ_S5P_UART_RX2, 62 .end = IRQ_UART2,
83 .flags = IORESOURCE_IRQ,
84 },
85 [2] = {
86 .start = IRQ_S5P_UART_TX2,
87 .end = IRQ_S5P_UART_TX2,
88 .flags = IORESOURCE_IRQ,
89 },
90 [3] = {
91 .start = IRQ_S5P_UART_ERR2,
92 .end = IRQ_S5P_UART_ERR2,
93 .flags = IORESOURCE_IRQ, 63 .flags = IORESOURCE_IRQ,
94 }, 64 },
95}; 65};
@@ -102,18 +72,8 @@ static struct resource s5p_uart3_resource[] = {
102 .flags = IORESOURCE_MEM, 72 .flags = IORESOURCE_MEM,
103 }, 73 },
104 [1] = { 74 [1] = {
105 .start = IRQ_S5P_UART_RX3, 75 .start = IRQ_UART3,
106 .end = IRQ_S5P_UART_RX3, 76 .end = IRQ_UART3,
107 .flags = IORESOURCE_IRQ,
108 },
109 [2] = {
110 .start = IRQ_S5P_UART_TX3,
111 .end = IRQ_S5P_UART_TX3,
112 .flags = IORESOURCE_IRQ,
113 },
114 [3] = {
115 .start = IRQ_S5P_UART_ERR3,
116 .end = IRQ_S5P_UART_ERR3,
117 .flags = IORESOURCE_IRQ, 77 .flags = IORESOURCE_IRQ,
118 }, 78 },
119#endif 79#endif
@@ -127,18 +87,8 @@ static struct resource s5p_uart4_resource[] = {
127 .flags = IORESOURCE_MEM, 87 .flags = IORESOURCE_MEM,
128 }, 88 },
129 [1] = { 89 [1] = {
130 .start = IRQ_S5P_UART_RX4, 90 .start = IRQ_UART4,
131 .end = IRQ_S5P_UART_RX4, 91 .end = IRQ_UART4,
132 .flags = IORESOURCE_IRQ,
133 },
134 [2] = {
135 .start = IRQ_S5P_UART_TX4,
136 .end = IRQ_S5P_UART_TX4,
137 .flags = IORESOURCE_IRQ,
138 },
139 [3] = {
140 .start = IRQ_S5P_UART_ERR4,
141 .end = IRQ_S5P_UART_ERR4,
142 .flags = IORESOURCE_IRQ, 92 .flags = IORESOURCE_IRQ,
143 }, 93 },
144#endif 94#endif
@@ -152,18 +102,8 @@ static struct resource s5p_uart5_resource[] = {
152 .flags = IORESOURCE_MEM, 102 .flags = IORESOURCE_MEM,
153 }, 103 },
154 [1] = { 104 [1] = {
155 .start = IRQ_S5P_UART_RX5, 105 .start = IRQ_UART5,
156 .end = IRQ_S5P_UART_RX5, 106 .end = IRQ_UART5,
157 .flags = IORESOURCE_IRQ,
158 },
159 [2] = {
160 .start = IRQ_S5P_UART_TX5,
161 .end = IRQ_S5P_UART_TX5,
162 .flags = IORESOURCE_IRQ,
163 },
164 [3] = {
165 .start = IRQ_S5P_UART_ERR5,
166 .end = IRQ_S5P_UART_ERR5,
167 .flags = IORESOURCE_IRQ, 107 .flags = IORESOURCE_IRQ,
168 }, 108 },
169#endif 109#endif
diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h
index ba9121c60a2a..144dbfc6506d 100644
--- a/arch/arm/plat-s5p/include/plat/irqs.h
+++ b/arch/arm/plat-s5p/include/plat/irqs.h
@@ -37,41 +37,6 @@
37#define IRQ_VIC1_BASE S5P_VIC1_BASE 37#define IRQ_VIC1_BASE S5P_VIC1_BASE
38#define IRQ_VIC2_BASE S5P_VIC2_BASE 38#define IRQ_VIC2_BASE S5P_VIC2_BASE
39 39
40/* UART interrupts, each UART has 4 intterupts per channel so
41 * use the space between the ISA and S3C main interrupts. Note, these
42 * are not in the same order as the S3C24XX series! */
43
44#define IRQ_S5P_UART_BASE0 (16)
45#define IRQ_S5P_UART_BASE1 (20)
46#define IRQ_S5P_UART_BASE2 (24)
47#define IRQ_S5P_UART_BASE3 (28)
48
49#define UART_IRQ_RXD (0)
50#define UART_IRQ_ERR (1)
51#define UART_IRQ_TXD (2)
52
53#define IRQ_S5P_UART_RX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_RXD)
54#define IRQ_S5P_UART_TX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_TXD)
55#define IRQ_S5P_UART_ERR0 (IRQ_S5P_UART_BASE0 + UART_IRQ_ERR)
56
57#define IRQ_S5P_UART_RX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_RXD)
58#define IRQ_S5P_UART_TX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_TXD)
59#define IRQ_S5P_UART_ERR1 (IRQ_S5P_UART_BASE1 + UART_IRQ_ERR)
60
61#define IRQ_S5P_UART_RX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_RXD)
62#define IRQ_S5P_UART_TX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_TXD)
63#define IRQ_S5P_UART_ERR2 (IRQ_S5P_UART_BASE2 + UART_IRQ_ERR)
64
65#define IRQ_S5P_UART_RX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_RXD)
66#define IRQ_S5P_UART_TX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_TXD)
67#define IRQ_S5P_UART_ERR3 (IRQ_S5P_UART_BASE3 + UART_IRQ_ERR)
68
69/* S3C compatibilty defines */
70#define IRQ_S3CUART_RX0 IRQ_S5P_UART_RX0
71#define IRQ_S3CUART_RX1 IRQ_S5P_UART_RX1
72#define IRQ_S3CUART_RX2 IRQ_S5P_UART_RX2
73#define IRQ_S3CUART_RX3 IRQ_S5P_UART_RX3
74
75/* VIC based IRQs */ 40/* VIC based IRQs */
76 41
77#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x)) 42#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x))
diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c
index a97c08957f49..afdaa1082b9f 100644
--- a/arch/arm/plat-s5p/irq.c
+++ b/arch/arm/plat-s5p/irq.c
@@ -17,42 +17,10 @@
17 17
18#include <asm/hardware/vic.h> 18#include <asm/hardware/vic.h>
19 19
20#include <linux/serial_core.h>
21#include <mach/map.h> 20#include <mach/map.h>
22#include <plat/regs-timer.h> 21#include <plat/regs-timer.h>
23#include <plat/regs-serial.h>
24#include <plat/cpu.h> 22#include <plat/cpu.h>
25#include <plat/irq-vic-timer.h> 23#include <plat/irq-vic-timer.h>
26#include <plat/irq-uart.h>
27
28/*
29 * Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
30 * are consecutive when looking up the interrupt in the demux routines.
31 */
32static struct s3c_uart_irq uart_irqs[] = {
33 [0] = {
34 .regs = S5P_VA_UART0,
35 .base_irq = IRQ_S5P_UART_BASE0,
36 .parent_irq = IRQ_UART0,
37 },
38 [1] = {
39 .regs = S5P_VA_UART1,
40 .base_irq = IRQ_S5P_UART_BASE1,
41 .parent_irq = IRQ_UART1,
42 },
43 [2] = {
44 .regs = S5P_VA_UART2,
45 .base_irq = IRQ_S5P_UART_BASE2,
46 .parent_irq = IRQ_UART2,
47 },
48#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
49 [3] = {
50 .regs = S5P_VA_UART3,
51 .base_irq = IRQ_S5P_UART_BASE3,
52 .parent_irq = IRQ_UART3,
53 },
54#endif
55};
56 24
57void __init s5p_init_irq(u32 *vic, u32 num_vic) 25void __init s5p_init_irq(u32 *vic, u32 num_vic)
58{ 26{
@@ -65,6 +33,4 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic)
65#endif 33#endif
66 34
67 s3c_init_vic_timer_irq(5, IRQ_TIMER0); 35 s3c_init_vic_timer_irq(5, IRQ_TIMER0);
68
69 s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
70} 36}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index b3e10659e4b8..dffa37bc4a0b 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -65,11 +65,6 @@ config SAMSUNG_IRQ_VIC_TIMER
65 help 65 help
66 Internal configuration to build the VIC timer interrupt code. 66 Internal configuration to build the VIC timer interrupt code.
67 67
68config SAMSUNG_IRQ_UART
69 bool
70 help
71 Internal configuration to build the IRQ UART demux code.
72
73# options for gpio configuration support 68# options for gpio configuration support
74 69
75config SAMSUNG_GPIOLIB_4BIT 70config SAMSUNG_GPIOLIB_4BIT
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 853764ba8cc5..1105922342fe 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -21,7 +21,6 @@ obj-y += dev-asocdma.o
21 21
22obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o 22obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
23 23
24obj-$(CONFIG_SAMSUNG_IRQ_UART) += irq-uart.o
25obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o 24obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o
26 25
27# ADC 26# ADC
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h
index bac36fa3becb..720734847027 100644
--- a/arch/arm/plat-samsung/include/plat/regs-serial.h
+++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -186,6 +186,11 @@
186#define S3C64XX_UINTSP 0x34 186#define S3C64XX_UINTSP 0x34
187#define S3C64XX_UINTM 0x38 187#define S3C64XX_UINTM 0x38
188 188
189#define S3C64XX_UINTM_RXD (0)
190#define S3C64XX_UINTM_TXD (2)
191#define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD)
192#define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD)
193
189/* Following are specific to S5PV210 */ 194/* Following are specific to S5PV210 */
190#define S5PV210_UCON_CLKMASK (1<<10) 195#define S5PV210_UCON_CLKMASK (1<<10)
191#define S5PV210_UCON_PCLK (0<<10) 196#define S5PV210_UCON_PCLK (0<<10)
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
deleted file mode 100644
index 3014c7226bd1..000000000000
--- a/arch/arm/plat-samsung/irq-uart.c
+++ /dev/null
@@ -1,96 +0,0 @@
1/* arch/arm/plat-samsung/irq-uart.c
2 * originally part of arch/arm/plat-s3c64xx/irq.c
3 *
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * Samsung- UART Interrupt handling
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/serial_core.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21
22#include <asm/mach/irq.h>
23
24#include <mach/map.h>
25#include <plat/irq-uart.h>
26#include <plat/regs-serial.h>
27#include <plat/cpu.h>
28
29/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
30 * are consecutive when looking up the interrupt in the demux routines.
31 */
32static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
33{
34 struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
35 struct irq_chip *chip = irq_get_chip(irq);
36 u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
37 int base = uirq->base_irq;
38
39 chained_irq_enter(chip, desc);
40
41 if (pend & (1 << 0))
42 generic_handle_irq(base);
43 if (pend & (1 << 1))
44 generic_handle_irq(base + 1);
45 if (pend & (1 << 2))
46 generic_handle_irq(base + 2);
47 if (pend & (1 << 3))
48 generic_handle_irq(base + 3);
49
50 chained_irq_exit(chip, desc);
51}
52
53static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
54{
55 void __iomem *reg_base = uirq->regs;
56 struct irq_chip_generic *gc;
57 struct irq_chip_type *ct;
58
59 /* mask all interrupts at the start. */
60 __raw_writel(0xf, reg_base + S3C64XX_UINTM);
61
62 gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base,
63 handle_level_irq);
64
65 if (!gc) {
66 pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n",
67 __func__, uirq->base_irq);
68 return;
69 }
70
71 ct = gc->chip_types;
72 ct->chip.irq_ack = irq_gc_ack_set_bit;
73 ct->chip.irq_mask = irq_gc_mask_set_bit;
74 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
75 ct->regs.ack = S3C64XX_UINTP;
76 ct->regs.mask = S3C64XX_UINTM;
77 irq_setup_generic_chip(gc, IRQ_MSK(4), IRQ_GC_INIT_MASK_CACHE,
78 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
79
80 irq_set_handler_data(uirq->parent_irq, uirq);
81 irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
82}
83
84/**
85 * s3c_init_uart_irqs() - initialise UART IRQs and the necessary demuxing
86 * @irq: The interrupt data for registering
87 * @nr_irqs: The number of interrupt descriptions in @irq.
88 *
89 * Register the UART interrupts specified by @irq including the demuxing
90 * routines. This supports the S3C6400 and newer style of devices.
91 */
92void __init s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs)
93{
94 for (; nr_irqs > 0; nr_irqs--, irq++)
95 s3c_init_uart_irq(irq);
96}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 05:17:43 -0500