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authorPaul Mundt <lethal@linux-sh.org>2009-06-24 05:23:52 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-06-24 05:23:52 -0400
commit26c92f3728d738aaa7e4859d5581323cd68096dd (patch)
treeb7cc2f49a6ffe6a6b88d19b33547a370ae314de6
parent00b9de9c249f51f09c19aa41cbbb3e3eb4eea807 (diff)
serial: sh-sci: Move SCBRR calculation algo in to platform data.
This permits each port to select its own SCBRR calculation algorithm, rather than having it all ifdef'ed in the header. There are presently only 5 different variations that all parts fall under. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c3
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-mxg.c1
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c8
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c4
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c4
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c2
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c3
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c2
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c2
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh4-202.c1
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c2
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c4
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c4
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c1
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c3
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c3
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c10
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c4
-rw-r--r--arch/sh/kernel/cpu/sh5/setup-sh5.c1
-rw-r--r--drivers/serial/sh-sci.c27
-rw-r--r--drivers/serial/sh-sci.h56
-rw-r--r--include/linux/serial_sci.h9
27 files changed, 122 insertions, 58 deletions
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index ace016b17036..86acede777b9 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -64,18 +64,21 @@ static struct plat_sci_port sci_platform_data[] = {
64 .mapbase = 0xf8400000, 64 .mapbase = 0xf8400000,
65 .flags = UPF_BOOT_AUTOCONF, 65 .flags = UPF_BOOT_AUTOCONF,
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2,
67 .type = PORT_SCIF, 68 .type = PORT_SCIF,
68 .irqs = { 88, 88, 88, 88 }, 69 .irqs = { 88, 88, 88, 88 },
69 }, { 70 }, {
70 .mapbase = 0xf8410000, 71 .mapbase = 0xf8410000,
71 .flags = UPF_BOOT_AUTOCONF, 72 .flags = UPF_BOOT_AUTOCONF,
72 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
74 .scbrr_algo_id = SCBRR_ALGO_2,
73 .type = PORT_SCIF, 75 .type = PORT_SCIF,
74 .irqs = { 92, 92, 92, 92 }, 76 .irqs = { 92, 92, 92, 92 },
75 }, { 77 }, {
76 .mapbase = 0xf8420000, 78 .mapbase = 0xf8420000,
77 .flags = UPF_BOOT_AUTOCONF, 79 .flags = UPF_BOOT_AUTOCONF,
78 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 80 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
81 .scbrr_algo_id = SCBRR_ALGO_2,
79 .type = PORT_SCIF, 82 .type = PORT_SCIF,
80 .irqs = { 96, 96, 96, 96 }, 83 .irqs = { 96, 96, 96, 96 },
81 }, { 84 }, {
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index 7ec658ce14f8..b2c3bcc01190 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -212,6 +212,7 @@ static struct plat_sci_port sci_platform_data[] = {
212 .mapbase = 0xff804000, 212 .mapbase = 0xff804000,
213 .flags = UPF_BOOT_AUTOCONF, 213 .flags = UPF_BOOT_AUTOCONF,
214 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 214 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
215 .scbrr_algo_id = SCBRR_ALGO_2,
215 .type = PORT_SCIF, 216 .type = PORT_SCIF,
216 .irqs = { 220, 220, 220, 220 }, 217 .irqs = { 220, 220, 220, 220 },
217 }, { 218 }, {
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index 2a2ac222f9c7..8d44917ce50b 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -182,48 +182,56 @@ static struct plat_sci_port sci_platform_data[] = {
182 .mapbase = 0xfffe8000, 182 .mapbase = 0xfffe8000,
183 .flags = UPF_BOOT_AUTOCONF, 183 .flags = UPF_BOOT_AUTOCONF,
184 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 184 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
185 .scbrr_algo_id = SCBRR_ALGO_2,
185 .type = PORT_SCIF, 186 .type = PORT_SCIF,
186 .irqs = { 180, 180, 180, 180 } 187 .irqs = { 180, 180, 180, 180 }
187 }, { 188 }, {
188 .mapbase = 0xfffe8800, 189 .mapbase = 0xfffe8800,
189 .flags = UPF_BOOT_AUTOCONF, 190 .flags = UPF_BOOT_AUTOCONF,
190 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 191 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
192 .scbrr_algo_id = SCBRR_ALGO_2,
191 .type = PORT_SCIF, 193 .type = PORT_SCIF,
192 .irqs = { 184, 184, 184, 184 } 194 .irqs = { 184, 184, 184, 184 }
193 }, { 195 }, {
194 .mapbase = 0xfffe9000, 196 .mapbase = 0xfffe9000,
195 .flags = UPF_BOOT_AUTOCONF, 197 .flags = UPF_BOOT_AUTOCONF,
196 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 198 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
199 .scbrr_algo_id = SCBRR_ALGO_2,
197 .type = PORT_SCIF, 200 .type = PORT_SCIF,
198 .irqs = { 188, 188, 188, 188 } 201 .irqs = { 188, 188, 188, 188 }
199 }, { 202 }, {
200 .mapbase = 0xfffe9800, 203 .mapbase = 0xfffe9800,
201 .flags = UPF_BOOT_AUTOCONF, 204 .flags = UPF_BOOT_AUTOCONF,
202 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 205 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
206 .scbrr_algo_id = SCBRR_ALGO_2,
203 .type = PORT_SCIF, 207 .type = PORT_SCIF,
204 .irqs = { 192, 192, 192, 192 } 208 .irqs = { 192, 192, 192, 192 }
205 }, { 209 }, {
206 .mapbase = 0xfffea000, 210 .mapbase = 0xfffea000,
207 .flags = UPF_BOOT_AUTOCONF, 211 .flags = UPF_BOOT_AUTOCONF,
208 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 212 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
213 .scbrr_algo_id = SCBRR_ALGO_2,
209 .type = PORT_SCIF, 214 .type = PORT_SCIF,
210 .irqs = { 196, 196, 196, 196 } 215 .irqs = { 196, 196, 196, 196 }
211 }, { 216 }, {
212 .mapbase = 0xfffea800, 217 .mapbase = 0xfffea800,
213 .flags = UPF_BOOT_AUTOCONF, 218 .flags = UPF_BOOT_AUTOCONF,
214 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 219 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
220 .scbrr_algo_id = SCBRR_ALGO_2,
215 .type = PORT_SCIF, 221 .type = PORT_SCIF,
216 .irqs = { 200, 200, 200, 200 } 222 .irqs = { 200, 200, 200, 200 }
217 }, { 223 }, {
218 .mapbase = 0xfffeb000, 224 .mapbase = 0xfffeb000,
219 .flags = UPF_BOOT_AUTOCONF, 225 .flags = UPF_BOOT_AUTOCONF,
220 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 226 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
227 .scbrr_algo_id = SCBRR_ALGO_2,
221 .type = PORT_SCIF, 228 .type = PORT_SCIF,
222 .irqs = { 204, 204, 204, 204 } 229 .irqs = { 204, 204, 204, 204 }
223 }, { 230 }, {
224 .mapbase = 0xfffeb800, 231 .mapbase = 0xfffeb800,
225 .flags = UPF_BOOT_AUTOCONF, 232 .flags = UPF_BOOT_AUTOCONF,
226 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 233 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
234 .scbrr_algo_id = SCBRR_ALGO_2,
227 .type = PORT_SCIF, 235 .type = PORT_SCIF,
228 .irqs = { 208, 208, 208, 208 } 236 .irqs = { 208, 208, 208, 208 }
229 }, { 237 }, {
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index 2c9f3ababfd7..a78d2a219f3b 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -178,24 +178,28 @@ static struct plat_sci_port sci_platform_data[] = {
178 .mapbase = 0xfffe8000, 178 .mapbase = 0xfffe8000,
179 .flags = UPF_BOOT_AUTOCONF, 179 .flags = UPF_BOOT_AUTOCONF,
180 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 180 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
181 .scbrr_algo_id = SCBRR_ALGO_2,
181 .type = PORT_SCIF, 182 .type = PORT_SCIF,
182 .irqs = { 192, 192, 192, 192 }, 183 .irqs = { 192, 192, 192, 192 },
183 }, { 184 }, {
184 .mapbase = 0xfffe8800, 185 .mapbase = 0xfffe8800,
185 .flags = UPF_BOOT_AUTOCONF, 186 .flags = UPF_BOOT_AUTOCONF,
186 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 187 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
188 .scbrr_algo_id = SCBRR_ALGO_2,
187 .type = PORT_SCIF, 189 .type = PORT_SCIF,
188 .irqs = { 196, 196, 196, 196 }, 190 .irqs = { 196, 196, 196, 196 },
189 }, { 191 }, {
190 .mapbase = 0xfffe9000, 192 .mapbase = 0xfffe9000,
191 .flags = UPF_BOOT_AUTOCONF, 193 .flags = UPF_BOOT_AUTOCONF,
192 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 194 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
195 .scbrr_algo_id = SCBRR_ALGO_2,
193 .type = PORT_SCIF, 196 .type = PORT_SCIF,
194 .irqs = { 200, 200, 200, 200 }, 197 .irqs = { 200, 200, 200, 200 },
195 }, { 198 }, {
196 .mapbase = 0xfffe9800, 199 .mapbase = 0xfffe9800,
197 .flags = UPF_BOOT_AUTOCONF, 200 .flags = UPF_BOOT_AUTOCONF,
198 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 201 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
202 .scbrr_algo_id = SCBRR_ALGO_2,
199 .type = PORT_SCIF, 203 .type = PORT_SCIF,
200 .irqs = { 204, 204, 204, 204 }, 204 .irqs = { 204, 204, 204, 204 },
201 }, { 205 }, {
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index 5a47987f3902..68b93ed44cc2 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -138,24 +138,28 @@ static struct plat_sci_port sci_platform_data[] = {
138 .mapbase = 0xfffe8000, 138 .mapbase = 0xfffe8000,
139 .flags = UPF_BOOT_AUTOCONF, 139 .flags = UPF_BOOT_AUTOCONF,
140 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 140 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
141 .scbrr_algo_id = SCBRR_ALGO_2,
141 .type = PORT_SCIF, 142 .type = PORT_SCIF,
142 .irqs = { 240, 240, 240, 240 }, 143 .irqs = { 240, 240, 240, 240 },
143 }, { 144 }, {
144 .mapbase = 0xfffe8800, 145 .mapbase = 0xfffe8800,
145 .flags = UPF_BOOT_AUTOCONF, 146 .flags = UPF_BOOT_AUTOCONF,
146 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 147 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
148 .scbrr_algo_id = SCBRR_ALGO_2,
147 .type = PORT_SCIF, 149 .type = PORT_SCIF,
148 .irqs = { 244, 244, 244, 244 }, 150 .irqs = { 244, 244, 244, 244 },
149 }, { 151 }, {
150 .mapbase = 0xfffe9000, 152 .mapbase = 0xfffe9000,
151 .flags = UPF_BOOT_AUTOCONF, 153 .flags = UPF_BOOT_AUTOCONF,
152 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 154 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
155 .scbrr_algo_id = SCBRR_ALGO_2,
153 .type = PORT_SCIF, 156 .type = PORT_SCIF,
154 .irqs = { 248, 248, 248, 248 }, 157 .irqs = { 248, 248, 248, 248 },
155 }, { 158 }, {
156 .mapbase = 0xfffe9800, 159 .mapbase = 0xfffe9800,
157 .flags = UPF_BOOT_AUTOCONF, 160 .flags = UPF_BOOT_AUTOCONF,
158 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 161 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
162 .scbrr_algo_id = SCBRR_ALGO_2,
159 .type = PORT_SCIF, 163 .type = PORT_SCIF,
160 .irqs = { 252, 252, 252, 252 }, 164 .irqs = { 252, 252, 252, 252 },
161 }, { 165 }, {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 28de53b281f3..27d03d836056 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -73,12 +73,14 @@ static struct plat_sci_port sci_platform_data[] = {
73 .flags = UPF_BOOT_AUTOCONF, 73 .flags = UPF_BOOT_AUTOCONF,
74 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | 74 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE |
75 SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, 75 SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0,
76 .scbrr_algo_id = SCBRR_ALGO_4,
76 .type = PORT_SCIF, 77 .type = PORT_SCIF,
77 .irqs = { 56, 56, 56 }, 78 .irqs = { 56, 56, 56 },
78 }, { 79 }, {
79 .mapbase = 0xa4400000, 80 .mapbase = 0xa4400000,
80 .flags = UPF_BOOT_AUTOCONF, 81 .flags = UPF_BOOT_AUTOCONF,
81 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, 82 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
83 .scbrr_algo_id = SCBRR_ALGO_4,
82 .type = PORT_SCIF, 84 .type = PORT_SCIF,
83 .irqs = { 52, 52, 52 }, 85 .irqs = { 52, 52, 52 },
84 }, { 86 }, {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index 50ac42836dc7..83c9a5a39685 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -111,6 +111,7 @@ static struct plat_sci_port sci_platform_data[] = {
111 .mapbase = 0xfffffe80, 111 .mapbase = 0xfffffe80,
112 .flags = UPF_BOOT_AUTOCONF, 112 .flags = UPF_BOOT_AUTOCONF,
113 .scscr = SCSCR_TE | SCSCR_RE, 113 .scscr = SCSCR_TE | SCSCR_RE,
114 .scbrr_algo_id = SCBRR_ALGO_2,
114 .type = PORT_SCI, 115 .type = PORT_SCI,
115 .irqs = { 23, 23, 23, 0 }, 116 .irqs = { 23, 23, 23, 0 },
116 }, 117 },
@@ -121,6 +122,7 @@ static struct plat_sci_port sci_platform_data[] = {
121 .mapbase = 0xa4000150, 122 .mapbase = 0xa4000150,
122 .flags = UPF_BOOT_AUTOCONF, 123 .flags = UPF_BOOT_AUTOCONF,
123 .scscr = SCSCR_TE | SCSCR_RE, 124 .scscr = SCSCR_TE | SCSCR_RE,
125 .scbrr_algo_id = SCBRR_ALGO_2,
124 .type = PORT_SCIF, 126 .type = PORT_SCIF,
125 .irqs = { 56, 56, 56, 56 }, 127 .irqs = { 56, 56, 56, 56 },
126 }, 128 },
@@ -131,6 +133,7 @@ static struct plat_sci_port sci_platform_data[] = {
131 .mapbase = 0xa4000140, 133 .mapbase = 0xa4000140,
132 .flags = UPF_BOOT_AUTOCONF, 134 .flags = UPF_BOOT_AUTOCONF,
133 .scscr = SCSCR_TE | SCSCR_RE, 135 .scscr = SCSCR_TE | SCSCR_RE,
136 .scbrr_algo_id = SCBRR_ALGO_2,
134 .type = PORT_IRDA, 137 .type = PORT_IRDA,
135 .irqs = { 52, 52, 52, 52 }, 138 .irqs = { 52, 52, 52, 52 },
136 }, 139 },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 007627ecb7c8..9a60ffd34a9f 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -102,6 +102,7 @@ static struct plat_sci_port sci_platform_data[] = {
102 .flags = UPF_BOOT_AUTOCONF, 102 .flags = UPF_BOOT_AUTOCONF,
103 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | 103 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
104 SCSCR_CKE1 | SCSCR_CKE0, 104 SCSCR_CKE1 | SCSCR_CKE0,
105 .scbrr_algo_id = SCBRR_ALGO_2,
105 .type = PORT_SCIF, 106 .type = PORT_SCIF,
106 .irqs = { 52, 52, 52, 52 }, 107 .irqs = { 52, 52, 52, 52 },
107 }, { 108 }, {
@@ -109,6 +110,7 @@ static struct plat_sci_port sci_platform_data[] = {
109 .flags = UPF_BOOT_AUTOCONF, 110 .flags = UPF_BOOT_AUTOCONF,
110 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | 111 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
111 SCSCR_CKE1 | SCSCR_CKE0, 112 SCSCR_CKE1 | SCSCR_CKE0,
113 .scbrr_algo_id = SCBRR_ALGO_2,
112 .type = PORT_SCIF, 114 .type = PORT_SCIF,
113 .irqs = { 56, 56, 56, 56 }, 115 .irqs = { 56, 56, 56, 56 },
114 }, { 116 }, {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 1fc3d9089199..48d50a65db32 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -53,12 +53,14 @@ static struct plat_sci_port sci_platform_data[] = {
53 .mapbase = 0xa4430000, 53 .mapbase = 0xa4430000,
54 .flags = UPF_BOOT_AUTOCONF, 54 .flags = UPF_BOOT_AUTOCONF,
55 .scscr = SCSCR_RE | SCSCR_TE, 55 .scscr = SCSCR_RE | SCSCR_TE,
56 .scbrr_algo_id = SCBRR_ALGO_4,
56 .type = PORT_SCIF, 57 .type = PORT_SCIF,
57 .irqs = { 80, 80, 80, 80 }, 58 .irqs = { 80, 80, 80, 80 },
58 }, { 59 }, {
59 .mapbase = 0xa4438000, 60 .mapbase = 0xa4438000,
60 .flags = UPF_BOOT_AUTOCONF, 61 .flags = UPF_BOOT_AUTOCONF,
61 .scscr = SCSCR_RE | SCSCR_TE, 62 .scscr = SCSCR_RE | SCSCR_TE,
63 .scbrr_algo_id = SCBRR_ALGO_4,
62 .type = PORT_SCIF, 64 .type = PORT_SCIF,
63 .irqs = { 81, 81, 81, 81 }, 65 .irqs = { 81, 81, 81, 81 },
64 }, { 66 }, {
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index 9aa6fa3ca4e6..ec2104b49ef7 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -20,6 +20,7 @@ static struct plat_sci_port sci_platform_data[] = {
20 .mapbase = 0xffe80000, 20 .mapbase = 0xffe80000,
21 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23 .scbrr_algo_id = SCBRR_ALGO_2,
23 .type = PORT_SCIF, 24 .type = PORT_SCIF,
24 .irqs = { 40, 41, 43, 42 }, 25 .irqs = { 40, 41, 43, 42 },
25 }, { 26 }, {
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 2159c439dce9..51a945e0d72c 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -41,6 +41,7 @@ static struct plat_sci_port sci_platform_data = {
41 .flags = UPF_BOOT_AUTOCONF, 41 .flags = UPF_BOOT_AUTOCONF,
42 .type = PORT_SCI, 42 .type = PORT_SCI,
43 .scscr = SCSCR_TE | SCSCR_RE, 43 .scscr = SCSCR_TE | SCSCR_RE,
44 .scbrr_algo_id = SCBRR_ALGO_2,
44 .irqs = { 23, 23, 23, 0 }, 45 .irqs = { 23, 23, 23, 0 },
45}; 46};
46 47
@@ -55,6 +56,7 @@ static struct plat_sci_port scif_platform_data = {
55 .mapbase = 0xffe80000, 56 .mapbase = 0xffe80000,
56 .flags = UPF_BOOT_AUTOCONF, 57 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, 58 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
59 .scbrr_algo_id = SCBRR_ALGO_2,
58 .type = PORT_SCIF, 60 .type = PORT_SCIF,
59 .irqs = { 40, 40, 40, 40 }, 61 .irqs = { 40, 40, 40, 40 },
60}; 62};
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 74b5e994724d..cee660fe1d90 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -131,24 +131,28 @@ static struct plat_sci_port sci_platform_data[] = {
131 .mapbase = 0xfe600000, 131 .mapbase = 0xfe600000,
132 .flags = UPF_BOOT_AUTOCONF, 132 .flags = UPF_BOOT_AUTOCONF,
133 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 133 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
134 .scbrr_algo_id = SCBRR_ALGO_2,
134 .type = PORT_SCIF, 135 .type = PORT_SCIF,
135 .irqs = { 52, 53, 55, 54 }, 136 .irqs = { 52, 53, 55, 54 },
136 }, { 137 }, {
137 .mapbase = 0xfe610000, 138 .mapbase = 0xfe610000,
138 .flags = UPF_BOOT_AUTOCONF, 139 .flags = UPF_BOOT_AUTOCONF,
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 140 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
141 .scbrr_algo_id = SCBRR_ALGO_2,
140 .type = PORT_SCIF, 142 .type = PORT_SCIF,
141 .irqs = { 72, 73, 75, 74 }, 143 .irqs = { 72, 73, 75, 74 },
142 }, { 144 }, {
143 .mapbase = 0xfe620000, 145 .mapbase = 0xfe620000,
144 .flags = UPF_BOOT_AUTOCONF, 146 .flags = UPF_BOOT_AUTOCONF,
145 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 147 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
148 .scbrr_algo_id = SCBRR_ALGO_2,
146 .type = PORT_SCIF, 149 .type = PORT_SCIF,
147 .irqs = { 76, 77, 79, 78 }, 150 .irqs = { 76, 77, 79, 78 },
148 }, { 151 }, {
149 .mapbase = 0xfe480000, 152 .mapbase = 0xfe480000,
150 .flags = UPF_BOOT_AUTOCONF, 153 .flags = UPF_BOOT_AUTOCONF,
151 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 154 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
155 .scbrr_algo_id = SCBRR_ALGO_2,
152 .type = PORT_SCI, 156 .type = PORT_SCI,
153 .irqs = { 80, 81, 82, 0 }, 157 .irqs = { 80, 81, 82, 0 },
154 }, { 158 }, {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 09fb5814d925..fbae06b1c98d 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -270,6 +270,7 @@ static struct plat_sci_port sci_platform_data[] = {
270 .mapbase = 0xffe00000, 270 .mapbase = 0xffe00000,
271 .flags = UPF_BOOT_AUTOCONF, 271 .flags = UPF_BOOT_AUTOCONF,
272 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 272 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
273 .scbrr_algo_id = SCBRR_ALGO_2,
273 .type = PORT_SCIF, 274 .type = PORT_SCIF,
274 .irqs = { 80, 80, 80, 80 }, 275 .irqs = { 80, 80, 80, 80 },
275 .clk = "scif0", 276 .clk = "scif0",
@@ -277,6 +278,7 @@ static struct plat_sci_port sci_platform_data[] = {
277 .mapbase = 0xffe10000, 278 .mapbase = 0xffe10000,
278 .flags = UPF_BOOT_AUTOCONF, 279 .flags = UPF_BOOT_AUTOCONF,
279 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 280 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
281 .scbrr_algo_id = SCBRR_ALGO_2,
280 .type = PORT_SCIF, 282 .type = PORT_SCIF,
281 .irqs = { 81, 81, 81, 81 }, 283 .irqs = { 81, 81, 81, 81 },
282 .clk = "scif1", 284 .clk = "scif1",
@@ -284,6 +286,7 @@ static struct plat_sci_port sci_platform_data[] = {
284 .mapbase = 0xffe20000, 286 .mapbase = 0xffe20000,
285 .flags = UPF_BOOT_AUTOCONF, 287 .flags = UPF_BOOT_AUTOCONF,
286 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 288 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
289 .scbrr_algo_id = SCBRR_ALGO_2,
287 .type = PORT_SCIF, 290 .type = PORT_SCIF,
288 .irqs = { 82, 82, 82, 82 }, 291 .irqs = { 82, 82, 82, 82 },
289 .clk = "scif2", 292 .clk = "scif2",
@@ -291,6 +294,7 @@ static struct plat_sci_port sci_platform_data[] = {
291 .mapbase = 0xffe30000, 294 .mapbase = 0xffe30000,
292 .flags = UPF_BOOT_AUTOCONF, 295 .flags = UPF_BOOT_AUTOCONF,
293 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 296 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
297 .scbrr_algo_id = SCBRR_ALGO_2,
294 .type = PORT_SCIF, 298 .type = PORT_SCIF,
295 .irqs = { 83, 83, 83, 83 }, 299 .irqs = { 83, 83, 83, 83 },
296 .clk = "scif3", 300 .clk = "scif3",
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 307777cf04cc..d4ee429032b1 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -281,6 +281,7 @@ static struct plat_sci_port sci_platform_data[] = {
281 .mapbase = 0xffe00000, 281 .mapbase = 0xffe00000,
282 .flags = UPF_BOOT_AUTOCONF, 282 .flags = UPF_BOOT_AUTOCONF,
283 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 283 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
284 .scbrr_algo_id = SCBRR_ALGO_2,
284 .type = PORT_SCIF, 285 .type = PORT_SCIF,
285 .irqs = { 80, 80, 80, 80 }, 286 .irqs = { 80, 80, 80, 80 },
286 .clk = "scif0", 287 .clk = "scif0",
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index ffc69bc95932..f7b0551bf104 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -306,6 +306,7 @@ static struct plat_sci_port sci_platform_data[] = {
306 .mapbase = 0xffe00000, 306 .mapbase = 0xffe00000,
307 .flags = UPF_BOOT_AUTOCONF, 307 .flags = UPF_BOOT_AUTOCONF,
308 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 308 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
309 .scbrr_algo_id = SCBRR_ALGO_2,
309 .type = PORT_SCIF, 310 .type = PORT_SCIF,
310 .irqs = { 80, 80, 80, 80 }, 311 .irqs = { 80, 80, 80, 80 },
311 .clk = "scif0", 312 .clk = "scif0",
@@ -313,6 +314,7 @@ static struct plat_sci_port sci_platform_data[] = {
313 .mapbase = 0xffe10000, 314 .mapbase = 0xffe10000,
314 .flags = UPF_BOOT_AUTOCONF, 315 .flags = UPF_BOOT_AUTOCONF,
315 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 316 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
317 .scbrr_algo_id = SCBRR_ALGO_2,
316 .type = PORT_SCIF, 318 .type = PORT_SCIF,
317 .irqs = { 81, 81, 81, 81 }, 319 .irqs = { 81, 81, 81, 81 },
318 .clk = "scif1", 320 .clk = "scif1",
@@ -320,6 +322,7 @@ static struct plat_sci_port sci_platform_data[] = {
320 .mapbase = 0xffe20000, 322 .mapbase = 0xffe20000,
321 .flags = UPF_BOOT_AUTOCONF, 323 .flags = UPF_BOOT_AUTOCONF,
322 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 324 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
325 .scbrr_algo_id = SCBRR_ALGO_2,
323 .type = PORT_SCIF, 326 .type = PORT_SCIF,
324 .irqs = { 82, 82, 82, 82 }, 327 .irqs = { 82, 82, 82, 82 },
325 .clk = "scif2", 328 .clk = "scif2",
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 6ce331a8f1bd..bb4837b9dcf4 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -322,6 +322,7 @@ static struct plat_sci_port sci_platform_data[] = {
322 .mapbase = 0xffe00000, 322 .mapbase = 0xffe00000,
323 .flags = UPF_BOOT_AUTOCONF, 323 .flags = UPF_BOOT_AUTOCONF,
324 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 324 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
325 .scbrr_algo_id = SCBRR_ALGO_2,
325 .type = PORT_SCIF, 326 .type = PORT_SCIF,
326 .irqs = { 80, 80, 80, 80 }, 327 .irqs = { 80, 80, 80, 80 },
327 .clk = "scif0", 328 .clk = "scif0",
@@ -329,6 +330,7 @@ static struct plat_sci_port sci_platform_data[] = {
329 .mapbase = 0xffe10000, 330 .mapbase = 0xffe10000,
330 .flags = UPF_BOOT_AUTOCONF, 331 .flags = UPF_BOOT_AUTOCONF,
331 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 332 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
333 .scbrr_algo_id = SCBRR_ALGO_2,
332 .type = PORT_SCIF, 334 .type = PORT_SCIF,
333 .irqs = { 81, 81, 81, 81 }, 335 .irqs = { 81, 81, 81, 81 },
334 .clk = "scif1", 336 .clk = "scif1",
@@ -336,6 +338,7 @@ static struct plat_sci_port sci_platform_data[] = {
336 .mapbase = 0xffe20000, 338 .mapbase = 0xffe20000,
337 .flags = UPF_BOOT_AUTOCONF, 339 .flags = UPF_BOOT_AUTOCONF,
338 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 340 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
341 .scbrr_algo_id = SCBRR_ALGO_2,
339 .type = PORT_SCIF, 342 .type = PORT_SCIF,
340 .irqs = { 82, 82, 82, 82 }, 343 .irqs = { 82, 82, 82, 82 },
341 .clk = "scif2", 344 .clk = "scif2",
@@ -343,6 +346,7 @@ static struct plat_sci_port sci_platform_data[] = {
343 .mapbase = 0xa4e30000, 346 .mapbase = 0xa4e30000,
344 .flags = UPF_BOOT_AUTOCONF, 347 .flags = UPF_BOOT_AUTOCONF,
345 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 348 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
349 .scbrr_algo_id = SCBRR_ALGO_3,
346 .type = PORT_SCIFA, 350 .type = PORT_SCIFA,
347 .irqs = { 56, 56, 56, 56 }, 351 .irqs = { 56, 56, 56, 56 },
348 .clk = "scif3", 352 .clk = "scif3",
@@ -350,6 +354,7 @@ static struct plat_sci_port sci_platform_data[] = {
350 .mapbase = 0xa4e40000, 354 .mapbase = 0xa4e40000,
351 .flags = UPF_BOOT_AUTOCONF, 355 .flags = UPF_BOOT_AUTOCONF,
352 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 356 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
357 .scbrr_algo_id = SCBRR_ALGO_3,
353 .type = PORT_SCIFA, 358 .type = PORT_SCIFA,
354 .irqs = { 88, 88, 88, 88 }, 359 .irqs = { 88, 88, 88, 88 },
355 .clk = "scif4", 360 .clk = "scif4",
@@ -357,6 +362,7 @@ static struct plat_sci_port sci_platform_data[] = {
357 .mapbase = 0xa4e50000, 362 .mapbase = 0xa4e50000,
358 .flags = UPF_BOOT_AUTOCONF, 363 .flags = UPF_BOOT_AUTOCONF,
359 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 364 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
365 .scbrr_algo_id = SCBRR_ALGO_3,
360 .type = PORT_SCIFA, 366 .type = PORT_SCIFA,
361 .irqs = { 109, 109, 109, 109 }, 367 .irqs = { 109, 109, 109, 109 },
362 .clk = "scif5", 368 .clk = "scif5",
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 4bf03c1ec8d6..c934b78e5658 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -29,6 +29,7 @@ static struct plat_sci_port sci_platform_data[] = {
29 .mapbase = 0xffe00000, 29 .mapbase = 0xffe00000,
30 .flags = UPF_BOOT_AUTOCONF, 30 .flags = UPF_BOOT_AUTOCONF,
31 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 31 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
32 .scbrr_algo_id = SCBRR_ALGO_2,
32 .type = PORT_SCIF, 33 .type = PORT_SCIF,
33 .irqs = { 80, 80, 80, 80 }, 34 .irqs = { 80, 80, 80, 80 },
34 .clk = "scif0", 35 .clk = "scif0",
@@ -36,6 +37,7 @@ static struct plat_sci_port sci_platform_data[] = {
36 .mapbase = 0xffe10000, 37 .mapbase = 0xffe10000,
37 .flags = UPF_BOOT_AUTOCONF, 38 .flags = UPF_BOOT_AUTOCONF,
38 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 39 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
40 .scbrr_algo_id = SCBRR_ALGO_2,
39 .type = PORT_SCIF, 41 .type = PORT_SCIF,
40 .irqs = { 81, 81, 81, 81 }, 42 .irqs = { 81, 81, 81, 81 },
41 .clk = "scif1", 43 .clk = "scif1",
@@ -43,6 +45,7 @@ static struct plat_sci_port sci_platform_data[] = {
43 .mapbase = 0xffe20000, 45 .mapbase = 0xffe20000,
44 .flags = UPF_BOOT_AUTOCONF, 46 .flags = UPF_BOOT_AUTOCONF,
45 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 47 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
48 .scbrr_algo_id = SCBRR_ALGO_2,
46 .type = PORT_SCIF, 49 .type = PORT_SCIF,
47 .irqs = { 82, 82, 82, 82 }, 50 .irqs = { 82, 82, 82, 82 },
48 .clk = "scif2", 51 .clk = "scif2",
@@ -50,6 +53,7 @@ static struct plat_sci_port sci_platform_data[] = {
50 .mapbase = 0xa4e30000, 53 .mapbase = 0xa4e30000,
51 .flags = UPF_BOOT_AUTOCONF, 54 .flags = UPF_BOOT_AUTOCONF,
52 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 55 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
56 .scbrr_algo_id = SCBRR_ALGO_3,
53 .type = PORT_SCIFA, 57 .type = PORT_SCIFA,
54 .irqs = { 56, 56, 56, 56 }, 58 .irqs = { 56, 56, 56, 56 },
55 .clk = "scif3", 59 .clk = "scif3",
@@ -57,6 +61,7 @@ static struct plat_sci_port sci_platform_data[] = {
57 .mapbase = 0xa4e40000, 61 .mapbase = 0xa4e40000,
58 .flags = UPF_BOOT_AUTOCONF, 62 .flags = UPF_BOOT_AUTOCONF,
59 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 63 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
64 .scbrr_algo_id = SCBRR_ALGO_3,
60 .type = PORT_SCIFA, 65 .type = PORT_SCIFA,
61 .irqs = { 88, 88, 88, 88 }, 66 .irqs = { 88, 88, 88, 88 },
62 .clk = "scif4", 67 .clk = "scif4",
@@ -64,6 +69,7 @@ static struct plat_sci_port sci_platform_data[] = {
64 .mapbase = 0xa4e50000, 69 .mapbase = 0xa4e50000,
65 .flags = UPF_BOOT_AUTOCONF, 70 .flags = UPF_BOOT_AUTOCONF,
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 71 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
72 .scbrr_algo_id = SCBRR_ALGO_3,
67 .type = PORT_SCIFA, 73 .type = PORT_SCIFA,
68 .irqs = { 109, 109, 109, 109 }, 74 .irqs = { 109, 109, 109, 109 },
69 .clk = "scif5", 75 .clk = "scif5",
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 76339c6da01e..ab02771ee888 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -41,18 +41,21 @@ static struct plat_sci_port sci_platform_data[] = {
41 .mapbase = 0xffe00000, 41 .mapbase = 0xffe00000,
42 .flags = UPF_BOOT_AUTOCONF, 42 .flags = UPF_BOOT_AUTOCONF,
43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
44 .scbrr_algo_id = SCBRR_ALGO_2,
44 .type = PORT_SCIF, 45 .type = PORT_SCIF,
45 .irqs = { 40, 40, 40, 40 }, 46 .irqs = { 40, 40, 40, 40 },
46 }, { 47 }, {
47 .mapbase = 0xffe08000, 48 .mapbase = 0xffe08000,
48 .flags = UPF_BOOT_AUTOCONF, 49 .flags = UPF_BOOT_AUTOCONF,
49 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 50 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
51 .scbrr_algo_id = SCBRR_ALGO_2,
50 .type = PORT_SCIF, 52 .type = PORT_SCIF,
51 .irqs = { 76, 76, 76, 76 }, 53 .irqs = { 76, 76, 76, 76 },
52 }, { 54 }, {
53 .mapbase = 0xffe10000, 55 .mapbase = 0xffe10000,
54 .flags = UPF_BOOT_AUTOCONF, 56 .flags = UPF_BOOT_AUTOCONF,
55 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 57 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
58 .scbrr_algo_id = SCBRR_ALGO_2,
56 .type = PORT_SCIF, 59 .type = PORT_SCIF,
57 .irqs = { 104, 104, 104, 104 }, 60 .irqs = { 104, 104, 104, 104 },
58 }, { 61 }, {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 07a41ff20504..746f4fb9ccf0 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -19,60 +19,70 @@ static struct plat_sci_port sci_platform_data[] = {
19 .mapbase = 0xff923000, 19 .mapbase = 0xff923000,
20 .flags = UPF_BOOT_AUTOCONF, 20 .flags = UPF_BOOT_AUTOCONF,
21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
22 .scbrr_algo_id = SCBRR_ALGO_2,
22 .type = PORT_SCIF, 23 .type = PORT_SCIF,
23 .irqs = { 61, 61, 61, 61 }, 24 .irqs = { 61, 61, 61, 61 },
24 }, { 25 }, {
25 .mapbase = 0xff924000, 26 .mapbase = 0xff924000,
26 .flags = UPF_BOOT_AUTOCONF, 27 .flags = UPF_BOOT_AUTOCONF,
27 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
29 .scbrr_algo_id = SCBRR_ALGO_2,
28 .type = PORT_SCIF, 30 .type = PORT_SCIF,
29 .irqs = { 62, 62, 62, 62 }, 31 .irqs = { 62, 62, 62, 62 },
30 }, { 32 }, {
31 .mapbase = 0xff925000, 33 .mapbase = 0xff925000,
32 .flags = UPF_BOOT_AUTOCONF, 34 .flags = UPF_BOOT_AUTOCONF,
33 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 35 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
36 .scbrr_algo_id = SCBRR_ALGO_2,
34 .type = PORT_SCIF, 37 .type = PORT_SCIF,
35 .irqs = { 63, 63, 63, 63 }, 38 .irqs = { 63, 63, 63, 63 },
36 }, { 39 }, {
37 .mapbase = 0xff926000, 40 .mapbase = 0xff926000,
38 .flags = UPF_BOOT_AUTOCONF, 41 .flags = UPF_BOOT_AUTOCONF,
39 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 42 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
43 .scbrr_algo_id = SCBRR_ALGO_2,
40 .type = PORT_SCIF, 44 .type = PORT_SCIF,
41 .irqs = { 64, 64, 64, 64 }, 45 .irqs = { 64, 64, 64, 64 },
42 }, { 46 }, {
43 .mapbase = 0xff927000, 47 .mapbase = 0xff927000,
44 .flags = UPF_BOOT_AUTOCONF, 48 .flags = UPF_BOOT_AUTOCONF,
45 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 49 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
50 .scbrr_algo_id = SCBRR_ALGO_2,
46 .type = PORT_SCIF, 51 .type = PORT_SCIF,
47 .irqs = { 65, 65, 65, 65 }, 52 .irqs = { 65, 65, 65, 65 },
48 }, { 53 }, {
49 .mapbase = 0xff928000, 54 .mapbase = 0xff928000,
50 .flags = UPF_BOOT_AUTOCONF, 55 .flags = UPF_BOOT_AUTOCONF,
51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 56 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
57 .scbrr_algo_id = SCBRR_ALGO_2,
52 .type = PORT_SCIF, 58 .type = PORT_SCIF,
53 .irqs = { 66, 66, 66, 66 }, 59 .irqs = { 66, 66, 66, 66 },
54 }, { 60 }, {
55 .mapbase = 0xff929000, 61 .mapbase = 0xff929000,
56 .flags = UPF_BOOT_AUTOCONF, 62 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 63 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
64 .scbrr_algo_id = SCBRR_ALGO_2,
58 .type = PORT_SCIF, 65 .type = PORT_SCIF,
59 .irqs = { 67, 67, 67, 67 }, 66 .irqs = { 67, 67, 67, 67 },
60 }, { 67 }, {
61 .mapbase = 0xff92a000, 68 .mapbase = 0xff92a000,
62 .flags = UPF_BOOT_AUTOCONF, 69 .flags = UPF_BOOT_AUTOCONF,
63 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 70 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
71 .scbrr_algo_id = SCBRR_ALGO_2,
64 .type = PORT_SCIF, 72 .type = PORT_SCIF,
65 .irqs = { 68, 68, 68, 68 }, 73 .irqs = { 68, 68, 68, 68 },
66 }, { 74 }, {
67 .mapbase = 0xff92b000, 75 .mapbase = 0xff92b000,
68 .flags = UPF_BOOT_AUTOCONF, 76 .flags = UPF_BOOT_AUTOCONF,
69 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 77 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
78 .scbrr_algo_id = SCBRR_ALGO_2,
70 .type = PORT_SCIF, 79 .type = PORT_SCIF,
71 .irqs = { 69, 69, 69, 69 }, 80 .irqs = { 69, 69, 69, 69 },
72 }, { 81 }, {
73 .mapbase = 0xff92c000, 82 .mapbase = 0xff92c000,
74 .flags = UPF_BOOT_AUTOCONF, 83 .flags = UPF_BOOT_AUTOCONF,
75 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 84 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
85 .scbrr_algo_id = SCBRR_ALGO_2,
76 .type = PORT_SCIF, 86 .type = PORT_SCIF,
77 .irqs = { 70, 70, 70, 70 }, 87 .irqs = { 70, 70, 70, 70 },
78 }, { 88 }, {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 2b355b67a33d..bcd411eb9cb0 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -221,12 +221,14 @@ static struct plat_sci_port sci_platform_data[] = {
221 .mapbase = 0xffe00000, 221 .mapbase = 0xffe00000,
222 .flags = UPF_BOOT_AUTOCONF, 222 .flags = UPF_BOOT_AUTOCONF,
223 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 223 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
224 .scbrr_algo_id = SCBRR_ALGO_1,
224 .type = PORT_SCIF, 225 .type = PORT_SCIF,
225 .irqs = { 40, 40, 40, 40 }, 226 .irqs = { 40, 40, 40, 40 },
226 }, { 227 }, {
227 .mapbase = 0xffe10000, 228 .mapbase = 0xffe10000,
228 .flags = UPF_BOOT_AUTOCONF, 229 .flags = UPF_BOOT_AUTOCONF,
229 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 230 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
231 .scbrr_algo_id = SCBRR_ALGO_1,
230 .type = PORT_SCIF, 232 .type = PORT_SCIF,
231 .irqs = { 76, 76, 76, 76 }, 233 .irqs = { 76, 76, 76, 76 },
232 }, { 234 }, {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index acd4b1d1b813..3ae2e2071009 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -203,6 +203,7 @@ static struct plat_sci_port sci_platform_data[] = {
203 .mapbase = 0xffea0000, 203 .mapbase = 0xffea0000,
204 .flags = UPF_BOOT_AUTOCONF, 204 .flags = UPF_BOOT_AUTOCONF,
205 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 205 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
206 .scbrr_algo_id = SCBRR_ALGO_1,
206 .type = PORT_SCIF, 207 .type = PORT_SCIF,
207 .irqs = { 40, 40, 40, 40 }, 208 .irqs = { 40, 40, 40, 40 },
208 .clk = "scif_fck", 209 .clk = "scif_fck",
@@ -210,6 +211,7 @@ static struct plat_sci_port sci_platform_data[] = {
210 .mapbase = 0xffeb0000, 211 .mapbase = 0xffeb0000,
211 .flags = UPF_BOOT_AUTOCONF, 212 .flags = UPF_BOOT_AUTOCONF,
212 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 213 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
214 .scbrr_algo_id = SCBRR_ALGO_1,
213 .type = PORT_SCIF, 215 .type = PORT_SCIF,
214 .irqs = { 44, 44, 44, 44 }, 216 .irqs = { 44, 44, 44, 44 },
215 .clk = "scif_fck", 217 .clk = "scif_fck",
@@ -217,6 +219,7 @@ static struct plat_sci_port sci_platform_data[] = {
217 .mapbase = 0xffec0000, 219 .mapbase = 0xffec0000,
218 .flags = UPF_BOOT_AUTOCONF, 220 .flags = UPF_BOOT_AUTOCONF,
219 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 221 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
222 .scbrr_algo_id = SCBRR_ALGO_1,
220 .type = PORT_SCIF, 223 .type = PORT_SCIF,
221 .irqs = { 60, 60, 60, 60 }, 224 .irqs = { 60, 60, 60, 60 },
222 .clk = "scif_fck", 225 .clk = "scif_fck",
@@ -224,6 +227,7 @@ static struct plat_sci_port sci_platform_data[] = {
224 .mapbase = 0xffed0000, 227 .mapbase = 0xffed0000,
225 .flags = UPF_BOOT_AUTOCONF, 228 .flags = UPF_BOOT_AUTOCONF,
226 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 229 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
230 .scbrr_algo_id = SCBRR_ALGO_1,
227 .type = PORT_SCIF, 231 .type = PORT_SCIF,
228 .irqs = { 61, 61, 61, 61 }, 232 .irqs = { 61, 61, 61, 61 },
229 .clk = "scif_fck", 233 .clk = "scif_fck",
@@ -231,6 +235,7 @@ static struct plat_sci_port sci_platform_data[] = {
231 .mapbase = 0xffee0000, 235 .mapbase = 0xffee0000,
232 .flags = UPF_BOOT_AUTOCONF, 236 .flags = UPF_BOOT_AUTOCONF,
233 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 237 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
238 .scbrr_algo_id = SCBRR_ALGO_1,
234 .type = PORT_SCIF, 239 .type = PORT_SCIF,
235 .irqs = { 62, 62, 62, 62 }, 240 .irqs = { 62, 62, 62, 62 },
236 .clk = "scif_fck", 241 .clk = "scif_fck",
@@ -238,6 +243,7 @@ static struct plat_sci_port sci_platform_data[] = {
238 .mapbase = 0xffef0000, 243 .mapbase = 0xffef0000,
239 .flags = UPF_BOOT_AUTOCONF, 244 .flags = UPF_BOOT_AUTOCONF,
240 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 245 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
246 .scbrr_algo_id = SCBRR_ALGO_1,
241 .type = PORT_SCIF, 247 .type = PORT_SCIF,
242 .irqs = { 63, 63, 63, 63 }, 248 .irqs = { 63, 63, 63, 63 },
243 .clk = "scif_fck", 249 .clk = "scif_fck",
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 347ce88de570..8b7ea4bd965d 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -28,6 +28,7 @@ static struct plat_sci_port sci_platform_data[] = {
28 .mapbase = 0xffea0000, 28 .mapbase = 0xffea0000,
29 .flags = UPF_BOOT_AUTOCONF, 29 .flags = UPF_BOOT_AUTOCONF,
30 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 30 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
31 .scbrr_algo_id = SCBRR_ALGO_1,
31 .type = PORT_SCIF, 32 .type = PORT_SCIF,
32 .irqs = { 40, 41, 43, 42 }, 33 .irqs = { 40, 41, 43, 42 },
33 }, 34 },
@@ -38,30 +39,35 @@ static struct plat_sci_port sci_platform_data[] = {
38 .mapbase = 0xffeb0000, 39 .mapbase = 0xffeb0000,
39 .flags = UPF_BOOT_AUTOCONF, 40 .flags = UPF_BOOT_AUTOCONF,
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 41 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
42 .scbrr_algo_id = SCBRR_ALGO_1,
41 .type = PORT_SCIF, 43 .type = PORT_SCIF,
42 .irqs = { 44, 44, 44, 44 }, 44 .irqs = { 44, 44, 44, 44 },
43 }, { 45 }, {
44 .mapbase = 0xffec0000, 46 .mapbase = 0xffec0000,
45 .flags = UPF_BOOT_AUTOCONF, 47 .flags = UPF_BOOT_AUTOCONF,
46 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 48 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
49 .scbrr_algo_id = SCBRR_ALGO_1,
47 .type = PORT_SCIF, 50 .type = PORT_SCIF,
48 .irqs = { 50, 50, 50, 50 }, 51 .irqs = { 50, 50, 50, 50 },
49 }, { 52 }, {
50 .mapbase = 0xffed0000, 53 .mapbase = 0xffed0000,
51 .flags = UPF_BOOT_AUTOCONF, 54 .flags = UPF_BOOT_AUTOCONF,
52 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 55 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
56 .scbrr_algo_id = SCBRR_ALGO_1,
53 .type = PORT_SCIF, 57 .type = PORT_SCIF,
54 .irqs = { 51, 51, 51, 51 }, 58 .irqs = { 51, 51, 51, 51 },
55 }, { 59 }, {
56 .mapbase = 0xffee0000, 60 .mapbase = 0xffee0000,
57 .flags = UPF_BOOT_AUTOCONF, 61 .flags = UPF_BOOT_AUTOCONF,
58 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 62 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
63 .scbrr_algo_id = SCBRR_ALGO_1,
59 .type = PORT_SCIF, 64 .type = PORT_SCIF,
60 .irqs = { 52, 52, 52, 52 }, 65 .irqs = { 52, 52, 52, 52 },
61 }, { 66 }, {
62 .mapbase = 0xffef0000, 67 .mapbase = 0xffef0000,
63 .flags = UPF_BOOT_AUTOCONF, 68 .flags = UPF_BOOT_AUTOCONF,
64 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 69 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
70 .scbrr_algo_id = SCBRR_ALGO_1,
65 .type = PORT_SCIF, 71 .type = PORT_SCIF,
66 .irqs = { 53, 53, 53, 53 }, 72 .irqs = { 53, 53, 53, 53 },
67 }, { 73 }, {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index eef94934f542..4a26cc304139 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -20,24 +20,28 @@ static struct plat_sci_port sci_platform_data[] = {
20 .mapbase = 0xffc30000, 20 .mapbase = 0xffc30000,
21 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23 .scbrr_algo_id = SCBRR_ALGO_2,
23 .type = PORT_SCIF, 24 .type = PORT_SCIF,
24 .irqs = { 40, 41, 43, 42 }, 25 .irqs = { 40, 41, 43, 42 },
25 }, { 26 }, {
26 .mapbase = 0xffc40000, 27 .mapbase = 0xffc40000,
27 .flags = UPF_BOOT_AUTOCONF, 28 .flags = UPF_BOOT_AUTOCONF,
28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 29 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
30 .scbrr_algo_id = SCBRR_ALGO_2,
29 .type = PORT_SCIF, 31 .type = PORT_SCIF,
30 .irqs = { 44, 45, 47, 46 }, 32 .irqs = { 44, 45, 47, 46 },
31 }, { 33 }, {
32 .mapbase = 0xffc50000, 34 .mapbase = 0xffc50000,
33 .flags = UPF_BOOT_AUTOCONF, 35 .flags = UPF_BOOT_AUTOCONF,
34 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 36 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
37 .scbrr_algo_id = SCBRR_ALGO_2,
35 .type = PORT_SCIF, 38 .type = PORT_SCIF,
36 .irqs = { 48, 49, 51, 50 }, 39 .irqs = { 48, 49, 51, 50 },
37 }, { 40 }, {
38 .mapbase = 0xffc60000, 41 .mapbase = 0xffc60000,
39 .flags = UPF_BOOT_AUTOCONF, 42 .flags = UPF_BOOT_AUTOCONF,
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
44 .scbrr_algo_id = SCBRR_ALGO_2,
41 .type = PORT_SCIF, 45 .type = PORT_SCIF,
42 .irqs = { 52, 53, 55, 54 }, 46 .irqs = { 52, 53, 55, 54 },
43 }, { 47 }, {
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
index 26fa10c560de..72aa86ec7446 100644
--- a/arch/sh/kernel/cpu/sh5/setup-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -21,6 +21,7 @@ static struct plat_sci_port sci_platform_data[] = {
21 .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000, 21 .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000,
22 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 22 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
24 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF, 25 .type = PORT_SCIF,
25 .irqs = { 39, 40, 42, 0 }, 26 .irqs = { 39, 40, 42, 0 },
26 }, { 27 }, {
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index 3a13e58e9c5d..386fb878680c 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -82,6 +82,9 @@ struct sci_port {
82 /* SCSCR initialization */ 82 /* SCSCR initialization */
83 unsigned int scscr; 83 unsigned int scscr;
84 84
85 /* SCBRR calculation algo */
86 unsigned int scbrr_algo_id;
87
85#ifdef CONFIG_HAVE_CLK 88#ifdef CONFIG_HAVE_CLK
86 /* Interface clock */ 89 /* Interface clock */
87 struct clk *iclk; 90 struct clk *iclk;
@@ -928,6 +931,27 @@ static void sci_shutdown(struct uart_port *port)
928 s->disable(port); 931 s->disable(port);
929} 932}
930 933
934static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
935 unsigned long freq)
936{
937 switch (algo_id) {
938 case SCBRR_ALGO_1:
939 return ((freq + 16 * bps) / (16 * bps) - 1);
940 case SCBRR_ALGO_2:
941 return ((freq + 16 * bps) / (32 * bps) - 1);
942 case SCBRR_ALGO_3:
943 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
944 case SCBRR_ALGO_4:
945 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
946 case SCBRR_ALGO_5:
947 return (((freq * 1000 / 32) / bps) - 1);
948 }
949
950 /* Warn, but use a safe default */
951 WARN_ON(1);
952 return ((freq + 16 * bps) / (32 * bps) - 1);
953}
954
931static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 955static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
932 struct ktermios *old) 956 struct ktermios *old)
933{ 957{
@@ -937,7 +961,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
937 961
938 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 962 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
939 if (likely(baud)) 963 if (likely(baud))
940 t = SCBRR_VALUE(baud, port->uartclk); 964 t = sci_scbrr_calc(s->scbrr_algo_id, baud, port->uartclk);
941 965
942 do { 966 do {
943 status = sci_in(port, SCxSR); 967 status = sci_in(port, SCxSR);
@@ -1108,7 +1132,6 @@ static void __devinit sci_init_single(struct platform_device *dev,
1108 sci_port->type = sci_port->port.type = p->type; 1132 sci_port->type = sci_port->port.type = p->type;
1109 1133
1110 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs)); 1134 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
1111
1112} 1135}
1113 1136
1114#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 1137#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 4aa0ac8e67dd..81104777a0a6 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -713,59 +713,3 @@ static inline int sci_rxd_in(struct uart_port *port)
713 return 1; 713 return 1;
714} 714}
715#endif 715#endif
716
717/*
718 * Values for the BitRate Register (SCBRR)
719 *
720 * The values are actually divisors for a frequency which can
721 * be internal to the SH3 (14.7456MHz) or derived from an external
722 * clock source. This driver assumes the internal clock is used;
723 * to support using an external clock source, config options or
724 * possibly command-line options would need to be added.
725 *
726 * Also, to support speeds below 2400 (why?) the lower 2 bits of
727 * the SCSMR register would also need to be set to non-zero values.
728 *
729 * -- Greg Banks 27Feb2000
730 *
731 * Answer: The SCBRR register is only eight bits, and the value in
732 * it gets larger with lower baud rates. At around 2400 (depending on
733 * the peripherial module clock) you run out of bits. However the
734 * lower two bits of SCSMR allow the module clock to be divided down,
735 * scaling the value which is needed in SCBRR.
736 *
737 * -- Stuart Menefy - 23 May 2000
738 *
739 * I meant, why would anyone bother with bitrates below 2400.
740 *
741 * -- Greg Banks - 7Jul2000
742 *
743 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
744 * tape reader as a console!
745 *
746 * -- Mitch Davis - 15 Jul 2000
747 */
748
749#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
750 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
751 defined(CONFIG_CPU_SUBTYPE_SH7786)
752#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
753#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
754 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
755 defined(CONFIG_CPU_SUBTYPE_SH7721)
756#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
757#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
758 defined(CONFIG_CPU_SUBTYPE_SH7724)
759static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
760{
761 if (port->type == PORT_SCIF)
762 return (clk+16*bps)/(32*bps)-1;
763 else
764 return ((clk*2)+16*bps)/(16*bps)-1;
765}
766#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
767#elif defined(__H8300H__) || defined(__H8300S__)
768#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
769#else /* Generic SH */
770#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
771#endif
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index f722a2275add..ff856b5bd276 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -7,6 +7,14 @@
7 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts) 7 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
8 */ 8 */
9 9
10enum {
11 SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */
12 SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */
13 SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
14 SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
15 SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */
16};
17
10#define SCSCR_TIE (1 << 7) 18#define SCSCR_TIE (1 << 7)
11#define SCSCR_RIE (1 << 6) 19#define SCSCR_RIE (1 << 6)
12#define SCSCR_TE (1 << 5) 20#define SCSCR_TE (1 << 5)
@@ -36,6 +44,7 @@ struct plat_sci_port {
36 upf_t flags; /* UPF_* flags */ 44 upf_t flags; /* UPF_* flags */
37 char *clk; /* clock string */ 45 char *clk; /* clock string */
38 46
47 unsigned int scbrr_algo_id; /* SCBRR calculation algo */
39 unsigned int scscr; /* SCSCR initialization */ 48 unsigned int scscr; /* SCSCR initialization */
40}; 49};
41 50
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-23 09:02:57 -0500