drm/i915: Write to display base last.

Writing to the DSPBASE register triggers the double-buffered update to
all the control registers, so always write it last in the update
sequence.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>

1 files changed, 2 insertions, 4 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 25e3866f9159..874ae30d5e4a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1585,15 +1585,13 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                       Start, Offset, x, y, crtc->fb->pitch);
         I915_WRITE(dspstride, crtc->fb->pitch);
         if (IS_I965G(dev)) {
-                I915_WRITE(dspbase, Offset);
-                I915_READ(dspbase);
                 I915_WRITE(dspsurf, Start);
-                I915_READ(dspsurf);
                 I915_WRITE(dsptileoff, (y << 16) | x);
+                I915_WRITE(dspbase, Offset);
         } else {
                 I915_WRITE(dspbase, Start + Offset);
-                I915_READ(dspbase);
         }
+        POSTING_READ(dspbase);
 
         if ((IS_I965G(dev) || plane == 0))
                 intel_update_fbc(crtc, &crtc->mode);