metag: perf: don't reset TXTACTCYC

The thread active cycle counter TXTACTCYC is used in __delay so it
shouldn't really be reset to zero by perf. Fix perf to just read the
value, and instead of clearing it, record the prev_count value in
enable_counter so that the delta calculations know about the previous
value.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>

1 files changed, 2 insertions, 5 deletions

diff --git a/arch/metag/kernel/perf/perf_event.c b/arch/metag/kernel/perf/perf_event.c
index 54fde35b4b9c..a1eff3687e8e 100644
--- a/arch/metag/kernel/perf/perf_event.c
+++ b/arch/metag/kernel/perf/perf_event.c
@@ -617,9 +617,7 @@ static void metag_pmu_enable_counter(struct hw_perf_event *event, int idx)
                 WARN_ONCE((config != 0x100),
                         "invalid configuration (%d) for counter (%d)\n",
                         config, idx);
-
-                /* Reset the cycle count */
-                __core_reg_set(TXTACTCYC, 0);
+                local64_set(&event->prev_count, __core_reg_get(TXTACTCYC));
                 goto unlock;
         }
 
@@ -708,9 +706,8 @@ static u64 metag_pmu_read_counter(int idx)
 {
         u32 tmp = 0;
 
-        /* The act of reading the cycle counter also clears it */
         if (METAG_INST_COUNTER == idx) {
-                __core_reg_swap(TXTACTCYC, tmp);
+                tmp = __core_reg_get(TXTACTCYC);
                 goto out;
         }