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authorLars-Peter Clausen <lars@metafoo.de>2012-08-10 12:36:00 -0400
committerJonathan Cameron <jic23@kernel.org>2012-08-27 13:10:36 -0400
commit1abec6ac69fe5aea1013c1e8f764d9e71a8e64c4 (patch)
treeb719a5c8766aeb7d01f18f4bbd9d35567a4e474d
parent32e0e7e08c32fbd61ddfb7e80ba96c13085f3d39 (diff)
staging:iio:ad7793: Use common Sigma Delta library
Convert the ad7793 driver to make use of the new common code for devices from the Analog Devices Sigma Delta family. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Diffstat
-rw-r--r--drivers/staging/iio/adc/Kconfig3
-rw-r--r--drivers/staging/iio/adc/ad7793.c624
-rw-r--r--drivers/staging/iio/adc/ad7793.h2
3 files changed, 75 insertions, 554 deletions
diff --git a/drivers/staging/iio/adc/Kconfig b/drivers/staging/iio/adc/Kconfig
index d0eb27be381c..f7d7e44af672 100644
--- a/drivers/staging/iio/adc/Kconfig
+++ b/drivers/staging/iio/adc/Kconfig
@@ -111,8 +111,7 @@ config AD7780
111config AD7793 111config AD7793
112 tristate "Analog Devices AD7792 AD7793 ADC driver" 112 tristate "Analog Devices AD7792 AD7793 ADC driver"
113 depends on SPI 113 depends on SPI
114 select IIO_BUFFER 114 select AD_SIGMA_DELTA
115 select IIO_TRIGGERED_BUFFER
116 help 115 help
117 Say yes here to build support for Analog Devices 116 Say yes here to build support for Analog Devices
118 AD7792 and AD7793 SPI analog to digital converters (ADC). 117 AD7792 and AD7793 SPI analog to digital converters (ADC).
diff --git a/drivers/staging/iio/adc/ad7793.c b/drivers/staging/iio/adc/ad7793.c
index 5c2fcd7d2def..90335958d9c9 100644
--- a/drivers/staging/iio/adc/ad7793.c
+++ b/drivers/staging/iio/adc/ad7793.c
@@ -24,6 +24,7 @@
24#include <linux/iio/trigger.h> 24#include <linux/iio/trigger.h>
25#include <linux/iio/trigger_consumer.h> 25#include <linux/iio/trigger_consumer.h>
26#include <linux/iio/triggered_buffer.h> 26#include <linux/iio/triggered_buffer.h>
27#include <linux/iio/adc/ad_sigma_delta.h>
27 28
28#include "ad7793.h" 29#include "ad7793.h"
29 30
@@ -36,27 +37,19 @@
36 */ 37 */
37 38
38struct ad7793_chip_info { 39struct ad7793_chip_info {
39 struct iio_chan_spec channel[7]; 40 struct iio_chan_spec channel[7];
40}; 41};
41 42
42struct ad7793_state { 43struct ad7793_state {
43 struct spi_device *spi;
44 struct iio_trigger *trig;
45 const struct ad7793_chip_info *chip_info; 44 const struct ad7793_chip_info *chip_info;
46 struct regulator *reg; 45 struct regulator *reg;
47 wait_queue_head_t wq_data_avail;
48 bool done;
49 bool irq_dis;
50 u16 int_vref_mv; 46 u16 int_vref_mv;
51 u16 mode; 47 u16 mode;
52 u16 conf; 48 u16 conf;
53 u32 scale_avail[8][2]; 49 u32 scale_avail[8][2];
54 50
55 /* 51 struct ad_sigma_delta sd;
56 * DMA (thus cache coherency maintenance) requires the 52
57 * transfer buffers to live in their own cache lines.
58 */
59 u8 data[4] ____cacheline_aligned;
60}; 53};
61 54
62enum ad7793_supported_device_ids { 55enum ad7793_supported_device_ids {
@@ -64,169 +57,41 @@ enum ad7793_supported_device_ids {
64 ID_AD7793, 57 ID_AD7793,
65}; 58};
66 59
67static int __ad7793_write_reg(struct ad7793_state *st, bool locked, 60static struct ad7793_state *ad_sigma_delta_to_ad7793(struct ad_sigma_delta *sd)
68 bool cs_change, unsigned char reg,
69 unsigned size, unsigned val)
70{ 61{
71 u8 *data = st->data; 62 return container_of(sd, struct ad7793_state, sd);
72 struct spi_transfer t = {
73 .tx_buf = data,
74 .len = size + 1,
75 .cs_change = cs_change,
76 };
77 struct spi_message m;
78
79 data[0] = AD7793_COMM_WRITE | AD7793_COMM_ADDR(reg);
80
81 switch (size) {
82 case 3:
83 data[1] = val >> 16;
84 data[2] = val >> 8;
85 data[3] = val;
86 break;
87 case 2:
88 data[1] = val >> 8;
89 data[2] = val;
90 break;
91 case 1:
92 data[1] = val;
93 break;
94 default:
95 return -EINVAL;
96 }
97
98 spi_message_init(&m);
99 spi_message_add_tail(&t, &m);
100
101 if (locked)
102 return spi_sync_locked(st->spi, &m);
103 else
104 return spi_sync(st->spi, &m);
105} 63}
106 64
107static int ad7793_write_reg(struct ad7793_state *st, 65static int ad7793_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
108 unsigned reg, unsigned size, unsigned val)
109{ 66{
110 return __ad7793_write_reg(st, false, false, reg, size, val); 67 struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
111}
112 68
113static int __ad7793_read_reg(struct ad7793_state *st, bool locked, 69 st->conf &= ~AD7793_CONF_CHAN_MASK;
114 bool cs_change, unsigned char reg, 70 st->conf |= AD7793_CONF_CHAN(channel);
115 int *val, unsigned size)
116{
117 u8 *data = st->data;
118 int ret;
119 struct spi_transfer t[] = {
120 {
121 .tx_buf = data,
122 .len = 1,
123 }, {
124 .rx_buf = data,
125 .len = size,
126 .cs_change = cs_change,
127 },
128 };
129 struct spi_message m;
130
131 data[0] = AD7793_COMM_READ | AD7793_COMM_ADDR(reg);
132
133 spi_message_init(&m);
134 spi_message_add_tail(&t[0], &m);
135 spi_message_add_tail(&t[1], &m);
136
137 if (locked)
138 ret = spi_sync_locked(st->spi, &m);
139 else
140 ret = spi_sync(st->spi, &m);
141 71
142 if (ret < 0) 72 return ad_sd_write_reg(&st->sd, AD7793_REG_CONF, 2, st->conf);
143 return ret;
144
145 switch (size) {
146 case 3:
147 *val = data[0] << 16 | data[1] << 8 | data[2];
148 break;
149 case 2:
150 *val = data[0] << 8 | data[1];
151 break;
152 case 1:
153 *val = data[0];
154 break;
155 default:
156 return -EINVAL;
157 }
158
159 return 0;
160} 73}
161 74
162static int ad7793_read_reg(struct ad7793_state *st, 75static int ad7793_set_mode(struct ad_sigma_delta *sd,
163 unsigned reg, int *val, unsigned size) 76 enum ad_sigma_delta_mode mode)
164{ 77{
165 return __ad7793_read_reg(st, 0, 0, reg, val, size); 78 struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
166}
167
168static int ad7793_read(struct ad7793_state *st, unsigned ch,
169 unsigned len, int *val)
170{
171 int ret;
172 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) | AD7793_CONF_CHAN(ch);
173 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
174 AD7793_MODE_SEL(AD7793_MODE_SINGLE);
175 79
176 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf); 80 st->mode &= ~AD7793_MODE_SEL_MASK;
81 st->mode |= AD7793_MODE_SEL(mode);
177 82
178 spi_bus_lock(st->spi->master); 83 return ad_sd_write_reg(&st->sd, AD7793_REG_MODE, 2, st->mode);
179 st->done = false;
180
181 ret = __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
182 sizeof(st->mode), st->mode);
183 if (ret < 0)
184 goto out;
185
186 st->irq_dis = false;
187 enable_irq(st->spi->irq);
188 wait_event_interruptible(st->wq_data_avail, st->done);
189
190 ret = __ad7793_read_reg(st, 1, 0, AD7793_REG_DATA, val, len);
191out:
192 spi_bus_unlock(st->spi->master);
193
194 return ret;
195} 84}
196 85
197static int ad7793_calibrate(struct ad7793_state *st, unsigned mode, unsigned ch) 86static const struct ad_sigma_delta_info ad7793_sigma_delta_info = {
198{ 87 .set_channel = ad7793_set_channel,
199 int ret; 88 .set_mode = ad7793_set_mode,
200 89 .has_registers = true,
201 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) | AD7793_CONF_CHAN(ch); 90 .addr_shift = 3,
202 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) | AD7793_MODE_SEL(mode); 91 .read_mask = BIT(6),
203 92};
204 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
205
206 spi_bus_lock(st->spi->master);
207 st->done = false;
208
209 ret = __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
210 sizeof(st->mode), st->mode);
211 if (ret < 0)
212 goto out;
213
214 st->irq_dis = false;
215 enable_irq(st->spi->irq);
216 wait_event_interruptible(st->wq_data_avail, st->done);
217
218 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
219 AD7793_MODE_SEL(AD7793_MODE_IDLE);
220
221 ret = __ad7793_write_reg(st, 1, 0, AD7793_REG_MODE,
222 sizeof(st->mode), st->mode);
223out:
224 spi_bus_unlock(st->spi->master);
225
226 return ret;
227}
228 93
229static const u8 ad7793_calib_arr[6][2] = { 94static const struct ad_sd_calib_data ad7793_calib_arr[6] = {
230 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M}, 95 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M},
231 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M}, 96 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M},
232 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M}, 97 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M},
@@ -237,59 +102,48 @@ static const u8 ad7793_calib_arr[6][2] = {
237 102
238static int ad7793_calibrate_all(struct ad7793_state *st) 103static int ad7793_calibrate_all(struct ad7793_state *st)
239{ 104{
240 int i, ret; 105 return ad_sd_calibrate_all(&st->sd, ad7793_calib_arr,
241 106 ARRAY_SIZE(ad7793_calib_arr));
242 for (i = 0; i < ARRAY_SIZE(ad7793_calib_arr); i++) {
243 ret = ad7793_calibrate(st, ad7793_calib_arr[i][0],
244 ad7793_calib_arr[i][1]);
245 if (ret)
246 goto out;
247 }
248
249 return 0;
250out:
251 dev_err(&st->spi->dev, "Calibration failed\n");
252 return ret;
253} 107}
254 108
255static int ad7793_setup(struct ad7793_state *st, 109static int ad7793_setup(struct iio_dev *indio_dev,
256 const struct ad7793_platform_data *pdata) 110 const struct ad7793_platform_data *pdata)
257{ 111{
112 struct ad7793_state *st = iio_priv(indio_dev);
258 int i, ret = -1; 113 int i, ret = -1;
259 unsigned long long scale_uv; 114 unsigned long long scale_uv;
260 u32 id; 115 u32 id;
261 116
262 /* reset the serial interface */ 117 /* reset the serial interface */
263 ret = spi_write(st->spi, (u8 *)&ret, sizeof(ret)); 118 ret = spi_write(st->sd.spi, (u8 *)&ret, sizeof(ret));
264 if (ret < 0) 119 if (ret < 0)
265 goto out; 120 goto out;
266 msleep(1); /* Wait for at least 500us */ 121 msleep(1); /* Wait for at least 500us */
267 122
268 /* write/read test for device presence */ 123 /* write/read test for device presence */
269 ret = ad7793_read_reg(st, AD7793_REG_ID, &id, 1); 124 ret = ad_sd_read_reg(&st->sd, AD7793_REG_ID, 1, &id);
270 if (ret) 125 if (ret)
271 goto out; 126 goto out;
272 127
273 id &= AD7793_ID_MASK; 128 id &= AD7793_ID_MASK;
274 129
275 if (!((id == AD7792_ID) || (id == AD7793_ID))) { 130 if (!((id == AD7792_ID) || (id == AD7793_ID))) {
276 dev_err(&st->spi->dev, "device ID query failed\n"); 131 dev_err(&st->sd.spi->dev, "device ID query failed\n");
277 goto out; 132 goto out;
278 } 133 }
279 134
280 st->mode = (pdata->mode & ~AD7793_MODE_SEL(-1)) | 135 st->mode = pdata->mode;
281 AD7793_MODE_SEL(AD7793_MODE_IDLE); 136 st->conf = pdata->conf;
282 st->conf = pdata->conf & ~AD7793_CONF_CHAN(-1);
283 137
284 ret = ad7793_write_reg(st, AD7793_REG_MODE, sizeof(st->mode), st->mode); 138 ret = ad7793_set_mode(&st->sd, AD_SD_MODE_IDLE);
285 if (ret) 139 if (ret)
286 goto out; 140 goto out;
287 141
288 ret = ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf); 142 ret = ad7793_set_channel(&st->sd, 0);
289 if (ret) 143 if (ret)
290 goto out; 144 goto out;
291 145
292 ret = ad7793_write_reg(st, AD7793_REG_IO, 146 ret = ad_sd_write_reg(&st->sd, AD7793_REG_IO,
293 sizeof(pdata->io), pdata->io); 147 sizeof(pdata->io), pdata->io);
294 if (ret) 148 if (ret)
295 goto out; 149 goto out;
@@ -311,184 +165,10 @@ static int ad7793_setup(struct ad7793_state *st,
311 165
312 return 0; 166 return 0;
313out: 167out:
314 dev_err(&st->spi->dev, "setup failed\n"); 168 dev_err(&st->sd.spi->dev, "setup failed\n");
315 return ret;
316}
317
318static int ad7793_ring_preenable(struct iio_dev *indio_dev)
319{
320 struct ad7793_state *st = iio_priv(indio_dev);
321 unsigned channel;
322 int ret;
323
324 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
325 return -EINVAL;
326 ret = iio_sw_buffer_preenable(indio_dev);
327 if (ret < 0)
328 return ret;
329
330 channel = find_first_bit(indio_dev->active_scan_mask,
331 indio_dev->masklength);
332
333 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
334 AD7793_MODE_SEL(AD7793_MODE_CONT);
335 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) |
336 AD7793_CONF_CHAN(indio_dev->channels[channel].address);
337
338 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
339
340 spi_bus_lock(st->spi->master);
341 __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
342 sizeof(st->mode), st->mode);
343
344 st->irq_dis = false;
345 enable_irq(st->spi->irq);
346
347 return 0;
348}
349
350static int ad7793_ring_postdisable(struct iio_dev *indio_dev)
351{
352 struct ad7793_state *st = iio_priv(indio_dev);
353
354 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
355 AD7793_MODE_SEL(AD7793_MODE_IDLE);
356
357 st->done = false;
358 wait_event_interruptible(st->wq_data_avail, st->done);
359
360 if (!st->irq_dis)
361 disable_irq_nosync(st->spi->irq);
362
363 __ad7793_write_reg(st, 1, 0, AD7793_REG_MODE,
364 sizeof(st->mode), st->mode);
365
366 return spi_bus_unlock(st->spi->master);
367}
368
369/**
370 * ad7793_trigger_handler() bh of trigger launched polling to ring buffer
371 **/
372
373static irqreturn_t ad7793_trigger_handler(int irq, void *p)
374{
375 struct iio_poll_func *pf = p;
376 struct iio_dev *indio_dev = pf->indio_dev;
377 struct iio_buffer *ring = indio_dev->buffer;
378 struct ad7793_state *st = iio_priv(indio_dev);
379 s64 dat64[2];
380 s32 *dat32 = (s32 *)dat64;
381
382 if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
383 __ad7793_read_reg(st, 1, 1, AD7793_REG_DATA,
384 dat32,
385 indio_dev->channels[0].scan_type.realbits/8);
386
387 /* Guaranteed to be aligned with 8 byte boundary */
388 if (indio_dev->scan_timestamp)
389 dat64[1] = pf->timestamp;
390
391 ring->access->store_to(ring, (u8 *)dat64, pf->timestamp);
392
393 iio_trigger_notify_done(indio_dev->trig);
394 st->irq_dis = false;
395 enable_irq(st->spi->irq);
396
397 return IRQ_HANDLED;
398}
399
400static const struct iio_buffer_setup_ops ad7793_ring_setup_ops = {
401 .preenable = &ad7793_ring_preenable,
402 .postenable = &iio_triggered_buffer_postenable,
403 .predisable = &iio_triggered_buffer_predisable,
404 .postdisable = &ad7793_ring_postdisable,
405 .validate_scan_mask = &iio_validate_scan_mask_onehot,
406};
407
408static int ad7793_register_ring_funcs_and_init(struct iio_dev *indio_dev)
409{
410 return iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
411 &ad7793_trigger_handler, &ad7793_ring_setup_ops);
412}
413
414static void ad7793_ring_cleanup(struct iio_dev *indio_dev)
415{
416 iio_triggered_buffer_cleanup(indio_dev);
417}
418
419/**
420 * ad7793_data_rdy_trig_poll() the event handler for the data rdy trig
421 **/
422static irqreturn_t ad7793_data_rdy_trig_poll(int irq, void *private)
423{
424 struct ad7793_state *st = iio_priv(private);
425
426 st->done = true;
427 wake_up_interruptible(&st->wq_data_avail);
428 disable_irq_nosync(irq);
429 st->irq_dis = true;
430 iio_trigger_poll(st->trig, iio_get_time_ns());
431
432 return IRQ_HANDLED;
433}
434
435static struct iio_trigger_ops ad7793_trigger_ops = {
436 .owner = THIS_MODULE,
437};
438
439static int ad7793_probe_trigger(struct iio_dev *indio_dev)
440{
441 struct ad7793_state *st = iio_priv(indio_dev);
442 int ret;
443
444 st->trig = iio_trigger_alloc("%s-dev%d",
445 spi_get_device_id(st->spi)->name,
446 indio_dev->id);
447 if (st->trig == NULL) {
448 ret = -ENOMEM;
449 goto error_ret;
450 }
451 st->trig->ops = &ad7793_trigger_ops;
452
453 ret = request_irq(st->spi->irq,
454 ad7793_data_rdy_trig_poll,
455 IRQF_TRIGGER_LOW,
456 spi_get_device_id(st->spi)->name,
457 indio_dev);
458 if (ret)
459 goto error_free_trig;
460
461 disable_irq_nosync(st->spi->irq);
462 st->irq_dis = true;
463 st->trig->dev.parent = &st->spi->dev;
464 st->trig->private_data = indio_dev;
465
466 ret = iio_trigger_register(st->trig);
467
468 /* select default trigger */
469 indio_dev->trig = st->trig;
470 if (ret)
471 goto error_free_irq;
472
473 return 0;
474
475error_free_irq:
476 free_irq(st->spi->irq, indio_dev);
477error_free_trig:
478 iio_trigger_free(st->trig);
479error_ret:
480 return ret; 169 return ret;
481} 170}
482 171
483static void ad7793_remove_trigger(struct iio_dev *indio_dev)
484{
485 struct ad7793_state *st = iio_priv(indio_dev);
486
487 iio_trigger_unregister(st->trig);
488 free_irq(st->spi->irq, indio_dev);
489 iio_trigger_free(st->trig);
490}
491
492static const u16 sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39, 33, 19, 172static const u16 sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39, 33, 19,
493 17, 16, 12, 10, 8, 6, 4}; 173 17, 16, 12, 10, 8, 6, 4};
494 174
@@ -531,7 +211,7 @@ static ssize_t ad7793_write_frequency(struct device *dev,
531 mutex_lock(&indio_dev->mlock); 211 mutex_lock(&indio_dev->mlock);
532 st->mode &= ~AD7793_MODE_RATE(-1); 212 st->mode &= ~AD7793_MODE_RATE(-1);
533 st->mode |= AD7793_MODE_RATE(i); 213 st->mode |= AD7793_MODE_RATE(i);
534 ad7793_write_reg(st, AD7793_REG_MODE, 214 ad_sd_write_reg(&st->sd, AD7793_REG_MODE,
535 sizeof(st->mode), st->mode); 215 sizeof(st->mode), st->mode);
536 mutex_unlock(&indio_dev->mlock); 216 mutex_unlock(&indio_dev->mlock);
537 ret = 0; 217 ret = 0;
@@ -585,26 +265,16 @@ static int ad7793_read_raw(struct iio_dev *indio_dev,
585 long m) 265 long m)
586{ 266{
587 struct ad7793_state *st = iio_priv(indio_dev); 267 struct ad7793_state *st = iio_priv(indio_dev);
588 int ret, smpl = 0; 268 int ret;
589 unsigned long long scale_uv; 269 unsigned long long scale_uv;
590 bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR); 270 bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR);
591 271
592 switch (m) { 272 switch (m) {
593 case IIO_CHAN_INFO_RAW: 273 case IIO_CHAN_INFO_RAW:
594 mutex_lock(&indio_dev->mlock); 274 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
595 if (iio_buffer_enabled(indio_dev))
596 ret = -EBUSY;
597 else
598 ret = ad7793_read(st, chan->address,
599 chan->scan_type.realbits / 8, &smpl);
600 mutex_unlock(&indio_dev->mlock);
601
602 if (ret < 0) 275 if (ret < 0)
603 return ret; 276 return ret;
604 277
605 *val = (smpl >> chan->scan_type.shift) &
606 ((1 << (chan->scan_type.realbits)) - 1);
607
608 return IIO_VAL_INT; 278 return IIO_VAL_INT;
609 279
610 case IIO_CHAN_INFO_SCALE: 280 case IIO_CHAN_INFO_SCALE:
@@ -675,17 +345,18 @@ static int ad7793_write_raw(struct iio_dev *indio_dev,
675 ret = -EINVAL; 345 ret = -EINVAL;
676 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) 346 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
677 if (val2 == st->scale_avail[i][1]) { 347 if (val2 == st->scale_avail[i][1]) {
348 ret = 0;
678 tmp = st->conf; 349 tmp = st->conf;
679 st->conf &= ~AD7793_CONF_GAIN(-1); 350 st->conf &= ~AD7793_CONF_GAIN(-1);
680 st->conf |= AD7793_CONF_GAIN(i); 351 st->conf |= AD7793_CONF_GAIN(i);
681 352
682 if (tmp != st->conf) { 353 if (tmp == st->conf)
683 ad7793_write_reg(st, AD7793_REG_CONF, 354 break;
684 sizeof(st->conf), 355
685 st->conf); 356 ad_sd_write_reg(&st->sd, AD7793_REG_CONF,
686 ad7793_calibrate_all(st); 357 sizeof(st->conf), st->conf);
687 } 358 ad7793_calibrate_all(st);
688 ret = 0; 359 break;
689 } 360 }
690 break; 361 break;
691 default: 362 default:
@@ -696,15 +367,6 @@ static int ad7793_write_raw(struct iio_dev *indio_dev,
696 return ret; 367 return ret;
697} 368}
698 369
699static int ad7793_validate_trigger(struct iio_dev *indio_dev,
700 struct iio_trigger *trig)
701{
702 if (indio_dev->trig != trig)
703 return -EINVAL;
704
705 return 0;
706}
707
708static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev, 370static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev,
709 struct iio_chan_spec const *chan, 371 struct iio_chan_spec const *chan,
710 long mask) 372 long mask)
@@ -717,166 +379,32 @@ static const struct iio_info ad7793_info = {
717 .write_raw = &ad7793_write_raw, 379 .write_raw = &ad7793_write_raw,
718 .write_raw_get_fmt = &ad7793_write_raw_get_fmt, 380 .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
719 .attrs = &ad7793_attribute_group, 381 .attrs = &ad7793_attribute_group,
720 .validate_trigger = ad7793_validate_trigger, 382 .validate_trigger = ad_sd_validate_trigger,
721 .driver_module = THIS_MODULE, 383 .driver_module = THIS_MODULE,
722}; 384};
723 385
724static const struct ad7793_chip_info ad7793_chip_info_tbl[] = { 386static const struct ad7793_chip_info ad7793_chip_info_tbl[] = {
725 [ID_AD7793] = { 387 [ID_AD7793] = {
726 .channel[0] = { 388 .channel = {
727 .type = IIO_VOLTAGE, 389 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, 24, 32, 0),
728 .differential = 1, 390 AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, 24, 32, 0),
729 .indexed = 1, 391 AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, 24, 32, 0),
730 .channel = 0, 392 AD_SD_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, 24, 32, 0),
731 .channel2 = 0, 393 AD_SD_TEMP_CHANNEL(4, AD7793_CH_TEMP, 24, 32, 0),
732 .address = AD7793_CH_AIN1P_AIN1M, 394 AD_SD_SUPPLY_CHANNEL(5, 3, AD7793_CH_AVDD_MONITOR, 24, 32, 0),
733 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | 395 IIO_CHAN_SOFT_TIMESTAMP(6),
734 IIO_CHAN_INFO_SCALE_SHARED_BIT |
735 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
736 .scan_index = 0,
737 .scan_type = IIO_ST('u', 24, 32, 0)
738 },
739 .channel[1] = {
740 .type = IIO_VOLTAGE,
741 .differential = 1,
742 .indexed = 1,
743 .channel = 1,
744 .channel2 = 1,
745 .address = AD7793_CH_AIN2P_AIN2M,
746 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
747 IIO_CHAN_INFO_SCALE_SHARED_BIT |
748 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
749 .scan_index = 1,
750 .scan_type = IIO_ST('u', 24, 32, 0)
751 },
752 .channel[2] = {
753 .type = IIO_VOLTAGE,
754 .differential = 1,
755 .indexed = 1,
756 .channel = 2,
757 .channel2 = 2,
758 .address = AD7793_CH_AIN3P_AIN3M,
759 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
760 IIO_CHAN_INFO_SCALE_SHARED_BIT |
761 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
762 .scan_index = 2,
763 .scan_type = IIO_ST('u', 24, 32, 0)
764 },
765 .channel[3] = {
766 .type = IIO_VOLTAGE,
767 .differential = 1,
768 .extend_name = "shorted",
769 .indexed = 1,
770 .channel = 2,
771 .channel2 = 2,
772 .address = AD7793_CH_AIN1M_AIN1M,
773 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
774 IIO_CHAN_INFO_SCALE_SHARED_BIT |
775 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
776 .scan_index = 3,
777 .scan_type = IIO_ST('u', 24, 32, 0)
778 },
779 .channel[4] = {
780 .type = IIO_TEMP,
781 .indexed = 1,
782 .channel = 0,
783 .address = AD7793_CH_TEMP,
784 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
785 IIO_CHAN_INFO_SCALE_SEPARATE_BIT,
786 .scan_index = 4,
787 .scan_type = IIO_ST('u', 24, 32, 0),
788 }, 396 },
789 .channel[5] = {
790 .type = IIO_VOLTAGE,
791 .extend_name = "supply",
792 .indexed = 1,
793 .channel = 4,
794 .address = AD7793_CH_AVDD_MONITOR,
795 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
796 IIO_CHAN_INFO_SCALE_SEPARATE_BIT |
797 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
798 .scan_index = 5,
799 .scan_type = IIO_ST('u', 24, 32, 0),
800 },
801 .channel[6] = IIO_CHAN_SOFT_TIMESTAMP(6),
802 }, 397 },
803 [ID_AD7792] = { 398 [ID_AD7792] = {
804 .channel[0] = { 399 .channel = {
805 .type = IIO_VOLTAGE, 400 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, 16, 32, 0),
806 .differential = 1, 401 AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, 16, 32, 0),
807 .indexed = 1, 402 AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, 16, 32, 0),
808 .channel = 0, 403 AD_SD_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, 16, 32, 0),
809 .channel2 = 0, 404 AD_SD_TEMP_CHANNEL(4, AD7793_CH_TEMP, 16, 32, 0),
810 .address = AD7793_CH_AIN1P_AIN1M, 405 AD_SD_SUPPLY_CHANNEL(5, 3, AD7793_CH_AVDD_MONITOR, 16, 32, 0),
811 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | 406 IIO_CHAN_SOFT_TIMESTAMP(6),
812 IIO_CHAN_INFO_SCALE_SHARED_BIT |
813 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
814 .scan_index = 0,
815 .scan_type = IIO_ST('u', 16, 32, 0)
816 },
817 .channel[1] = {
818 .type = IIO_VOLTAGE,
819 .differential = 1,
820 .indexed = 1,
821 .channel = 1,
822 .channel2 = 1,
823 .address = AD7793_CH_AIN2P_AIN2M,
824 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
825 IIO_CHAN_INFO_SCALE_SHARED_BIT |
826 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
827 .scan_index = 1,
828 .scan_type = IIO_ST('u', 16, 32, 0)
829 },
830 .channel[2] = {
831 .type = IIO_VOLTAGE,
832 .differential = 1,
833 .indexed = 1,
834 .channel = 2,
835 .channel2 = 2,
836 .address = AD7793_CH_AIN3P_AIN3M,
837 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
838 IIO_CHAN_INFO_SCALE_SHARED_BIT |
839 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
840 .scan_index = 2,
841 .scan_type = IIO_ST('u', 16, 32, 0)
842 },
843 .channel[3] = {
844 .type = IIO_VOLTAGE,
845 .differential = 1,
846 .extend_name = "shorted",
847 .indexed = 1,
848 .channel = 2,
849 .channel2 = 2,
850 .address = AD7793_CH_AIN1M_AIN1M,
851 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
852 IIO_CHAN_INFO_SCALE_SHARED_BIT |
853 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
854 .scan_index = 3,
855 .scan_type = IIO_ST('u', 16, 32, 0)
856 },
857 .channel[4] = {
858 .type = IIO_TEMP,
859 .indexed = 1,
860 .channel = 0,
861 .address = AD7793_CH_TEMP,
862 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
863 IIO_CHAN_INFO_SCALE_SEPARATE_BIT,
864 .scan_index = 4,
865 .scan_type = IIO_ST('u', 16, 32, 0),
866 }, 407 },
867 .channel[5] = {
868 .type = IIO_VOLTAGE,
869 .extend_name = "supply",
870 .indexed = 1,
871 .channel = 4,
872 .address = AD7793_CH_AVDD_MONITOR,
873 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
874 IIO_CHAN_INFO_SCALE_SEPARATE_BIT |
875 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
876 .scan_index = 5,
877 .scan_type = IIO_ST('u', 16, 32, 0),
878 },
879 .channel[6] = IIO_CHAN_SOFT_TIMESTAMP(6),
880 }, 408 },
881}; 409};
882 410
@@ -903,6 +431,8 @@ static int __devinit ad7793_probe(struct spi_device *spi)
903 431
904 st = iio_priv(indio_dev); 432 st = iio_priv(indio_dev);
905 433
434 ad_sd_init(&st->sd, indio_dev, spi, &ad7793_sigma_delta_info);
435
906 st->reg = regulator_get(&spi->dev, "vcc"); 436 st->reg = regulator_get(&spi->dev, "vcc");
907 if (!IS_ERR(st->reg)) { 437 if (!IS_ERR(st->reg)) {
908 ret = regulator_enable(st->reg); 438 ret = regulator_enable(st->reg);
@@ -923,7 +453,6 @@ static int __devinit ad7793_probe(struct spi_device *spi)
923 st->int_vref_mv = 1170; /* Build-in ref */ 453 st->int_vref_mv = 1170; /* Build-in ref */
924 454
925 spi_set_drvdata(spi, indio_dev); 455 spi_set_drvdata(spi, indio_dev);
926 st->spi = spi;
927 456
928 indio_dev->dev.parent = &spi->dev; 457 indio_dev->dev.parent = &spi->dev;
929 indio_dev->name = spi_get_device_id(spi)->name; 458 indio_dev->name = spi_get_device_id(spi)->name;
@@ -932,17 +461,11 @@ static int __devinit ad7793_probe(struct spi_device *spi)
932 indio_dev->num_channels = 7; 461 indio_dev->num_channels = 7;
933 indio_dev->info = &ad7793_info; 462 indio_dev->info = &ad7793_info;
934 463
935 init_waitqueue_head(&st->wq_data_avail); 464 ret = ad_sd_setup_buffer_and_trigger(indio_dev);
936
937 ret = ad7793_register_ring_funcs_and_init(indio_dev);
938 if (ret) 465 if (ret)
939 goto error_disable_reg; 466 goto error_disable_reg;
940 467
941 ret = ad7793_probe_trigger(indio_dev); 468 ret = ad7793_setup(indio_dev, pdata);
942 if (ret)
943 goto error_unreg_ring;
944
945 ret = ad7793_setup(st, pdata);
946 if (ret) 469 if (ret)
947 goto error_remove_trigger; 470 goto error_remove_trigger;
948 471
@@ -953,9 +476,7 @@ static int __devinit ad7793_probe(struct spi_device *spi)
953 return 0; 476 return 0;
954 477
955error_remove_trigger: 478error_remove_trigger:
956 ad7793_remove_trigger(indio_dev); 479 ad_sd_cleanup_buffer_and_trigger(indio_dev);
957error_unreg_ring:
958 ad7793_ring_cleanup(indio_dev);
959error_disable_reg: 480error_disable_reg:
960 if (!IS_ERR(st->reg)) 481 if (!IS_ERR(st->reg))
961 regulator_disable(st->reg); 482 regulator_disable(st->reg);
@@ -974,8 +495,7 @@ static int ad7793_remove(struct spi_device *spi)
974 struct ad7793_state *st = iio_priv(indio_dev); 495 struct ad7793_state *st = iio_priv(indio_dev);
975 496
976 iio_device_unregister(indio_dev); 497 iio_device_unregister(indio_dev);
977 ad7793_remove_trigger(indio_dev); 498 ad_sd_cleanup_buffer_and_trigger(indio_dev);
978 ad7793_ring_cleanup(indio_dev);
979 499
980 if (!IS_ERR(st->reg)) { 500 if (!IS_ERR(st->reg)) {
981 regulator_disable(st->reg); 501 regulator_disable(st->reg);
diff --git a/drivers/staging/iio/adc/ad7793.h b/drivers/staging/iio/adc/ad7793.h
index 64f7d41dc453..0e296d88412b 100644
--- a/drivers/staging/iio/adc/ad7793.h
+++ b/drivers/staging/iio/adc/ad7793.h
@@ -41,6 +41,7 @@
41 41
42/* Mode Register Bit Designations (AD7793_REG_MODE) */ 42/* Mode Register Bit Designations (AD7793_REG_MODE) */
43#define AD7793_MODE_SEL(x) (((x) & 0x7) << 13) /* Operation Mode Select */ 43#define AD7793_MODE_SEL(x) (((x) & 0x7) << 13) /* Operation Mode Select */
44#define AD7793_MODE_SEL_MASK (0x7 << 13) /* Operation Mode Select mask */
44#define AD7793_MODE_CLKSRC(x) (((x) & 0x3) << 6) /* ADC Clock Source Select */ 45#define AD7793_MODE_CLKSRC(x) (((x) & 0x3) << 6) /* ADC Clock Source Select */
45#define AD7793_MODE_RATE(x) ((x) & 0xF) /* Filter Update Rate Select */ 46#define AD7793_MODE_RATE(x) ((x) & 0xF) /* Filter Update Rate Select */
46 47
@@ -70,6 +71,7 @@
70#define AD7793_CONF_REFSEL (1 << 7) /* INT/EXT Reference Select */ 71#define AD7793_CONF_REFSEL (1 << 7) /* INT/EXT Reference Select */
71#define AD7793_CONF_BUF (1 << 4) /* Buffered Mode Enable */ 72#define AD7793_CONF_BUF (1 << 4) /* Buffered Mode Enable */
72#define AD7793_CONF_CHAN(x) ((x) & 0x7) /* Channel select */ 73#define AD7793_CONF_CHAN(x) ((x) & 0x7) /* Channel select */
74#define AD7793_CONF_CHAN_MASK 0x7 /* Channel select mask */
73 75
74#define AD7793_CH_AIN1P_AIN1M 0 /* AIN1(+) - AIN1(-) */ 76#define AD7793_CH_AIN1P_AIN1M 0 /* AIN1(+) - AIN1(-) */
75#define AD7793_CH_AIN2P_AIN2M 1 /* AIN2(+) - AIN2(-) */ 77#define AD7793_CH_AIN2P_AIN2M 1 /* AIN2(+) - AIN2(-) */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-28 02:09:42 -0400