diff options
author | Pavel Roskin <proski@gnu.org> | 2011-07-07 18:13:24 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-07-08 11:44:28 -0400 |
commit | 0a5d381348fcb12d27289b3a66824fb3481911ce (patch) | |
tree | fd5a1a8e52f71fcf342f9c145d3614cf788ef250 | |
parent | b988a887a448be479696544de31656754c133f30 (diff) |
ath5k: replace spaces with tabs as suggested by checkpatch.pl
Signed-off-by: Pavel Roskin <proski@gnu.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r-- | drivers/net/wireless/ath/ath5k/ath5k.h | 114 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath5k/base.h | 2 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath5k/eeprom.c | 8 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath5k/initvals.c | 12 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath5k/phy.c | 6 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath5k/reg.h | 34 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath5k/reset.c | 2 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath5k/rfbuffer.h | 4 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath5k/rfgain.h | 2 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath5k/sysfs.c | 4 |
10 files changed, 94 insertions, 94 deletions
diff --git a/drivers/net/wireless/ath/ath5k/ath5k.h b/drivers/net/wireless/ath/ath5k/ath5k.h index c4c02d5145c2..79e11ff40fc3 100644 --- a/drivers/net/wireless/ath/ath5k/ath5k.h +++ b/drivers/net/wireless/ath/ath5k/ath5k.h | |||
@@ -39,34 +39,34 @@ | |||
39 | #include "../ath.h" | 39 | #include "../ath.h" |
40 | 40 | ||
41 | /* PCI IDs */ | 41 | /* PCI IDs */ |
42 | #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ | 42 | #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ |
43 | #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ | 43 | #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ |
44 | #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ | 44 | #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ |
45 | #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ | 45 | #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ |
46 | #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ | 46 | #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ |
47 | #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ | 47 | #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ |
48 | #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ | 48 | #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ |
49 | #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ | 49 | #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ |
50 | #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ | 50 | #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ |
51 | #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ | 51 | #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ |
52 | #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ | 52 | #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ |
53 | #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ | 53 | #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ |
54 | #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ | 54 | #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ |
55 | #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ | 55 | #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ |
56 | #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ | 56 | #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ |
57 | #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ | 57 | #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ |
58 | #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ | 58 | #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ |
59 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ | 59 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ |
60 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ | 60 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ |
61 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ | 61 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ |
62 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ | 62 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ |
63 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ | 63 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ |
64 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ | 64 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ |
65 | #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ | 65 | #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ |
66 | #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ | 66 | #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ |
67 | #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ | 67 | #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ |
68 | #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ | 68 | #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ |
69 | #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ | 69 | #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ |
70 | 70 | ||
71 | /****************************\ | 71 | /****************************\ |
72 | GENERIC DRIVER DEFINITIONS | 72 | GENERIC DRIVER DEFINITIONS |
@@ -374,7 +374,7 @@ struct ath5k_srev_name { | |||
374 | * they are exclusive. | 374 | * they are exclusive. |
375 | * | 375 | * |
376 | */ | 376 | */ |
377 | #define MODULATION_XR 0x00000200 | 377 | #define MODULATION_XR 0x00000200 |
378 | /* | 378 | /* |
379 | * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a | 379 | * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a |
380 | * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s | 380 | * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s |
@@ -495,9 +495,9 @@ enum ath5k_tx_queue { | |||
495 | */ | 495 | */ |
496 | enum ath5k_tx_queue_subtype { | 496 | enum ath5k_tx_queue_subtype { |
497 | AR5K_WME_AC_BK = 0, /*Background traffic*/ | 497 | AR5K_WME_AC_BK = 0, /*Background traffic*/ |
498 | AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ | 498 | AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ |
499 | AR5K_WME_AC_VI, /*Video traffic*/ | 499 | AR5K_WME_AC_VI, /*Video traffic*/ |
500 | AR5K_WME_AC_VO, /*Voice traffic*/ | 500 | AR5K_WME_AC_VO, /*Voice traffic*/ |
501 | }; | 501 | }; |
502 | 502 | ||
503 | /* | 503 | /* |
@@ -791,47 +791,47 @@ extern int ath5k_modparam_nohwcrypt; | |||
791 | * enum ath5k_int - Hardware interrupt masks helpers | 791 | * enum ath5k_int - Hardware interrupt masks helpers |
792 | * | 792 | * |
793 | * @AR5K_INT_RX: mask to identify received frame interrupts, of type | 793 | * @AR5K_INT_RX: mask to identify received frame interrupts, of type |
794 | * AR5K_ISR_RXOK or AR5K_ISR_RXERR | 794 | * AR5K_ISR_RXOK or AR5K_ISR_RXERR |
795 | * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) | 795 | * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) |
796 | * @AR5K_INT_RXNOFRM: No frame received (?) | 796 | * @AR5K_INT_RXNOFRM: No frame received (?) |
797 | * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The | 797 | * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The |
798 | * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's | 798 | * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's |
799 | * LinkPtr is NULL. For more details, refer to: | 799 | * LinkPtr is NULL. For more details, refer to: |
800 | * http://www.freepatentsonline.com/20030225739.html | 800 | * http://www.freepatentsonline.com/20030225739.html |
801 | * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). | 801 | * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). |
802 | * Note that Rx overrun is not always fatal, on some chips we can continue | 802 | * Note that Rx overrun is not always fatal, on some chips we can continue |
803 | * operation without reseting the card, that's why int_fatal is not | 803 | * operation without reseting the card, that's why int_fatal is not |
804 | * common for all chips. | 804 | * common for all chips. |
805 | * @AR5K_INT_TX: mask to identify received frame interrupts, of type | 805 | * @AR5K_INT_TX: mask to identify received frame interrupts, of type |
806 | * AR5K_ISR_TXOK or AR5K_ISR_TXERR | 806 | * AR5K_ISR_TXOK or AR5K_ISR_TXERR |
807 | * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) | 807 | * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) |
808 | * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold | 808 | * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold |
809 | * We currently do increments on interrupt by | 809 | * We currently do increments on interrupt by |
810 | * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 | 810 | * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 |
811 | * @AR5K_INT_MIB: Indicates the either Management Information Base counters or | 811 | * @AR5K_INT_MIB: Indicates the either Management Information Base counters or |
812 | * one of the PHY error counters reached the maximum value and should be | 812 | * one of the PHY error counters reached the maximum value and should be |
813 | * read and cleared. | 813 | * read and cleared. |
814 | * @AR5K_INT_RXPHY: RX PHY Error | 814 | * @AR5K_INT_RXPHY: RX PHY Error |
815 | * @AR5K_INT_RXKCM: RX Key cache miss | 815 | * @AR5K_INT_RXKCM: RX Key cache miss |
816 | * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a | 816 | * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a |
817 | * beacon that must be handled in software. The alternative is if you | 817 | * beacon that must be handled in software. The alternative is if you |
818 | * have VEOL support, in that case you let the hardware deal with things. | 818 | * have VEOL support, in that case you let the hardware deal with things. |
819 | * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing | 819 | * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing |
820 | * beacons from the AP have associated with, we should probably try to | 820 | * beacons from the AP have associated with, we should probably try to |
821 | * reassociate. When in IBSS mode this might mean we have not received | 821 | * reassociate. When in IBSS mode this might mean we have not received |
822 | * any beacons from any local stations. Note that every station in an | 822 | * any beacons from any local stations. Note that every station in an |
823 | * IBSS schedules to send beacons at the Target Beacon Transmission Time | 823 | * IBSS schedules to send beacons at the Target Beacon Transmission Time |
824 | * (TBTT) with a random backoff. | 824 | * (TBTT) with a random backoff. |
825 | * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? | 825 | * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? |
826 | * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now | 826 | * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now |
827 | * until properly handled | 827 | * until properly handled |
828 | * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA | 828 | * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA |
829 | * errors. These types of errors we can enable seem to be of type | 829 | * errors. These types of errors we can enable seem to be of type |
830 | * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. | 830 | * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. |
831 | * @AR5K_INT_GLOBAL: Used to clear and set the IER | 831 | * @AR5K_INT_GLOBAL: Used to clear and set the IER |
832 | * @AR5K_INT_NOCARD: signals the card has been removed | 832 | * @AR5K_INT_NOCARD: signals the card has been removed |
833 | * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same | 833 | * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same |
834 | * bit value | 834 | * bit value |
835 | * | 835 | * |
836 | * These are mapped to take advantage of some common bits | 836 | * These are mapped to take advantage of some common bits |
837 | * between the MACs, to be able to set intr properties | 837 | * between the MACs, to be able to set intr properties |
@@ -968,9 +968,9 @@ enum ath5k_capability_type { | |||
968 | AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ | 968 | AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ |
969 | AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ | 969 | AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ |
970 | AR5K_CAP_XR = 16, /* Supports XR mode */ | 970 | AR5K_CAP_XR = 16, /* Supports XR mode */ |
971 | AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ | 971 | AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ |
972 | AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ | 972 | AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ |
973 | AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ | 973 | AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ |
974 | AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ | 974 | AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ |
975 | }; | 975 | }; |
976 | 976 | ||
@@ -1362,12 +1362,12 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, | |||
1362 | 1362 | ||
1363 | static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah) | 1363 | static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah) |
1364 | { | 1364 | { |
1365 | return &ah->common; | 1365 | return &ah->common; |
1366 | } | 1366 | } |
1367 | 1367 | ||
1368 | static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah) | 1368 | static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah) |
1369 | { | 1369 | { |
1370 | return &(ath5k_hw_common(ah)->regulatory); | 1370 | return &(ath5k_hw_common(ah)->regulatory); |
1371 | } | 1371 | } |
1372 | 1372 | ||
1373 | #ifdef CONFIG_ATHEROS_AR231X | 1373 | #ifdef CONFIG_ATHEROS_AR231X |
diff --git a/drivers/net/wireless/ath/ath5k/base.h b/drivers/net/wireless/ath/ath5k/base.h index b294f3305011..3016562a7711 100644 --- a/drivers/net/wireless/ath/ath5k/base.h +++ b/drivers/net/wireless/ath/ath5k/base.h | |||
@@ -251,7 +251,7 @@ struct ath5k_softc { | |||
251 | unsigned int nexttbtt; /* next beacon time in TU */ | 251 | unsigned int nexttbtt; /* next beacon time in TU */ |
252 | struct ath5k_txq *cabq; /* content after beacon */ | 252 | struct ath5k_txq *cabq; /* content after beacon */ |
253 | 253 | ||
254 | int power_level; /* Requested tx power in dbm */ | 254 | int power_level; /* Requested tx power in dbm */ |
255 | bool assoc; /* associate state */ | 255 | bool assoc; /* associate state */ |
256 | bool enable_beacon; /* true if beacons are on */ | 256 | bool enable_beacon; /* true if beacons are on */ |
257 | 257 | ||
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.c b/drivers/net/wireless/ath/ath5k/eeprom.c index 1fef84f87c78..4198f4ef88d9 100644 --- a/drivers/net/wireless/ath/ath5k/eeprom.c +++ b/drivers/net/wireless/ath/ath5k/eeprom.c | |||
@@ -223,14 +223,14 @@ static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset, | |||
223 | ah->ah_ant_ctl[mode][AR5K_ANT_CTL] = | 223 | ah->ah_ant_ctl[mode][AR5K_ANT_CTL] = |
224 | (ee->ee_ant_control[mode][0] << 4); | 224 | (ee->ee_ant_control[mode][0] << 4); |
225 | ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] = | 225 | ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] = |
226 | ee->ee_ant_control[mode][1] | | 226 | ee->ee_ant_control[mode][1] | |
227 | (ee->ee_ant_control[mode][2] << 6) | | 227 | (ee->ee_ant_control[mode][2] << 6) | |
228 | (ee->ee_ant_control[mode][3] << 12) | | 228 | (ee->ee_ant_control[mode][3] << 12) | |
229 | (ee->ee_ant_control[mode][4] << 18) | | 229 | (ee->ee_ant_control[mode][4] << 18) | |
230 | (ee->ee_ant_control[mode][5] << 24); | 230 | (ee->ee_ant_control[mode][5] << 24); |
231 | ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] = | 231 | ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] = |
232 | ee->ee_ant_control[mode][6] | | 232 | ee->ee_ant_control[mode][6] | |
233 | (ee->ee_ant_control[mode][7] << 6) | | 233 | (ee->ee_ant_control[mode][7] << 6) | |
234 | (ee->ee_ant_control[mode][8] << 12) | | 234 | (ee->ee_ant_control[mode][8] << 12) | |
235 | (ee->ee_ant_control[mode][9] << 18) | | 235 | (ee->ee_ant_control[mode][9] << 18) | |
236 | (ee->ee_ant_control[mode][10] << 24); | 236 | (ee->ee_ant_control[mode][10] << 24); |
diff --git a/drivers/net/wireless/ath/ath5k/initvals.c b/drivers/net/wireless/ath/ath5k/initvals.c index e49340d18df4..4bfdc2e20dfa 100644 --- a/drivers/net/wireless/ath/ath5k/initvals.c +++ b/drivers/net/wireless/ath/ath5k/initvals.c | |||
@@ -113,8 +113,8 @@ static const struct ath5k_ini ar5210_ini[] = { | |||
113 | { AR5K_PHY(28), 0x0000000f }, | 113 | { AR5K_PHY(28), 0x0000000f }, |
114 | { AR5K_PHY(29), 0x00000080 }, | 114 | { AR5K_PHY(29), 0x00000080 }, |
115 | { AR5K_PHY(30), 0x00000004 }, | 115 | { AR5K_PHY(30), 0x00000004 }, |
116 | { AR5K_PHY(31), 0x00000018 }, /* 0x987c */ | 116 | { AR5K_PHY(31), 0x00000018 }, /* 0x987c */ |
117 | { AR5K_PHY(64), 0x00000000 }, /* 0x9900 */ | 117 | { AR5K_PHY(64), 0x00000000 }, /* 0x9900 */ |
118 | { AR5K_PHY(65), 0x00000000 }, | 118 | { AR5K_PHY(65), 0x00000000 }, |
119 | { AR5K_PHY(66), 0x00000000 }, | 119 | { AR5K_PHY(66), 0x00000000 }, |
120 | { AR5K_PHY(67), 0x00800000 }, | 120 | { AR5K_PHY(67), 0x00800000 }, |
@@ -549,7 +549,7 @@ static const struct ath5k_ini ar5212_ini_common_start[] = { | |||
549 | { AR5K_DIAG_SW_5211, 0x00000000 }, | 549 | { AR5K_DIAG_SW_5211, 0x00000000 }, |
550 | { AR5K_ADDAC_TEST, 0x00000000 }, | 550 | { AR5K_ADDAC_TEST, 0x00000000 }, |
551 | { AR5K_DEFAULT_ANTENNA, 0x00000000 }, | 551 | { AR5K_DEFAULT_ANTENNA, 0x00000000 }, |
552 | { AR5K_FRAME_CTL_QOSM, 0x000fc78f }, | 552 | { AR5K_FRAME_CTL_QOSM, 0x000fc78f }, |
553 | { AR5K_XRMODE, 0x2a82301a }, | 553 | { AR5K_XRMODE, 0x2a82301a }, |
554 | { AR5K_XRDELAY, 0x05dc01e0 }, | 554 | { AR5K_XRDELAY, 0x05dc01e0 }, |
555 | { AR5K_XRTIMEOUT, 0x1f402710 }, | 555 | { AR5K_XRTIMEOUT, 0x1f402710 }, |
@@ -760,9 +760,9 @@ static const struct ath5k_ini_mode rf5111_ini_mode_end[] = { | |||
760 | 760 | ||
761 | static const struct ath5k_ini rf5111_ini_common_end[] = { | 761 | static const struct ath5k_ini rf5111_ini_common_end[] = { |
762 | { AR5K_DCU_FP, 0x00000000 }, | 762 | { AR5K_DCU_FP, 0x00000000 }, |
763 | { AR5K_PHY_AGC, 0x00000000 }, | 763 | { AR5K_PHY_AGC, 0x00000000 }, |
764 | { AR5K_PHY_ADC_CTL, 0x00022ffe }, | 764 | { AR5K_PHY_ADC_CTL, 0x00022ffe }, |
765 | { 0x983c, 0x00020100 }, | 765 | { 0x983c, 0x00020100 }, |
766 | { AR5K_PHY_GAIN_OFFSET, 0x1284613c }, | 766 | { AR5K_PHY_GAIN_OFFSET, 0x1284613c }, |
767 | { AR5K_PHY_PAPD_PROBE, 0x00004883 }, | 767 | { AR5K_PHY_PAPD_PROBE, 0x00004883 }, |
768 | { 0x9940, 0x00000004 }, | 768 | { 0x9940, 0x00000004 }, |
diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c index 55441913344d..4e982b65404a 100644 --- a/drivers/net/wireless/ath/ath5k/phy.c +++ b/drivers/net/wireless/ath/ath5k/phy.c | |||
@@ -2456,7 +2456,7 @@ static void | |||
2456 | ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, | 2456 | ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, |
2457 | s16 *table_max) | 2457 | s16 *table_max) |
2458 | { | 2458 | { |
2459 | u8 *pcdac_out = ah->ah_txpower.txp_pd_table; | 2459 | u8 *pcdac_out = ah->ah_txpower.txp_pd_table; |
2460 | u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; | 2460 | u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; |
2461 | u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; | 2461 | u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; |
2462 | s16 min_pwr, max_pwr; | 2462 | s16 min_pwr, max_pwr; |
@@ -2502,7 +2502,7 @@ static void | |||
2502 | ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, | 2502 | ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, |
2503 | s16 *table_max, u8 pdcurves) | 2503 | s16 *table_max, u8 pdcurves) |
2504 | { | 2504 | { |
2505 | u8 *pcdac_out = ah->ah_txpower.txp_pd_table; | 2505 | u8 *pcdac_out = ah->ah_txpower.txp_pd_table; |
2506 | u8 *pcdac_low_pwr; | 2506 | u8 *pcdac_low_pwr; |
2507 | u8 *pcdac_high_pwr; | 2507 | u8 *pcdac_high_pwr; |
2508 | u8 *pcdac_tmp; | 2508 | u8 *pcdac_tmp; |
@@ -2596,7 +2596,7 @@ ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, | |||
2596 | static void | 2596 | static void |
2597 | ath5k_write_pcdac_table(struct ath5k_hw *ah) | 2597 | ath5k_write_pcdac_table(struct ath5k_hw *ah) |
2598 | { | 2598 | { |
2599 | u8 *pcdac_out = ah->ah_txpower.txp_pd_table; | 2599 | u8 *pcdac_out = ah->ah_txpower.txp_pd_table; |
2600 | int i; | 2600 | int i; |
2601 | 2601 | ||
2602 | /* | 2602 | /* |
diff --git a/drivers/net/wireless/ath/ath5k/reg.h b/drivers/net/wireless/ath/ath5k/reg.h index d12b827033c1..060a4c522ab2 100644 --- a/drivers/net/wireless/ath/ath5k/reg.h +++ b/drivers/net/wireless/ath/ath5k/reg.h | |||
@@ -72,7 +72,7 @@ | |||
72 | #define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */ | 72 | #define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */ |
73 | #define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */ | 73 | #define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */ |
74 | #define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */ | 74 | #define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */ |
75 | #define AR5K_CFG_IBSS 0x00000020 /* 0-BSS, 1-IBSS [5211+] */ | 75 | #define AR5K_CFG_IBSS 0x00000020 /* 0-BSS, 1-IBSS [5211+] */ |
76 | #define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */ | 76 | #define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */ |
77 | #define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */ | 77 | #define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */ |
78 | #define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (Disable dynamic clock) */ | 78 | #define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (Disable dynamic clock) */ |
@@ -303,7 +303,7 @@ | |||
303 | #define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ | 303 | #define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ |
304 | #define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ | 304 | #define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ |
305 | #define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ | 305 | #define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ |
306 | #define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ | 306 | #define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ |
307 | #define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ | 307 | #define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ |
308 | #define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */ | 308 | #define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */ |
309 | #define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */ | 309 | #define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */ |
@@ -397,7 +397,7 @@ | |||
397 | #define AR5K_IMR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ | 397 | #define AR5K_IMR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ |
398 | #define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ | 398 | #define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ |
399 | #define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ | 399 | #define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ |
400 | #define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ | 400 | #define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ |
401 | #define AR5K_IMR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ | 401 | #define AR5K_IMR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ |
402 | #define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/ | 402 | #define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/ |
403 | #define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */ | 403 | #define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */ |
@@ -1328,16 +1328,16 @@ | |||
1328 | #define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */ | 1328 | #define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */ |
1329 | #define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \ | 1329 | #define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \ |
1330 | AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211) | 1330 | AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211) |
1331 | #define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ | 1331 | #define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ |
1332 | #define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ | 1332 | #define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ |
1333 | #define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ | 1333 | #define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ |
1334 | #define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ | 1334 | #define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ |
1335 | #define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ | 1335 | #define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ |
1336 | #define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ | 1336 | #define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ |
1337 | #define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame [5212+] */ | 1337 | #define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame [5212+] */ |
1338 | #define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests [5212+] */ | 1338 | #define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests [5212+] */ |
1339 | #define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors [5212+] */ | 1339 | #define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors [5212+] */ |
1340 | #define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors [5212+] */ | 1340 | #define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors [5212+] */ |
1341 | #define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /* [5211] */ | 1341 | #define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /* [5211] */ |
1342 | #define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /* [5211] */ | 1342 | #define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /* [5211] */ |
1343 | #define AR5K_RX_FILTER_PHYERR \ | 1343 | #define AR5K_RX_FILTER_PHYERR \ |
@@ -1461,7 +1461,7 @@ | |||
1461 | * ADDAC test register [5211+] | 1461 | * ADDAC test register [5211+] |
1462 | */ | 1462 | */ |
1463 | #define AR5K_ADDAC_TEST 0x8054 /* Register Address */ | 1463 | #define AR5K_ADDAC_TEST 0x8054 /* Register Address */ |
1464 | #define AR5K_ADDAC_TEST_TXCONT 0x00000001 /* Test continuous tx */ | 1464 | #define AR5K_ADDAC_TEST_TXCONT 0x00000001 /* Test continuous tx */ |
1465 | #define AR5K_ADDAC_TEST_TST_MODE 0x00000002 /* Test mode */ | 1465 | #define AR5K_ADDAC_TEST_TST_MODE 0x00000002 /* Test mode */ |
1466 | #define AR5K_ADDAC_TEST_LOOP_EN 0x00000004 /* Enable loop */ | 1466 | #define AR5K_ADDAC_TEST_LOOP_EN 0x00000004 /* Enable loop */ |
1467 | #define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008 /* Loop length (field) */ | 1467 | #define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008 /* Loop length (field) */ |
@@ -2038,7 +2038,7 @@ | |||
2038 | #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S 24 | 2038 | #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S 24 |
2039 | 2039 | ||
2040 | /* Low thresholds */ | 2040 | /* Low thresholds */ |
2041 | #define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c | 2041 | #define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c |
2042 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x00000001 | 2042 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x00000001 |
2043 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f00 | 2043 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f00 |
2044 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S 8 | 2044 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S 8 |
@@ -2281,22 +2281,22 @@ | |||
2281 | #define AR5K_PHY_RADAR 0x9954 | 2281 | #define AR5K_PHY_RADAR 0x9954 |
2282 | #define AR5K_PHY_RADAR_ENABLE 0x00000001 | 2282 | #define AR5K_PHY_RADAR_ENABLE 0x00000001 |
2283 | #define AR5K_PHY_RADAR_DISABLE 0x00000000 | 2283 | #define AR5K_PHY_RADAR_DISABLE 0x00000000 |
2284 | #define AR5K_PHY_RADAR_INBANDTHR 0x0000003e /* Inband threshold | 2284 | #define AR5K_PHY_RADAR_INBANDTHR 0x0000003e /* Inband threshold |
2285 | 5-bits, units unknown {0..31} | 2285 | 5-bits, units unknown {0..31} |
2286 | (? MHz ?) */ | 2286 | (? MHz ?) */ |
2287 | #define AR5K_PHY_RADAR_INBANDTHR_S 1 | 2287 | #define AR5K_PHY_RADAR_INBANDTHR_S 1 |
2288 | 2288 | ||
2289 | #define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0 /* Pulse RSSI/SNR threshold | 2289 | #define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0 /* Pulse RSSI/SNR threshold |
2290 | 6-bits, dBm range {0..63} | 2290 | 6-bits, dBm range {0..63} |
2291 | in dBm units. */ | 2291 | in dBm units. */ |
2292 | #define AR5K_PHY_RADAR_PRSSI_THR_S 6 | 2292 | #define AR5K_PHY_RADAR_PRSSI_THR_S 6 |
2293 | 2293 | ||
2294 | #define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000 /* Pulse height threshold | 2294 | #define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000 /* Pulse height threshold |
2295 | 6-bits, dBm range {0..63} | 2295 | 6-bits, dBm range {0..63} |
2296 | in dBm units. */ | 2296 | in dBm units. */ |
2297 | #define AR5K_PHY_RADAR_PHEIGHT_THR_S 12 | 2297 | #define AR5K_PHY_RADAR_PHEIGHT_THR_S 12 |
2298 | 2298 | ||
2299 | #define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000 /* Radar RSSI/SNR threshold. | 2299 | #define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000 /* Radar RSSI/SNR threshold. |
2300 | 6-bits, dBm range {0..63} | 2300 | 6-bits, dBm range {0..63} |
2301 | in dBm units. */ | 2301 | in dBm units. */ |
2302 | #define AR5K_PHY_RADAR_RSSI_THR_S 18 | 2302 | #define AR5K_PHY_RADAR_RSSI_THR_S 18 |
diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c index 1676a3e3dc3d..3188204d8fda 100644 --- a/drivers/net/wireless/ath/ath5k/reset.c +++ b/drivers/net/wireless/ath/ath5k/reset.c | |||
@@ -25,7 +25,7 @@ | |||
25 | 25 | ||
26 | #include <asm/unaligned.h> | 26 | #include <asm/unaligned.h> |
27 | 27 | ||
28 | #include <linux/pci.h> /* To determine if a card is pci-e */ | 28 | #include <linux/pci.h> /* To determine if a card is pci-e */ |
29 | #include <linux/log2.h> | 29 | #include <linux/log2.h> |
30 | #include <linux/platform_device.h> | 30 | #include <linux/platform_device.h> |
31 | #include "ath5k.h" | 31 | #include "ath5k.h" |
diff --git a/drivers/net/wireless/ath/ath5k/rfbuffer.h b/drivers/net/wireless/ath/ath5k/rfbuffer.h index 16b67e84906d..5d11c23b4297 100644 --- a/drivers/net/wireless/ath/ath5k/rfbuffer.h +++ b/drivers/net/wireless/ath/ath5k/rfbuffer.h | |||
@@ -254,7 +254,7 @@ static const struct ath5k_ini_rfbuffer rfb_5111[] = { | |||
254 | 254 | ||
255 | /* RFX112 (Derby 1) */ | 255 | /* RFX112 (Derby 1) */ |
256 | 256 | ||
257 | /* BANK 6 len pos col */ | 257 | /* BANK 6 len pos col */ |
258 | #define AR5K_RF5112_OB_2GHZ { 3, 269, 0 } | 258 | #define AR5K_RF5112_OB_2GHZ { 3, 269, 0 } |
259 | #define AR5K_RF5112_DB_2GHZ { 3, 272, 0 } | 259 | #define AR5K_RF5112_DB_2GHZ { 3, 272, 0 } |
260 | 260 | ||
@@ -495,7 +495,7 @@ static const struct ath5k_ini_rfbuffer rfb_5112a[] = { | |||
495 | /* BANK 2 len pos col */ | 495 | /* BANK 2 len pos col */ |
496 | #define AR5K_RF2413_RF_TURBO { 1, 1, 2 } | 496 | #define AR5K_RF2413_RF_TURBO { 1, 1, 2 } |
497 | 497 | ||
498 | /* BANK 6 len pos col */ | 498 | /* BANK 6 len pos col */ |
499 | #define AR5K_RF2413_OB_2GHZ { 3, 168, 0 } | 499 | #define AR5K_RF2413_OB_2GHZ { 3, 168, 0 } |
500 | #define AR5K_RF2413_DB_2GHZ { 3, 165, 0 } | 500 | #define AR5K_RF2413_DB_2GHZ { 3, 165, 0 } |
501 | 501 | ||
diff --git a/drivers/net/wireless/ath/ath5k/rfgain.h b/drivers/net/wireless/ath/ath5k/rfgain.h index 1354d8c392c8..70c9a45609f0 100644 --- a/drivers/net/wireless/ath/ath5k/rfgain.h +++ b/drivers/net/wireless/ath/ath5k/rfgain.h | |||
@@ -452,7 +452,7 @@ static const struct ath5k_ini_rfgain rfgain_2425[] = { | |||
452 | 452 | ||
453 | /* Check if our current measurement is inside our | 453 | /* Check if our current measurement is inside our |
454 | * current variable attenuation window */ | 454 | * current variable attenuation window */ |
455 | #define AR5K_GAIN_CHECK_ADJUST(_g) \ | 455 | #define AR5K_GAIN_CHECK_ADJUST(_g) \ |
456 | ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high) | 456 | ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high) |
457 | 457 | ||
458 | struct ath5k_gain_opt_step { | 458 | struct ath5k_gain_opt_step { |
diff --git a/drivers/net/wireless/ath/ath5k/sysfs.c b/drivers/net/wireless/ath/ath5k/sysfs.c index 929c68cdf8ab..1090bbab9459 100644 --- a/drivers/net/wireless/ath/ath5k/sysfs.c +++ b/drivers/net/wireless/ath/ath5k/sysfs.c | |||
@@ -11,7 +11,7 @@ static ssize_t ath5k_attr_show_##name(struct device *dev, \ | |||
11 | char *buf) \ | 11 | char *buf) \ |
12 | { \ | 12 | { \ |
13 | struct ath5k_softc *sc = dev_get_drvdata(dev); \ | 13 | struct ath5k_softc *sc = dev_get_drvdata(dev); \ |
14 | return snprintf(buf, PAGE_SIZE, "%d\n", get); \ | 14 | return snprintf(buf, PAGE_SIZE, "%d\n", get); \ |
15 | } \ | 15 | } \ |
16 | \ | 16 | \ |
17 | static ssize_t ath5k_attr_store_##name(struct device *dev, \ | 17 | static ssize_t ath5k_attr_store_##name(struct device *dev, \ |
@@ -34,7 +34,7 @@ static ssize_t ath5k_attr_show_##name(struct device *dev, \ | |||
34 | char *buf) \ | 34 | char *buf) \ |
35 | { \ | 35 | { \ |
36 | struct ath5k_softc *sc = dev_get_drvdata(dev); \ | 36 | struct ath5k_softc *sc = dev_get_drvdata(dev); \ |
37 | return snprintf(buf, PAGE_SIZE, "%d\n", get); \ | 37 | return snprintf(buf, PAGE_SIZE, "%d\n", get); \ |
38 | } \ | 38 | } \ |
39 | static DEVICE_ATTR(name, S_IRUGO, ath5k_attr_show_##name, NULL) | 39 | static DEVICE_ATTR(name, S_IRUGO, ath5k_attr_show_##name, NULL) |
40 | 40 | ||