ENGR00286961-1 ASoC: fsl_ssi: add period size constraint for dual fifo mode

When using dual fifo mode, we need to keep period size as an even number
due to behavior of SDMA script. Otherwise, it might neglect the 2nd fifo
at each period when its size appears to be an odd number.

Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <b42378@freescale.com>

1 files changed, 9 insertions, 0 deletions

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 928bbcbe598f..a75043d4cc61 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -339,6 +339,15 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 
                 clk_prepare_enable(ssi_private->coreclk);
                 clk_prepare_enable(ssi_private->clk);
+
+                /* When using dual fifo mode, it would be safer if we ensure
+                 * its period size to be an even number. If appearing to an
+                 * odd number, the 2nd fifo might be neglected by SDMA sciprt
+                 * at the end of each period.
+                 */
+                if (ssi_private->use_dual_fifo)
+                        snd_pcm_hw_constraint_step(substream->runtime, 0,
+                                        SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
         }
 
         /*