ENGR00286960-1 arm: imx: initialize clock gate status

Some clocks gates need to be set to 2b'01 to allow CCM
auto disabling them when system enters WAIT mode, this
setting can save many runtime power. These clock gates
are normally always enabled, so no need to add another
status for clk gate enable function, just set them to
right status when system boot up is good enough.

Signed-off-by: Anson Huang <b20788@freescale.com>

2 files changed, 48 insertions, 0 deletions

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 6f29fa652621..69a49f1338f7 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -24,6 +24,8 @@
 #include "common.h"
 #include "hardware.h"
 
+#define CCM_CCGR_OFFSET(index)  (index * 2)
+
 static const char *step_sels[]  = { "osc", "pll2_pfd2_396m", };
 static const char *pll1_sw_sels[]       = { "pll1_sys", "step", };
 static const char *periph_pre_sels[]    = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
@@ -437,6 +439,31 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
                         pr_err("i.MX6q clk %d: register failed with %ld\n",
                                 i, PTR_ERR(clk[i]));
 
+        /* Initialize clock gate status */
+        writel_relaxed(1 << CCM_CCGR_OFFSET(11) |
+                3 << CCM_CCGR_OFFSET(1) |
+                3 << CCM_CCGR_OFFSET(0), base + 0x68);
+        if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
+                writel_relaxed(3 << CCM_CCGR_OFFSET(11) |
+                        3 << CCM_CCGR_OFFSET(10), base + 0x6c);
+        else
+                writel_relaxed(3 << CCM_CCGR_OFFSET(10), base + 0x6c);
+        writel_relaxed(1 << CCM_CCGR_OFFSET(12) |
+                3 << CCM_CCGR_OFFSET(11) |
+                3 << CCM_CCGR_OFFSET(10) |
+                3 << CCM_CCGR_OFFSET(9) |
+                3 << CCM_CCGR_OFFSET(8), base + 0x70);
+        writel_relaxed(3 << CCM_CCGR_OFFSET(14) |
+                1 << CCM_CCGR_OFFSET(13) |
+                3 << CCM_CCGR_OFFSET(12) |
+                1 << CCM_CCGR_OFFSET(11) |
+                3 << CCM_CCGR_OFFSET(10), base + 0x74);
+        writel_relaxed(3 << CCM_CCGR_OFFSET(7) |
+                3 << CCM_CCGR_OFFSET(6) |
+                3 << CCM_CCGR_OFFSET(4), base + 0x78);
+        writel_relaxed(1 << CCM_CCGR_OFFSET(0), base + 0x7c);
+        writel_relaxed(0, base + 0x80);
+
         clk_data.clks = clk;
         clk_data.clk_num = ARRAY_SIZE(clk);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 0b078c4fb8b3..7ff93fa2e84f 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -22,6 +22,8 @@
 #define PFD3_CLK_GATE                   (1 << 31)
 #define CCDR_CH0_HS_BYP         17
 
+#define CCM_CCGR_OFFSET(index)  (index * 2)
+
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/err.h>
@@ -365,6 +367,25 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
                         pr_err("i.MX6SL clk %d: register failed with %ld\n",
                                 i, PTR_ERR(clks[i]));
 
+        /* Initialize clock gate status */
+        writel_relaxed(1 << CCM_CCGR_OFFSET(11) |
+                3 << CCM_CCGR_OFFSET(1) |
+                3 << CCM_CCGR_OFFSET(0), base + 0x68);
+        writel_relaxed(3 << CCM_CCGR_OFFSET(10), base + 0x6c);
+        writel_relaxed(1 << CCM_CCGR_OFFSET(11) |
+                3 << CCM_CCGR_OFFSET(10) |
+                3 << CCM_CCGR_OFFSET(9) |
+                3 << CCM_CCGR_OFFSET(8), base + 0x70);
+        writel_relaxed(3 << CCM_CCGR_OFFSET(14) |
+                3 << CCM_CCGR_OFFSET(13) |
+                3 << CCM_CCGR_OFFSET(12) |
+                3 << CCM_CCGR_OFFSET(11) |
+                3 << CCM_CCGR_OFFSET(10), base + 0x74);
+        writel_relaxed(3 << CCM_CCGR_OFFSET(7) |
+                3 << CCM_CCGR_OFFSET(4), base + 0x78);
+        writel_relaxed(1 << CCM_CCGR_OFFSET(0), base + 0x7c);
+        writel_relaxed(0, base + 0x80);
+
         clk_data.clks = clks;
         clk_data.clk_num = ARRAY_SIZE(clks);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);