/*
* Copyright 2011, 2014 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <dt-bindings/clock/imx6sx-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include "imx6sx-pinfunc.h"
#include "skeleton.dtsi"
/ {
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
gpio5 = &gpio6;
gpio6 = &gpio7;
lcdif0 = &lcdif1;
lcdif1 = &lcdif2;
csi0 = &csi1;
csi1 = &csi2;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
mmc3 = &usdhc4;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
996000 1250000
792000 1175000
396000 1075000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC uV */
996000 1175000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6SX_CLK_ARM>, <&clks IMX6SX_CLK_PLL2_PFD2>, <&clks IMX6SX_CLK_STEP>,
<&clks IMX6SX_CLK_PLL1_SW>, <&clks IMX6SX_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <®_arm>;
soc-supply = <®_soc>;
};
};
intc: interrupt-controller@00a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
clock-frequency = <24000000>;
};
};
pu_dummy: pudummy_reg {
compatible = "fsl,imx6-dummy-pureg"; /* only used in ldo-bypass */
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
ranges;
busfreq {
compatible = "fsl,imx6_busfreq";
clocks = <&clks IMX6SX_CLK_PLL2_BUS>, <&clks IMX6SX_CLK_PLL2_PFD2>,
<&clks IMX6SX_CLK_PLL2_198M>, <&clks IMX6SX_CLK_ARM>,
<&clks IMX6SX_CLK_PLL3_USB_OTG>, <&clks IMX6SX_CLK_PERIPH>,
<&clks IMX6SX_CLK_PERIPH_PRE>, <&clks IMX6SX_CLK_PERIPH_CLK2>,
<&clks IMX6SX_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SX_CLK_OSC>,
<&clks IMX6SX_CLK_PLL1_SYS>, <&clks IMX6SX_CLK_PERIPH2>,
<&clks IMX6SX_CLK_AHB>, <&clks IMX6SX_CLK_OCRAM>,
<&clks IMX6SX_CLK_PLL1_SW>, <&clks IMX6SX_CLK_PERIPH2_PRE>,
<&clks IMX6SX_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SX_CLK_PERIPH2_CLK2>,
<&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_MMDC_P0_FAST>;
clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
"periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb", "ocram", "pll1_sw",
"periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "mmdc";
fsl,max_ddr_freq = <400000000>;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 94 0x04>;
};
ocrams: sram@008f8000 {
compatible = "fsl,lpm-sram";
reg = <0x008f8000 0x4000>;
clocks = <&clks IMX6SX_CLK_OCRAM_S>;
};
ocrams_ddr: sram@00900000 {
compatible = "fsl,ddr-lpm-sram";
reg = <0x00900000 0x1000>;
clocks = <&clks IMX6SX_CLK_OCRAM>;
};
ocram: sram@00901000 {
compatible = "mmio-sram";
reg = <0x00901000 0x1F000>;
clocks = <&clks IMX6SX_CLK_OCRAM>;
};
L2: l2-cache@00a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <0 92 0x04>;
cache-unified;
cache-level = <2>;
arm,tag-latency = <4 2 3>;
arm,data-latency = <4 2 3>;
};
gpu: gpu@01800000 {
compatible = "fsl,imx6sx-gpu", "fsl,imx6q-gpu";
reg = <0x01800000 0x4000>, <0x80000000 0x0>;
reg-names = "iobase_3d", "phys_baseaddr";
interrupts = <0 10 0x04>;
interrupt-names = "irq_3d";
clocks = <&clks IMX6SX_CLK_GPU_AXI_PODF>, <&clks IMX6SX_CLK_GPU>,
<&clks 0>;
clock-names = "gpu3d_axi_clk", "gpu3d_clk",
"gpu3d_shader_clk";
resets = <&src 0>;
reset-names = "gpu3d";
pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
};
dma_apbh: dma-apbh@01804000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x01804000 0x2000>;
interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clks IMX6SX_CLK_APBH_DMA>;
};
gpmi: gpmi-nand@01806000{
compatible = "fsl,imx6sx-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
reg-names = "gpmi-nand", "bch";
interrupts = <0 15 0x04>;
interrupt-names = "bch";
clocks = <&clks IMX6SX_CLK_GPMI_IO>, <&clks IMX6SX_CLK_GPMI_APB>,
<&clks IMX6SX_CLK_GPMI_BCH>, <&clks IMX6SX_CLK_GPMI_BCH_APB>,
<&clks IMX6SX_CLK_PER1_BCH>;
clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
"gpmi_bch_apb", "per1_bch";
dmas = <&dma_apbh 0>;
dma-names = "rx-tx";
status = "disabled";
};
aips-bus@02000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x40000>;
ranges;
ecspi1: ecspi@02008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
reg = <0x02008000 0x4000>;
interrupts = <0 31 0x04>;
clocks = <&clks IMX6SX_CLK_ECSPI1>,
<&clks IMX6SX_CLK_ECSPI1>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi2: ecspi@0200c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
reg = <0x0200c000 0x4000>;
interrupts = <0 32 0x04>;
clocks = <&clks IMX6SX_CLK_ECSPI2>,
<&clks IMX6SX_CLK_ECSPI2>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi3: ecspi@02010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
reg = <0x02010000 0x4000>;
interrupts = <0 33 0x04>;
clocks = <&clks IMX6SX_CLK_ECSPI3>,
<&clks IMX6SX_CLK_ECSPI3>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi4: ecspi@02014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
reg = <0x02014000 0x4000>;
interrupts = <0 34 0x04>;
clocks = <&clks IMX6SX_CLK_ECSPI4>,
<&clks IMX6SX_CLK_ECSPI4>;
clock-names = "ipg", "per";
status = "disabled";
};
spdif: spdif@02004000 {
compatible = "fsl,imx6sx-spdif",
"fsl,imx35-spdif";
reg = <0x02004000 0x4000>;
interrupts = <0 52 0x04>;
dmas = <&sdma 14 18 0>,
<&sdma 15 18 0>;
dma-names = "rx", "tx";
clocks = <&clks IMX6SX_CLK_SPDIF>,
<&clks IMX6SX_CLK_OSC>,
<&clks IMX6SX_CLK_SPDIF>,
<&clks 0>, <&clks 0>, <&clks 0>,
<&clks IMX6SX_CLK_IPG>,
<&clks 0>, <&clks 0>,
<&clks IMX6SX_CLK_SPBA>;
clock-names = "core", "rxtx0",
"rxtx1", "rxtx2",
"rxtx3", "rxtx4",
"rxtx5", "rxtx6",
"rxtx7", "dma";
status = "disabled";
};
esai: esai@02024000 {
compatible = "fsl,imx35-esai";
reg = <0x02024000 0x4000>;
interrupts = <0 51 0x04>;
clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
<&clks IMX6SX_CLK_ESAI_MEM>,
<&clks IMX6SX_CLK_ESAI_EXTAL>,
<&clks IMX6SX_CLK_ESAI_IPG>,
<&clks IMX6SX_CLK_SPBA>;
clock-names = "core", "mem", "extal", "fsys", "dma";
fsl,esai-dma-events = <24 23>;
fsl,flags = <1>;
status = "disabled";
};
asrc: asrc@02034000 {
compatible = "fsl,imx53-asrc";
reg = <0x02034000 0x4000>;
interrupts = <0 50 0x04>;
clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
<&clks IMX6SX_CLK_ASRC_IPG>,
<&clks IMX6SX_CLK_SPDIF>,
<&clks IMX6SX_CLK_SPBA>;
clock-names = "mem", "ipg", "asrck", "dma";
dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, <&sdma 19 20 1>,
<&sdma 20 20 1>, <&sdma 21 20 1>, <&sdma 22 20 1>;
dma-names = "rxa", "rxb", "rxc",
"txa", "txb", "txc";
status = "okay";
};
asrc_p2p: asrc_p2p {
compatible = "fsl,imx6q-asrc-p2p";
fsl,p2p-rate = <48000>;
fsl,p2p-width = <16>;
fsl,asrc-dma-rx-events = <17 18 19>;
fsl,asrc-dma-tx-events = <20 21 22>;
status = "okay";
};
ssi1: ssi@02028000 {
compatible = "fsl,imx6sx-ssi","fsl,imx21-ssi";
reg = <0x02028000 0x4000>;
interrupts = <0 46 0x04>;
clocks = <&clks IMX6SX_CLK_SSI1_IPG>, <&clks IMX6SX_CLK_SSI1>;
clock-names = "ipg", "baud";
dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
dma-names = "rx", "tx";
status = "disabled";
};
ssi2: ssi@0202c000 {
compatible = "fsl,imx6sx-ssi","fsl,imx21-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <0 47 0x04>;
clocks = <&clks IMX6SX_CLK_SSI2_IPG>, <&clks IMX6SX_CLK_SSI2>;
clock-names = "ipg", "baud";
dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
dma-names = "rx", "tx";
status = "disabled";
};
ssi3: ssi@02030000 {
compatible = "fsl,imx6sx-ssi","fsl,imx21-ssi";
reg = <0x02030000 0x4000>;
interrupts = <0 48 0x04>;
clocks = <&clks IMX6SX_CLK_SSI3_IPG>, <&clks IMX6SX_CLK_SSI3>;
clock-names = "ipg", "baud";
dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart1: serial@02020000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
clocks = <&clks IMX6SX_CLK_UART_IPG>, <&clks IMX6SX_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
spba@0203c000 {
reg = <0x0203c000 0x4000>;
};
};
aipstz@0207c000 { /* AIPSTZ1 */
reg = <0x0207c000 0x4000>;
};
gpt: gpt@02098000 {
compatible = "fsl,imx6sx-gpt";
reg = <0x02098000 0x4000>;
interrupts = <0 55 0x04>;
clocks = <&clks IMX6SX_CLK_GPT_BUS>, <&clks IMX6SX_CLK_GPT_SERIAL>;
clock-names = "ipg", "per";
};
clks: ccm@020c4000 {
compatible = "fsl,imx6sx-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 0x04 0 88 0x04>;
#clock-cells = <1>;
};
anatop: anatop@020c8000 {
compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
"syscon", "simple-bus";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
regulator-1p1@110 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1375000>;
regulator-always-on;
anatop-reg-offset = <0x110>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
};
regulator-3p0@120 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
anatop-reg-offset = <0x120>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
};
regulator-2p5@130 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2100000>;
regulator-max-microvolt = <2875000>;
regulator-always-on;
anatop-reg-offset = <0x130>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2100000>;
anatop-max-voltage = <2875000>;
};
reg_arm: regulator-vddcore@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "cpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <0>;
anatop-vol-bit-width = <5>;
anatop-delay-reg-offset = <0x170>;
anatop-delay-bit-shift = <24>;
anatop-delay-bit-width = <2>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
reg_pcie: regulator-vddpcie@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "vddpcie";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
anatop-delay-reg-offset = <0x170>;
anatop-delay-bit-shift = <26>;
anatop-delay-bit-width = <2>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
reg_soc: regulator-vddsoc@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <18>;
anatop-vol-bit-width = <5>;
anatop-delay-reg-offset = <0x170>;
anatop-delay-bit-shift = <28>;
anatop-delay-bit-width = <2>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
};
tempmon: tempmon {
compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
interrupts = <0 49 0x04>;
fsl,tempmon = <&anatop>;
fsl,tempmon-data = <&ocotp>;
clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
};
flexcan1: can@02090000 {
compatible = "fsl,imx6q-flexcan";
reg = <0x02090000 0x4000>;
interrupts = <0 110 0x04>;
clocks = <&clks IMX6SX_CLK_CAN1_IPG>, <&clks IMX6SX_CLK_CAN1_SERIAL>;
clock-names = "ipg", "per";
stop-mode = <&gpr 0x10 1 0x10 17>;
status = "disabled";
};
flexcan2: can@02094000 {
compatible = "fsl,imx6q-flexcan";
reg = <0x02094000 0x4000>;
interrupts = <0 111 0x04>;
clocks = <&clks IMX6SX_CLK_CAN2_IPG>, <&clks IMX6SX_CLK_CAN2_SERIAL>;
clock-names = "ipg", "per";
stop-mode = <&gpr 0x10 2 0x10 18>;
status = "disabled";
};
snvs@020cc000 {
compatible = "fsl,sec-v4.0-mon", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x020cc000 0x4000>;
snvs-rtc-lp@34 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
reg = <0x34 0x58>;
interrupts = <0 19 0x04 0 20 0x04>;
};
};
snvs-pwrkey@0x020cc000 {
compatible = "fsl,imx6sx-snvs-pwrkey";
reg = <0x020cc000 0x4000>;
interrupts = <0 4 0x4>;
fsl,keycode = <116>; /* KEY_POWER */
fsl,wakeup;
};
src: src@020d8000 {
compatible = "fsl,imx6q-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <0 91 0x04 0 96 0x04>;
#reset-cells = <1>;
};
gpc: gpc@020dc000 {
compatible = "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupts = <0 89 0x04>;
clocks = <&clks IMX6SX_CLK_GPU>, <&clks IMX6SX_CLK_IPG>,
<&clks IMX6SX_CLK_PXP_AXI>, <&clks IMX6SX_CLK_DISPLAY_AXI>,
<&clks IMX6SX_CLK_LCDIF1_PIX>, <&clks IMX6SX_CLK_LCDIF_APB>,
<&clks IMX6SX_CLK_LCDIF2_PIX>, <&clks IMX6SX_CLK_CSI>;
clock-names = "gpu3d_core", "ipg", "pxp_axi", "disp_axi", "lcdif1_pix",
"lcdif_axi", "lcdif2_pix", "csi_mclk";
pu-supply = <&pu_dummy>;
pcie-supply = <®_pcie>;
fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400200>;
};
gpio1: gpio@0209c000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x0209c000 0x4000>;
interrupts = <0 66 0x04 0 67 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@020a0000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020a0000 0x4000>;
interrupts = <0 68 0x04 0 69 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@020a4000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020a4000 0x4000>;
interrupts = <0 70 0x04 0 71 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@020a8000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020a8000 0x4000>;
interrupts = <0 72 0x04 0 73 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@020ac000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020ac000 0x4000>;
interrupts = <0 74 0x04 0 75 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio@020b0000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020b0000 0x4000>;
interrupts = <0 76 0x04 0 77 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio7: gpio@020b4000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020b4000 0x4000>;
interrupts = <0 78 0x04 0 79 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
wdog1: wdog@020bc000 {
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 0x04>;
clocks = <&clks IMX6SX_CLK_DUMMY>;
};
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6sx-iomuxc";
reg = <0x020e0000 0x4000>;
};
gpr: iomuxc-gpr@020e4000 {
compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
reg = <0x020e4000 0x4000>;
};
ldb: ldb@020e0014 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb";
gpr = <&gpr>;
status = "disabled";
clocks = <&clks IMX6SX_CLK_LDB_DI0>,
<&clks IMX6SX_CLK_LCDIF1_SEL>,
<&clks IMX6SX_CLK_LCDIF2_SEL>,
<&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>,
<&clks IMX6SX_CLK_LDB_DI0_DIV_7>,
<&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>;
clock-names = "ldb_di0",
"di0_sel",
"di1_sel",
"ldb_di0_div_3_5",
"ldb_di0_div_7",
"ldb_di0_div_sel";
lvds-channel@0 {
reg = <0>;
status = "disabled";
};
};
canfd1: canfd@020e8000 {
compatible = "bosch,m_can";
reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
reg-names = "canfd", "message_ram";
interrupts = <0 114 0x04>;
clocks = <&clks IMX6SX_CLK_CANFD>;
mram-cfg = <0x0 0 0 32 0 0 0 1>;
status = "disabled";
};
canfd2: canfd@020f0000 {
compatible = "bosch,m_can";
reg = <0x020f0000 0x4000>, <0x02298000 0x4000>;
reg-names = "canfd", "message_ram";
interrupts = <0 115 0x04>;
clocks = <&clks IMX6SX_CLK_CANFD>;
mram-cfg = <0x400 0 0 32 0 0 0 1>;
status = "disabled";
};
pwm1: pwm@02080000 {
#pwm-cells = <2>;
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <0 83 0x04>;
clocks = <&clks IMX6SX_CLK_PWM1>, <&clks IMX6SX_CLK_PWM1>;
clock-names = "ipg", "per";
};
pwm2: pwm@02084000 {
#pwm-cells = <2>;
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <0 84 0x04>;
clocks = <&clks IMX6SX_CLK_PWM2>, <&clks IMX6SX_CLK_PWM2>;
clock-names = "ipg", "per";
};
pwm3: pwm@02088000 {
#pwm-cells = <2>;
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <0 85 0x04>;
clocks = <&clks IMX6SX_CLK_PWM3>, <&clks IMX6SX_CLK_PWM3>;
clock-names = "ipg", "per";
};
pwm4: pwm@0208c000 {
#pwm-cells = <2>;
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <0 86 0x04>;
clocks = <&clks IMX6SX_CLK_PWM4>, <&clks IMX6SX_CLK_PWM4>;
clock-names = "ipg", "per";
};
sdma: sdma@020ec000 {
compatible = "fsl,imx6sx-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <0 2 0x04>;
clocks = <&clks IMX6SX_CLK_SDMA>, <&clks IMX6SX_CLK_SDMA>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
gpr = <&gpr>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
};
usbphy1: usbphy@020c9000 {
compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>;
interrupts = <0 44 0x04>;
clocks = <&clks IMX6SX_CLK_USBPHY1>;
fsl,anatop = <&anatop>;
};
usbphy2: usbphy@020ca000 {
compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
reg = <0x020ca000 0x1000>;
interrupts = <0 45 0x04>;
clocks = <&clks IMX6SX_CLK_USBPHY2>;
fsl,anatop = <&anatop>;
};
usbphy_nop1: usbphy_nop1 {
compatible = "usb-nop-xceiv";
clocks = <&clks IMX6SX_CLK_USBPHY1>;
clock-names = "main_clk";
};
};
aips-bus@02100000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
aipstz@0217c000 { /* AIPSTZ2 */
reg = <0x0217c000 0x4000>;
};
audmux: audmux@021d8000 {
compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
reg = <0x021d8000 0x4000>;
status = "disabled";
};
sai1: sai@021d4000 {
compatible = "fsl,imx6sx-sai";
reg = <0x021d4000 0x4000>;
interrupts = <0 97 0x04>;
clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
<&clks IMX6SX_CLK_SAI1>,
<&clks 0>, <&clks 0>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "rx", "tx";
dmas = <&sdma 31 23 0>, <&sdma 32 23 0>;
dma-source = <&gpr 0 15 0 16>;
status = "disabled";
};
sai2: sai@021dc000 {
compatible = "fsl,imx6sx-sai";
reg = <0x021dc000 0x4000>;
interrupts = <0 98 0x04>;
clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
<&clks IMX6SX_CLK_SAI2>,
<&clks 0>, <&clks 0>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "rx", "tx";
dmas = <&sdma 33 23 0>, <&sdma 34 23 0>;
dma-source = <&gpr 0 17 0 18>;
status = "disabled";
};
fec1: ethernet@02188000 {
compatible = "fsl,imx6sx-fec";
reg = <0x02188000 0x4000>;
interrupts = <0 118 0x04 0 119 0x04>;
clocks = <&clks IMX6SX_CLK_ENET>, <&clks IMX6SX_CLK_ENET_AHB>,
<&clks IMX6SX_CLK_ENET_PTP>, <&clks IMX6SX_CLK_ENET_REF>,
<&clks IMX6SX_CLK_ENET_PTP>;
clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out";
status = "disabled";
};
mlb: mlb@0218c000 {
compatible = "fsl,imx6sx-mlb50";
reg = <0x0218c000 0x4000>;
interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
clocks = <&clks IMX6SX_CLK_MLB>;
clock-names = "mlb";
iram = <&ocram>;
status = "disabled";
};
fec2: ethernet@021b4000 {
compatible = "fsl,imx6sx-fec";
reg = <0x021b4000 0x4000>;
interrupts = <0 102 0x04 0 103 0x04>;
clocks = <&clks IMX6SX_CLK_ENET>, <&clks IMX6SX_CLK_ENET_AHB>,
<&clks IMX6SX_CLK_ENET_PTP>, <&clks IMX6SX_CLK_ENET2_REF_125M>,
<&clks IMX6SX_CLK_ENET_PTP>;
clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out";
status = "disabled";
};
weim: weim@021b8000 {
compatible = "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
interrupts = <0 14 0x04>;
clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
status = "disabled";
};
i2c1: i2c@021a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
reg = <0x021a0000 0x4000>;
interrupts = <0 36 0x04>;
clocks = <&clks IMX6SX_CLK_I2C1>;
status = "disabled";
};
i2c2: i2c@021a4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
reg = <0x021a4000 0x4000>;
interrupts = <0 37 0x04>;
clocks = <&clks IMX6SX_CLK_I2C2>;
status = "disabled";
};
i2c3: i2c@021a8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
reg = <0x021a8000 0x4000>;
interrupts = <0 38 0x04>;
clocks = <&clks IMX6SX_CLK_I2C3>;
status = "disabled";
};
i2c4: i2c@021f8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
reg = <0x021f8000 0x4000>;
interrupts = <0 35 0x04>;
clocks = <&clks IMX6SX_CLK_I2C4>;
status = "disabled";
};
usbotg1: usb@02184000 {
compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
reg = <0x02184000 0x200>;
interrupts = <0 43 0x04>;
clocks = <&clks IMX6SX_CLK_USBOH3>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc 0>;
fsl,anatop = <&anatop>;
status = "disabled";
};
usbotg2: usb@02184200 {
compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
reg = <0x02184200 0x200>;
interrupts = <0 42 0x04>;
clocks = <&clks IMX6SX_CLK_USBOH3>;
fsl,usbphy = <&usbphy2>;
fsl,usbmisc = <&usbmisc 1>;
status = "disabled";
};
usbh: usb@02184400 {
compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
reg = <0x02184400 0x200>;
interrupts = <0 40 0x04>;
clocks = <&clks IMX6SX_CLK_USBOH3>;
fsl,usbmisc = <&usbmisc 2>;
phy_type = "hsic";
fsl,usbphy = <&usbphy_nop1>;
fsl,anatop = <&anatop>;
status = "disabled";
};
usbmisc: usbmisc: usbmisc@02184800 {
#index-cells = <1>;
compatible = "fsl,imx6sx-usbmisc";
reg = <0x02184800 0x200>;
clocks = <&clks IMX6SX_CLK_USBOH3>;
};
usdhc1: usdhc@02190000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <0 22 0x04>;
clocks = <&clks IMX6SX_CLK_USDHC1>, <&clks IMX6SX_CLK_USDHC1>, <&clks IMX6SX_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc2: usdhc@02194000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <0 23 0x04>;
clocks = <&clks IMX6SX_CLK_USDHC2>, <&clks IMX6SX_CLK_USDHC2>, <&clks IMX6SX_CLK_USDHC2>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc3: usdhc@02198000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <0 24 0x04>;
clocks = <&clks IMX6SX_CLK_USDHC3>, <&clks IMX6SX_CLK_USDHC3>, <&clks IMX6SX_CLK_USDHC3>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc4: usdhc@0219c000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <0 25 0x04>;
clocks = <&clks IMX6SX_CLK_USDHC4>, <&clks IMX6SX_CLK_USDHC4>, <&clks IMX6SX_CLK_USDHC4>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
mmdc0: mmdc@021b0000 { /* MMDC0 */
compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
};
ocotp: ocotp-ctrl@021bc000 {
compatible = "syscon";
reg = <0x021bc000 0x4000>;
};
ocotp-fuse@021bc000 {
compatible = "fsl,imx6sx-ocotp", "fsl,imx6q-ocotp";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6SX_CLK_OCOTP>;
};
qspi2: qspi@021e4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-qspi";
reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <0 109 0x04>;
clocks = <&clks IMX6SX_CLK_QSPI2>,
<&clks IMX6SX_CLK_QSPI2>;
clock-names = "qspi_en", "qspi";
status = "disabled";
};
romcp@021ac000 {
compatible = "fsl,imx6sx-romcp", "syscon";
reg = <0x021ac000 0x4000>;
};
tzasc@021d0000 { /* TZASC1 */
reg = <0x021d0000 0x4000>;
interrupts = <0 108 0x04>;
};
uart2: serial@021e8000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021e8000 0x4000>;
interrupts = <0 27 0x04>;
clocks = <&clks IMX6SX_CLK_UART_IPG>, <&clks IMX6SX_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart3: serial@021ec000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021ec000 0x4000>;
interrupts = <0 28 0x04>;
clocks = <&clks IMX6SX_CLK_UART_IPG>, <&clks IMX6SX_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart4: serial@021f0000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f0000 0x4000>;
interrupts = <0 29 0x04>;
clocks = <&clks IMX6SX_CLK_UART_IPG>, <&clks IMX6SX_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart5: serial@021f4000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f4000 0x4000>;
interrupts = <0 30 0x04>;
clocks = <&clks IMX6SX_CLK_UART_IPG>, <&clks IMX6SX_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
qosc: qosc@021fc000 {
compatible = "fsl,imx6sx-qosc";
reg = <0x021fc000 0x4000>;
};
};
aips-bus@02200000 { /* AIPS3 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02200000 0x100000>;
ranges;
spba-bus@02200000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02240000 0x40000>;
ranges;
dcic1: dcic@0220c000 {
compatible = "fsl,imx6sx-dcic";
reg = <0x0220c000 0x4000>;
interrupts = <0 124 0x04>;
clocks = <&clks IMX6SX_CLK_DCIC1>,
<&clks IMX6SX_CLK_DISPLAY_AXI>;
clock-names = "dcic", "disp-axi";
gpr = <&gpr>;
status = "disabled";
};
dcic2: dcic@02210000 {
compatible = "fsl,imx6sx-dcic";
reg = <0x02210000 0x4000>;
interrupts = <0 125 0x04>;
clocks = <&clks IMX6SX_CLK_DCIC2>,
<&clks IMX6SX_CLK_DISPLAY_AXI>;
clock-names = "dcic", "disp-axi";
gpr = <&gpr>;
status = "disabled";
};
csi1: csi@02214000 {
compatible = "fsl,imx6sx-csi", "fsl,imx6sl-csi";
reg = <0x02214000 0x4000>;
interrupts = <0 7 0x04>;
clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
<&clks IMX6SX_CLK_CSI>,
<&clks IMX6SX_CLK_DCIC1>;
clock-names = "disp-axi", "csi_mclk", "dcic";
status = "disabled";
};
csi2: csi@0221c000 {
compatible = "fsl,imx6sx-csi", "fsl,imx6sl-csi";
reg = <0x0221c000 0x4000>;
interrupts = <0 41 0x04>;
clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
<&clks IMX6SX_CLK_CSI>,
<&clks IMX6SX_CLK_DCIC2>;
clock-names = "disp-axi", "csi_mclk", "dcic";
status = "disabled";
};
lcdif1: lcdif@02220000 {
compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
reg = <0x02220000 0x4000>;
interrupts = <0 5 0x04>;
clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
<&clks IMX6SX_CLK_LCDIF_APB>,
<&clks IMX6SX_CLK_DISPLAY_AXI>;
clock-names = "pix", "axi", "disp_axi";
status = "disabled";
};
lcdif2: lcdif@02224000 {
compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
reg = <0x02224000 0x4000>;
interrupts = <0 6 0x04>;
clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
<&clks IMX6SX_CLK_LCDIF_APB>,
<&clks IMX6SX_CLK_DISPLAY_AXI>;
clock-names = "pix", "axi", "disp_axi";
status = "disabled";
};
pxp: pxp@02218000 {
compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
reg = <0x02218000 0x4000>;
interrupts = <0 8 0x04>;
clocks = <&clks IMX6SX_CLK_PXP_AXI>,
<&clks IMX6SX_CLK_DISPLAY_AXI>;
clock-names = "pxp-axi", "disp-axi";
status = "disabled";
};
vadc: vadc@02228000 {
compatible = "fsl,imx6sx-vadc";
reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
reg-names = "vadc-vafe", "vadc-vdec";
clocks = <&clks IMX6SX_CLK_VADC>,
<&clks IMX6SX_CLK_CSI>;
clock-names = "vadc", "csi";
gpr = <&gpr>;
csi_id = <0>;
status = "disabled";
};
spba@0223c000 {
reg = <0x0223c000 0x4000>;
};
};
aipstz@0227c000 { /* AIPSTZ3 */
reg = <0x0227c000 0x4000>;
};
adc1: adc@02280000 {
compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
reg = <0x02280000 0x4000>;
interrupts = <0 100 0x04>;
clocks = <&clks IMX6SX_CLK_IPG>;
clock-names = "adc";
num-channels = <4>;
status = "disabled";
};
adc2: adc@02284000 {
compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
reg = <0x02284000 0x4000>;
interrupts = <0 101 0x04>;
clocks = <&clks IMX6SX_CLK_IPG>;
clock-names = "adc";
num-channels = <4>;
status = "disabled";
};
sema4: sema4@02290000 { /* sema4 */
compatible = "fsl,imx6sx-sema4";
reg = <0x02290000 0x4000>;
interrupts = <0 116 0x04>;
status = "okay";
};
mu: mu@02294000 { /* mu */
compatible = "fsl,imx6sx-mu", "syscon";
reg = <0x02294000 0x4000>;
interrupts = <0 99 0x04>;
};
mccdemo: mccdemo{
compatible = "fsl,imx6sx-mcc-demo";
status = "okay";
};
};
pcie: pcie@0x08000000 {
compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
reg = <0x08ffc000 0x4000>; /* DBI */
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000 /* configuration space */
0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
num-lanes = <1>;
interrupts = <0 123 0x04>;
clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, <&clks IMX6SX_CLK_PCIE_AXI>,
<&clks IMX6SX_CLK_LVDS1_OUT>, <&clks IMX6SX_CLK_DISPLAY_AXI>;
clock-names = "pcie_ref_125m", "pcie_axi", "lvds_gate", "display_axi";
pcie-supply = <®_pcie>;
status = "disabled";
};
};
};
&iomuxc {
audmux {
pinctrl_audmux_1: audmuxgrp-1 {
fsl,pins = <
MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0
MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0
MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0
MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0
MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0
>;
};
pinctrl_audmux_2: audmuxgrp-2 {
fsl,pins = <
MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0
MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0
MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0
MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0
>;
};
};
ecspi4 {
pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 {
fsl,pins = <
MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000
>;
};
pinctrl_ecspi4_1: ecspi4grp-1 {
fsl,pins = <
MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1
MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1
MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1
>;
};
};
canfd1 {
pinctrl_canfd1_1: canfd1grp-1 {
fsl,pins = <
MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x1b0b0
MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x1b0b0
>;
};
};
canfd2 {
pinctrl_canfd2_1: canfd2grp-1 {
fsl,pins = <
MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x1b0b0
MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x1b0b0
>;
};
};
csi {
pinctrl_csi_0: csigrp-0 {
fsl,pins = <
MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0
MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0
MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0
MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0
MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0
MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0
MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0
MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0
MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0
MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0
MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0
MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0
MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0
MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0
MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000
MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000
>;
};
pinctrl_csi_1: csigrp-1 {
fsl,pins = <
MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0
MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0
MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0
MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0
MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0
MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0
MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0
MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0
MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0
MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0
MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0
MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0
MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000
MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000
>;
};
};
enet1 {
pinctrl_enet1_1: enet1grp-1 {
fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
>;
};
pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 {
fsl,pins = <
MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
>;
};
};
enet2 {
pinctrl_enet2_1: enet2grp-1 {
fsl,pins = <
MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b1
MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b0
MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b0
MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b0
MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b0
MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
>;
};
};
esai {
pinctrl_esai_1: esaigrp-1 {
fsl,pins = <
MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030
MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
>;
};
};
flexcan1 {
pinctrl_flexcan1_1: flexcan1grp-1 {
fsl,pins = <
MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0
MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0
>;
};
};
flexcan2 {
pinctrl_flexcan2_1: flexcan2grp-1 {
fsl,pins = <
MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0
>;
};
};
gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
>;
};
};
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c1_2: i2c1grp-2 {
fsl,pins = <
MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1
MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1
>;
};
};
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
>;
};
};
i2c3 {
pinctrl_i2c3_1: i2c3grp-1 {
fsl,pins = <
MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1
MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
>;
};
pinctrl_i2c3_2: i2c3grp-2 {
fsl,pins = <
MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
>;
};
};
i2c4 {
pinctrl_i2c4_1: i2c4grp-1 {
fsl,pins = <
MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
>;
};
pinctrl_i2c4_2: i2c4grp-2 {
fsl,pins = <
MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1
MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1
>;
};
};
lcdif1 {
pinctrl_lcdif_dat_0: lcdifdatgrp-0 {
fsl,pins = <
MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
>;
};
pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 {
fsl,pins = <
MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
>;
};
};
mlb {
pinctrl_mlb_1: mlbgrp-1 {
fsl,pins = <
MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31
MX6SX_PAD_SD2_CLK__MLB_SIG 0x31
MX6SX_PAD_SD2_CMD__MLB_CLK 0x31
>;
};
};
pwm3 {
pinctrl_pwm3_0: pwm3grp-0 {
fsl,pins = <
MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0
>;
};
pinctrl_pwm3_1: pwm3grp-1 {
fsl,pins = <
MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
>;
};
};
pwm4 {
pinctrl_pwm4_0: pwm4grp-0 {
fsl,pins = <
MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
>;
};
};
qspi2 {
pinctrl_qspi2_1: qspi2grp_1 {
fsl,pins = <
MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
>;
};
};
sai1 {
pinctrl_sai1_1: sai1grp_1 {
fsl,pins = <
MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030
MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030
MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030
MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030
MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030
MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030
>;
};
pinctrl_sai1_2: sai1grp_2 {
fsl,pins = <
MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0
MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0
MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0
MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0
MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0
>;
};
};
sai2 {
pinctrl_sai2_1: sai2grp_1 {
fsl,pins = <
MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030
MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030
MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030
MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030
>;
};
};
spdif {
pinctrl_spdif_1: spdifgrp-1 {
fsl,pins = <
MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0
MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
>;
};
pinctrl_spdif_2: spdifgrp-2 {
fsl,pins = <
MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
>;
};
pinctrl_uart1_2: uart1grp-2 {
fsl,pins = <
MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1
MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1
>;
};
};
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
>;
};
pinctrl_uart2_2: uart2grp-2 {
fsl,pins = <
MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1
MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1
>;
};
};
uart5 {
pinctrl_uart5_1: uart5grp-1 {
fsl,pins = <
MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
>;
};
};
usbh {
pinctrl_usbh_1: usbhgrp-1 {
fsl,pins = <
MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030
MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030
>;
};
pinctrl_usbh_2: usbhgrp-2 {
fsl,pins = <
MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030
>;
};
};
usbotg1 {
pinctrl_usbotg1_1: usbotg1grp-1 {
fsl,pins = <
MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usbotg1_2: usbotg1grp-2 {
fsl,pins = <
MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usbotg1_3: usbotg1grp-3 {
fsl,pins = <
MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059
>;
};
};
usbotg2 {
pinctrl_usbotg2_1: usbotg2grp-1 {
fsl,pins = <
MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059
>;
};
pinctrl_usbotg2_2: usbotg2grp-2 {
fsl,pins = <
MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059
>;
};
pinctrl_usbotg2_3: usbotg2grp-3 {
fsl,pins = <
MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059
>;
};
};
usdhc1 {
pinctrl_usdhc1_1: usdhc1grp-1 {
fsl,pins = <
MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};
};
usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
>;
};
};
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
>;
};
pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
>;
};
pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
>;
};
};
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
fsl,pins = <
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
>;
};
pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz {
fsl,pins = <
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
>;
};
pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz {
fsl,pins = <
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
>;
};
pinctrl_usdhc4_2: usdhc4grp-2 {
fsl,pins = <
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
>;
};
};
weim {
pinctrl_weim_cs0_1: weim_cs0grp-1 {
fsl,pins = <
MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1
>;
};
pinctrl_weim_nor_1: weim_norgrp-1 {
fsl,pins = <
MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1
MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1
MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060
/* data */
MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0
MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0
MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0
MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0
MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0
MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0
MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0
MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0
MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0
MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0
MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0
MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0
MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0
MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0
MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0
MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0
/* address */
MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1
MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1
MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1
MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1
MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1
MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1
MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1
MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1
MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1
MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1
MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1
MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1
MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1
MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1
MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1
MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1
MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1
MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1
MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1
MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1
MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1
MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1
MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1
MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1
MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1
MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1
>;
};
};
};
