/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include "imx6dl-pinfunc.h"
#include "imx6qdl.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
996000 1275000
792000 1175000
396000 1075000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
996000 1175000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks 104>, <&clks 6>, <&clks 16>,
<&clks 17>, <&clks 170>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <®_arm>;
pu-supply = <®_pu>;
soc-supply = <®_soc>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
};
soc {
busfreq { /* BUSFREQ */
compatible = "fsl,imx6_busfreq";
clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
<&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>, <&clks 230>, <&clks 22> , <&clks 8>;
clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
"periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_alt_sel", "axi_sel", "pll3_pfd1_540m";
interrupts = <0 107 0x04>, <0 112 0x4>;
interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
fsl,max_ddr_freq = <400000000>;
};
gpu: gpu@00130000 {
compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
<0x0 0x0>;
reg-names = "iobase_3d", "iobase_2d",
"phys_baseaddr";
interrupts = <0 9 0x04>, <0 10 0x04>;
interrupt-names = "irq_3d", "irq_2d";
clocks = <&clks 143>, <&clks 27>,
<&clks 121>, <&clks 122>,
<&clks 0>;
clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
"gpu2d_clk", "gpu3d_clk",
"gpu3d_shader_clk";
resets = <&src 0>, <&src 3>;
reset-names = "gpu3d", "gpu2d";
pu-supply = <®_pu>;
};
ocrams: sram@00900000 {
compatible = "fsl,lpm-sram";
reg = <0x00900000 0x4000>;
clocks = <&clks 142>;
};
ocrams_ddr: sram@00904000 {
compatible = "fsl,ddr-lpm-sram";
reg = <0x00904000 0x1000>;
clocks = <&clks 142>;
};
ocram: sram@00905000 {
compatible = "mmio-sram";
reg = <0x00905000 0x1B000>;
clocks = <&clks 142>;
};
hdmi_core: hdmi_core@00120000 {
compatible = "fsl,imx6dl-hdmi-core";
reg = <0x00120000 0x9000>;
clocks = <&clks 124>, <&clks 123>;
clock-names = "hdmi_isfr", "hdmi_iahb";
status = "disabled";
};
hdmi_video: hdmi_video@020e0000 {
compatible = "fsl,imx6dl-hdmi-video";
reg = <0x020e0000 0x1000>;
reg-names = "hdmi_gpr";
interrupts = <0 115 0x04>;
clocks = <&clks 124>, <&clks 123>;
clock-names = "hdmi_isfr", "hdmi_iahb";
status = "disabled";
};
hdmi_audio: hdmi_audio@00120000 {
compatible = "fsl,imx6dl-hdmi-audio";
clocks = <&clks 124>, <&clks 123>;
clock-names = "hdmi_isfr", "hdmi_iahb";
dmas = <&sdma 2 22 0>;
dma-names = "tx";
status = "disabled";
};
hdmi_cec: hdmi_cec@00120000 {
compatible = "fsl,imx6dl-hdmi-cec";
interrupts = <0 115 0x04>;
status = "disabled";
};
aips1: aips-bus@02000000 {
vpu@02040000 {
iramsize = <0>;
status = "okay";
};
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc";
};
dcic2: dcic@020e8000 {
clocks = <&clks 232>, <&clks 231>; /* DCIC2 depend on DCIC1 clock in imx6dl*/
clock-names = "dcic", "disp-axi";
};
pxp: pxp@020f0000 {
compatible = "fsl,imx6dl-pxp-dma";
reg = <0x020f0000 0x4000>;
interrupts = <0 98 0x04>;
clocks = <&clks 133>, <&clks 0>;
clock-names = "pxp-axi", "disp-axi";
status = "disabled";
};
epdc: epdc@020f4000 {
compatible = "fsl,imx6dl-epdc";
reg = <0x020f4000 0x4000>;
interrupts = <0 97 0x04>;
clocks = <&clks 133>, <&clks 137>;
clock-names = "epdc_axi", "epdc_pix";
};
lcdif: lcdif@020f8000 {
reg = <0x020f8000 0x4000>;
interrupts = <0 39 0x04>;
};
};
aips2: aips-bus@02100000 {
mipi_dsi: mipi@021e0000 {
compatible = "fsl,imx6dl-mipi-dsi";
reg = <0x021e0000 0x4000>;
interrupts = <0 102 0x04>;
gpr = <&gpr>;
clocks = <&clks 138>, <&clks 204>;
clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
status = "disabled";
};
i2c4: i2c@021f8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx1-i2c";
reg = <0x021f8000 0x4000>;
interrupts = <0 35 0x04>;
status = "disabled";
};
};
};
};
&iomuxc {
epdc {
pinctrl_epdc_0: epdcgrp-0 {
fsl,pins = <
MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x80000000
MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x80000000
MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x80000000
MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x80000000
MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x80000000
MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x80000000
MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x80000000
MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x80000000
MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x80000000
MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x80000000
MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x80000000
MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x80000000
MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x80000000
MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x80000000
MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x80000000
MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x80000000
MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x80000000
MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x80000000
MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x80000000
MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x80000000
>;
};
};
};
&ldb {
compatible = "fsl,imx6dl-ldb", "fsl,imx53-ldb";
clocks = <&clks 135>, <&clks 136>,
<&clks 39>, <&clks 40>,
<&clks 41>,
<&clks 184>, <&clks 185>,
<&clks 205>, <&clks 206>,
<&clks 207>, <&clks 208>;
clock-names = "ldb_di0", "ldb_di1",
"di0_sel", "di1_sel",
"di2_sel",
"ldb_di0_div_3_5", "ldb_di1_div_3_5",
"ldb_di0_div_7", "ldb_di1_div_7",
"ldb_di0_div_sel", "ldb_di1_div_sel";
};
