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path: root/tools/perf/scripts/python/event_analyzing_sample.py
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# event_analyzing_sample.py: general event handler in python
# SPDX-License-Identifier: GPL-2.0
#
# Current perf report is already very powerful with the annotation integrated,
# and this script is not trying to be as powerful as perf report, but
# providing end user/developer a flexible way to analyze the events other
# than trace points.
#
# The 2 database related functions in this script just show how to gather
# the basic information, and users can modify and write their own functions
# according to their specific requirement.
#
# The first function "show_general_events" just does a basic grouping for all
# generic events with the help of sqlite, and the 2nd one "show_pebs_ll" is
# for a x86 HW PMU event: PEBS with load latency data.
#

import os
import sys
import math
import struct
import sqlite3

sys.path.append(os.environ['PERF_EXEC_PATH'] + \
        '/scripts/python/Perf-Trace-Util/lib/Perf/Trace')

from perf_trace_context import *
from EventClass import *

#
# If the perf.data has a big number of samples, then the insert operation
# will be very time consuming (about 10+ minutes for 10000 samples) if the
# .db database is on disk. Move the .db file to RAM based FS to speedup
# the handling, which will cut the time down to several seconds.
#
con = sqlite3.connect("/dev/shm/perf.db")
con.isolation_level = None

def trace_begin():
	print "In trace_begin:\n"

        #
        # Will create several tables at the start, pebs_ll is for PEBS data with
        # load latency info, while gen_events is for general event.
        #
        con.execute("""
                create table if not exists gen_events (
                        name text,
                        symbol text,
                        comm text,
                        dso text
                );""")
        con.execute("""
                create table if not exists pebs_ll (
                        name text,
                        symbol text,
                        comm text,
                        dso text,
                        flags integer,
                        ip integer,
                        status integer,
                        dse integer,
                        dla integer,
                        lat integer
                );""")

#
# Create and insert event object to a database so that user could
# do more analysis with simple database commands.
#
def process_event(param_dict):
        event_attr = param_dict["attr"]
        sample     = param_dict["sample"]
        raw_buf    = param_dict["raw_buf"]
        comm       = param_dict["comm"]
        name       = param_dict["ev_name"]

        # Symbol and dso info are not always resolved
        if (param_dict.has_key("dso")):
                dso = param_dict["dso"]
        else:
                dso = "Unknown_dso"

        if (param_dict.has_key("symbol")):
                symbol = param_dict["symbol"]
        else:
                symbol = "Unknown_symbol"

        # Create the event object and insert it to the right table in database
        event = create_event(name, comm, dso, symbol, raw_buf)
        insert_db(event)

def insert_db(event):
        if event.ev_type == EVTYPE_GENERIC:
                con.execute("insert into gen_events values(?, ?, ?, ?)",
                                (event.name, event.symbol, event.comm, event.dso))
        elif event.ev_type == EVTYPE_PEBS_LL:
                event.ip &= 0x7fffffffffffffff
                event.dla &= 0x7fffffffffffffff
                con.execute("insert into pebs_ll values (?, ?, ?, ?, ?, ?, ?, ?, ?, ?)",
                        (event.name, event.symbol, event.comm, event.dso, event.flags,
                                event.ip, event.status, event.dse, event.dla, event.lat))

def trace_end():
	print "In trace_end:\n"
        # We show the basic info for the 2 type of event classes
        show_general_events()
        show_pebs_ll()
        con.close()

#
# As the event number may be very big, so we can't use linear way
# to show the histogram in real number, but use a log2 algorithm.
#

def num2sym(num):
        # Each number will have at least one '#'
        snum = '#' * (int)(math.log(num, 2) + 1)
        return snum

def show_general_events():

        # Check the total record number in the table
        count = con.execute("select count(*) from gen_events")
        for t in count:
                print "There is %d records in gen_events table" % t[0]
                if t[0] == 0:
                        return

        print "Statistics about the general events grouped by thread/symbol/dso: \n"

         # Group by thread
        commq = con.execute("select comm, count(comm) from gen_events group by comm order by -count(comm)")
        print "\n%16s %8s %16s\n%s" % ("comm", "number", "histogram", "="*42)
        for row in commq:
             print "%16s %8d     %s" % (row[0], row[1], num2sym(row[1]))

        # Group by symbol
        print "\n%32s %8s %16s\n%s" % ("symbol", "number", "histogram", "="*58)
        symbolq = con.execute("select symbol, count(symbol) from gen_events group by symbol order by -count(symbol)")
        for row in symbolq:
             print "%32s %8d     %s" % (row[0], row[1], num2sym(row[1]))

        # Group by dso
        print "\n%40s %8s %16s\n%s" % ("dso", "number", "histogram", "="*74)
        dsoq = con.execute("select dso, count(dso) from gen_events group by dso order by -count(dso)")
        for row in dsoq:
             print "%40s %8d     %s" % (row[0], row[1], num2sym(row[1]))

#
# This function just shows the basic info, and we could do more with the
# data in the tables, like checking the function parameters when some
# big latency events happen.
#
def show_pebs_ll():

        count = con.execute("select count(*) from pebs_ll")
        for t in count:
                print "There is %d records in pebs_ll table" % t[0]
                if t[0] == 0:
                        return

        print "Statistics about the PEBS Load Latency events grouped by thread/symbol/dse/latency: \n"

        # Group by thread
        commq = con.execute("select comm, count(comm) from pebs_ll group by comm order by -count(comm)")
        print "\n%16s %8s %16s\n%s" % ("comm", "number", "histogram", "="*42)
        for row in commq:
             print "%16s %8d     %s" % (row[0], row[1], num2sym(row[1]))

        # Group by symbol
        print "\n%32s %8s %16s\n%s" % ("symbol", "number", "histogram", "="*58)
        symbolq = con.execute("select symbol, count(symbol) from pebs_ll group by symbol order by -count(symbol)")
        for row in symbolq:
             print "%32s %8d     %s" % (row[0], row[1], num2sym(row[1]))

        # Group by dse
        dseq = con.execute("select dse, count(dse) from pebs_ll group by dse order by -count(dse)")
        print "\n%32s %8s %16s\n%s" % ("dse", "number", "histogram", "="*58)
        for row in dseq:
             print "%32s %8d     %s" % (row[0], row[1], num2sym(row[1]))

        # Group by latency
        latq = con.execute("select lat, count(lat) from pebs_ll group by lat order by lat")
        print "\n%32s %8s %16s\n%s" % ("latency", "number", "histogram", "="*58)
        for row in latq:
             print "%32s %8d     %s" % (row[0], row[1], num2sym(row[1]))

def trace_unhandled(event_name, context, event_fields_dict):
		print ' '.join(['%s=%s'%(k,str(v))for k,v in sorted(event_fields_dict.items())])
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/*
 * ahci-tegra.c - AHCI SATA support for TEGRA AHCI device
 *
 * Copyright (c) 2011-2018, NVIDIA Corporation.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 *
 * libata documentation is available via 'make {ps|pdf}docs',
 * as Documentation/DocBook/libata.*
 *
 * AHCI hardware documentation:
 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
 *
 */

#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/device.h>
#include <linux/dmi.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_device.h>
#include <linux/libata.h>
#include <linux/regulator/machine.h>
#include <linux/pm_runtime.h>
#include "ahci.h"

#include <linux/clk.h>
#include <linux/clk/tegra.h>
#include <linux/tegra-powergate.h>
#include <linux/platform_data/tegra-ahci-shield.h>

#include <linux/version.h>
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
#include <soc/tegra/chip-id.h>
#else
#include <linux/tegra-soc.h>
#endif

#include <linux/of_device.h>
#include <linux/of_address.h>
#include "../../arch/arm/mach-tegra/iomap.h"
#include <linux/tegra_prod.h>
#include <linux/tegra_pm_domains.h>
#include <linux/reset.h>
#include <linux/phy/phy.h>
#include <linux/ahci_platform.h>
#include <soc/tegra/pmc.h>
#include <soc/tegra/fuse.h>

#define DRV_NAME	"tegra-sata"
#define DRV_VERSION	"1.0"

#define ENABLE_AHCI_DBG_PRINT			0
#if ENABLE_AHCI_DBG_PRINT
#define AHCI_DBG_PRINT(fmt, arg...)  printk(KERN_ERR fmt, ## arg)
#else
#define AHCI_DBG_PRINT(fmt, arg...) do {} while (0)
#endif

/* number of AHCI ports */
#define TEGRA_AHCI_NUM_PORTS			1

#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
/* idle timeout for PM in msec */
#define TEGRA_AHCI_DEFAULT_IDLE_TIME		10000
#endif

/* Bit 0 (EN_FPCI) to allow FPCI accesses to SATA */
#define SATA_CONFIGURATION_0_OFFSET		0x180
#define EN_FPCI					(1 << 0)
#define CLK_OVERRIDE				(1 << 31)

#define SATA_INTR_MASK_0_OFFSET			0x188
#define IP_INT_MASK				(1 << 16)

/* Need to write 0x00400200 to 0x70020094 */
#define SATA_FPCI_BAR5_0_OFFSET			0x094
#define CPU_IER_SATA_CTL			(1 << 23)

#define AHCI_BAR5_CONFIG_LOCATION		0x24
#define TEGRA_SATA_BAR5_INIT_PROGRAM		0xFFFFFFFF
#define TEGRA_SATA_BAR5_FINAL_PROGRAM		0x40020000

#define FUSE_SATA_CALIB_OFFSET			0x224
#define FUSE_SATA_CALIB_MASK			0x3

#define T_SATA0_CFG_PHY_REG			0x120
#define T_SATA0_CFG_PHY_SQUELCH_MASK		(1 << 24)
#define PHY_USE_7BIT_ALIGN_DET_FOR_SPD_MASK	(1 << 11)

#define T_SATA0_CFG_POWER_GATE			0x4ac
#define POWER_GATE_SSTS_RESTORED_MASK		(1 << 23)
#define POWER_GATE_SSTS_RESTORED_YES		(1 << 23)
#define POWER_GATE_SSTS_RESTORED_NO		(0 << 23)

#define T_SATA0_DBG0_OFFSET			0x550

#define T_SATA0_INDEX_OFFSET			0x680
#define SATA0_NONE_SELECTED			0
#define SATA0_CH1_SELECTED			(1 << 0)

#define T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET	0x690
#define SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT	0
#define SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK	(0xff << 0)
#define SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT	8
#define SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK	(0xff << 8)

#define T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET	0x694
#define SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT	0
#define SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK	(0xff << 0)
#define SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT	12
#define SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK	(0xff << 12)
#define SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ_SHIFT	24
#define SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ_MASK	(0xf << 24)

#define T_SATA0_CFG_LINK_0				0x174
#define T_SATA0_CFG_LINK_0_USE_POSEDGE_SCTL_DET		BIT(24)

/* AHCI config space defines */
#define TEGRA_PRIVATE_AHCI_CC_BKDR		0x4a4
#define TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE	0x54c
#define TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN	(1 << 12)
#define TEGRA_PRIVATE_AHCI_CC_BKDR_PGM		0x01060100

/* AHCI HBA_CAP */
#define TEGRA_PRIVATE_AHCI_CAP_BKDR		0xa0
#define T_SATA0_AHCI_HBA_CAP_BKDR		0x300
#define AHCI_HBA_PLL_CTRL_0			0xa8

#define CLAMP_TXCLK_ON_SLUMBER			(1 << 13)
#define CLAMP_TXCLK_ON_DEVSLP			(1 << 24)
#define SHUTDOWN_TXCLK_ON_DEVSLP		(1 << 22)
#define SHUTDOWN_TXCLK_ON_SLUMBER		(1 << 6)
#define NO_CLAMP_SHUT_DOWN			(1 << 3)

#define TEGRA_SATA_IO_SPACE_OFFSET		4
#define TEGRA_SATA_ENABLE_IO_SPACE		(1 << 0)
#define TEGRA_SATA_ENABLE_MEM_SPACE		(1 << 1)
#define TEGRA_SATA_ENABLE_BUS_MASTER		(1 << 2)
#define TEGRA_SATA_ENABLE_SERR			(1 << 8)
#define TEGRA_SATA_CORE_CLOCK_FREQ_HZ		(102*1000*1000)
#define TEGRA_SATA_OOB_CLOCK_FREQ_HZ		(204*1000*1000)

#define APB_PMC_SATA_PWRGT_0_REG		0x1ac

#define CLK_RST_SATA_PLL_CFG0_REG		0x490
#define CLK_RST_SATA_PLL_CFG1_REG		0x494
#define CLK_RST_CONTROLLER_RST_DEVICES_V_0	0x358
#define CLK_RST_CONTROLLER_RST_DEVICES_W_0	0x35c
#define CLK_RST_CONTROLLER_RST_DEV_W_CLR_0	0x43c
#define CLK_RST_CONTROLLER_RST_DEV_V_CLR_0	0x434
#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR_0	0x444
#define CLK_RST_CONTROLLER_CLK_ENB_V_SET_0	0x440
#define CLK_RST_CONTROLLER_CLK_ENB_V_0		0x360
#define CLK_RST_CONTROLLER_RST_DEV_W_SET	0x438
#define CLK_RST_CONTROLLER_RST_DEV_V_SET	0x430
#define SET_CEC_RESET				0x100


#define CLR_CLK_ENB_SATA_OOB			(1 << 27)
#define CLR_CLK_ENB_SATA			(1 << 28)

#define T_SATA0_FIFO				0x170
#define T_SATA0_FIFO_L2P_FIFO_DEPTH_MASK	(0xf<<12)
#define T_SATA0_FIFO_L2P_FIFO_DEPTH_SHIFT	12

#define CLK_RST_CONTROLLER_PLLE_MISC_0		0x0ec
#define CLK_RST_CONTROLLER_PLLE_MISC_0_VALUE	0x00070300
#define CLK_RST_CONTROLLER_PLLE_BASE_0		0xe8
#define PLLE_ENABLE				(1 << 30)
#define PLLE_ENABLE_T210			(1 << 31)
#define CLK_RST_CONTROLLER_PLLE_AUX_0		0x48c
#define CLK_RST_CONTROLLER_PLLE_AUX_0_MASK	(1 << 1)

#define CLR_SATACOLD_RST			(1 << 1)
#define SWR_SATACOLD_RST			(1 << 1)
#define SWR_SATA_RST				(1 << 28)
#define SWR_SATA_OOB_RST			(1 << 27)
#define DEVSLP_OVERRIDE				(1 << 17)
#define SDS_SUPPORT				(1 << 13)
#define DESO_SUPPORT				(1 << 15)
#define SATA_AUX_PAD_PLL_CNTL_1_REG		0x00
#define SATA_AUX_MISC_CNTL_1_REG		0x08
#define SATA_AUX_SPARE_CFG0_0			0x18

/* for tegra_pmc_sata_pwrgt_update() */
#define PMC_SATA_PG_INFO_MASK			(1 << 6)
#define PMC_SATA_PG_INFO_ON				(1 << 6)
#define PMC_SATA_PG_INFO_OFF			(0 << 6)
#define PLLE_IDDQ_SWCTL_MASK			(1 << 4)
#define PADPHY_IDDQ_OVERRIDE_VALUE_MASK		(1 << 3)
#define PADPHY_IDDQ_OVERRIDE_VALUE_ON		(1 << 3)
#define PADPHY_IDDQ_OVERRIDE_VALUE_OFF		(0 << 3)
#define PADPHY_IDDQ_SWCTL_MASK			(1 << 2)
#define PADPHY_IDDQ_SWCTL_ON			(1 << 2)
#define PADPHY_IDDQ_SWCTL_OFF			(0 << 2)
#define PADPLL_IDDQ_OVERRIDE_VALUE_MASK		(1 << 1)
#define PADPLL_IDDQ_OVERRIDE_VALUE_ON		(1 << 1)
#define PADPLL_IDDQ_OVERRIDE_VALUE_OFF		(0 << 1)
#define PADPLL_IDDQ_SWCTL_MASK			(1 << 0)
#define PADPLL_IDDQ_SWCTL_ON			(1 << 0)
#define PADPLL_IDDQ_SWCTL_OFF			(0 << 0)

#define START					(1 < 8)
#define PARTID_VALUE				0x8

#define SAX_MASK				(1 << 8)

/* for CLK_RST_SATA_PLL_CFG0_REG */
#define PADPLL_RESET_OVERRIDE_VALUE_MASK	(1 << 1)
#define PADPLL_RESET_OVERRIDE_VALUE_ON		(1 << 1)
#define PADPLL_RESET_OVERRIDE_VALUE_OFF		(0 << 1)
#define PADPLL_RESET_SWCTL_MASK			(1 << 0)
#define PADPLL_RESET_SWCTL_ON			(1 << 0)
#define PADPLL_RESET_SWCTL_OFF			(0 << 0)
#define PLLE_IDDQ_SWCTL_ON			(1 << 4)
#define PLLE_IDDQ_SWCTL_OFF			(0 << 4)
#define PLLE_SATA_SEQ_ENABLE			(1 << 24)
#define PLLE_SATA_SEQ_START_STATE		(1 << 25)
#define SATA_SEQ_PADPLL_PD_INPUT_VALUE		(1 << 7)
#define SATA_SEQ_LANE_PD_INPUT_VALUE		(1 << 6)
#define SATA_SEQ_RESET_INPUT_VALUE		(1 << 5)
#define SATA_PADPLL_SLEEP_IDDQ			(1 << 13)
#define SATA_PADPLL_USE_LOCKDET			(1 << 2)

/* for CLK_RST_SATA_PLL_CFG1_REG */
#define IDDQ2LANE_SLUMBER_DLY_MASK		(0xffL << 16)
#define IDDQ2LANE_SLUMBER_DLY_SHIFT		16
#define IDDQ2LANE_SLUMBER_DLY_3MS		(3 << 16)
#define IDDQ2LANE_IDDQ_DLY_SHIFT		0
#define IDDQ2LANE_IDDQ_DLY_MASK			(0xffL << 0)

/* for SATA_AUX_PAD_PLL_CNTL_1_REG */
#define REFCLK_SEL_MASK				(3 << 11)
#define REFCLK_SEL_INT_CML			(0 << 11)
#define LOCKDET_FIELD				(1 << 6)

/* for SATA_AUX_MISC_CNTL_1_REG */
#define NVA2SATA_OOB_ON_POR_MASK		(1 << 7)
#define NVA2SATA_OOB_ON_POR_YES			(1 << 7)
#define NVA2SATA_OOB_ON_POR_NO			(0 << 7)
#define L0_RX_IDLE_T_SAX_SHIFT			5
#define L0_RX_IDLE_T_SAX_MASK			(3 << 5)
#define L0_RX_IDLE_T_NPG_SHIFT			3
#define L0_RX_IDLE_T_NPG_MASK			(3 << 3)
#define L0_RX_IDLE_T_MUX_MASK			(1 << 2)
#define L0_RX_IDLE_T_MUX_FROM_APB_MISC		(1 << 2)
#define L0_RX_IDLE_T_MUX_FROM_SATA		(0 << 2)

#define SSTAT_IPM_STATE_MASK			0xF00
#define SSTAT_IPM_SLUMBER_STATE			0x600

#define SATA_AXI_BAR5_START_0			0x54
#define SATA_AXI_BAR5_SZ_0			0x14
#define SATA_AXI_BAR5_START_VALUE		0x70020
#define AXI_BAR5_SIZE_VALUE			0x00008
#define FPCI_BAR5_0_START_VALUE			0x0010000
#define FPCI_BAR5_0_FINAL_VALUE			0x40020100
#define FPCI_BAR5_0_ACCESS_TYPE			(1 << 0)

/* Spread Settings */
#define SATA0_CHX_PHY_CTRL11_0			0x6D0
#define SATA0_CHX_PHY_CTRL2_0			0x69c
#define GEN2_RX_EQ				(0x2800 << 16)
#define CDR_CNTL_GEN1				0x23

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0	0x68
#define PLLE_SSCCENTER				(1 << 14)
#define PLLE_SSCINVERT				(1 << 15)
#define PLLE_SSCMAX				(0x25)
#define PLLE_SSCINCINTRV			(0x20 << 24)
#define PLLE_SSCINC				(1 << 16)
#define PLLE_BYPASS_SS				(1 << 10)
#define PLLE_SSCBYP				(1 << 12)
#define PLLE_INTERP_RESET			(1 << 11)

#define SATA_AUX_RX_STAT_INT_0			0x110c
#define SATA_RX_STAT_INT_DISABLE		(1 << 2)
#define SATA_AUX_RX_STAT_INT_0_SATA_DEVSLP	(0x1 << 7)

#define SATA_AUX_MISC_CNTL_1_0			0x1108
#define SATA_AUX_MISC_CNTL_1_0_DEVSLP_OVERRIDE	(0x1 << 17)

#define T_SATA0_NVOOB				0x114
#define T_SATA0_NVOOB_COMMA_CNT			(0x7 << 28)
#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_SHIFT	24
#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK	(3 << 24)
#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_SHIFT	26
#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK	(3 << 26)

#define PXSSTS_DEVICE_DETECTED			(1 << 0)

/*Electrical settings for better link stability */
#define SATA_CHX_PHY_CTRL17_0			0x6e8
#define SATA_CHX_PHY_CTRL18_0			0x6ec
#define SATA_CHX_PHY_CTRL20_0			0x6f4
#define SATA_CHX_PHY_CTRL21_0			0x6f8

#define SATA0_CFG_35_0                          0x094
#define IDP_INDEX                               (0x2a << 2)

#define SATA0_AHCI_IDP1_0                       0x098
#define SATA0_AHCI_IDP1_0_DATA			(1 << 6 | 1 << 22)

#define SATA0_CFG_PHY_1_0                       0x12c
#define PAD_IDDQ_EN                             (1 << 23)
#define PAD_PLL_IDDQ_EN                         (1 << 22)

/* SATA Port Registers*/
#define PXSSTS						0X28
#define T_AHCI_PORT_PXSSTS_IPM_MASK			(0xF00)
#define T_AHCI_PORT_PXSSTS_IPM_SHIFT			(8)

#define TEGRA_AHCI_READ_LOG_EXT_NOENTRY			0x80

#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
static struct of_device_id tegra_sata_pd[] = {
	{ .compatible = "nvidia,tegra210-sata-pd", },
	{},
};
#endif

enum {
	AHCI_PCI_BAR = 5,
};

enum tegra_ahci_port_runtime_status {
	TEGRA_AHCI_PORT_RUNTIME_ACTIVE	= 1,
	TEGRA_AHCI_PORT_RUNTIME_PARTIAL	= 2,
	TEGRA_AHCI_PORT_RUNTIME_SLUMBER	= 6,
	TEGRA_AHCI_PORT_RUNTIME_DEVSLP	= 8,
};

enum port_idle_status {
	PORT_IS_NOT_IDLE,
	PORT_IS_IDLE,
	PORT_IS_IDLE_NOT_SLUMBER,
	PORT_IS_SLUMBER,
};

enum sata_state {
	SATA_ON,
	SATA_OFF,
	SATA_GOING_ON,
	SATA_GOING_OFF,
	SATA_ABORT_OFF,
};

enum clk_gate_state {
	CLK_OFF,
	CLK_ON,
};

enum sata_connectors {
	MINI_SATA,
	MICRO_SATA,
	SLIMLINE_SATA,
	E_SATA,
	E_SATA_P,
	SATA_EXPRESS,
	STANDARD_SATA,
};

/* Sata Pad Cntrl Values */
struct sata_pad_cntrl {
	u8 gen1_tx_amp;
	u8 gen1_tx_peak;
	u8 gen2_tx_amp;
	u8 gen2_tx_peak;
};

/*
 *  tegra_ahci_host_priv is the extension of ahci_host_priv
 *  with extra fields: idle_timer, pg_save, pg_state, etc.
 */
struct tegra_ahci_host_priv {
	struct ahci_host_priv	ahci_host_priv;
	struct regulator	**power_rails;
	void __iomem		*bars_table[6];
	struct ata_host		*host;
	struct timer_list	idle_timer;
	struct device		*dev;
	struct platform_device *pdev;
	void			*pg_save;
	enum sata_state		pg_state;
	enum sata_connectors	sata_connector;
	struct clk		*clk_sata;
	struct clk		*clk_sata_oob;
	struct clk		*clk_pllp;
	struct clk		*clk_cml1;
	struct reset_control	*rst_sata;
	struct reset_control	*rst_sata_oob;
	struct reset_control	*rst_sata_cold;
	enum clk_gate_state	clk_state;
	s16			gen2_rx_eq;
	int			pexp_gpio_high;
	int			pexp_gpio_low;
	enum tegra_chipid	cid;
	struct tegra_sata_soc_data *soc_data;
	struct tegra_prod	*prod_list;
	void __iomem		*base_list[6];
	u32			reg_offset[6];
	void __iomem		*base_car;
	struct sata_pad_cntrl	pad_val;
	bool 			dtContainsPadval;
	bool			skip_rtpm;
	u8 fifo_depth;
};

#ifdef	CONFIG_DEBUG_FS
static int tegra_ahci_dump_debuginit(void);
#endif
static int tegra_ahci_init_one(struct platform_device *pdev);
static int tegra_ahci_t210_controller_init(void *hpriv, int lp0);
static int tegra_ahci_remove_one(struct platform_device *pdev);
static void tegra_ahci_shutdown(struct platform_device *pdev);
static void tegra_ahci_put_sata_in_iddq(struct ata_host *host);

#ifdef CONFIG_PM
static bool tegra_ahci_power_un_gate(struct ata_host *host);
static bool tegra_ahci_power_gate(struct ata_host *host);
static void tegra_ahci_abort_power_gate(struct ata_host *host);
static int tegra_ahci_controller_suspend(struct platform_device *pdev);
static int tegra_ahci_controller_resume(struct platform_device *pdev);
#ifndef CONFIG_TEGRA_SATA_IDLE_POWERGATE
static int tegra_ahci_suspend(struct platform_device *pdev, pm_message_t mesg);
static int tegra_ahci_resume(struct platform_device *pdev);
#else
static int tegra_ahci_suspend(struct device *dev);
static int tegra_ahci_resume(struct device *dev);
#endif
static enum port_idle_status tegra_ahci_is_port_idle(struct ata_port *ap);
static bool tegra_ahci_are_all_ports_idle(struct ata_host *host);
#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
#ifndef CONFIG_TEGRA_AHCI_CONTEXT_RESTORE
static void tegra_ahci_iddqlane_config(void);
static bool tegra_ahci_pad_resume(struct ata_host *host);
static bool tegra_ahci_pad_suspend(struct ata_host *host);
static void tegra_ahci_abort_pad_suspend(struct ata_host *host);
#endif
static int tegra_ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
static int tegra_ahci_port_resume(struct ata_port *ap);
static int tegra_ahci_runtime_suspend(struct device *dev);
static int tegra_ahci_runtime_resume(struct device *dev);
#endif
#else
#define tegra_ahci_controller_suspend	NULL
#define tegra_ahci_controller_resume	NULL
#define tegra_ahci_suspend		NULL
#define tegra_ahci_resume		NULL
#endif

static int tegra_ahci_hardreset(struct ata_link *link, unsigned int *class,
			  unsigned long deadline);
static int tegra_ahci_softreset(struct ata_link *link, unsigned int *class,
			  unsigned long deadline);
static unsigned int tegra_ahci_qc_issue(struct ata_queued_cmd *qc);

static struct scsi_host_template ahci_sht = {
	AHCI_SHT("tegra-sata"),
};

static struct ata_port_operations tegra_ahci_ops = {
	.inherits	= &ahci_ops,
	.qc_issue	= tegra_ahci_qc_issue,
#ifdef CONFIG_PM
#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
	.port_suspend           = tegra_ahci_port_suspend,
	.port_resume            = tegra_ahci_port_resume,
#endif
#endif
	.hardreset	= tegra_ahci_hardreset,
	.softreset	= tegra_ahci_softreset,
};

static const struct ata_port_info ahci_port_info = {
	.flags		= AHCI_FLAG_COMMON,
	.pio_mask	= 0x1f, /* pio0-4 */
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &tegra_ahci_ops,
};

#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
static const struct dev_pm_ops tegra_ahci_dev_rt_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(tegra_ahci_suspend, tegra_ahci_resume)
	SET_RUNTIME_PM_OPS(tegra_ahci_runtime_suspend,
			tegra_ahci_runtime_resume, NULL)
};
#endif

static char * const t210_rail_names[] = {"dvdd_sata_pll", "hvdd_sata",
			"l0_hvddio_sata", "l0_dvddio_sata", "hvdd_pex_pll_e"};

static const struct tegra_sata_soc_data tegra210_sata_data = {
	.sata_regulator_names = t210_rail_names,
	.num_sata_regulators = ARRAY_SIZE(t210_rail_names),
	.controller_init = tegra_ahci_t210_controller_init,
};

static const struct of_device_id of_ahci_tegra_match[] = {
	{
		.compatible = "nvidia,tegra210-ahci-sata-shield",
		.data = &tegra210_sata_data,
	},
	{},
};

MODULE_DEVICE_TABLE(of, of_ahci_tegra_match);

static const struct of_device_id car_match[] = {
	{ .compatible = "nvidia,tegra210-car", },
	{},
};

static struct platform_driver tegra_platform_ahci_driver = {
	.probe		= tegra_ahci_init_one,
	.remove		= tegra_ahci_remove_one,
	.shutdown	= tegra_ahci_shutdown,
#ifdef CONFIG_PM
#ifndef CONFIG_TEGRA_SATA_IDLE_POWERGATE
	.suspend	= tegra_ahci_suspend,
	.resume		= tegra_ahci_resume,
#endif
#endif
	.driver = {
		.name = DRV_NAME,
		.owner = THIS_MODULE,
		.of_match_table = of_match_ptr(of_ahci_tegra_match),
#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
		.pm      = &tegra_ahci_dev_rt_ops,
#endif
	},
};

static struct tegra_ahci_host_priv *g_tegra_hpriv;

static inline u32 port_readl(u32 offset)
{
	u32 val;
	void __iomem *addr = g_tegra_hpriv->base_list[1] + 0x100 + offset;

	val = readl(addr);
	AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", addr, val);
	return val;
}

static inline void port_writel(u32 val, u32 offset)
{
	void __iomem *addr = g_tegra_hpriv->base_list[1] + 0x100 + offset;

	AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", addr, val);
	writel(val, addr);
	readl(addr);
}

static inline u32 bar5_readl(u32 offset)
{
	u32 val;
	void __iomem *addr = g_tegra_hpriv->base_list[1] + offset;

	val = readl(addr);
	AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", addr, val);
	return val;
}

static inline void bar5_writel(u32 val, u32 offset)
{
	void __iomem *addr = g_tegra_hpriv->base_list[1] + offset;

	AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", addr, val);
	writel(val, addr);
	readl(addr);
}

static inline u32 clk_readl(u32 offset)
{
	u32 val;
	void __iomem *addr = g_tegra_hpriv->base_car + offset;

	val = readl(addr);
	AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", addr, val);
	return val;
}

static inline void clk_writel(u32 val, u32 offset)
{
	void __iomem *addr = g_tegra_hpriv->base_car+offset;

	AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", addr, val);
	writel(val, addr);
	readl(addr);
}

static inline u32 misc_readl(u32 offset)
{
	u32 val;
	void __iomem *addr = g_tegra_hpriv->base_list[2] + offset;

	val = readl(addr);
	AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", addr, val);
	return val;
}

static inline void misc_writel(u32 val, u32 offset)
{
	void __iomem *addr = g_tegra_hpriv->base_list[2] + offset;

	AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", addr, val);
	writel(val, addr);
	readl(addr);
}

static inline u32 sata_readl(u32 offset)
{
	u32 val;
	void __iomem *addr = g_tegra_hpriv->base_list[3] + offset;

	val = readl(addr);
	AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", addr, val);
	return val;
}

static inline void sata_writel(u32 val, u32 offset)
{
	void __iomem *addr = g_tegra_hpriv->base_list[3] + offset;

	AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", addr, val);
	writel(val, addr);
	readl(addr);
}

static inline u32 scfg_readl(u32 offset)
{
	u32 val;
	void __iomem *addr = g_tegra_hpriv->base_list[0] + offset;

	val = readl(addr);
	AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", addr, val);
	return val;
}

static inline void scfg_writel(u32 val, u32 offset)
{
	void __iomem *addr = g_tegra_hpriv->base_list[0] + offset;

	AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", addr, val);
	writel(val, addr);
	readl(addr);
}

static inline u32 fuse_readl(u32 offset)
{
	u32 val;

	if (!tegra_fuse_readl(offset, &val)) {
		pr_err("%s: failed to read fuse register at 0x%x\n", __func__,
				offset);
		return 0;
	}

	return val;
}

static struct sata_pad_cntrl sata_calib_pad_val[] = {
	{	/* SATA_CALIB[1:0]  = 00 */
		0x18,
		0x04,
		0x18,
		0x0a
	},
	{	/* SATA_CALIB[1:0]  = 01 */
		0x0e,
		0x04,
		0x14,
		0x0a
	},
	{	/* SATA_CALIB[1:0]  = 10 */
		0x0e,
		0x07,
		0x1a,
		0x0e
	},
	{	/* SATA_CALIB[1:0]  = 11 */
		0x14,
		0x0e,
		0x1a,
		0x0e
	}
};

static u32 tegra_ahci_get_port_status(void)
{
	u32 val;

	val = port_readl(PXSSTS);

	return val;
}

static void tegra_ahci_set_pad_cntrl_regs(
			struct tegra_ahci_host_priv *tegra_hpriv)
{
	int	calib_val;
	int	val;
	int	i;
	int	err = 0;

	if (tegra_hpriv->cid == TEGRA_CHIPID_TEGRA21) {
		err = tegra_prod_set_by_name(
				tegra_hpriv->base_list,
				"prod",
				tegra_hpriv->prod_list);
		if (err) {
			dev_err(tegra_hpriv->dev,
					"Prod setting from DT failed\n");
		} else {
			scfg_writel(0x55010000, SATA_CHX_PHY_CTRL17_0);
			scfg_writel(0x55010000, SATA_CHX_PHY_CTRL18_0);
			scfg_writel(0x1, SATA_CHX_PHY_CTRL20_0);
			scfg_writel(0x1, SATA_CHX_PHY_CTRL21_0);
		}
		return;
	}

	calib_val = fuse_readl(FUSE_SATA_CALIB_OFFSET) & FUSE_SATA_CALIB_MASK;

	val = clk_readl(CLK_RST_CONTROLLER_PLLE_SS_CNTL_0);
	val &= ~(PLLE_SSCCENTER | PLLE_SSCINVERT);
	val |= (PLLE_SSCMAX | PLLE_SSCINCINTRV | PLLE_SSCINC);
	clk_writel(val, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0);

	val = clk_readl(CLK_RST_CONTROLLER_PLLE_SS_CNTL_0);
	val &= ~(PLLE_BYPASS_SS | PLLE_SSCBYP);
	clk_writel(val, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0);

	udelay(2);

	val = clk_readl(CLK_RST_CONTROLLER_PLLE_SS_CNTL_0);
	val &= ~(PLLE_INTERP_RESET);
	clk_writel(val, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0);

	for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
		scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);

		val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
		val &= ~SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
		val |= (sata_calib_pad_val[calib_val].gen1_tx_amp <<
			SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT);
		scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);

		val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
		val &= ~SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
		val |= (sata_calib_pad_val[calib_val].gen1_tx_peak <<
			SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT);
		scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);

		val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
		val &= ~SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
		val |= (sata_calib_pad_val[calib_val].gen2_tx_amp <<
			SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT);
		scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);

		val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
		val &= ~SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
		val |= (sata_calib_pad_val[calib_val].gen2_tx_peak <<
			SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT);
		scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);

		val = GEN2_RX_EQ;
		scfg_writel(val, SATA0_CHX_PHY_CTRL11_0);

		val = CDR_CNTL_GEN1;
		scfg_writel(val, SATA0_CHX_PHY_CTRL2_0);
	}
	scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
}

static int tegra_ahci_get_rails(struct tegra_ahci_host_priv *tegra_hpriv)
{
	struct regulator *reg;
	int i;
	int ret = 0;

	tegra_hpriv->power_rails = devm_kzalloc(tegra_hpriv->dev,
			tegra_hpriv->soc_data->num_sata_regulators
			* sizeof(struct regulator *), GFP_KERNEL);

	for (i = 0; i < tegra_hpriv->soc_data->num_sata_regulators; ++i) {
		reg = devm_regulator_get(tegra_hpriv->dev,
				tegra_hpriv->soc_data->sata_regulator_names[i]);
		if (IS_ERR(reg)) {
			dev_err(tegra_hpriv->dev, "%s:can't get regulator %s\n",
				__func__,
				tegra_hpriv->soc_data->sata_regulator_names[i]);
			WARN_ON(1);
			ret = PTR_ERR(reg);
			tegra_hpriv->power_rails[i] = NULL;
			goto exit;
		}
		tegra_hpriv->power_rails[i] = reg;
	}
exit:
	return ret;
}

static int tegra_ahci_power_off_rails(struct tegra_ahci_host_priv *tegra_hpriv,
		int num_reg)
{
	struct regulator *reg;
	int i;
	int ret = 0;
	int rc = 0;

	for (i = 0; i < num_reg; ++i) {
		reg = tegra_hpriv->power_rails[i];
		if (!IS_ERR(reg)) {
			ret = regulator_disable(reg);
			if (ret) {
				dev_err(tegra_hpriv->dev,
				"%s: can't disable regulator[%d]\n",
					__func__, i);
				WARN_ON(1);
				rc = ret;
			}
		}
	}

	return rc;
}

static int tegra_ahci_power_on_rails(struct tegra_ahci_host_priv *tegra_hpriv)
{
	int i;
	int ret = 0;

	for (i = 0; i < tegra_hpriv->soc_data->num_sata_regulators; ++i) {
		ret = regulator_enable(tegra_hpriv->power_rails[i]);
		if (ret) {
			dev_err(tegra_hpriv->dev,
				"%s: can't enable regulator[%d]\n",
				__func__, i);
			WARN_ON(1);
			tegra_ahci_power_off_rails(tegra_hpriv, i);
			goto exit;
		}
	}

exit:
	return ret;
}

static void tegra_first_level_clk_gate(void)
{
	if (g_tegra_hpriv->clk_state == CLK_OFF)
		return;

	clk_disable_unprepare(g_tegra_hpriv->clk_sata);
	clk_disable_unprepare(g_tegra_hpriv->clk_sata_oob);
	if (g_tegra_hpriv->clk_cml1)
		clk_disable_unprepare(g_tegra_hpriv->clk_cml1);
	g_tegra_hpriv->clk_state = CLK_OFF;
}

static int tegra_first_level_clk_ungate(void)
{
	int ret = 0;
	const char *err_clk_name;

	if (g_tegra_hpriv->clk_state == CLK_ON) {
		ret = -1;
		return ret;
	}

	if (clk_prepare_enable(g_tegra_hpriv->clk_sata)) {
		err_clk_name = "SATA";
		goto clk_sata_enb_error;
	}
	if (clk_prepare_enable(g_tegra_hpriv->clk_sata_oob)) {
		err_clk_name = "SATA_OOB";
		goto clk_sata_oob_enb_error;
	}

	if (g_tegra_hpriv->clk_cml1 &&
		clk_prepare_enable(g_tegra_hpriv->clk_cml1)) {
		err_clk_name = "cml1";
		goto clk_cml1_enb_error;
	}
	g_tegra_hpriv->clk_state = CLK_ON;

	return ret;

clk_cml1_enb_error:
	clk_disable_unprepare(g_tegra_hpriv->clk_sata_oob);
clk_sata_oob_enb_error:
	clk_disable_unprepare(g_tegra_hpriv->clk_sata);
clk_sata_enb_error:
	pr_err("%s: unable to enable %s clock\n", __func__, err_clk_name);
	return -ENODEV;
}

static int tegra_request_pexp_gpio(struct tegra_ahci_host_priv *tegra_hpriv)
{
	u32 val = 0;
	int err = 0;
	if (gpio_is_valid(tegra_hpriv->pexp_gpio_high)) {
		val = gpio_request(tegra_hpriv->pexp_gpio_high,
				"ahci-tegra");
		if (val) {
			pr_err("failed to allocate Port expander gpio\n");
			err = -ENODEV;
			goto exit;
		}
		gpio_direction_output(tegra_hpriv->pexp_gpio_high, 1);
	}

	if (gpio_is_valid(tegra_hpriv->pexp_gpio_low)) {
		val = gpio_request(tegra_hpriv->pexp_gpio_low,
				"ahci-tegra");
		if (val) {
			pr_err("failed to allocate Port expander gpio\n");
			err = -ENODEV;
			goto exit;
		}
		gpio_direction_output(tegra_hpriv->pexp_gpio_low, 0);
	}

exit:
	return err;
}

static void tegra_free_pexp_gpio(struct tegra_ahci_host_priv *tegra_hpriv)
{
	if (gpio_is_valid(tegra_hpriv->pexp_gpio_high))
		gpio_free(tegra_hpriv->pexp_gpio_high);
	if (gpio_is_valid(tegra_hpriv->pexp_gpio_low))
		gpio_free(tegra_hpriv->pexp_gpio_low);

}

static unsigned int tegra_ahci_qc_issue(struct ata_queued_cmd *qc)
{
	if (qc->tf.command == ATA_CMD_READ_LOG_EXT &&
			qc->tf.lbal == ATA_LOG_SATA_NCQ) {
		u8 *buf =
		(u8 *) page_address((const struct page *)qc->sg->page_link);

		/*
		 * Since our SATA Controller does not support this command
		 * don't send this command to the drive instead complete
		 * the function here and indicate to the upper layer
		 * that there is no entries in the buffer.
		 */
		buf += qc->sg->offset;
		buf[0] = TEGRA_AHCI_READ_LOG_EXT_NOENTRY;
		qc->complete_fn(qc);

		return 0;
	}

	return ahci_ops.qc_issue(qc);
}

static int tegra_ahci_t210_controller_init(void *hpriv, int lp0)
{
	struct tegra_ahci_host_priv *tegra_hpriv = hpriv;
	struct clk *clk_sata = NULL;
	struct clk *clk_sata_oob = NULL;
	struct clk *clk_pllp = NULL;
	struct reset_control *rst_sata = NULL;
	struct reset_control *rst_sata_oob = NULL;
	struct reset_control *rst_sata_cold = NULL;
	int err = 0;
	u32 val;
#if defined(CONFIG_TEGRA_SILICON_PLATFORM)
	int partition_id;
#endif

	if (!lp0) {
		err = tegra_ahci_get_rails(tegra_hpriv);
		if (err) {
			pr_err("%s: fails to get rails (%d)\n", __func__, err);
			goto exit;
		}
		err = tegra_ahci_power_on_rails(tegra_hpriv);
		if (err) {
			pr_err("%s: fails to power on rails (%d)\n",
					__func__, err);
			goto exit;
		}
		err = tegra_request_pexp_gpio(tegra_hpriv);
		if (err < 0) {
			tegra_free_pexp_gpio(tegra_hpriv);
			goto exit;
		}

		tegra_hpriv->clk_cml1 = NULL;

		/* pll_p is the parent of tegra_sata and tegra_sata_oob */
		clk_pllp = clk_get_sys(NULL, "pll_p");
		if (IS_ERR_OR_NULL(clk_pllp)) {
			pr_err("%s: unable to get PLL_P clock\n", __func__);
			err = PTR_ERR(clk_pllp);
			goto exit;
		}
		tegra_hpriv->clk_pllp = clk_pllp;

		clk_sata = devm_clk_get(tegra_hpriv->dev, "sata");
		if (IS_ERR_OR_NULL(clk_sata)) {
			pr_err("%s: unable to get SATA clock\n", __func__);
			err = PTR_ERR(clk_sata);
			goto exit;
		}
		tegra_hpriv->clk_sata = clk_sata;

		clk_sata_oob = devm_clk_get(tegra_hpriv->dev, "sata_oob");
		if (IS_ERR_OR_NULL(clk_sata_oob)) {
			pr_err("%s: unable to get SATA OOB clock\n", __func__);
			err = PTR_ERR(clk_sata_oob);
			goto exit;
		}
		tegra_hpriv->clk_sata_oob = clk_sata_oob;

		rst_sata = devm_reset_control_get(tegra_hpriv->dev, "sata");
		if (IS_ERR_OR_NULL(rst_sata)) {
			pr_err("%s: unable to get SATA reset\n", __func__);
			err = PTR_ERR(rst_sata);
			goto exit;
		}
		tegra_hpriv->rst_sata = rst_sata;

		rst_sata_oob = devm_reset_control_get(tegra_hpriv->dev,
			"sata-oob");
		if (IS_ERR_OR_NULL(rst_sata_oob)) {
			pr_err("%s: unable to get SATA OOB reset\n", __func__);
			err = PTR_ERR(rst_sata_oob);
			goto exit;
		}
		tegra_hpriv->rst_sata_oob = rst_sata_oob;

		rst_sata_cold = devm_reset_control_get(tegra_hpriv->dev,
			"sata-cold");
		if (IS_ERR_OR_NULL(rst_sata_cold)) {
			pr_err("%s: unable to get SATA COLD reset\n", __func__);
			err = PTR_ERR(rst_sata_cold);
			goto exit;
		}
		tegra_hpriv->rst_sata_cold = rst_sata_cold;
	}

	reset_control_assert(tegra_hpriv->rst_sata);
	reset_control_assert(tegra_hpriv->rst_sata_oob);
	reset_control_assert(tegra_hpriv->rst_sata_cold);
	udelay(10);

	/* need to establish both clocks divisors before setting clk sources */
	clk_set_rate(tegra_hpriv->clk_sata,
			clk_get_rate(tegra_hpriv->clk_sata)/10);
	clk_set_rate(tegra_hpriv->clk_sata_oob,
			clk_get_rate(tegra_hpriv->clk_sata_oob)/10);

	/* set SATA clk and SATA_OOB clk source */
	clk_set_parent(tegra_hpriv->clk_sata,
			tegra_hpriv->clk_pllp);
	clk_set_parent(tegra_hpriv->clk_sata_oob,
			tegra_hpriv->clk_pllp);

	/* Configure SATA clocks */
	/* Core clock runs at 102MHz */
	if (clk_set_rate(tegra_hpriv->clk_sata,
			TEGRA_SATA_CORE_CLOCK_FREQ_HZ)) {
		err = -ENODEV;
		goto exit;
	}
	/* OOB clock runs at 204MHz */
	if (clk_set_rate(tegra_hpriv->clk_sata_oob,
			TEGRA_SATA_OOB_CLOCK_FREQ_HZ)) {
		err = -ENODEV;
		goto exit;
	}

	if (clk_prepare_enable(tegra_hpriv->clk_sata)) {
		pr_err("%s: unable to enable SATA clock\n", __func__);
		err = -ENODEV;
		goto exit;
	}

	if (clk_prepare_enable(tegra_hpriv->clk_sata_oob)) {
		pr_err("%s: unable to enable SATA OOB clock\n", __func__);
		err = -ENODEV;
		goto exit;
	}

	err = ahci_platform_enable_resources(hpriv);
	if (err) {
		pr_err("%s: unable to enable resources\n", __func__);
		goto exit;
	}

	g_tegra_hpriv->clk_state = CLK_ON;

	reset_control_deassert(tegra_hpriv->rst_sata);
	reset_control_deassert(tegra_hpriv->rst_sata_oob);
	reset_control_deassert(tegra_hpriv->rst_sata_cold);

	/* select internal CML ref clk
	 * select PLLE as input to IO phy */
	val = misc_readl(SATA_AUX_PAD_PLL_CNTL_1_REG);
	val &= ~REFCLK_SEL_MASK;
	val |= REFCLK_SEL_INT_CML;
	misc_writel(val, SATA_AUX_PAD_PLL_CNTL_1_REG);

	if (!lp0) {
#if defined(CONFIG_TEGRA_SILICON_PLATFORM)
#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
		partition_id = tegra_pd_get_powergate_id(tegra_sata_pd);
		if (partition_id < 0)
			return -EINVAL;
#else
		partition_id = TEGRA_POWERGATE_SATA;
#endif
		err = tegra_unpowergate_partition(partition_id);
		if (err) {
			pr_err("%s: ** failed to turn-on SATA (0x%x) **\n",
					__func__, err);
			goto exit;
		}
#endif
	}

	/* clear NVA2SATA_OOB_ON_POR in SATA_AUX_MISC_CNTL_1_REG */
	val = misc_readl(SATA_AUX_MISC_CNTL_1_REG);
	val &= ~NVA2SATA_OOB_ON_POR_MASK;
	misc_writel(val, SATA_AUX_MISC_CNTL_1_REG);

	/* Revisit: Disable devslp until all devslp bugs are fixed */
	val = misc_readl(SATA_AUX_MISC_CNTL_1_REG);
	val &= ~SDS_SUPPORT;
	misc_writel(val, SATA_AUX_MISC_CNTL_1_REG);

	val = sata_readl(SATA_CONFIGURATION_0_OFFSET);
	val |= EN_FPCI;
	sata_writel(val, SATA_CONFIGURATION_0_OFFSET);

	val |= CLK_OVERRIDE;
	sata_writel(val, SATA_CONFIGURATION_0_OFFSET);


	/* program sata pad control based on the fuse */
	tegra_ahci_set_pad_cntrl_regs(tegra_hpriv);

	/*
	 * clear bit T_SATA0_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD of
	 * T_SATA0_CFG_PHY_0
	 */
	val = scfg_readl(T_SATA0_CFG_PHY_REG);
	val |= T_SATA0_CFG_PHY_SQUELCH_MASK;
	val &= ~PHY_USE_7BIT_ALIGN_DET_FOR_SPD_MASK;
	scfg_writel(val, T_SATA0_CFG_PHY_REG);

	val = scfg_readl(T_SATA0_NVOOB);
	val |= (1 << T_SATA0_NVOOB_SQUELCH_FILTER_MODE_SHIFT);
	val |= (3 << T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_SHIFT);
	val |= T_SATA0_NVOOB_COMMA_CNT;
	scfg_writel(val, T_SATA0_NVOOB);

	/*
	 * WAR: Before enabling SATA PLL shutdown, lockdet needs to be ignored.
	 *      To ignore lockdet, T_SATA0_DBG0_OFFSET register bit 10 needs to
	 *      be 1, and bit 8 needs to be 0.
	 */
	val = scfg_readl(T_SATA0_DBG0_OFFSET);
	val |= (1 << 10);
	val &= ~(1 << 8);
	scfg_writel(val, T_SATA0_DBG0_OFFSET);

	/* program class code and programming interface for AHCI */
	val = scfg_readl(TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
	val |= TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
	scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
	scfg_writel(TEGRA_PRIVATE_AHCI_CC_BKDR_PGM, TEGRA_PRIVATE_AHCI_CC_BKDR);
	val &= ~TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
	scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);

	/* Program config space registers: */

	/* Enable BUS_MASTER+MEM+IO space, and SERR */
	val = scfg_readl(TEGRA_SATA_IO_SPACE_OFFSET);
	val |= TEGRA_SATA_ENABLE_IO_SPACE | TEGRA_SATA_ENABLE_MEM_SPACE |
		TEGRA_SATA_ENABLE_BUS_MASTER | TEGRA_SATA_ENABLE_SERR;
	scfg_writel(val, TEGRA_SATA_IO_SPACE_OFFSET);

	/* program bar5 space, by first writing 1's to bar5 register */
	scfg_writel(TEGRA_SATA_BAR5_INIT_PROGRAM, AHCI_BAR5_CONFIG_LOCATION);
	/* flush */
	val = scfg_readl(AHCI_BAR5_CONFIG_LOCATION);

	/* then, write the BAR5_FINAL_PROGRAM address */
	scfg_writel(TEGRA_SATA_BAR5_FINAL_PROGRAM, AHCI_BAR5_CONFIG_LOCATION);
	/* flush */
	scfg_readl(AHCI_BAR5_CONFIG_LOCATION);

	sata_writel((FPCI_BAR5_0_FINAL_VALUE >> 8),
			SATA_FPCI_BAR5_0_OFFSET);

	val = scfg_readl(T_SATA0_AHCI_HBA_CAP_BKDR);
	val |= (HOST_CAP_ALPM | HOST_CAP_SSC | HOST_CAP_PART | HOST_CAP_PMP);
	scfg_writel(val, T_SATA0_AHCI_HBA_CAP_BKDR);

	val = bar5_readl(AHCI_HBA_PLL_CTRL_0);
	val |= (SHUTDOWN_TXCLK_ON_SLUMBER | SHUTDOWN_TXCLK_ON_DEVSLP);
	val &= ~NO_CLAMP_SHUT_DOWN;
	bar5_writel(val, AHCI_HBA_PLL_CTRL_0);

	val = scfg_readl(SATA0_CFG_35_0);
	val |= (IDP_INDEX);
	scfg_writel(val, SATA0_CFG_35_0);

	val = scfg_readl(SATA0_AHCI_IDP1_0);
	val |= SATA0_AHCI_IDP1_0_DATA;
	scfg_writel(val, SATA0_AHCI_IDP1_0);

	val = scfg_readl(SATA0_CFG_PHY_1_0);
	val |= (PAD_IDDQ_EN | PAD_PLL_IDDQ_EN);
	scfg_writel(val, SATA0_CFG_PHY_1_0);

	/* set IP_INT_MASK */
	val = sata_readl(SATA_INTR_MASK_0_OFFSET);
	val |= IP_INT_MASK;
	sata_writel(val, SATA_INTR_MASK_0_OFFSET);

	/* set fifo l2p depth */
	if (tegra_hpriv->fifo_depth != 0) {
		val = scfg_readl(T_SATA0_FIFO);
		val &= ~T_SATA0_FIFO_L2P_FIFO_DEPTH_MASK;
		val |= tegra_hpriv->fifo_depth <<
			T_SATA0_FIFO_L2P_FIFO_DEPTH_SHIFT;
		scfg_writel(val, T_SATA0_FIFO);
	}

exit:
	if (err && !lp0) {
		/* turn off all SATA power rails; ignore returned status */
		tegra_ahci_power_off_rails(tegra_hpriv,
			tegra_hpriv->soc_data->num_sata_regulators);
	}
	return err;
}

static void tegra_ahci_controller_remove(struct platform_device *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	struct tegra_ahci_host_priv *tegra_hpriv;
	int status;

	tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;

#ifdef CONFIG_PM
	/* call tegra_ahci_controller_suspend() to power-down the SATA */
	status = tegra_ahci_controller_suspend(pdev);
	if (status)
		dev_err(host->dev, "remove: error suspend SATA (0x%x)\n",
				   status);
#else
	/* power off the sata */
#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
	int partition_id;
	partition_id = tegra_pd_get_powergate_id(tegra_sata_pd);
	if (partition_id < 0)
		return -EINVAL;
#else
	partition_id = TEGRA_POWERGATE_SATA;
#endif
	status = tegra_powergate_partition_with_clk_off(partition_id);
	if (status)
		dev_err(host->dev, "remove: error turn-off SATA (0x%x)\n",
				   status);
	tegra_ahci_power_off_rails(tegra_hpriv,
		tegra_hpriv->soc_data->num_sata_regulators);
#endif

}

#ifdef CONFIG_PM
static int tegra_ahci_controller_suspend(struct platform_device *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	struct tegra_ahci_host_priv *tegra_hpriv;

	tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;

	if (tegra_hpriv->pg_state == SATA_OFF)
		dev_dbg(host->dev, "suspend: SATA already power gated\n");
	else {
		bool pg_ok;

		dev_dbg(host->dev, "suspend: power gating SATA...\n");
		pg_ok = tegra_ahci_power_gate(host);
		if (pg_ok) {
			dev_dbg(host->dev, "suspend: SATA is power gated\n");
		} else {
			tegra_ahci_abort_power_gate(host);
			return -EBUSY;
		}
	}

	return tegra_ahci_power_off_rails(tegra_hpriv,
		tegra_hpriv->soc_data->num_sata_regulators);
}

static int tegra_ahci_controller_resume(struct platform_device *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	struct tegra_ahci_host_priv *tegra_hpriv;
	int err;

	tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;

	err = tegra_ahci_power_on_rails(tegra_hpriv);
	if (err) {
		pr_err("%s: fails to power on rails (%d)\n", __func__, err);
		return err;
	}

	if (tegra_hpriv->pg_state == SATA_ON) {
		dev_dbg(host->dev, "resume: SATA already powered on\n");
	} else {
		dev_dbg(host->dev, "resume: powering on SATA...\n");
		tegra_ahci_power_un_gate(host);
	}
	tegra_first_level_clk_gate();

	return 0;
}

#ifndef CONFIG_TEGRA_SATA_IDLE_POWERGATE