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path: root/drivers/gpu/drm/i915/Kconfig
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config DRM_I915
	tristate "Intel 8xx/9xx/G3x/G4x/HD Graphics"
	depends on DRM
	depends on X86 && PCI
	select INTEL_GTT
	select INTERVAL_TREE
	# we need shmfs for the swappable backing store, and in particular
	# the shmem_readpage() which depends upon tmpfs
	select SHMEM
	select TMPFS
	select DRM_KMS_HELPER
	select DRM_PANEL
	select DRM_MIPI_DSI
	# i915 depends on ACPI_VIDEO when ACPI is enabled
	# but for select to work, need to select ACPI_VIDEO's dependencies, ick
	select BACKLIGHT_LCD_SUPPORT if ACPI
	select BACKLIGHT_CLASS_DEVICE if ACPI
	select INPUT if ACPI
	select ACPI_VIDEO if ACPI
	select ACPI_BUTTON if ACPI
	help
	  Choose this option if you have a system that has "Intel Graphics
	  Media Accelerator" or "HD Graphics" integrated graphics,
	  including 830M, 845G, 852GM, 855GM, 865G, 915G, 945G, 965G,
	  G35, G41, G43, G45 chipsets and Celeron, Pentium, Core i3,
	  Core i5, Core i7 as well as Atom CPUs with integrated graphics.
	  If M is selected, the module will be called i915.  AGP support
	  is required for this driver to work. This driver is used by
	  the Intel driver in X.org 6.8 and XFree86 4.4 and above. It
	  replaces the older i830 module that supported a subset of the
	  hardware in older X.org releases.

	  Note that the older i810/i815 chipsets require the use of the
	  i810 driver instead, and the Atom z5xx series has an entirely
	  different implementation.

config DRM_I915_PRELIMINARY_HW_SUPPORT
	bool "Enable preliminary support for prerelease Intel hardware by default"
	depends on DRM_I915
	default n
	help
	  Choose this option if you have prerelease Intel hardware and want the
	  i915 driver to support it by default.  You can enable such support at
	  runtime with the module option i915.preliminary_hw_support=1; this
	  option changes the default for that module option.

	  If in doubt, say "N".

config DRM_I915_USERPTR
	bool "Always enable userptr support"
	depends on DRM_I915
	select MMU_NOTIFIER
	default y
	help
	  This option selects CONFIG_MMU_NOTIFIER if it isn't already
	  selected to enabled full userptr support.

	  If in doubt, say "Y".

config DRM_I915_GVT
        bool "Enable Intel GVT-g graphics virtualization host support"
        depends on DRM_I915
        default n
        help
	  Choose this option if you want to enable Intel GVT-g graphics
	  virtualization technology host support with integrated graphics.
	  With GVT-g, it's possible to have one integrated graphics
	  device shared by multiple VMs under different hypervisors.

	  Note that at least one hypervisor like Xen or KVM is required for
	  this driver to work, and it only supports newer device from
	  Broadwell+. For further information and setup guide, you can
	  visit: http://01.org/igvt-g.

	  Now it's just a stub to support the modifications of i915 for
	  GVT device model. It requires at least one MPT modules for Xen/KVM
	  and other components of GVT device model to work. Use it under
	  you own risk.

	  If in doubt, say "N".

menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
source drivers/gpu/drm/i915/Kconfig.debug
endmenu


















































































































                                                                     
/*
 * cirrus.h 1.4 1999/10/25 20:03:34
 *
 * The contents of this file are subject to the Mozilla Public License
 * Version 1.1 (the "License"); you may not use this file except in
 * compliance with the License. You may obtain a copy of the License
 * at http://www.mozilla.org/MPL/
 *
 * Software distributed under the License is distributed on an "AS IS"
 * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
 * the License for the specific language governing rights and
 * limitations under the License. 
 *
 * The initial developer of the original code is David A. Hinds
 * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
 * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
 *
 * Alternatively, the contents of this file may be used under the
 * terms of the GNU General Public License version 2 (the "GPL"), in which
 * case the provisions of the GPL are applicable instead of the
 * above.  If you wish to allow the use of your version of this file
 * only under the terms of the GPL and not to allow others to use
 * your version of this file under the MPL, indicate your decision by
 * deleting the provisions above and replace them with the notice and
 * other provisions required by the GPL.  If you do not delete the
 * provisions above, a recipient may use your version of this file
 * under either the MPL or the GPL.
 */

#ifndef _LINUX_CIRRUS_H
#define _LINUX_CIRRUS_H

#define PD67_MISC_CTL_1		0x16	/* Misc control 1 */
#define PD67_FIFO_CTL		0x17	/* FIFO control */
#define PD67_MISC_CTL_2		0x1E	/* Misc control 2 */
#define PD67_CHIP_INFO		0x1f	/* Chip information */
#define PD67_ATA_CTL		0x026	/* 6730: ATA control */
#define PD67_EXT_INDEX		0x2e	/* Extension index */
#define PD67_EXT_DATA		0x2f	/* Extension data */

/* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
#define PD67_DATA_MASK0		0x01	/* Data mask 0 */
#define PD67_DATA_MASK1		0x02	/* Data mask 1 */
#define PD67_DMA_CTL		0x03	/* DMA control */

/* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
#define PD67_EXT_CTL_1		0x03	/* Extension control 1 */
#define PD67_MEM_PAGE(n)	((n)+5)	/* PCI window bits 31:24 */
#define PD67_EXTERN_DATA	0x0a
#define PD67_MISC_CTL_3		0x25
#define PD67_SMB_PWR_CTL	0x26

/* I/O window address offset */
#define PD67_IO_OFF(w)		(0x36+((w)<<1))

/* Timing register sets */
#define PD67_TIME_SETUP(n)	(0x3a + 3*(n))
#define PD67_TIME_CMD(n)	(0x3b + 3*(n))
#define PD67_TIME_RECOV(n)	(0x3c + 3*(n))

/* Flags for PD67_MISC_CTL_1 */
#define PD67_MC1_5V_DET		0x01	/* 5v detect */
#define PD67_MC1_MEDIA_ENA	0x01	/* 6730: Multimedia enable */
#define PD67_MC1_VCC_3V		0x02	/* 3.3v Vcc */
#define PD67_MC1_PULSE_MGMT	0x04
#define PD67_MC1_PULSE_IRQ	0x08
#define PD67_MC1_SPKR_ENA	0x10
#define PD67_MC1_INPACK_ENA	0x80

/* Flags for PD67_FIFO_CTL */
#define PD67_FIFO_EMPTY		0x80

/* Flags for PD67_MISC_CTL_2 */