path: root/arch/arm/mach-s5pc100/clock.c

/* linux/arch/arm/mach-s5pc100/clock.c
 *
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com/
 *
 * S5PC100 - Clock support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <mach/map.h>

#include <plat/cpu-freq.h>
#include <mach/regs-clock.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>

#include "common.h"

static struct clk s5p_clk_otgphy = {
	.name		= "otg_phy",
};

static struct clk dummy_apb_pclk = {
	.name		= "apb_pclk",
	.id		= -1,
};

static struct clk *clk_src_mout_href_list[] = {
	[0] = &s5p_clk_27m,
	[1] = &clk_fin_hpll,
};

static struct clksrc_sources clk_src_mout_href = {
	.sources	= clk_src_mout_href_list,
	.nr_sources	= ARRAY_SIZE(clk_src_mout_href_list),
};

static struct clksrc_clk clk_mout_href = {
	.clk = {
		.name           = "mout_href",
	},
	.sources        = &clk_src_mout_href,
	.reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
};

static struct clk *clk_src_mout_48m_list[] = {
	[0] = &clk_xusbxti,
	[1] = &s5p_clk_otgphy,
};

static struct clksrc_sources clk_src_mout_48m = {
	.sources	= clk_src_mout_48m_list,
	.nr_sources	= ARRAY_SIZE(clk_src_mout_48m_list),
};

static struct clksrc_clk clk_mout_48m = {
	.clk = {
		.name           = "mout_48m",
	},
	.sources        = &clk_src_mout_48m,
	.reg_src        = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
};

static struct clksrc_clk clk_mout_mpll = {
	.clk = {
		.name           = "mout_mpll",
	},
	.sources        = &clk_src_mpll,
	.reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
};


static struct clksrc_clk clk_mout_apll = {
	.clk    = {
		.name           = "mout_apll",
	},
	.sources        = &clk_src_apll,
	.reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
};

static struct clksrc_clk clk_mout_epll = {
	.clk    = {
		.name           = "mout_epll",
	},
	.sources        = &clk_src_epll,
	.reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
};

static struct clk *clk_src_mout_hpll_list[] = {
	[0] = &s5p_clk_27m,
};

static struct clksrc_sources clk_src_mout_hpll = {
	.sources	= clk_src_mout_hpll_list,
	.nr_sources	= ARRAY_SIZE(clk_src_mout_hpll_list),
};

static struct clksrc_clk clk_mout_hpll = {
	.clk    = {
		.name           = "mout_hpll",
	},
	.sources        = &clk_src_mout_hpll,
	.reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
};

static struct clksrc_clk clk_div_apll = {
	.clk	= {
		.name	= "div_apll",
		.parent	= &clk_mout_apll.clk,
	},
	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
};

static struct clksrc_clk clk_div_arm = {
	.clk	= {
		.name	= "div_arm",
		.parent	= &clk_div_apll.clk,
	},
	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
};

static struct clksrc_clk clk_div_d0_bus = {
	.clk	= {
		.name	= "div_d0_bus",
		.parent	= &clk_div_arm.clk,
	},
	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
};

static struct clksrc_clk clk_div_pclkd0 = {
	.clk	= {
		.name	= "div_pclkd0",
		.parent	= &clk_div_d0_bus.clk,
	},
	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
};

static struct clksrc_clk clk_div_secss = {
	.clk	= {
		.name	= "div_secss",
		.parent	= &clk_div_d0_bus.clk,
	},
	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size