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generated by cgit v1.2.2 (git 2.25.0) at 2025-10-02 14:45:23 -0400
t">|| var->yres > 1024) printk(KERN_ERR "%s: invalid yres %d\n", fbi->fb.fix.id, var->yres); if (var->vsync_len < 1 || var->vsync_len > 64) printk(KERN_ERR "%s: invalid vsync_len %d\n", fbi->fb.fix.id, var->vsync_len); if (var->upper_margin < 0 || var->upper_margin > 255) printk(KERN_ERR "%s: invalid upper_margin %d\n", fbi->fb.fix.id, var->upper_margin); if (var->lower_margin < 0 || var->lower_margin > 255) printk(KERN_ERR "%s: invalid lower_margin %d\n", fbi->fb.fix.id, var->lower_margin); #endif new_regs.lccr0 = fbi->lccr0 | LCCR0_LEN | LCCR0_LDM | LCCR0_BAM | LCCR0_ERM | LCCR0_LtlEnd | LCCR0_DMADel(0); new_regs.lccr1 = LCCR1_DisWdth(var->xres) + LCCR1_HorSnchWdth(var->hsync_len) + LCCR1_BegLnDel(var->left_margin) + LCCR1_EndLnDel(var->right_margin); /* * If we have a dual scan LCD, then we need to halve * the YRES parameter. */ yres = var->yres; if (fbi->lccr0 & LCCR0_Dual) yres /= 2; new_regs.lccr2 = LCCR2_DisHght(yres) + LCCR2_VrtSnchWdth(var->vsync_len) + LCCR2_BegFrmDel(var->upper_margin) + LCCR2_EndFrmDel(var->lower_margin); pcd = get_pcd(var->pixclock, cpufreq_get(0)); new_regs.lccr3 = LCCR3_PixClkDiv(pcd) | fbi->lccr3 | (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) | (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL); DPRINTK("nlccr0 = 0x%08lx\n", new_regs.lccr0); DPRINTK("nlccr1 = 0x%08lx\n", new_regs.lccr1); DPRINTK("nlccr2 = 0x%08lx\n", new_regs.lccr2); DPRINTK("nlccr3 = 0x%08lx\n", new_regs.lccr3); half_screen_size = var->bits_per_pixel; half_screen_size = half_screen_size * var->xres * var->yres / 16; /* Update shadow copy atomically */ local_irq_save(flags); fbi->dbar1 = fbi->palette_dma; fbi->dbar2 = fbi->screen_dma + half_screen_size; fbi->reg_lccr0 = new_regs.lccr0; fbi->reg_lccr1 = new_regs.lccr1; fbi->reg_lccr2 = new_regs.lccr2; fbi->reg_lccr3 = new_regs.lccr3; local_irq_restore(flags); /* * Only update the registers if the controller is enabled * and something has changed. */ if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) || (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) || (DBAR1 != fbi->dbar1) || (DBAR2 != fbi->dbar2)) sa1100fb_schedule_work(fbi, C_REENABLE); return 0; } /* * NOTE! The following functions are purely helpers for set_ctrlr_state. * Do not call them directly; set_ctrlr_state does the correct serialisation * to ensure that things happen in the right way 100% of time time. * -- rmk */ static inline void __sa1100fb_backlight_power(struct sa1100fb_info *fbi, int on) { DPRINTK("backlight o%s\n", on ? "n" : "ff"); if (sa1100fb_backlight_power) sa1100fb_backlight_power(on); } static inline void __sa1100fb_lcd_power(struct sa1100fb_info *fbi, int on) { DPRINTK("LCD power o%s\n", on ? "n" : "ff"); if (sa1100fb_lcd_power) sa1100fb_lcd_power(on); } static void sa1100fb_setup_gpio(struct sa1100fb_info *fbi) { u_int mask = 0; /* * Enable GPIO<9:2> for LCD use if: * 1. Active display, or * 2. Color Dual Passive display * * see table 11.8 on page 11-27 in the SA1100 manual * -- Erik. * * SA1110 spec update nr. 25 says we can and should * clear LDD15 to 12 for 4 or 8bpp modes with active * panels. */ if ((fbi->reg_lccr0 & LCCR0_CMS) == LCCR0_Color && (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) != 0) { mask = GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8; if (fbi->fb.var.bits_per_pixel > 8 || (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) == LCCR0_Dual) mask |= GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12; } if (mask) { GPDR |= mask; GAFR |= mask; } } static void sa1100fb_enable_controller(struct sa1100fb_info *fbi) { DPRINTK("Enabling LCD controller\n"); /* * Make sure the mode bits are present in the first palette entry */ fbi->palette_cpu[0] &= 0xcfff; fbi->palette_cpu[0] |= palette_pbs(&fbi->fb.var); /* Sequence from 11.7.10 */ LCCR3 = fbi->reg_lccr3; LCCR2 = fbi->reg_lccr2; LCCR1 = fbi->reg_lccr1; LCCR0 = fbi->reg_lccr0 & ~LCCR0_LEN; DBAR1 = fbi->dbar1; DBAR2 = fbi->dbar2; LCCR0 |= LCCR0_LEN; if (machine_is_shannon()) { GPDR |= SHANNON_GPIO_DISP_EN; GPSR |= SHANNON_GPIO_DISP_EN; } DPRINTK("DBAR1 = 0x%08x\n", DBAR1); DPRINTK("DBAR2 = 0x%08x\n", DBAR2); DPRINTK("LCCR0 = 0x%08x\n", LCCR0); DPRINTK("LCCR1 = 0x%08x\n", LCCR1); DPRINTK("LCCR2 = 0x%08x\n", LCCR2); DPRINTK("LCCR3 = 0x%08x\n", LCCR3); } static void sa1100fb_disable_controller(struct sa1100fb_info *fbi) { DECLARE_WAITQUEUE(wait, current); DPRINTK("Disabling LCD controller\n"); if (machine_is_shannon()) { GPCR |= SHANNON_GPIO_DISP_EN; } set_current_state(TASK_UNINTERRUPTIBLE); add_wait_queue(&fbi->ctrlr_wait, &wait); LCSR = 0xffffffff; /* Clear LCD Status Register */ LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */ LCCR0 &= ~LCCR0_LEN; /* Disable LCD Controller */ schedule_timeout(20 * HZ / 1000); remove_wait_queue(&fbi->ctrlr_wait, &wait); } /* * sa1100fb_handle_irq: Handle 'LCD DONE' interrupts. */ static irqreturn_t sa1100fb_handle_irq(int irq, void *dev_id) { struct sa1100fb_info *fbi = dev_id; unsigned int lcsr = LCSR; if (lcsr & LCSR_LDD) { LCCR0 |= LCCR0_LDM; wake_up(&fbi->ctrlr_wait); } LCSR = lcsr; return IRQ_HANDLED; } /* * This function must be called from task context only, since it will * sleep when disabling the LCD controller, or if we get two contending * processes trying to alter state. */ static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state) { u_int old_state; down(&fbi->ctrlr_sem); old_state = fbi->state; /* * Hack around fbcon initialisation. */ if (old_state == C_STARTUP && state == C_REENABLE) state = C_ENABLE; switch (state) { case C_DISABLE_CLKCHANGE: /* * Disable controller for clock change. If the * controller is already disabled, then do nothing. */ if (old_state != C_DISABLE && old_state != C_DISABLE_PM) { fbi->state = state; sa1100fb_disable_controller(fbi); } break; case C_DISABLE_PM: case C_DISABLE: /* * Disable controller */ if (old_state != C_DISABLE) { fbi->state = state; __sa1100fb_backlight_power(fbi, 0); if (old_state != C_DISABLE_CLKCHANGE) sa1100fb_disable_controller(fbi); __sa1100fb_lcd_power(fbi, 0); } break; case C_ENABLE_CLKCHANGE: /* * Enable the controller after clock change. Only * do this if we were disabled for the clock change. */ if (old_state == C_DISABLE_CLKCHANGE) { fbi->state = C_ENABLE; sa1100fb_enable_controller(fbi); } break; case C_REENABLE: /* * Re-enable the controller only if it was already * enabled. This is so we reprogram the control * registers. */ if (old_state == C_ENABLE) { sa1100fb_disable_controller(fbi); sa1100fb_setup_gpio(fbi); sa1100fb_enable_controller(fbi); } break; case C_ENABLE_PM: /* * Re-enable the controller after PM. This is not * perfect - think about the case where we were doing * a clock change, and we suspended half-way through. */ if (old_state != C_DISABLE_PM) break; /* fall through */ case C_ENABLE: /* * Power up the LCD screen, enable controller, and * turn on the backlight. */ if (old_state != C_ENABLE) { fbi->state = C_ENABLE; sa1100fb_setup_gpio(fbi); __sa1100fb_lcd_power(fbi, 1); sa1100fb_enable_controller(fbi); __sa1100fb_backlight_power(fbi, 1); } break; } up(&fbi->ctrlr_sem); } /* * Our LCD controller task (which is called when we blank or unblank) * via keventd. */ static void sa1100fb_task(struct work_struct *w) { struct sa1100fb_info *fbi = container_of(w, struct sa1100fb_info, task); u_int state = xchg(&fbi->task_state, -1); set_ctrlr_state(fbi, state); } #ifdef CONFIG_CPU_FREQ /* * Calculate the minimum DMA period over all displays that we own. * This, together with the SDRAM bandwidth defines the slowest CPU * frequency that can be selected. */ static unsigned int sa1100fb_min_dma_period(struct sa1100fb_info *fbi) { #if 0 unsigned int min_period = (unsigned int)-1; int i; for (i = 0; i < MAX_NR_CONSOLES; i++) { struct display *disp = &fb_display[i]; unsigned int period; /* * Do we own this display? */ if (disp->fb_info != &fbi->fb) continue; /* * Ok, calculate its DMA period */ period = sa1100fb_display_dma_period(&disp->var); if (period < min_period) min_period = period; } return min_period; #else /* * FIXME: we need to verify _all_ consoles. */ return sa1100fb_display_dma_period(&fbi->fb.var); #endif } /* * CPU clock speed change handler. We need to adjust the LCD timing * parameters when the CPU clock is adjusted by the power management * subsystem. */ static int sa1100fb_freq_transition(struct notifier_block *nb, unsigned long val, void *data) { struct sa1100fb_info *fbi = TO_INF(nb, freq_transition); struct cpufreq_freqs *f = data; u_int pcd; switch (val) { case CPUFREQ_PRECHANGE: set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE); break; case CPUFREQ_POSTCHANGE: pcd = get_pcd(fbi->fb.var.pixclock, f->new); fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd); set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE); break; } return 0; } static int sa1100fb_freq_policy(struct notifier_block *nb, unsigned long val, void *data) { struct sa1100fb_info *fbi = TO_INF(nb, freq_policy); struct cpufreq_policy *policy = data; switch (val) { case CPUFREQ_ADJUST: case CPUFREQ_INCOMPATIBLE: printk(KERN_DEBUG "min dma period: %d ps, " "new clock %d kHz\n", sa1100fb_min_dma_period(fbi), policy->max); /* todo: fill in min/max values */ break; case CPUFREQ_NOTIFY: do {} while(0); /* todo: panic if min/max values aren't fulfilled * [can't really happen unless there's a bug in the * CPU policy verififcation process * */ break; } return 0; } #endif #ifdef CONFIG_PM /* * Power management hooks. Note that we won't be called from IRQ context, * unlike the blank functions above, so we may sleep. */ static int sa1100fb_suspend(struct platform_device *dev, pm_message_t state) { struct sa1100fb_info *fbi = platform_get_drvdata(dev); set_ctrlr_state(fbi, C_DISABLE_PM); return 0; } static int sa1100fb_resume(struct platform_device *dev) { struct sa1100fb_info *fbi = platform_get_drvdata(dev); set_ctrlr_state(fbi, C_ENABLE_PM); return 0; } #else #define sa1100fb_suspend NULL #define sa1100fb_resume NULL #endif /* * sa1100fb_map_video_memory(): * Allocates the DRAM memory for the frame buffer. This buffer is * remapped into a non-cached, non-buffered, memory region to * allow palette and pixel writes to occur without flushing the * cache. Once this area is remapped, all virtual memory * access to the video memory should occur at the new region. */ static int __init sa1100fb_map_video_memory(struct sa1100fb_info *fbi) { /* * We reserve one page for the palette, plus the size * of the framebuffer. */ fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE); fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size, &fbi->map_dma, GFP_KERNEL); if (fbi->map_cpu) { fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE; fbi->screen_dma = fbi->map_dma + PAGE_SIZE; /* * FIXME: this is actually the wrong thing to place in * smem_start. But fbdev suffers from the problem that * it needs an API which doesn't exist (in this case, * dma_writecombine_mmap) */ fbi->fb.fix.smem_start = fbi->screen_dma; } return fbi->map_cpu ? 0 : -ENOMEM; } /* Fake monspecs to fill in fbinfo structure */ static struct fb_monspecs monspecs __initdata = { .hfmin = 30000, .hfmax = 70000, .vfmin = 50, .vfmax = 65, }; static struct sa1100fb_info * __init sa1100fb_init_fbinfo(struct device *dev) { struct sa1100fb_mach_info *inf; struct sa1100fb_info *fbi; fbi = kmalloc(sizeof(struct sa1100fb_info) + sizeof(u32) * 16, GFP_KERNEL); if (!fbi) return NULL; memset(fbi, 0, sizeof(struct sa1100fb_info)); fbi->dev = dev; strcpy(fbi->fb.fix.id, SA1100_NAME); fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS; fbi->fb.fix.type_aux = 0; fbi->fb.fix.xpanstep = 0; fbi->fb.fix.ypanstep = 0; fbi->fb.fix.ywrapstep = 0; fbi->fb.fix.accel = FB_ACCEL_NONE; fbi->fb.var.nonstd = 0; fbi->fb.var.activate = FB_ACTIVATE_NOW; fbi->fb.var.height = -1; fbi->fb.var.width = -1; fbi->fb.var.accel_flags = 0; fbi->fb.var.vmode = FB_VMODE_NONINTERLACED; fbi->fb.fbops = &sa1100fb_ops; fbi->fb.flags = FBINFO_DEFAULT; fbi->fb.monspecs = monspecs; fbi->fb.pseudo_palette = (fbi + 1); fbi->rgb[RGB_8] = &rgb_8; fbi->rgb[RGB_16] = &def_rgb_16; inf = sa1100fb_get_machine_info(fbi); /* * People just don't seem to get this. We don't support * anything but correct entries now, so panic if someone * does something stupid. */ if (inf->lccr3 & (LCCR3_VrtSnchL|LCCR3_HorSnchL|0xff) || inf->pixclock == 0) panic("sa1100fb error: invalid LCCR3 fields set or zero " "pixclock."); fbi->max_xres = inf->xres; fbi->fb.var.xres = inf->xres; fbi->fb.var.xres_virtual = inf->xres; fbi->max_yres = inf->yres; fbi->fb.var.yres = inf->yres; fbi->fb.var.yres_virtual = inf->yres; fbi->max_bpp = inf->bpp; fbi->fb.var.bits_per_pixel = inf->bpp; fbi->fb.var.pixclock = inf->pixclock; fbi->fb.var.hsync_len = inf->hsync_len; fbi->fb.var.left_margin = inf->left_margin; fbi->fb.var.right_margin = inf->right_margin; fbi->fb.var.vsync_len = inf->vsync_len; fbi->fb.var.upper_margin = inf->upper_margin; fbi->fb.var.lower_margin = inf->lower_margin; fbi->fb.var.sync = inf->sync; fbi->fb.var.grayscale = inf->cmap_greyscale; fbi->cmap_inverse = inf->cmap_inverse; fbi->cmap_static = inf->cmap_static; fbi->lccr0 = inf->lccr0; fbi->lccr3 = inf->lccr3; fbi->state = C_STARTUP; fbi->task_state = (u_char)-1; fbi->fb.fix.smem_len = fbi->max_xres * fbi->max_yres * fbi->max_bpp / 8; init_waitqueue_head(&fbi->ctrlr_wait); INIT_WORK(&fbi->task, sa1100fb_task); init_MUTEX(&fbi->ctrlr_sem); return fbi; } static int __init sa1100fb_probe(struct platform_device *pdev) { struct sa1100fb_info *fbi; int ret, irq; irq = platform_get_irq(pdev, 0); if (irq < 0) return -EINVAL; if (!request_mem_region(0xb0100000, 0x10000, "LCD")) return -EBUSY; fbi = sa1100fb_init_fbinfo(&pdev->dev); ret = -ENOMEM; if (!fbi) goto failed; /* Initialize video memory */ ret = sa1100fb_map_video_memory(fbi); if (ret) goto failed; ret = request_irq(irq, sa1100fb_handle_irq, IRQF_DISABLED, "LCD", fbi); if (ret) { printk(KERN_ERR "sa1100fb: request_irq failed: %d\n", ret); goto failed; } #ifdef ASSABET_PAL_VIDEO if (machine_is_assabet()) ASSABET_BCR_clear(ASSABET_BCR_LCD_ON); #endif /* * This makes sure that our colour bitfield * descriptors are correctly initialised. */ sa1100fb_check_var(&fbi->fb.var, &fbi->fb); platform_set_drvdata(pdev, fbi); ret = register_framebuffer(&fbi->fb); if (ret < 0) goto err_free_irq; #ifdef CONFIG_CPU_FREQ fbi->freq_transition.notifier_call = sa1100fb_freq_transition; fbi->freq_policy.notifier_call = sa1100fb_freq_policy; cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER); cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER); #endif /* This driver cannot be unloaded at the moment */ return 0; err_free_irq: free_irq(irq, fbi); failed: platform_set_drvdata(pdev, NULL); kfree(fbi); release_mem_region(0xb0100000, 0x10000); return ret; } static struct platform_driver sa1100fb_driver = { .probe = sa1100fb_probe, .suspend = sa1100fb_suspend, .resume = sa1100fb_resume, .driver = { .name = "sa11x0-fb", }, }; int __init sa1100fb_init(void) { if (fb_get_options("sa1100fb", NULL)) return -ENODEV; return platform_driver_register(&sa1100fb_driver); } int __init sa1100fb_setup(char *options) { #if 0 char *this_opt; if (!options || !*options) return 0; while ((this_opt = strsep(&options, ",")) != NULL) { if (!strncmp(this_opt, "bpp:", 4)) current_par.max_bpp = simple_strtoul(this_opt + 4, NULL, 0); if (!strncmp(this_opt, "lccr0:", 6)) lcd_shadow.lccr0 = simple_strtoul(this_opt + 6, NULL, 0); if (!strncmp(this_opt, "lccr1:", 6)) { lcd_shadow.lccr1 = simple_strtoul(this_opt + 6, NULL, 0); current_par.max_xres = (lcd_shadow.lccr1 & 0x3ff) + 16; } if (!strncmp(this_opt, "lccr2:", 6)) { lcd_shadow.lccr2 = simple_strtoul(this_opt + 6, NULL, 0); current_par.max_yres = (lcd_shadow. lccr0 & LCCR0_SDS) ? ((lcd_shadow. lccr2 & 0x3ff) + 1) * 2 : ((lcd_shadow.lccr2 & 0x3ff) + 1); } if (!strncmp(this_opt, "lccr3:", 6)) lcd_shadow.lccr3 = simple_strtoul(this_opt + 6, NULL, 0); } #endif return 0; } module_init(sa1100fb_init); MODULE_DESCRIPTION("StrongARM-1100/1110 framebuffer driver"); MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-02 14:45:23 -0400