| Commit message (Expand) | Author | Age | |
|---|---|---|---|
| * | soc: xilinx: xlnx_vcu: Use bitwise & rather than logical && on clkoutdiv | Gustavo A. R. Silva | 2018-01-16 |
| * | soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver | Dhaval Shah | 2018-01-08 |
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index : litmus-rt-ext-res.git | |
| LITMUS^RT with extended reservations for Forbidden Zones paper @ RTAS'20 | Zelin Tong |
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