Commit message (Collapse) | Author | Age | |
---|---|---|---|
* | drm/mediatek: modify the factor to make the pll_rate set in the 1G-2G range | Junzhi Zhao | 2016-10-18 |
| | | | | | | | | | | | | | Currently, the code sets the "pll" to the desired multiple of the pixel clock manully(4*3m 8*3,etc). The valid range of the pll is 1G-2G, however, when the pixel clock is bigger than 167MHz, the "pll" will be set to a invalid value( > 2G), then the "pll" will be 2GHz, thus the pixel clock will be in correct. Change the factor to make the "pll" be set in the (1G, 2G) range. Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> | ||
* | drm/mediatek: mtk_dpi: remove invalid error message | Philipp Zabel | 2016-06-01 |
| | | | | | | | | | Do not try to dereference dpi if it is NULL. Since dpi can never be NULL when mtk_dpi_set_display_mode() is called, remove the message. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> | ||
* | drm/mediatek: Add DPI sub driver | Jie Qiu | 2016-05-06 |
Add DPI connector/encoder to support HDMI output via the attached HDMI bridge. Signed-off-by: Jie Qiu <jie.qiu@mediatek.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |